Thin Film Transistor Substrate

Abstract

To improve the characteristics of an oxide semiconductor thin film transistor.SOLUTION: A thin film transistor substrate includes an insulating substrate, a conductor layer including a top-gate electrode part of an oxide semiconductor thin film transistor, an oxide semiconductor layer including a channel region of the oxide semiconductor thin film transistor below the top-gate electrode part, and an upper insulator layer between the conductor layer and the oxide semiconductor layer. The oxide semiconductor layer includes low-resistance regions with lower resistance than the channel region. The low-resistance regions have the channel region therebetween in a substrate surface direction and include low-resistance cause impurities of the low-resistance regions. The concentration profile of the low-resistance cause impurities in a lamination direction exhibits one or more peaks. The one or more peaks exist outside the oxide semiconductor layer.SELECTED DRAWING: Figure 9A

Description

[Technical field]

[0001] The present disclosure relates to a thin film transistor substrate. [Background technology]

[0002] A technology that combines low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs into one circuit has been put to practical use. For example, a pixel circuit that includes a low-temperature polysilicon TFT and an oxide semiconductor TFT has been proposed. By combining both a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT with low leakage current into a circuit, it is possible to improve the circuit characteristics and reduce power consumption.

[0003] The semiconductor layer of an oxide semiconductor TFT includes a channel region and source / drain regions sandwiching the channel region. The source / drain regions are low-resistance regions with lower resistance than the channel region. The low-resistance regions can be formed by exposing the oxide semiconductor layer to plasma of a specific element, or by irradiating the oxide semiconductor layer with impurity ions by ion implantation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 0127329 [Patent Document 2] U.S. Patent Application Publication No. 2020 / 0219954 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to reduce the resistance of the oxide semiconductor layer, it is important that the channel length is as designed. Therefore, when reducing the resistance of the oxide semiconductor layer by ion implantation, it is important to accurately control the concentration profile of the implanted ions. If the impurity concentration remaining in the oxide semiconductor layer is too high, the channel length becomes short, and the short channel TFT may not operate normally. [Means for solving the problem]

[0006] A thin film transistor substrate according to an embodiment of the present disclosure includes an insulating substrate, a conductor layer including a top gate electrode portion of an oxide semiconductor thin film transistor, an oxide semiconductor layer including a channel region of the oxide semiconductor thin film transistor below the top gate electrode portion, and an upper insulator layer between the conductor layer and the oxide semiconductor layer. The oxide semiconductor layer includes a low-resistance region having a lower resistance than the channel region. The low-resistance region sandwiches the channel region in the in-plane direction of the substrate and includes low-resistance impurities of the low-resistance region. A concentration profile of the low-resistance impurities in the stacking direction shows one or more peaks. The one or more peaks are present outside the oxide semiconductor layer. Effect of the Invention

[0007] According to one aspect of the present disclosure, the characteristics of an oxide semiconductor thin film transistor can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 shows a schematic configuration example of an OLED display device. [Diagram 2] 2 shows a configuration example of a pixel circuit. [Diagram 3] 2 is a schematic diagram showing a cross-sectional structure of a portion of a TFT substrate. [Figure 4] An example of a CMOS circuit is shown below. [Diagram 5] 1 shows a schematic example of the cross-sectional structure of a CMOS circuit. [Figure 6A] An example of a method for manufacturing an oxide semiconductor TFT will be described. [Figure 6B]An example of a method for manufacturing an oxide semiconductor TFT will be described. [Figure 6C] An example of a method for manufacturing an oxide semiconductor TFT will be described. [Figure 6D] An example of a method for manufacturing an oxide semiconductor TFT will be described. [Figure 7A] Another example of the method for manufacturing an oxide semiconductor TFT will be described. [Figure 7B] Another example of the method for manufacturing an oxide semiconductor TFT will be described. [Figure 7C] Another example of the method for manufacturing an oxide semiconductor TFT will be described. [Figure 7D] Another example of the method for manufacturing an oxide semiconductor TFT will be described. [Figure 8] 4 shows the implantation of impurity ions into an oxide semiconductor TFT in a comparative example. [Figure 9A] 1 shows an example of an impurity concentration profile of an oxide semiconductor TFT and its vicinity in one embodiment of this specification. [Figure 9B] 1 shows an example of a measurement of a boron concentration profile in an IGZO-TFT and its vicinity in one embodiment of the present specification. [Figure 9C] 1 shows measurement results of an oxide semiconductor TFT according to an embodiment of the present specification. [Figure 10A] 1 shows an example of an impurity concentration profile of an oxide semiconductor TFT and its vicinity in one embodiment of this specification. [Figure 10B] 1 shows an example of an impurity concentration profile of an oxide semiconductor TFT and its vicinity in one embodiment of this specification. [Figure 11] Schematic diagram of the dC / dV signal and its relationship with carrier concentration when an n-type semiconductor is analyzed by SCM. [Figure 12] 4 shows a change in dC / dV signal value in an oxide semiconductor layer in one embodiment of the present specification. [Figure 13] 4 shows a change in dC / dV signal value in an oxide semiconductor layer in one embodiment of the present specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure. For ease of explanation, the dimensions and shapes of the objects illustrated may be exaggerated.

[0010] [Summary] In the following, an OLED (Organic Light-Emitting Diode) display device will be described as an example of a device including a thin film transistor substrate. The OLED display device of the present disclosure includes a low-temperature polysilicon thin film transistor (LTPS TFT) and an oxide semiconductor TFT in a pixel circuit and / or a peripheral circuit. An example of an oxide semiconductor is IGZO (Indium Gallium Zinc Oxide). The OLED display device can be used not only in OLEDs but also in flat panel displays such as liquid crystal displays, memory devices, high voltage devices, and other electronic devices.

[0011] Since the leakage current of the oxide semiconductor TFT is small, for example, the oxide semiconductor TFT is used as a switch transistor connected to a storage capacitor (capacitor element) for maintaining the gate potential of a drive transistor in a pixel circuit. A low-temperature polysilicon TFT with high mobility is used as a drive transistor. The configuration of the present disclosure can be applied to devices other than a display device.

[0012] In one embodiment of the present specification, the resistance of an oxide semiconductor layer is reduced by impurity ion implantation. The reduced resistance region includes the source / drain region of an oxide semiconductor TFT. In reducing the resistance of an oxide semiconductor layer, it is important that the channel length is as designed. Therefore, when reducing the resistance of an oxide semiconductor layer by ion implantation, it is important to accurately control the concentration profile of the implanted ions. If the impurity concentration remaining in the oxide semiconductor layer is too high, the channel length becomes short, and the short channel TFT may not operate normally.

[0013] In one embodiment of the present specification, the impurity concentration profile in the stacking direction shows one or more peaks, and the one or more peaks are located outside the oxide semiconductor layer. In this way, by shifting the peak position of the impurity concentration profile from the oxide semiconductor layer, it is possible to more easily form a desired low-resistance region of the oxide semiconductor.

[0014] In one embodiment of the present specification, the oxide semiconductor layer includes a transition region in which the carrier concentration increases from the end of the top gate electrode toward the outside. This configuration can realize more preferable characteristics of the oxide semiconductor TFT. Furthermore, the dC / dV value of the SCM analysis of the transition region shows a negative minimum value. Specifically, the dC / dV value shows a negative value at the end of the top gate electrode, decreases as the distance from the top gate electrode increases toward the outside, shows a minimum value, and then increases with increasing distance. The dC / dV value reaches zero outside the transition region. This configuration can realize more preferable characteristics of the oxide semiconductor TFT.

[0015] [Display device configuration] 1 is a schematic diagram showing an example of the configuration of an OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which OLED elements and pixel circuits are formed, and a thin film encapsulation structure (TFE: Thin Film Encapsulation) 20 that encapsulates the organic light-emitting elements. The thin film encapsulation structure 20 is one of the encapsulation structures, and as another example, the encapsulation structure may include a encapsulation substrate that encapsulates the organic light-emitting elements, and a joint (glass frit seal portion) that joins the TFT substrate 10 and the encapsulation substrate. For example, dry nitrogen is filled between the TFT substrate 10 and the encapsulation substrate.

[0016] A scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via an FPC (Flexible Printed Circuit) 35. The scan driver 31, the emission driver 32, and the protection circuit 33 are peripheral circuits formed on the TFT substrate 10.

[0017] The scan driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emitting period of each pixel. The driver IC 34 is implemented using, for example, an anisotropic conductive film (ACF).

[0018] The protection circuit 33 prevents electrostatic damage to elements in the pixel circuits. The driver IC 34 provides power and timing signals (control signals) to the scan driver 31 and the emission driver 32. Furthermore, the driver IC 34 provides power and data signals to the demultiplexer 36.

[0019] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 switches the output data line of the data signal from the driver IC 34 d times within a scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 34.

[0020] [Circuit configuration] On the TFT substrate 10, a plurality of pixel circuits are formed, which control the current supplied to the anode electrodes of a plurality of sub-pixels (also simply called pixels). FIG. 2 shows an example of the configuration of the pixel circuits. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the emission of the OLED element E1. The transistors are TFTs. The transistors other than the drive transistor T1 are switch transistors.

[0021] The selection transistor T2 is a switch for selecting a subpixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and has a gate terminal connected to a scanning line 16. A source terminal is connected to a data line 15. A drain terminal is connected to the gate terminal of the driving transistor T1.

[0022] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the drain terminal of the emission transistor T3, and the drain terminal is connected to the OLED element E1. A storage capacitor C1 is formed between the gate terminal of the driving transistor T1 and the power line 18.

[0023] The emission transistor T3 is a switch that controls the supply and stop of the driving current to the OLED element E1. The emission transistor T3 is a p-channel polysilicon TFT, and the gate terminal is connected to the emission control line 17. The source terminal of the emission transistor T3 is connected to the power supply line 18. The drain terminal is connected to the source terminal of the driving transistor T1.

[0024] Next, the operation of the pixel circuit will be described. The scan driver 31 outputs a selection pulse to the scan line 16 to turn on the selection transistor T2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage throughout one frame period. The hold voltage changes the conductance of the drive transistor T1 in an analog manner, and the drive transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0025] The emission transistor T3 is located on a supply path of the driving current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is in an on state, the driving current is supplied to the OLED element E1. When the emission transistor T3 is in an off state, the supply is stopped. By controlling the on / off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled. Note that the pixel circuit in FIG. 2 is an example, and the pixel circuit may have other configurations.

[0026] [TFT substrate configuration] In the following, a configuration example of a TFT substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT will be described. The oxide semiconductor is, for example, IGZO. The configuration described in this specification can be applied to a TFT substrate including TFTs made of other types of oxide semiconductors.

[0027] 3 shows a schematic cross-sectional structure of a portion of the TFT substrate. A low-temperature polysilicon TFT 141, an oxide semiconductor TFT 142, a storage capacitor 143, and an OLED element 144 are formed on an insulating substrate 101. These correspond to the drive transistor T1, the selection transistor T2, the storage capacitor C1, and the OLED element E1 shown in FIG. 2, respectively.

[0028] The insulating substrate 101 is a flexible or inflexible substrate made of resin or glass. The low-temperature polysilicon TFT 141 includes a low-temperature polysilicon portion 102. The low-temperature polysilicon portion 102 is included in a low-temperature polysilicon layer and is an island-shaped low-temperature polysilicon film or a part of a larger low-temperature polysilicon film. The low-temperature polysilicon portion 102 includes source / drain regions 104, 105 and a channel region 103 between the source / drain regions 104, 105 in the in-plane direction.

[0029] The source / drain regions 104, 105 are formed of low-temperature polysilicon whose resistance has been reduced by high-concentration impurity implantation, and are connected to source / drain electrode portions 109, 110. The channel region 103 is formed of low-temperature polysilicon whose resistance has not been reduced (high-resistance low-temperature polysilicon).

[0030] The low-temperature polysilicon portion 102 is included in a low-temperature polysilicon layer. The low-temperature polysilicon layer includes low-temperature polysilicon portions of low-temperature polysilicon TFTs of a plurality of pixel circuits. The low-temperature polysilicon layer is formed (directly) on an insulating substrate 101. In the example of Fig. 3, the low-temperature polysilicon portion 102 contacts the insulating substrate 101, but there may be another insulating layer (e.g., a silicon nitride layer) between them.

[0031] The low-temperature polysilicon TFT 141 has a top gate structure. The low-temperature polysilicon TFT may include a bottom gate in addition to the top gate. The low-temperature polysilicon TFT 141 further includes a gate electrode portion 107 and a gate insulator portion present between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulator portion is a portion of the insulator layer 106 between the gate electrode portion 107 and the channel region 103. The insulator layer 106 includes a gate insulator portion of another low-temperature polysilicon TFT. The channel region 103, the gate insulator portion, and the gate electrode portion 107 are stacked in this order from below (from the substrate side), and the gate insulator portion is in contact with the channel region 103 and the gate electrode portion 107.

[0032] The gate electrode portion 107 is made of a conductor and is included in the conductor layer. The gate electrode portion 107 is made of, for example, a metal. Any metal material may be used, and examples of the metal material include Mo, W, Nb, and Al. Insulator layer 106 is made of silicon oxide in this example.

[0033] The interlayer insulating film 108 is formed so as to cover the low-temperature polysilicon portion 102, the gate insulator portion, and the gate electrode portion 107. The interlayer insulating film 108 is, for example, a silicon nitride film. The source / drain electrode portions 109, 110 are formed on the interlayer insulating film 108 and are in contact with the source / drain regions 104, 105 via contact holes in the interlayer insulating film 108 and the insulator layer 106. The source / drain electrode portions 109, 110 can be made of, for example, Al or Ti.

[0034] The storage capacitor 143 includes a lower electrode portion 111, an upper electrode portion 120 facing the lower electrode portion 111, and an insulator portion between the lower electrode portion 111 and the upper electrode portion 120. The lower electrode portion 111 is continuous with the source / drain electrode portion 110 on the interlayer insulating film 108. The lower electrode portion 111 is included in the same conductor layer as the source / drain electrode portions 109, 110.

[0035] An interlayer insulating film 112 is laminated on the interlayer insulating film 108. The interlayer insulating film 112 is, for example, a silicon oxide film. The interlayer insulating film 112 is formed so as to cover the lower electrode portion 111, the source / drain electrode portions 109, 110, and the interlayer insulating film 108. In the region between the lower electrode portion 111 and the upper electrode portion 120, the interlayer insulating film 112 constitutes an insulator portion.

[0036] The oxide semiconductor TFT 142 includes an oxide semiconductor section 113. The oxide semiconductor section 113 is, for example, one oxide semiconductor active film or a part thereof, and includes source / drain regions 115, 116 and a channel region 114 between the source / drain regions 115, 116 in the in-plane direction.

[0037] The source / drain regions 115, 116 are formed of low-resistance IGZO, and are connected to source / drain electrode portions 122, 123. The channel region 114 is formed of IGZO that has not been low-resistance (high-resistance IGZO).

[0038] The oxide semiconductor portion 113 is included in an oxide semiconductor layer. The oxide semiconductor layer includes the oxide semiconductor portions of a plurality of oxide semiconductor TFTs. The oxide semiconductor layer is formed on an interlayer insulating film 112.

[0039] The oxide semiconductor TFT 142 has a top gate structure. The oxide semiconductor TFT 142 may include a bottom gate in addition to the top gate. The oxide semiconductor TFT 142 further includes a gate electrode portion 119 and a gate insulator portion that is present between the gate electrode portion 119 and the channel region 114 in the stacking direction. The gate insulator portion is a portion of the insulator layer 117 between the gate electrode portion 119 and the channel region 114.

[0040] The channel region 114, the gate insulator portion, and the gate electrode portion 119 are laminated in this order from below (from the substrate side), and the gate insulator portion is in contact with the channel region 114 and the gate electrode portion 119. The gate electrode portion 119 is formed of a conductor and is included in the conductor layer. The gate electrode portion 119 is formed of, for example, a metal. Any metal material may be used, and examples of the metal material that may be used include Mo, W, Nb, and Al. The insulator layer 117 may be made of, for example, silicon oxide.

[0041] FIG. 3 shows one low-temperature polysilicon TFT and one oxide semiconductor TFT as an example, but the other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit also have the same structure.

[0042] The interlayer insulating film 121 is formed to cover the oxide semiconductor portion 113, the gate insulator portion, and the gate electrode portion 119 of the oxide semiconductor TFT 142, and the upper electrode portion 120 of the storage capacitor 143. The interlayer insulating film 121 covers a part of the interlayer insulating film 112. The interlayer insulating film 121 is, for example, a silicon oxide film.

[0043] Source / drain electrode units 122, 123 of the oxide semiconductor TFT 142 are formed on the interlayer insulating film 121. The source / drain electrode units 122, 123 are connected to source / drain regions 115, 116 of the oxide semiconductor TFT 142 via contact holes formed in the interlayer insulating film 121 and the insulator layer 117.

[0044] Furthermore, the connection portion 129 continuous with the source / drain electrode portion 123 is connected to the upper electrode portion 120 of the storage capacitor 143 via contact holes formed in the interlayer insulating film 121 and the insulator layer 117, and is connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 via contact holes formed in the interlayer insulating films 121, 112, 108 and the insulator layer 117.

[0045] The connection portion 129 interconnects the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107. The source / drain electrode portions 122, 123 and the connection portion 129 are included in a conductor layer. Any material may be used for the conductor layer, and for example, Al or Ti may be used.

[0046] An insulating planarization film 124 is laminated so as to cover the exposed portions of the conductor layer and the interlayer insulating film 121. The planarization film 124 can be made of, for example, an organic material. An anode electrode section 125 is formed on the planarization film 124. The anode electrode section 125 is connected to the source / drain electrode section 109 of the low-temperature polysilicon TFT 141 via contact holes in the planarization film 124, the interlayer insulating films 121 and 112, and the insulator layer 117.

[0047] The anode electrode section 125 includes three layers: a transparent film such as ITO or IZO, a reflective film of a metal such as Ag, Mg, Al, or Pt, or an alloy containing these metals, and the transparent film. Note that the three-layer structure of the anode electrode section 125 is just an example, and it may be a two-layer structure.

[0048] An insulating pixel definition layer 126 is formed on the anode electrode section 125 to separate the OLED elements 144. The pixel definition layer 126 can be made of, for example, an organic material. An organic light-emitting film 127 is formed on the anode electrode section 125. The organic light-emitting film 127 is composed of, from the bottom up, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The layered structure of the organic light-emitting film 127 is determined by design.

[0049] Furthermore, a cathode electrode unit 128 is formed on the organic light-emitting film 127. The cathode electrode unit 128 of one OLED element 144 is a part of a continuous conductor film. The cathode electrode unit 128 transmits a part of visible light from the organic light-emitting film 127. The laminated film of the anode electrode unit 125, the organic light-emitting film 127, and the cathode electrode unit 128 formed in the opening of the pixel definition layer 126 constitutes the OLED element 144.

[0050] Next, a CMOS (Complementary Metal-Oxide-Semiconductor) circuit configuration included in the driver circuits 31 and 32 on the TFT substrate will be described. Fig. 4 shows an example of a CMOS circuit. The CMOS circuit includes a p-channel low-temperature polysilicon TFT 201 and an n-channel oxide semiconductor TFT 202. The source / drain of the low-temperature polysilicon TFT 201 is connected to the source / drain of the n-channel oxide semiconductor TFT 202. The gates of the low-temperature polysilicon TFT 201 and the oxide semiconductor TFT 202 are connected, and the same signal is input to them.

[0051] 5 is a schematic diagram showing an example of the cross-sectional structure of the CMOS circuit shown in FIG. 4. The differences from the cross-sectional structure shown in FIG. 3 will be mainly described. In the example shown in FIG. 5, the retention capacitance of the example shown in FIG. 143 In addition, the source / drain electrode section 210 of the low-temperature polysilicon TFT 201 and the source / drain electrode section 223 of the oxide semiconductor TFT 202 are connected, and further, the gate electrode section 207 and the gate electrode section 219 are connected.

[0052] In one example, the low-temperature polysilicon TFT 201 in Fig. 5 has a similar structure to the low-temperature polysilicon TFT 141 shown in Fig. 3, although their sizes may differ. The low-temperature polysilicon TFT 201 includes a low-temperature polysilicon portion 208, a gate insulator portion, and a gate electrode portion 207. The gate insulator portion is the portion of the insulator layer 106 between the gate electrode portion 207 and the low-temperature polysilicon portion 208.

[0053] The low-temperature polysilicon portion 208 includes a channel region 203 and source / drain regions 204, 205. Source / drain electrode portions 209, 210 are connected to the source / drain regions 204, 205 via contact holes in the interlayer insulating film .

[0054] The low-temperature polysilicon portion 208, the gate insulator portion, the gate electrode portion 207, and the source / drain electrode portions 209 and 210 correspond to the low-temperature polysilicon portion 102, the gate insulator portion, the gate electrode portion 107, and the source / drain electrode portions 109 and 110 shown in Fig. 3, respectively. Corresponding components are included in the same layer.

[0055] In one example, the oxide semiconductor TFT 202 in Fig. 5 has a similar configuration to the oxide semiconductor TFT 142 shown in Fig. 3. The sizes of these may be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213, a gate insulator portion, and a gate electrode portion 219. The gate insulator portion is a portion between the gate electrode portion 219 and the oxide semiconductor portion 213 in the insulator layer 117.

[0056] The oxide semiconductor portion 213 includes a channel region 214 and source / drain regions 215, 216. The oxide semiconductor portion 213, the gate insulator portion, and the gate electrode portion 219 correspond to the oxide semiconductor portion 113, the gate insulator portion, and the gate electrode portion 119 shown in Fig. 3, respectively. Corresponding components are included in the same layer.

[0057] The connection portion 229 is continuous with the source / drain electrode portion 223 of the oxide semiconductor TFT 202, and is connected to the source / drain electrode portion 210 of the low-temperature polysilicon TFT 201 through a contact hole penetrating the interlayer insulating films 112, 121 and the insulator layer 117. The connection portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 through a contact hole penetrating the interlayer insulating film 121 and the planarizing film 124. The connection portion 230 is further connected to the gate electrode portion 207 of the low-temperature polysilicon TFT 201 through a contact hole penetrating the interlayer insulating films 108, 112, 121, the planarizing film 124 and the insulator layer 117.

[0058] In the following, examples of methods for fabricating an oxide semiconductor are described. Figures 6A to 6D show one method, where impurities are implanted into the oxide semiconductor through the gate insulator. Figures 7A to 7D show another method, where the gate insulator is etched away and impurities are implanted into the oxide semiconductor.

[0059] 6A, the manufacturing method is to form an interlayer insulating film 112 by using, for example, CVD (Chemical Vapor Deposition), and then form an oxide semiconductor portion 113. The oxide semiconductor portion 113 is formed, for example, by forming an oxide semiconductor layer by a sputtering method or the like, and patterning the oxide semiconductor layer by photolithography. Next, an insulator layer 117 is formed by using, for example, CVD. The manufacturing method is to form a metal film by using a sputtering method or the like, and after patterning a mask by photolithography, the metal film is etched to form a gate electrode portion 119.

[0060] 6B, in the manufacturing method, an impurity (e.g., boron) is implanted into the oxide semiconductor portion 113 through an insulator layer 117. By the impurity ion implantation, low-resistance source / drain regions 115, 116 are formed in the oxide semiconductor portion 113. The region therebetween is a channel region 114.

[0061] The acceleration voltage of the impurity ions is, for example, 20 keV to 80 keV. As described later, in one embodiment of this specification, the concentration profile of the impurity has a peak at a position outside the oxide semiconductor portion 113.

[0062] 6C, the manufacturing method forms an interlayer insulating film 121 so as to cover the gate electrode portion 119 and the insulator layer 117. The interlayer insulating film 121 can be formed by, for example, CVD. Referring to FIG. 6D, the manufacturing method forms contact holes in the interlayer insulating film 121 and the insulator layer 117 by etching after patterning a mask by photolithography. Furthermore, the manufacturing method forms a metal film by a sputtering method or the like, and after patterning a mask by photolithography, et cetera, the metal film is etched to form source / drain electrode portions 122, 123.

[0063] 7A, the manufacturing method is to form an interlayer insulating film 162 by using, for example, CVD, and then form an oxide semiconductor portion 163. The oxide semiconductor portion 163 is formed, for example, by forming an oxide semiconductor layer by a sputtering method or the like, and patterning the oxide semiconductor layer by photolithography. Next, an insulator layer 176 is formed by using, for example, CVD. The manufacturing method is to form a metal film by using a sputtering method or the like, and after patterning a mask by photolithography, the metal film is etched to form a gate electrode portion 169.

[0064] 7B, in the manufacturing method, the insulator layer 176 is etched using the gate electrode portion 169 as a mask to form the gate insulator portion 177. As a result, the insulator on a region of the oxide semiconductor portion 163 that is not covered by the gate electrode portion 169 is removed and exposed.

[0065] Thereafter, impurities (for example, boron) are implanted into the oxide semiconductor portion 163. By the impurity ion implantation, low resistance regions 165 and 166 are formed in the oxide semiconductor portion 163. These are the source / drain regions of the oxide semiconductor TFT 192. The region therebetween is the channel region 164.

[0066] The acceleration voltage of the impurity ions is, for example, 10 keV to 30 keV. As described later, in one embodiment of this specification, the concentration profile of the impurity is 6 It has a peak at a position outside of 3.

[0067] 7C, the manufacturing method forms an interlayer insulating film 181 so as to cover the gate electrode portion 169 and the insulator layer 178. The interlayer insulating film 181 can be formed by, for example, CVD. Referring to FIG. 7D, the manufacturing method forms contact holes in the interlayer insulating film 181 and the insulator layer 178 by etching after patterning a mask by photolithography. Furthermore, the manufacturing method forms a metal film by a sputtering method or the like, and after patterning a mask by photolithography, et cetera, the metal film is etched to form source / drain electrode portions 182, 183.

[0068] [Impurity concentration profile] The impurity concentration profile of the oxide semiconductor TFT is described below. In one embodiment of the present specification, a low resistance region is formed in the oxide semiconductor part of the oxide semiconductor TFT by impurity ion implantation. The low resistance impurity elements used for low resistance include, for example, B, He, Ne, Ar, H, P, etc.

[0069] 8 shows the implantation of impurity ions into an oxide semiconductor TFT in a comparative example. An interlayer insulating film 311 and a lower insulator layer 312 are laminated on a substrate (not shown). The oxide semiconductor TFT includes an oxide semiconductor section 302 on the lower insulator layer 312. The oxide semiconductor TFT has a top-gate structure and includes a gate electrode section 301 on the oxide semiconductor section 302. An upper insulator layer 313 is present between the oxide semiconductor section 302 and the gate electrode section 301. A portion of the upper insulator layer 313 between the gate electrode section 301 and the oxide semiconductor section is a gate insulator section.

[0070] 8, impurity ions are implanted using the gate electrode portion 301 as a mask to form low-resistance regions 304 and 305 in the oxide semiconductor portion 302. The region sandwiched between the low-resistance regions 304 and 305 in the in-plane direction is a high-resistance channel region 303.

[0071] 8 is a schematic diagram showing a concentration profile of impurity ions implanted by impurity ion implantation in the stacking direction. In the example of FIG. 8, the impurity concentration profile shows one peak 321, and the peak 321 is located in the oxide semiconductor portion 302.

[0072] The resistance value of the n-type low resistance regions 304, 305 is determined by the concentration of oxygen defects formed in the oxide semiconductor portion 302 due to damage caused by impurity ion implantation. As shown in Fig. 8, in a configuration in which an impurity concentration peak 321 exists in the oxide semiconductor portion 302, ΔL becomes large, making it difficult to shorten the channel of the oxide semiconductor TFT. ΔL is the distance from the end of the gate electrode portion 301 to the low resistance region that overlaps with the gate electrode portion 301 in a plan view. When ΔL is 0, the channel length L is equal to the length of the gate electrode portion 301.

[0073] In a low-temperature polysilicon TFT, the concentration of impurities remaining in the low-temperature polysilicon portion determines the resistance value of the p-type low-resistance low-temperature polysilicon portion. Therefore, the impurity concentration profile is controlled so that the peak position of the impurity concentration is present in the low-temperature polysilicon portion. The impurities are, for example, B (boron) or P (phosphorus). On the other hand, as described above, impurity ion implantation into an oxide semiconductor forms a resistive region by damaging the oxide semiconductor layer. Therefore, the peak position of the impurity concentration has a higher degree of freedom than impurity ion implantation into low-temperature polysilicon.

[0074] In one embodiment of the present specification, the impurity concentration profile is controlled so that the peak position of the impurity concentration is located outside the oxide semiconductor layer. For example, the impurity concentration profile is controlled so that the impurity concentration peak is located at the upper part, the lower part, or the upper part and the lower part of the oxide semiconductor layer. This makes it possible to reduce ΔL in the oxide semiconductor portion.

[0075] 9A shows an example of an impurity concentration profile of an oxide semiconductor TFT and its vicinity in one embodiment of this specification. FIG. 9A shows the circuit configuration example shown in FIG. 3. A part of the configuration example shown in FIG. 3 is omitted. The following description will be made based on the circuit configuration example described with reference to FIG. 5. CMOS It is also applicable to circuits.

[0076] The impurity concentration profile shown in FIG. 9A shows only one peak 331. The peak impurity concentration is, for example, 1E18 or more and 1E21 / cc or less. The impurity concentration peak 331 is located in the interlayer insulating film 112 below the oxide semiconductor portion 113. The interlayer insulating film 112 is an example of a lower insulator layer. The position of the impurity concentration peak 331 can be adjusted by controlling the acceleration voltage of the impurity ions. Also, the value of the impurity concentration can be adjusted by controlling the injection amount. In one example, the impurity concentration peak 331 and the oxide semiconductor portion 113 in the stacking direction are 113 The distance between the center of the oxide semiconductor portion 113 and the thickness of the oxide semiconductor portion 113 is equal to or greater than the thickness of the oxide semiconductor portion 113.

[0077] 9A includes an oxide semiconductor TFT 142 and a lower low-temperature polysilicon TFT 141. The impurity concentration profile of the low-temperature polysilicon TFT 141 is controlled so that the peak position of the impurity concentration is in the low-temperature polysilicon portion. The impurity concentration profile can be adjusted by controlling the acceleration voltage of the impurity ions.

[0078] In the low-temperature polysilicon TFT 141, more preferable characteristics can be obtained by terminating the dangling bonds of the low-temperature polysilicon with hydrogen. For this reason, a specific insulator layer, for example, the interlayer insulating film 108, may be formed of silicon nitride containing hydrogen. Also, when a circuit is formed on a flexible substrate made of polyimide, a silicon nitride layer is formed to prevent the propagation of moisture.

[0079] 9A shows an impurity concentration peak in the interlayer insulating film 112 below the oxide semiconductor portion 113. By forming the interlayer insulating film 112 from an insulator other than silicon nitride, such as silicon oxide, it is possible to suppress the diffusion of hydrogen from the silicon nitride layer below to the oxide semiconductor portion. In particular, by using B (boron) as the impurity, a greater suppression effect can be obtained. Furthermore, an interlayer insulating film 112 with a high concentration of B can exhibit high impact resistance.

[0080] 9B shows an example of a measurement of a boron concentration profile in an IGZO-TFT and its vicinity in one embodiment of this specification. FIG. 9B shows a boron concentration profile 702 and a signal intensity profile 701 caused by indium. The peak of the signal intensity caused by indium indicates the location in the depth direction where the IGZO film exists. Note that point 703 in the boron concentration profile 702 is a signal peak caused by noise, not a concentration peak.

[0081] 9B shows a measurement example of an embodiment in which the peak of the boron concentration is located below the IGZO film. In this way, when the peak of the boron concentration is located below the IGZO film, the diffusion of hydrogen from the film (e.g., silicon nitride layer) below the peak of the boron concentration to the IGZO film can be suppressed, and the characteristics of the short-channel TFT can be stabilized.

[0082] 9C shows the measurement results of an oxide semiconductor TFT according to an embodiment of the present specification. The horizontal axis indicates the gate voltage, and the vertical axis indicates the drain current. FIG. 9C shows the measurement results of a short-channel TFT with a gate length L=2 um. It has been shown that the oxide semiconductor TFT according to this embodiment operates correctly even in a short-channel TFT.

[0083] 10A shows an example of an impurity concentration profile of an oxide semiconductor TFT and its vicinity in one embodiment of this specification. FIG. 10A shows the circuit configuration example shown in FIG. 3. A part of the configuration example shown in FIG. 3 is omitted. The following description will be made based on the circuit configuration example described with reference to FIG. CMOS It is also applicable to circuits.

[0084] The impurity concentration profile shown in FIG. 10A shows only one peak 332. The peak impurity concentration is, for example, 1E18 or more and 1E21 / cc or less. The impurity concentration peak 332 is located in the insulator layer 117 above the oxide semiconductor portion 113. The insulator layer 117 is an example of an upper insulator layer. The position of the impurity concentration peak 332 can be adjusted by controlling the acceleration voltage of the impurity ions. Also, the value of the impurity concentration can be adjusted by controlling the injection amount. In one example, the impurity concentration peak 332 and the oxide semiconductor portion 113 in the stacking direction are 113 The distance between the center of the oxide semiconductor portion 113 and the thickness of the oxide semiconductor portion 113 is equal to or greater than the thickness of the oxide semiconductor portion 113.

[0085] 10A shows an impurity concentration peak in the insulator layer 117 above the oxide semiconductor portion 113. Therefore, the influence of the etching solution on the oxide semiconductor portion in the manufacturing process can be reduced. In particular, by using B (boron) as the impurity, a greater reduction effect can be obtained.

[0086] 9A and 10A each show only one impurity concentration peak. The impurity concentration of other examples may show multiple peaks (maximum values). All the peaks are located outside the oxide semiconductor portion.

[0087] 10B shows an example of an impurity concentration profile showing two peaks. The impurity concentration profile 333 shows two peaks, one of which is located in the interlayer insulating film 112 and the other in the insulator layer 117. This makes it possible to suppress undesirable effects from the lower and upper layers on the oxide semiconductor. The impurity concentration profile showing these two peaks can be formed by implanting impurity ions twice at different acceleration voltages.

[0088] In the examples shown in Figures 3, 5, 9A, 10A and 10B, the gate insulator of the TFT is part of the insulator layer covering the entire display area. In another example, the gate insulator may be formed by etching after the gate insulator layer is deposited. The insulating material of the gate insulator may be different from the insulating material of the upper insulator layer around it, e.g., the interlayer insulating film. The low resistance region is in direct contact with the upper insulator layer.

[0089] [Carrier concentration profile] Next, the carrier concentration profile in the in-plane direction of the oxide semiconductor layer will be described. The in-plane direction is a direction parallel to the main surface of the substrate and perpendicular to the stacking direction. First, the relationship between the carrier concentration and the dC / dV signal obtained by analyzing an n-type semiconductor with SCM (Scanning Capacitance Microscopy) will be described. Here, C is the local MOS capacitance formed between the scanning conductive probe and the oxide semiconductor, and V is the voltage applied to the conductive probe.

[0090] FIG. 11 shows a schematic diagram of the relationship between the dC / dV signal and the carrier concentration when an n-type semiconductor is subjected to SCM analysis. The horizontal axis indicates the carrier concentration, and the vertical axis indicates the dC / dV signal value. The dC / dV signal value is higher for high carrier concentrations (N + ) and low carrier concentration (N - ) approaches 0. The dC / dV signal value is negative for carrier concentrations between high and low carrier concentrations.

[0091] The dC / dV signal value is -) to high carrier concentration (N + ), it gradually decreases toward n-type semiconductor, reaches a minimum at a specific carrier concentration, and then gradually increases. The carrier concentration at which it reaches a minimum depends on the material of the n-type semiconductor.

[0092] 12 shows a change in dC / dV signal value in an oxide semiconductor layer in one embodiment of the present specification. IGZO is used as an example of the oxide semiconductor. FIG. 12 shows a change in dC / dV signal value near one end of a top gate electrode of an oxide semiconductor TFT having a top gate structure.

[0093] The oxide semiconductor TFT includes an IGZO layer 402 laminated on a lower insulator layer 401 , a gate insulator layer 403 laminated on the IGZO layer 402 , and a gate electrode section 404 laminated on the gate insulator layer 403 .

[0094] The graph of FIG. 12 shows a top gate electrode signal 411 and a dC / dV signal value 413. As described above, the dC / dV signal value represents the carrier concentration. The horizontal axis represents the length in the channel direction, and the vertical axis represents the dC / dV signal value. The dC / dV signal value 413 includes a transition region 415 and a high carrier concentration region 416 on the outside of the top gate electrode portion 404. The dC / dV signal value 413 gradually increases from the end 405 of the top gate electrode toward the inside, approaching 0.

[0095] The high carrier concentration region 416 has a carrier concentration in the range of, for example, 1E19 / cc or more and 1E21 / cc or less. The transition region 415 exists between the high carrier concentration region 416 and an edge of the top gate electrode portion 404. The length of the transition region 415 is, for example, 0.2 microns or more and 2.5 microns or less.

[0096] The transition region is a region where the carrier concentration distribution in the IGZO changes from low to high in the direction from the end 405 of the top gate electrode toward the source / drain electrodes. As shown in Fig. 12, the minimum value of the dC / dV signal value is outside the top gate electrode portion 404 in a plan view, and further exists within the transition region 415. The carrier concentration profile showing the transition region 415 from the end 405 of the top gate electrode can exhibit more suitable characteristics of the oxide semiconductor TFT.

[0097] 13 shows a change in dC / dV signal value in an oxide semiconductor layer in one embodiment of the present specification. IGZO is used as an example of an oxide semiconductor. FIG. 13 shows a change in dC / dV signal value near one end of a top gate electrode of an oxide semiconductor TFT having a top gate structure. The structure of the oxide semiconductor TFT is the same as the example shown in FIG.

[0098] 13 shows a graph of a top gate electrode signal 451 and a dC / dV signal value 453. The horizontal axis indicates the length in the channel direction, and the vertical axis indicates the dC / dV signal value. The dC / dV signal value 453 includes a transition region 455 and a high carrier concentration region 456 outside the top gate electrode portion 404. The dC / dV signal value 453 shows a substantially constant value from the end 405 of the top gate electrode toward the inside.

[0099] The high carrier concentration region 456 has a carrier concentration in the range of, for example, 1E19 / cc or more and 1E21 / cc or less. The transition region 455 exists between the high carrier concentration region 456 and an end of the top gate electrode portion 404. The length of the transition region 455 is, for example, 0.2 microns or more and 2.5 microns or less.

[0100] The transition region is a region where the carrier concentration distribution in the IGZO in the direction from the end 405 of the top gate electrode toward the source-drain electrode changes from low concentration to high concentration. As shown in FIG. 13, the minimum value of the dC / dV signal value is outside the top gate electrode portion 404 in a plan view, and further exists in the transition region 455. The carrier concentration profile showing the transition region 455 from the end 405 of the top gate electrode can show more suitable characteristics of the oxide semiconductor TFT. Note that only one of the carrier concentration profile described with reference to FIGS. 12 and 13 and the impurity concentration profile described with reference to FIGS. 9A and 10A may be established.

[0101] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0102] 1 OLED display device, 10 TFT substrate, 31 scan driver, 32 emission driver, 101 insulating substrate, 102 low-temperature polysilicon portion, 106 insulator layer, 107 gate electrode portion, 111 lower electrode portion, 113 oxide semiconductor portion, 114 channel region, 115, 116 source / drain region, 117 insulator layer, 119 gate electrode portion, 120 upper electrode portion, 122, 123 source / drain electrode portion, 134 OLED element, 141 low-temperature polysilicon TFT, 142 oxide semiconductor TFT, 143 storage capacitor, 144 OLED element

Claims

1. A thin film transistor substrate, An insulating substrate; a conductor layer including a top gate electrode portion of an oxide semiconductor thin film transistor; an oxide semiconductor layer including a channel region of the oxide semiconductor thin film transistor under the top gate electrode portion; an upper insulator layer between the conductor layer and the oxide semiconductor layer; Including, the oxide semiconductor layer includes a low-resistance region having a lower resistance than the channel region, the low resistance regions sandwich the channel region in an in-plane direction of the substrate, and contain low resistance impurities that cause the low resistance regions to become low resistance; The concentration profile of the low resistance impurity in the stacking direction shows one or more peaks, the one or more peaks are present outside the oxide semiconductor layer; Thin film transistor substrate.

2. 2. The thin film transistor substrate according to claim 1, a peak of the one or more peaks is present in the upper insulator layer; Thin film transistor substrate.

3. 2. The thin film transistor substrate according to claim 1, Further comprising a lower insulator layer below the oxide semiconductor layer, a peak of the one or more peaks is present in the lower insulator layer; Thin film transistor substrate.

4. 4. The thin film transistor substrate according to claim 3, the one or more peaks consist of a first peak and a second peak, the one peak is the first peak, the second peak is in the upper insulator layer; Thin film transistor substrate.

5. 2. The thin film transistor substrate according to claim 1, a distance between a position of a peak closest to the oxide semiconductor layer among the one or more peaks and a center of the oxide semiconductor layer in the stacking direction is equal to or greater than a thickness of the oxide semiconductor layer. Thin film transistor substrate.

6. 2. The thin film transistor substrate according to claim 1, The low resistance impurity is boron. Thin film transistor substrate.

7. 4. The thin film transistor substrate according to claim 3, a polysilicon layer located below the lower insulating layer and including a channel region of a polysilicon thin film transistor; a hydrogen-containing silicon nitride layer between the polysilicon layer and the lower insulator layer; Further comprising: Thin film transistor substrate.

8. 2. The thin film transistor substrate according to claim 1, the low resistance region includes a transition region on an outer side from an end of the top gate electrode portion, In the transition region, the carrier concentration increases with distance from the channel region. Thin film transistor substrate.

9. 9. The thin film transistor substrate according to claim 8, The dC / dV signal value of the SCM analysis of the transition region shows a minimum negative value. Thin film transistor substrate.

10. 9. The thin film transistor substrate according to claim 8, a lower insulator layer below the oxide semiconductor layer; a polysilicon layer located below the lower insulating layer and including a channel region of a polysilicon thin film transistor; Thin film transistor substrate.

Images