Semiconductor Device

Abstract

To provide a semiconductor device capable of incorporating a rectifying element in a gate driver IC and hardly causes a trouble such as increase of a leakage current, degrading of a withstand voltage, and destruction of an element.SOLUTION: A semiconductor device 100 includes: a semiconductor substrate 110 having a p-type substrate 111 and an n-type first semiconductor layer 112; a first electrode 120; a second electrode 130; an element separation film 140; an insulating film 150; and a third electrode 160 arranged on the insulating film 150. The first electrode 120 is electrically connected to a first circuit C1 connected with a first power source Vin. The second electrode 130 is electrically connected to a second circuit C2 connected with a second power source Vcc. The semiconductor substrate 110 is formed in a region facing the third electrode 160 while having a depth reaching the substrate 111 through the insulating film 150, and further includes a p-type back gate region 113 having an impurity concentration in a range of 1x1010 cm-3 to 1x1015 cm-3.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is known a power conversion circuit (e.g., an inverter) that includes a high-side switch connected to a high-voltage power supply (DC input power supply Vin) and a low-side switch connected to the high-side switch. In such a power conversion circuit (hereinafter referred to as a conventional power conversion circuit), when an n-channel transistor with a small on-resistance is used as the high-side switch, a gate voltage exceeding a threshold voltage Vgs (Vth) must be applied between the gate and source of the high-side switch in order to turn on the high-side switch. However, since the source voltage rises to the voltage of the DC input power supply Vin, a gate voltage higher than the voltage of the DC input power supply Vin must be applied. It is generally known that a bootstrap circuit is provided to generate such a high gate voltage (for example, see Patent Document 1).

[0003] FIG. 8 is a circuit diagram showing a conventional power conversion circuit 9. The conventional power conversion circuit 9 includes a high-side switch Q1, a low-side switch Q2, a gate driver IC10 (IC: Integrated Circuit), and a bootstrap circuit 20, as shown in FIG. The bootstrap circuit 20 has a capacitance 22 (bootstrap capacitance) and a bootstrap diode 24 as a rectifying element. One electrode of the capacitance 22 is connected to a connection point N between the high-side switch Q1 and the low-side switch Q2, and the other electrode is connected to the high-side drive circuit 11 of the gate driver IC10. The bootstrap diode 24 has an anode electrode connected to a drive power supply Vcc, which is a low-voltage source, and a cathode electrode connected to the capacitance 22 and the high-side drive circuit 11. The high-side switch Q1 and the low-side switch Q2 are arranged in a high-voltage region, and the low-side drive circuit 12 of the gate driver IC10 is arranged in a relatively low-voltage region. Generally, the capacitance 22 and the bootstrap diode 24 of the bootstrap circuit 20 are mounted as external components of the gate driver IC10.

[0004] In the conventional bootstrap circuit 20, when the high-side switch Q1 is off and the low-side switch Q2 is on, the capacitor 22 is charged from the drive power supply Vcc via the bootstrap diode 24. When the low-side switch Q2 is turned off, the voltage Vs (the source voltage of the high-side switch Q1) at the connection point N between the high-side switch Q1 and the low-side switch Q2 rises to the output voltage of the DC input power supply Vin, and a voltage obtained by superimposing the voltage of the capacitor 22 on the voltage Vs at the connection point N is applied to the high-side drive circuit 11. This makes it possible to apply a gate voltage higher than the voltage of the DC input power supply Vin to the high-side switch Q1, and to turn on the high-side switch Q1. In addition, the bootstrap diode 24 as a rectifying element can pass a current from the driving power supply Vcc to the capacitance 22 (forward bias) when the high-side switch Q1 is off and the low-side switch Q2 is on, and when the voltage of the capacitance 22 is superimposed on the high-side driving circuit 11, it becomes reverse biased and can prevent a current from flowing back from the capacitance 22 side to the driving power supply Vcc side. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 9-65571 Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, with the demand for miniaturization of electrical equipment, there is a demand to incorporate the rectifier element, which has been mounted as an external component, into the gate driver IC 10. In this case, it is desirable to realize miniaturization by forming the rectifier element integrally with the semiconductor substrate. Therefore, it is considered to form the bootstrap diode 24 on the semiconductor substrate by using a semiconductor device having the following configuration (hereinafter referred to as the semiconductor device 900 according to the background art).

[0007] FIG. 9 is a cross-sectional view shown for explaining a semiconductor device 900 according to the background art. As shown in FIG. 9, a semiconductor device 900 according to the related art is a p-type - 911, n-type (n - a first semiconductor layer 912 of n-type (n + A first contact region CR1 of p-type (p + the first semiconductor layer 912 is an n-type anode region 919; a first electrode 920 disposed above the semiconductor body 910 and in contact with the semiconductor body 910; a second electrode 930 disposed above the semiconductor body 910 at a position spaced apart from the first electrode 920 and in contact with the semiconductor body 910; an element isolation film 940 formed in a region between the first electrode 920 and the second electrode 930 on the surface of the semiconductor body 910; an insulating film 950 disposed between the second electrode 930 and the element isolation film 940 on the surface of the semiconductor body 910; and a third electrode 960 disposed on the insulating film 950. The bootstrap diode 24 is composed of the p-type anode region 919 and the n-type first semiconductor layer 912.

[0008] However, in the semiconductor device 900 according to the background art, a parasitic transistor constituted by a p-type anode region 919, an n-type first semiconductor layer 912, and a p-type substrate 911 turns on, causing a parasitic current to flow between the second electrode 930 and the substrate 911, which may result in problems such as an increase in leakage current, a decrease in breakdown voltage, and element destruction, and it is difficult to form a bootstrap diode as a rectifying element on a semiconductor substrate.

[0009] The present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device in which a rectifying element can be formed on a semiconductor substrate without causing problems such as an increase in leakage current, a decrease in withstand voltage, and element destruction, and in which the rectifying element can be formed on a semiconductor substrate and the rectifying element can be incorporated into a gate driver IC. [Means for solving the problem]

[0010] A semiconductor device according to the present invention includes a semiconductor substrate having a first conductive type substrate and a first semiconductor layer of a second conductive type formed on the substrate, a first electrode disposed above the semiconductor substrate and in contact with the semiconductor substrate, a second electrode disposed above the semiconductor substrate at a position spaced apart from the first electrode and in contact with the semiconductor substrate, an element isolation film formed in a region between the first electrode and the second electrode on a surface of the semiconductor substrate, an insulating film disposed between the second electrode and the element isolation film on the surface of the semiconductor substrate, and a third electrode disposed on the insulating film, wherein the first electrode is electrically connected to a first circuit connected to a first power supply, and the second electrode is electrically connected to a second circuit connected to a second power supply, and the semiconductor substrate is formed at least in a region facing the third electrode via the insulating film to a depth reaching the substrate, and an impurity concentration is 1×10 10 cm -3 ~1×10 15 cm -3 The semiconductor device further comprises a back gate region of the first conductivity type located within the range of .

[0011] According to the semiconductor device of the present invention, the semiconductor substrate has a first conductive type back gate region formed at a depth reaching the substrate in a region facing the third electrode through at least the insulating film, so that the second electrode, the back gate region, the first semiconductor layer, the insulating film, and the third electrode constitute a field effect transistor. Therefore, when the voltage Vcc of the second electrode is higher than the voltage Vb of the first electrode, the third electrode is turned on to allow a current to flow from the second electrode to the first electrode to charge the capacitance, and when the voltage Vcc of the second electrode is lower than the voltage Vb of the first electrode, the third electrode is turned off to cut off the current. Therefore, the function of a rectifying element can be realized similarly to a conventional bootstrap diode.

[0012] However, when a bootstrap diode is used as a rectifying element in a bootstrap circuit, a voltage drop equivalent to the forward voltage, which is a characteristic of a diode, occurs, causing a drop in the voltage applied to the capacitance from the driving power supply Vcc, making it difficult to charge the capacitance to a voltage close to the driving power supply Vcc. In contrast, according to the semiconductor device of the present invention, a field effect transistor consisting of a second electrode, a back gate region, a first semiconductor layer, an insulating film, and a third electrode is used as a rectifying element, so that a voltage drop equivalent to the forward voltage does not occur as in the case of using a bootstrap diode, and the capacitance can be charged to a voltage close to the driving power supply Vcc (see FIG. 5).

[0013] Incidentally, in order to turn on a field effect transistor, a voltage higher than that of the source electrode must be applied between the gate and source. Therefore, when a field effect transistor is used as a rectifying element in a bootstrap circuit, the field effect transistor cannot be turned on unless a voltage higher than the driving power supply Vcc is applied to the gate electrode (third electrode). Furthermore, when attempting to lower the voltage applied to the substrate, the threshold voltage becomes higher due to the substrate bias effect, and therefore it is necessary to further increase the voltage applied to the gate electrode (third electrode). However, according to the semiconductor device of the present invention, the impurity concentration of the backgate region is 1×10 10 cm -3~1×10 15 cm -3 Since the threshold voltage is within the range, the threshold voltage becomes extremely small (close to 0V), and the channel can be easily formed. In addition, the electric field spreading in the back gate region becomes small, so the influence of the substrate bias effect can be reduced. As a result, it is no longer necessary to apply a voltage higher than necessary to the third electrode in order to turn on the semiconductor device, and the semiconductor device can be turned on and off with an appropriate voltage.

[0014] According to the semiconductor device of the present invention, the semiconductor substrate has a first conductive type back gate region formed at a depth reaching the substrate in a region facing the third electrode via at least an insulating film, and a field effect transistor is formed by the second electrode, the back gate region, the first semiconductor layer, the insulating film, and the third electrode. Therefore, a parasitic transistor that causes a parasitic current to flow between the second electrode 130 and the substrate is unlikely to be formed. Therefore, problems such as an increase in leakage current, a decrease in breakdown voltage, and element destruction due to the parasitic current are unlikely to occur, and the rectifying element can be formed on the semiconductor substrate. As a result, the rectifying element can be built into the gate driver IC.

[0015] Furthermore, according to the semiconductor device of the present invention, since the semiconductor device includes an isolation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor substrate, and the semiconductor substrate, the first semiconductor layer, and the isolation film form a RESURF structure, the voltage applied to the relatively high voltage first electrode can be dropped to approach the voltage of the second electrode connected to a relatively low voltage circuit. Therefore, a relatively high voltage region and a relatively low voltage region can be formed on the same semiconductor substrate. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a circuit diagram shown for explaining a power conversion circuit 1 according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a semiconductor device 100 according to a first embodiment. [Diagram 3]It is a cross-sectional view shown to explain the state of the semiconductor device 100 according to Embodiment 1 during conduction (during charging, Vcc > Vb). [Figure 4] It is a cross-sectional view shown to explain the state of the semiconductor device 100 according to Embodiment 1 during non-conduction (reverse bias, Vcc < Vb). [Diagram 5] It is a graph showing the relationship between the voltage Vb on the first electrode 120 side and the charging current Ib during conduction (during charging) and non-conduction (reverse bias). [Figure 6] It is a cross-sectional view shown to explain the semiconductor device 101 according to Embodiment 2. [Figure 7] It is a cross-sectional view shown to explain the semiconductor device 102 according to Embodiment 3. [Figure 8] It is a circuit diagram shown to explain the conventional power conversion circuit 9. [Figure 9] It is a cross-sectional view shown to explain the semiconductor device 900 according to the background art. Note that reference numeral 922 indicates the first field plate, reference numeral 962 indicates the second field plate, and reference numeral 964 indicates the external connection portion. [Embodiment for Carrying Out the Invention]

[0017] Hereinafter, the semiconductor device of the present invention will be described based on the embodiments shown in the drawings. Note that each drawing is a schematic diagram and does not necessarily strictly reflect actual dimensions.

[0018] [Embodiment 1] 1. Configuration of the power conversion circuit 1 in Embodiment 1 First, the power conversion circuit 1 in Embodiment 1 in which the bootstrap FET (semiconductor device 100 according to Embodiment 1), which is the semiconductor device of the present invention, is provided will be described. FIG. 1 is a circuit diagram shown to explain the power conversion circuit 1 in Embodiment 1. As shown in FIG. 1, the power conversion circuit 1 in Embodiment 1 includes a high-side switch Q1, a low-side switch Q2, a capacitor 22, and a gate driver IC 10.

[0019] The high-side switch Q1 is connected to a DC input power supply Vin. One end of the low-side switch Q2 is connected to the high-side switch Q1, and the other end is connected to a reference potential. Appropriate switch elements can be used as the high-side switch Q1 and the low-side switch Q2, and in the first embodiment, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used. The high-side switch Q1 and the low-side switch Q2 constitute a part of a main circuit C1 which is a first circuit, and an output terminal OUT is connected to a connection point N between the high-side switch Q1 and the low-side switch Q2. The main circuit C1 is connected to a DC input power supply Vin (first power supply).

[0020] The capacitor 22 has one electrode connected to a connection point N between the high-side switch Q1 and the low-side switch Q2, and the other electrode connected to the high-side drive circuit 11 of the gate driver IC 10. The capacitor 22 is mounted as an external component of the gate driver IC 10.

[0021] The gate driver IC 10 includes a high-side drive circuit 11, a low-side drive circuit 12, a bootstrap FET (the semiconductor device 100 according to the first embodiment), and a plurality of terminals (terminals Vb, Vs, HO, LO, and GND).

[0022] The high-side drive circuit 11 controls the on / off of the high-side switch Q1. The high-side drive circuit 11 is connected to a connection point N between the high-side switch Q1 and the low-side switch Q2 via a Vs terminal. The high-side drive circuit 11 is also connected to a bootstrap FET (the semiconductor device 100 according to the first embodiment) and to a capacitor 22 via a Vb terminal. The high-side drive circuit 11 is also connected to the gate electrode of the high-side switch Q1 via an output terminal HO.

[0023] The low-side drive circuit 12 controls the on / off of the low-side switch Q2. The low-side drive circuit 12 constitutes a part of the second circuit C2, and is connected to a drive power supply Vcc (second power supply), and is connected to a ground potential via a GND terminal, and is connected to a gate electrode of the low-side switch Q2 via an output terminal LO. Note that the second power supply voltage, which is the output voltage of the drive power supply Vcc (second power supply), is lower than the first power supply voltage, which is the output voltage of the DC input power supply Vin (first power supply).

[0024] The bootstrap FET (semiconductor device 100 according to the first embodiment) has one electrode connected to the low-side drive circuit 12 and the drive power supply Vcc, and the other electrode connected to the capacitor 22 and the high-side drive circuit 11. The gate electrode of the bootstrap FET (semiconductor device 100 according to the first embodiment) is connected to the electrode (one electrode) on the drive power supply Vcc side, and the back gate BG is connected to a reference potential. The bootstrap FET (semiconductor device 100 according to the first embodiment) and the capacitor 22 form a bootstrap circuit 20.

[0025] As the bootstrap FET of the present invention, field effect transistors of various configurations can be used. In the first embodiment, however, in order to enable incorporation into the gate driver IC, the semiconductor device 100 according to the first embodiment formed on the same semiconductor substrate as the high side drive circuit 11 and the low side drive circuit 12 is used as the field effect transistor.

[0026] 2. Configuration of the semiconductor device 100 according to the first embodiment Fig. 2 is a cross-sectional view for explaining the semiconductor device 100 in the embodiment 1. As shown in Fig. 2, the semiconductor device 100 according to the embodiment 1 includes a semiconductor substrate 110, a first electrode 120, a first field plate 122, a second electrode 130, an element isolation film 140, insulating films 150 and 152, a third electrode 160, a second field plate 162, a connection portion 164, and a fourth electrode 170. Although not shown, the semiconductor device 100 according to the embodiment 1 is formed on the same semiconductor substrate as at least a part of the high side drive circuit 11 and the low side drive circuit 12, and is built into the gate driver IC 10.

[0027] The semiconductor substrate 110 is made of a predetermined semiconductor material. The lower portion of the semiconductor substrate 110 is entirely p-type (p - A n-type (n-type) substrate 111 is formed in a predetermined region on the substrate 111. - A first semiconductor layer 112 of p-type (p-type) is formed on the substrate 111, and a region adjacent to the first semiconductor layer 112 on the substrate 111 is - A back gate region 113 having a lattice structure (type) is formed on the first semiconductor layer 112. The boundary between the first semiconductor layer 112 and the back gate region 113 is located opposite a third electrode 160 (described later) across an insulating film 150 formed on the surface of the semiconductor substrate 110, and a part of the back gate region 113 is formed in a region opposite the third electrode 160 with the insulating film 150 interposed therebetween.

[0028] The back gate region 113 has the same composition as the substrate 111 and is formed continuously from the substrate 111. The back gate region 113 is formed to a depth that reaches the substrate 111 from the surface of the semiconductor base 110. The impurity concentration of the substrate 111 and the back gate region 113 is 1×10 10 cm -3 ~1×10 15 cm -3 This is a lower concentration than that of a typical back gate region.

[0029] In the region where the first semiconductor layer 112 is formed, a part of the surface of the first semiconductor layer 112 in the region opposite to the back gate region 113 side is an n-type (n + In other words, the first contact region CR1 is formed on the surface of the first semiconductor layer 112 on the opposite side to the back gate region 113 side with an element isolation film 140 (described later) sandwiched therebetween. The impurity concentration of the first contact region CR1 is higher than the impurity concentration of the first semiconductor layer 112.

[0030] In the region where the back gate region 113 is formed, a part of the surface of the back gate region 113 is doped with n-type (n + A p-type (p-type) second contact region CR2 is formed in a part of the surface of the back gate region 113 at a position farther from the first semiconductor layer 112 than the second contact region CR2 and separated from the second contact region CR2. + The impurity concentration of the second contact region CR2 is higher than the impurity concentration of the first semiconductor layer 112, and the impurity concentration of the third contact region CR3 is higher than the impurity concentration of the substrate 111.

[0031] An element isolation film 140 is formed on the surface of the central region of the first semiconductor layer 112. An insulating film 152 is formed on the surface of the semiconductor substrate 110 (first semiconductor layer 112) on the side opposite the back gate region 113 with respect to the element isolation film 140. An insulating film 150 is formed on the surface of the semiconductor substrate 110 (first semiconductor layer 112 and back gate region 113) on the back gate region 113 side with respect to the element isolation film 140. The element isolation film 140 is a LOCOS film made of SiO2, and about half of its thickness is buried in the semiconductor substrate 110. The element isolation film 140, the substrate 111 of the semiconductor substrate 110, and the first semiconductor layer 112 form a RESURF structure. The insulating films 150 and 152 are thermal oxide films.

[0032] The first electrode 120 is disposed above the semiconductor substrate 110, at a position opposite to the side where the back gate region 113 is formed with respect to the element isolation film 140. The first electrode 120 is in contact with a first contact region CR1 of the semiconductor substrate 110 through an opening formed in the insulating film 152. The first electrode 120 is connected to the high side drive circuit 11 and a capacitor 22, and is electrically connected to the main circuit C1 through the capacitor 22 (see FIG. 1). The first electrode 120 is made of a metal (e.g., aluminum).

[0033] The first field plate 122 is formed from above the surface of the insulating film 152 to above the surface of the element isolation film 140 so as to cover the insulating film 152 and the element isolation film 140, and is connected to the first electrode 120. In the first embodiment, the first field plate 122 is made of polysilicon, but may be made of a metal (e.g., aluminum), a silicide (e.g., a metal silicide such as aluminum silicide (AlSi) or nickel silicide (NiSi)), or another appropriate conductor.

[0034] The second electrode 130 is disposed above the semiconductor substrate 110 at a position opposite to the first electrode 120 with the element isolation film 140 therebetween (therefore, the element isolation film 140 is formed in the region between the first electrode 120 and the second electrode 130). The second electrode 130 is electrically connected to an external driving power supply Vcc and the low-side driving circuit 12. The second electrode 130 is in contact with a second contact region CR2 of the semiconductor substrate 110 via an opening formed in the insulating film 150. The second electrode 130 is made of a metal (e.g., aluminum).

[0035] The third electrode 160 is a film-like member disposed on the insulating film 150 at a position in contact with the element isolation film 140. Although the third electrode 160 is a film-like member in the first embodiment, it does not have to be a film-like member. The third electrode 160 faces a part of the back gate region 113 and a part of the first semiconductor layer 112 via the insulating film 150. The second field plate 162 is connected to the third electrode 160 and is formed on the surface of the element isolation film 140. The second field plate 162 is integrated with the third electrode 160. In Embodiment 1, the third electrode 160 and the second field plate 162 are made of polysilicon, but may be made of a metal (e.g., aluminum), a silicide (e.g., a metal silicide such as aluminum silicide (AlSi) or nickel silicide (NiSi)), or other appropriate conductors. One side of the connection portion 164 is connected to the second electrode 130, and the other side extends onto the second field plate 162 and is connected to the second field plate 162. The connection portion 164 is made of a metal (e.g., aluminum).

[0036] The fourth electrode 170 is connected to the third contact region CR3 and the back gate region 113 of the semiconductor substrate 110 through an opening formed in the insulating film 150. Since the fourth electrode 170 is connected to an external reference potential, the potentials of the substrate 111 and the back gate region 113 become the reference potential.

[0037] 3. Operation of the semiconductor device 100 according to Embodiment 1 Next, it will be described that the semiconductor device 100 according to Embodiment 1 has a function as a rectifying element of a bootstrap circuit. FIG. 3 is a cross-sectional view showing the state of the semiconductor device 100 according to Embodiment 1 during conduction (charging, Vcc > Vb). FIG. 4 is a cross-sectional view showing the state of the semiconductor device 100 according to Embodiment 1 during non-conduction (reverse bias, Vcc < Vb).

[0038] (1) During conduction (charging, Vcc > Vb) When the low-side switch Q2 is switched on, the voltage Vcc of the driving power supply becomes larger than the voltage Vb on the capacitor 22 side. In the semiconductor device 100 according to the first embodiment, the first electrode 120 is connected to the capacitor 22, and the second electrode 130 is connected to the driving power supply Vcc. Therefore, the semiconductor device 100 according to the first embodiment has a configuration similar to that of an n-channel MOS in which the first electrode 120 is a source electrode, the second electrode 130 is a drain electrode, and the third electrode 160 is a gate electrode (see FIG. 3). Since the third electrode 160, which is a gate electrode, is connected to the second electrode 130, which is a drain electrode, a gate-source voltage is generated, the gate electrode is turned on, and a channel region 113′ is formed in the back gate region 113 that faces the third electrode 160 with the insulating film 150 interposed therebetween. Therefore, a current flows from the driving power supply Vcc through the second electrode 130, the channel region 113', the first semiconductor layer 112, the first contact region CR1, and the first electrode 120 to the capacitor 22, and the capacitor 22 is charged.

[0039] (2) When not conducting (when the body diode is reverse biased, Vcc <Vb) When the low-side switch Q2 is switched off, the voltage Vs at the connection point N between the high-side switch Q1 and the low-side switch Q2 rises, and the voltage Vb also rises accordingly, and the voltage Vcc of the driving power supply soon becomes smaller than the voltage Vb on the capacitor 22 side. Therefore, the semiconductor device 100 according to the first embodiment has a configuration similar to that of an n-channel MOS in which the first electrode 120 is a drain electrode, the second electrode 130 is a source electrode, and the third electrode 160 is a gate electrode (see FIG. 4). Since the third electrode 160, which is the gate electrode, is connected to the second electrode 130, which is the source electrode, the gate-source voltage becomes 0, no channel region 113' is formed in the backgate region 113, and the semiconductor device 100 is not turned on (a reverse bias is applied to the body diode formed by the p-type backgate region 113 and the n-type first semiconductor layer 112). Therefore, when the voltage of the capacitance 22 is superimposed on the high side drive circuit 11, no current flows from the capacitance 22 to the drive power supply Vcc, and the reverse current flow from the capacitance 22 to the drive power supply Vcc can be prevented.

[0040] Next, a description will be given of the relationship between the voltage Vb and the charging current Ib flowing through the semiconductor device 100. FIG.

[0041] 5, when the voltage Vb is small, the voltage Vcc of the driving power supply becomes larger than the voltage Vb on the capacitor 22 side, so that the semiconductor device 100 turns on and a charging current Ib flows from the driving power supply Vcc to the capacitor 22. As the capacitor 22 is charged, the voltage Vb gradually increases, and as the difference between the voltage Vcc of the driving power supply Vcc and the voltage Vb of the capacitor 22 becomes smaller, the charging current Ib gradually decreases.

[0042] Here, since the semiconductor device according to the first embodiment uses a field effect transistor as a rectifying element, a voltage drop is unlikely to occur as occurs when a bootstrap diode is used. Therefore, the charging current Ib flows until the voltage Vb becomes close to the voltage Vcc. In addition, in the semiconductor device 100 according to the first embodiment, the impurity concentration of the back gate region 113 is extremely low, so that the threshold voltage is extremely low and the charging current Ib can maintain a predetermined value even when the voltage Vb becomes close to the voltage Vcc.

[0043] When the voltage Vcc of the second electrode becomes almost the same as the voltage Vb of the first electrode, the charging current Ib drops sharply and almost stops flowing. When the voltage Vcc of the second electrode becomes smaller than the voltage Vb of the first electrode, the channel region of the semiconductor device 100 disappears, resulting in a reverse bias, and almost no charging current Ib flows.

[0044] In this manner, the semiconductor device 100 according to the first embodiment functions as a rectifying element that controls the charging and discharging of the capacitance.

[0045] 4. Effects of the semiconductor device 100 according to the first embodiment According to the semiconductor device 100 of the first embodiment, the semiconductor substrate 110 has an n-type back gate region 113 formed at a depth reaching the substrate 111 in a region facing the third electrode 160 through at least the insulating film 150, and the second electrode 130, the back gate region 113, the first semiconductor layer 112, the insulating film 150, and the third electrode 160 constitute a field effect transistor. Therefore, when the voltage Vcc of the second electrode 130 is larger than the voltage Vb of the first electrode 120, the third electrode 160 is turned on to allow a current to flow from the second electrode 130 to the first electrode 120, thereby charging the capacitance, and when the voltage Vcc of the second electrode 130 is smaller than the voltage Vb of the first electrode 120, the third electrode 160 is turned off to cut off the current. Therefore, the function of a rectifying element can be realized in the same way as a conventional bootstrap diode.

[0046] However, when a bootstrap diode is used as a rectifying element in a bootstrap circuit, a voltage drop equivalent to the forward voltage occurs as a characteristic of the diode, so that the voltage applied to the capacitance from the driving power supply Vcc drops, making it difficult to charge the capacitance to a voltage close to the driving power supply Vcc. In contrast, according to the semiconductor device 100 of the first embodiment, a field effect transistor constituted by the second electrode 130, the back gate region 113, the first semiconductor layer 112, the insulating film 150, and the third electrode 160 is used as a rectifying element, so that a voltage drop equivalent to the forward voltage does not occur as in the case of using a bootstrap diode, and the capacitance 22 can be charged to a voltage close to the driving power supply Vcc (see FIG. 5).

[0047] Incidentally, in order to turn on a field effect transistor, it is necessary to apply a voltage between the gate and source that is higher than the source electrode. Therefore, when a field effect transistor is used as a rectifying element in a bootstrap circuit, the field effect transistor cannot be turned on unless a voltage higher than the driving power supply Vcc is applied to the gate electrode (third electrode). Furthermore, when attempting to lower the voltage applied to the substrate, the threshold voltage becomes higher due to the substrate bias effect, and therefore it is necessary to further increase the voltage applied to the gate electrode (third electrode). However, according to the semiconductor device 100 of the first embodiment, the impurity concentration of the back gate region 113 is 1×10 10 cm -3 ~1×10 15 cm -3 Since the threshold voltage is within the range, the threshold voltage becomes extremely small (close to 0 V), and the channel region 113' can be easily formed. In addition, the electric field spreading in the back gate region 113 becomes small, so that the influence of the substrate bias effect can be reduced. As a result, it is no longer necessary to apply a voltage higher than necessary to the third electrode 160 in order to turn on the semiconductor device, and the semiconductor device can be turned on and off with an appropriate voltage.

[0048] The impurity concentration of the back gate region 113 is set to 1×10 10 cm -3 The reason for the above is that the impurity concentration of the back gate region 113 is 1×10 10 cm -3 If the impurity concentration of the back gate region 113 is less than 10, the pn junction between the back gate region 113 and the first semiconductor layer 112 cannot form a sufficient potential barrier when reverse bias is applied, and a reverse current may flow between the first electrode 120 and the second electrode 130 when reverse bias is applied, making it difficult to maintain the function as a rectifying element. 15 cm -3 The reason why the impurity concentration of the back gate region 113 is set to 10 15 cm -3If it exceeds this value, the threshold voltage becomes high and it becomes difficult to form the channel region 113′, so that it is necessary to apply a relatively high voltage to the third electrode 160.

[0049] Furthermore, according to the semiconductor device 100 of the first embodiment, the semiconductor substrate 110 has a p-type back gate region 113 formed at a depth reaching the substrate 111 at least in a region facing the third electrode 160 via the insulating film 150, and a parasitic transistor that causes a parasitic current to flow between the second electrode 130 and the substrate 111 is unlikely to be formed. Therefore, problems such as an increase in leakage current, a decrease in breakdown voltage, and element destruction due to the parasitic current are unlikely to occur, and the rectifying element can be formed in the semiconductor substrate. As a result, the rectifying element can be built into the gate driver IC.

[0050] Furthermore, the semiconductor device 100 according to the first embodiment includes the element isolation film 140 formed in the region between the first electrode 120 and the second electrode 130 on the surface of the semiconductor base 110, and the substrate 111 and the first semiconductor layer 112 of the semiconductor base 110, and the element isolation film 140 form a semiconductor device having a RESURF structure, so that the voltage applied to the first electrode 120, which is a relatively high voltage, can be dropped to approach the voltage of the second electrode 130 connected to a relatively low voltage circuit. Therefore, a relatively high voltage region and a relatively low voltage region can be formed on the same substrate.

[0051] Furthermore, according to the semiconductor device 100 of the first embodiment, since the third electrode 160 is connected to the second electrode 130, even if a driving circuit or the like for switching is not provided, a forward bias is generated when the voltage Vcc of the second electrode 130 is larger than the voltage Vb of the first electrode 120, and a reverse bias is generated when the voltage Vcc of the second electrode 130 is smaller than the voltage Vb of the first electrode 120. Therefore, a semiconductor device having a function as a rectifying element with a simple configuration is provided.

[0052] Moreover, according to the semiconductor device 100 of the first embodiment, since the substrate 111 is connected to the reference potential, even if a small voltage is applied to the third electrode 160, the channel region 113' is easily formed in the back gate region 113. Furthermore, since the electric field spreading in the back gate region 113 is small, the influence of the substrate bias effect can be further reduced.

[0053] Furthermore, according to the semiconductor device 100 of embodiment 1, the first electrode 120 is electrically connected to the drive circuit (high side drive circuit 11) that controls the on / off of the high side switch Q1 of the main circuit C1 and the capacitor 22, and the second electrode 130 is electrically connected to the drive power supply Vcc, thereby providing a semiconductor device that functions as a rectifying element of a bootstrap circuit.

[0054] Furthermore, according to the semiconductor device 100 of embodiment 1, the semiconductor device 100 is formed on the same semiconductor substrate as the high side drive circuit 11 and the low side drive circuit 12 that control the on / off of the switches Q1 and Q2 of the first circuit. Therefore, the semiconductor device 100, which is a rectifying element, can be built into a gate driver IC, making it a semiconductor device that meets the demand for miniaturization of electrical equipment.

[0055] Furthermore, according to the semiconductor device 100 of embodiment 1, the semiconductor body 110 has an n-type second contact region CR2 having a higher concentration than the first semiconductor layer 112 in a region connected to the second electrode 130, and the back gate region 113 is also formed in the region between the second contact region CR2 and the substrate 111. Therefore, the semiconductor body 110 can be constructed simply by forming the n-type first semiconductor layer 112, the first contact region CR1, the second contact region CR2 and the third contact region CR3 on a p-type semiconductor substrate, and a semiconductor device having the above-mentioned effects with a simple configuration can be obtained.

[0056] [Embodiment 2] FIG. 6 is a cross-sectional view shown for explaining a semiconductor device 101 according to the second embodiment. The semiconductor device 101 according to the second embodiment has a configuration basically similar to that of the semiconductor device 100 according to the first embodiment, but differs from the semiconductor device 100 according to the first embodiment in that the fourth electrode 170 is not arranged and the semiconductor device 101 according to the second embodiment further includes an n-type semiconductor region 118. That is, in the semiconductor device 101 according to the second embodiment, the semiconductor substrate 110 includes an n-type semiconductor region 118 having a lower impurity concentration than the second contact region CR2, which is formed in a region surrounding the second contact region CR2, as shown in FIG. 6. The impurity concentration of the n-type semiconductor region 118 is lower than the impurity concentration of the first semiconductor layer 112.

[0057] In the semiconductor device 101 according to the second embodiment, the fourth electrode 170 of the first embodiment is not formed, but the substrate 111 is connected to a reference potential. Also, the second electrode 130 and the third electrode 160 are not connected, and a voltage can be applied to the third electrode 160 to form a channel in the back gate region 113a.

[0058] Thus, the semiconductor device 101 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in that the fourth electrode 170 is not arranged and further includes the n-type semiconductor region 118. However, as in the semiconductor device 100 according to the first embodiment, the semiconductor substrate 110 has a p-type backgate region 113a formed at a depth reaching the substrate 111 at least in a region facing the third electrode 160 via the insulating film 150, and a parasitic transistor that causes a parasitic current to flow between the second electrode 130 and the substrate 111 is unlikely to be formed. Therefore, the rectifying element can be formed in the semiconductor substrate without problems such as an increase in leakage current, a decrease in withstand voltage, and element destruction due to the parasitic current. As a result, the rectifying element can be built into the gate driver IC.

[0059] Furthermore, according to the semiconductor device 101 of embodiment 2, the semiconductor substrate 110 has, in a region connected to the second electrode 130, an n-type second contact region CR2 having a higher concentration than the first semiconductor layer 112, and an n-type semiconductor region 118 having a lower concentration than the second contact region CR2 formed in a region surrounding the second contact region CR2, so that a withstand voltage between the third electrode 160, which is a gate electrode, and the second electrode 130, which is a source electrode, can be ensured during reverse bias.

[0060] The semiconductor device 101 of embodiment 2 has a configuration similar to that of the semiconductor device 100 of embodiment 1 except that the fourth electrode 170 is not arranged and the semiconductor device 101 further has an n-type semiconductor region 118, and therefore has the corresponding effects among the effects of the semiconductor device 100 of embodiment 1.

[0061] [Embodiment 3] FIG. 7 is a cross-sectional view shown for explaining a semiconductor device 102 according to the third embodiment. The semiconductor device 102 according to the third embodiment basically has the same configuration as the semiconductor device 101 according to the second embodiment, but differs from the semiconductor device 101 according to the second embodiment in that the n-type semiconductor region 118a is in contact with the substrate (see FIG. 7). That is, in the semiconductor device 102 according to the third embodiment, the n-type semiconductor region 118a is formed in a region in contact with the second electrode 130 to a depth reaching the substrate 111, and is in contact with the substrate 111.

[0062] While the method of forming the n-type semiconductor region 118a and the back gate region 113b can be selected appropriately, in the third embodiment, a semiconductor base body in which the substrate 111 and the n-type semiconductor layer are laminated is prepared, and a columnar (columnar when viewed in cross section) back gate region is formed in the n-type semiconductor layer, and the n-type semiconductor layer is separated into the n-type first semiconductor layer 112 and the n-type semiconductor region 118a. Therefore, the impurity concentration of the n-type semiconductor region 118a is the same as that of the first semiconductor layer 112, and the back gate region 113b is a columnar region formed in a region facing the third electrode 160 via the insulating film 150, with a depth reaching the substrate 111.

[0063] Thus, the semiconductor device 102 according to the third embodiment differs from the semiconductor device 101 according to the second embodiment in that the n-type semiconductor region is in contact with the substrate, but like the semiconductor device 101 according to the second embodiment, the semiconductor substrate 110 has a p-type backgate region 113b formed at a depth reaching the substrate 111 at least in a region facing the third electrode 160 via the insulating film 150, and a parasitic transistor that causes a parasitic current to flow between the second electrode 130 and the substrate 111 is unlikely to be formed. Therefore, the rectifying element can be formed in the semiconductor substrate without problems such as an increase in leakage current due to parasitic current, a decrease in withstand voltage, and element destruction. As a result, the rectifying element can be built into the gate driver IC.

[0064] Furthermore, according to the semiconductor device 102 of the third embodiment, the impurity concentration of the n-type semiconductor region 118a is the same as that of the first semiconductor layer 112, so that by forming a columnar backgate region in the n-type semiconductor layer, the n-type semiconductor layer can be formed separately into the n-type first semiconductor layer 112 and the n-type semiconductor region 118a. Therefore, there is no need to add a new process for forming the n-type semiconductor region 118a, and the semiconductor device can be manufactured by a simple method.

[0065] The semiconductor device 102 of the third embodiment has a similar configuration to the semiconductor device 101 of the second embodiment except that the n-type semiconductor region is in contact with the substrate, and therefore has the corresponding effects among the effects of the semiconductor device 101 of the second embodiment.

[0066] Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment. The present invention can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0067] (1) The numbers, materials, shapes, positions, sizes, and other elements of the components described in the above embodiments are merely examples and may be changed without impairing the effects of the present invention.

[0068] (2) In the above embodiment 1, a fourth electrode is provided to connect substrate 111 to a reference potential, but the present invention is not limited to this. The potential of substrate 111 may be the reference potential without providing a fourth electrode, or substrate 111 may not be connected to the reference potential. Also, in embodiments 2 and 3, a fourth electrode is not provided, but the present invention is not limited to this. The fourth electrode may be provided to connect substrate 111 to a reference potential, or the potential may be a potential other than the reference potential.

[0069] (3) In the above embodiment 1, the third electrode is connected to the second electrode, but the present invention is not limited to this. The third electrode may not be connected to the second electrode, and a voltage may be applied to the third electrode to turn the semiconductor device on and off. In addition, in embodiments 2 and 3, the third electrode is not connected to the second electrode, and a voltage is applied to the third electrode to turn the semiconductor device on and off, but the present invention is not limited to this. The third electrode may be connected to the second electrode.

[0070] (4) In each of the above embodiments, the back gate region is connected to the substrate 111, but the present invention is not limited to this. The back gate region does not have to be connected to the substrate 111. In addition, the impurity concentration of the substrate 111 and the impurity concentration of the back gate region may be different.

[0071] (5) In each of the above embodiments, the semiconductor device is used as a rectifying element in a bootstrap circuit, but the present invention is not limited to this. The semiconductor device may be used as a rectifying element other than a bootstrap circuit. [Explanation of symbols]

[0072] 10...High side drive circuit, 20...Low side drive circuit, 22...Capacitor, 100, 101, 102...Semiconductor device, 110...Semiconductor substrate, 111...Substrate, 112...First semiconductor layer, CR1...First contact region, CR2...Second contact region, CR3...Third contact region, 113, 113a, 113b...Back gate region, 118, 118a...N-type semiconductor region, 120...First electrode, 130...Second electrode, 140...Element isolation film, 150, 152...Insulating film, 160...Third electrode, 170...Fourth electrode, C1...First circuit, C2...Second circuit

Claims

1. a semiconductor body having a substrate of a first conductivity type and a first semiconductor layer of a second conductivity type formed on the substrate; a first electrode disposed above the semiconductor body and in contact with the semiconductor body; a second electrode disposed above the semiconductor body at a position spaced apart from the first electrode and in contact with the semiconductor body; an isolation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor substrate; an insulating film disposed between the second electrode and the element isolation film on a surface of the semiconductor substrate; a third electrode disposed on the insulating film; the first electrode is electrically connected to a first circuit connected to a first power source; the second electrode is electrically connected to a second circuit connected to a second power source; The semiconductor substrate is The insulating film is formed at least in a region facing the third electrode with the insulating film interposed therebetween to a depth reaching the substrate, and the impurity concentration is 1×10 １０ cm －３ ~1×10 １５ cm －３ a back gate region of the first conductivity type within a range of 4. A semiconductor device comprising: a back gate region having an impurity concentration that is the same as or substantially the same as a substrate;

2. 2. The semiconductor device according to claim 1, wherein a second power supply voltage which is an output voltage of the second power supply is lower than a first power supply voltage which is an output voltage of the first power supply.

3. 3. The semiconductor device according to claim 1, wherein the third electrode is electrically connected to the second electrode.

4. 3. The semiconductor device according to claim 1, wherein a predetermined voltage is applied to the third electrode based on a signal.

5. 5. The semiconductor device according to claim 1, wherein the substrate is connected to a reference potential.

6. the first electrode is electrically connected to a drive circuit that controls on / off of a switch element of the first circuit and a capacitance that is connected to the drive circuit; the second electrode is electrically connected to a driving power source which is the second power source, 6. The semiconductor device according to claim 1, wherein the semiconductor device and the drive circuit are formed on the same semiconductor substrate.

7. the semiconductor substrate further includes a contact region of a second conductivity type having a higher concentration than the first semiconductor layer, the contact region being formed in a region connected to the second electrode; 7. The semiconductor device according to claim 1, wherein the back gate region is also formed in a region between the contact region and the substrate.

8. the semiconductor substrate further includes a contact region of a second conductivity type having a higher concentration than the first semiconductor layer, the contact region being formed in a region connected to the second electrode, and a semiconductor region of a second conductivity type having a lower concentration than the contact region, the contact region being formed in a region surrounding the contact region; 7. The semiconductor device according to claim 1, wherein the back gate region is also formed between the second conductive type semiconductor region and the substrate.

9. 9. The semiconductor device according to claim 8, wherein the impurity concentration of the second conductive type semiconductor region is the same as the impurity concentration of the first semiconductor layer.

10. a semiconductor body having a substrate of a first conductivity type and a first semiconductor layer of a second conductivity type formed on the substrate; a first electrode disposed above the semiconductor body and in contact with the semiconductor body; a second electrode disposed above the semiconductor body at a position spaced apart from the first electrode and in contact with the semiconductor body; an isolation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor substrate; an insulating film disposed between the second electrode and the element isolation film on a surface of the semiconductor substrate; a third electrode disposed on the insulating film; the first electrode is electrically connected to a first circuit connected to a first power source; the second electrode is electrically connected to a second circuit connected to a second power source; The semiconductor substrate is The insulating film is formed at least in a region facing the third electrode with the insulating film interposed therebetween to a depth reaching the substrate, and the impurity concentration is 1×10 １０ cm －３ ~1×10 １５ cm －３ a back gate region of the first conductivity type within a range of the semiconductor substrate further includes a contact region of a second conductivity type having a higher concentration than the first semiconductor layer, the contact region being formed in a region connected to the second electrode, and a semiconductor region of a second conductivity type having a lower concentration than the contact region, the contact region being formed in a region surrounding the contact region; The semiconductor device according to claim 1, wherein the second conductive type semiconductor region is in contact with the substrate.

11. a semiconductor body having a substrate of a first conductivity type and a first semiconductor layer of a second conductivity type formed on the substrate; a first electrode disposed above the semiconductor body and in contact with the semiconductor body; a second electrode disposed above the semiconductor body at a position spaced apart from the first electrode and in contact with the semiconductor body; an isolation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor substrate; an insulating film disposed between the second electrode and the element isolation film on a surface of the semiconductor substrate; a third electrode disposed on the insulating film; the first electrode is electrically connected to a first circuit connected to a first power source; the second electrode is electrically connected to a second circuit connected to a second power source; The semiconductor substrate is The insulating film is formed at least in a region facing the third electrode with the insulating film interposed therebetween to a depth reaching the substrate, and the impurity concentration is 1×10 １０ cm －３ ~1×10 １５ cm －３ a back gate region of the first conductivity type within a range of the semiconductor substrate further includes a contact region of a second conductivity type having a higher concentration than the first semiconductor layer, the contact region being formed in a region connected to the second electrode, and a semiconductor region of a second conductivity type having a lower concentration than the contact region, the contact region being formed in a region surrounding the contact region; The back gate region is also formed between the second conductive type semiconductor region and the substrate, The semiconductor device according to claim 1, wherein the second conductive type semiconductor region has an impurity concentration lower than an impurity concentration of the first semiconductor layer.

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