Semiconductor Device

Abstract

To provide a semiconductor device having stable electric characteristics by the use of an oxide semiconductor film, in which the concentration of impurities included in the vicinity of a surface where the oxide semiconductor film is formed is reduced and the crystallinity of the oxide semiconductor film is improved.SOLUTION: A transistor 110 includes a substrate 100, a gate electrode 101, a gate insulating film 102 covering the gate electrode and including an oxide containing silicon, an oxide semiconductor film 103 provided in a region overlapping at least the gate electrode in contact with the gate insulating film, a source electrode 105a and a drain electrode 105b connecting to the oxide semiconductor film, and a protective insulating film 109. In a first region where the thickness of the oxide semiconductor film from an interface with the gate insulating film is 5 nm or less, the silicon concentration is 1.0 atom% or less. The silicon concentration in a region of the oxide semiconductor film other than the first region is lower than the silicon concentration in the first region, and at least the first region includes a crystal part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. There are.

[0004] For example, indium (In), gallium (Ga), and nickel are used as active layers of transistors. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ).

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. The transistor using an oxide semiconductor has high on-state characteristics (such as on-state current). Further improvements in properties are required for application to functional devices, and the formation of oxide semiconductors In Patent Document 2, a crystallization technique is being developed by heat-treating an oxide semiconductor. A technique for crystallization by this has been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2008-311342 A Summary of the Invention [Problem to be solved by the invention]

[0007] The oxide semiconductor film used in the transistor is formed by a sputtering method. However, when sputtering an oxide semiconductor film, ionized rare gas Elements and particles that are repelled from the target surface are deposited on oxide semiconductor films such as gate insulating films. This can cause the particles of the film to be blown away. The particles that are repelled from the film are taken into the oxide semiconductor film as impurity elements. As a result, impurity elements are introduced at a high concentration in the vicinity of a surface where the oxide semiconductor film is formed. In addition, when the impurity element remains in the vicinity of the surface where the oxide semiconductor film is formed, the transistor This is a factor that affects the characteristics of the Zysta.

[0008] In addition, when an impurity element is taken into the vicinity of a surface where the oxide semiconductor film is formed, the impurity element Therefore, the crystallization of the oxide semiconductor film is inhibited. Amorphous regions remain near the surfaces.

[0009] In view of this, it is conceivable to thicken the oxide semiconductor film and use the crystalline region on the surface. In order to reduce parasitic capacitance and operate a transistor with low power consumption, an oxide semiconductor film In that case, the channel formation region is preferably formed near the surface where the oxide semiconductor film is to be formed. Since the oxide semiconductor film is formed in the vicinity of the surface on which the oxide semiconductor film is to be formed, it is preferable that the oxide semiconductor film be crystallized up to the vicinity of the surface on which the oxide semiconductor film is to be formed.

[0010] In view of such a problem, a method for reducing the concentration of impurities in the vicinity of a surface where an oxide semiconductor film is formed is disclosed. Another object is to improve the crystallinity of an oxide semiconductor film. In addition, by using the oxide semiconductor film, a semiconductor device having stable electrical characteristics can be obtained. One of the purposes of this agreement is to provide [Means for solving the problem]

[0011] One embodiment of the disclosed invention is a semiconductor device including a gate electrode and an oxide including silicon covering the gate electrode. a gate insulating film including a gate electrode and a gate insulating film provided in a region that is in contact with the gate insulating film and overlaps at least the gate electrode; The oxide semiconductor film is electrically connected to a source electrode and a drain electrode. The oxide semiconductor film has a shielding layer extending from an interface with the gate insulating film toward the oxide semiconductor film. The silicon is distributed at a concentration of 1.0 atomic % or less in a first region. The semiconductor device further includes a crystal portion.

[0012] Further, one embodiment of the disclosed invention is a gate electrode and an oxide film containing silicon covering the gate electrode. a gate insulating film including a gate electrode and a gate insulating film including a gate electrode; a channel protective film provided in contact with the oxide semiconductor film; A source electrode and a drain electrode are provided on the channel protective film and electrically connected to the oxide semiconductor film. and a gate electrode, the oxide semiconductor film being formed from an interface with the gate insulating film toward the oxide semiconductor film. The silicon concentration in the first region is 1.0 atomic % or less. The semiconductor device includes a crystal portion within the region.

[0013] In each of the above configurations, the first region has a thickness of 5 nm or less from the interface with the gate insulating film. The concentration of silicon in the first region is smaller than that of silicon in the first region. It is preferable that the concentration of the amine be less than that of the amine.

[0014] In each of the above structures, a crystal part is preferably included in a region other than the first region of the oxide semiconductor film. I wish.

[0015] Further, one embodiment of the disclosed invention is a gate electrode and an oxide film containing silicon covering the gate electrode. a gate insulating film including a gate electrode and a gate insulating film including a gate electrode; A source electrode and a drain electrode electrically connected to the oxide semiconductor film are provided. The oxide semiconductor film covers the source electrode and the drain electrode, and the oxide semiconductor film covers the source electrode and the drain electrode. a protective insulating film containing an oxide semiconductor film, and the oxide semiconductor film is A first region in which silicon is distributed toward the semiconductor film at a concentration of 1.0 atomic % or less, and an oxidized The oxide semiconductor film has a silicon content of 1.0 atomic % from the interface with the protective insulating film toward the oxide semiconductor film. and a second region having a concentration of at least The semiconductor device includes a crystal portion.

[0016] In the above configuration, the first region has a thickness of 5 nm or less from the interface with the gate insulating film. the second region is present in a range having a thickness of 5 nm or less from the interface with the protective insulating film, The concentration of silicon contained in the area other than the first area and the second area is It is preferable that the concentration of silicon contained in the SiO 2 film is smaller than the concentration of silicon contained in the SiO 2 film.

[0017] In the above structure, a region other than the first region and the second region of the oxide semiconductor film is It is preferable that the crystal portion is contained.

[0018] In each of the above structures, the crystal portion has a c-axis aligned along the interface between the oxide semiconductor film and the gate insulating film. It is preferable that the alignment is perpendicular to the direction of the arrows.

[0019] In each of the above configurations, the concentration of silicon contained in the first region is 0.1 atomic % or less. It is preferable that there is.

[0020] In each of the above structures, the gate insulating film contains carbon, and the carbon concentration in the first region is is 1.0×10 20 atoms / cm 3 It is preferable that the following is true: Effect of the Invention

[0021] According to one embodiment of the disclosed invention, a concentration of impurities in an oxide semiconductor film in the vicinity of a surface where the oxide semiconductor film is formed is In addition, the crystallinity of the oxide semiconductor film can be improved. By using the oxide semiconductor film, a semiconductor device having stable electrical characteristics can be provided. It can be provided. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] Model diagram used for calculations. [Figure 7] A diagram showing the calculation results. [Figure 8] A diagram showing the calculation results. [Figure 9] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 10] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 11] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 12] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 13] FIG. [Figure 14] 11 is a graph showing measurement results according to an embodiment of the present invention. [Figure 15] FIG. 2 is a diagram showing a structure of a sample according to an embodiment of the present invention. [Figure 16] 11 is a graph showing measurement results according to an embodiment of the present invention. [Figure 17] FIG. 2 is a diagram showing a structure of a sample according to an embodiment of the present invention. [Figure 18] 11 is a graph showing measurement results according to an embodiment of the present invention. [Figure 19] FIG. 2 is a diagram showing a structure of a sample according to an embodiment of the present invention. [Figure 20] 11 is a graph showing measurement results according to an embodiment of the present invention. [Figure 21] Model diagram used for calculations. [Figure 22] Model diagram used for calculations. [Figure 23] A diagram showing the calculation results. [Figure 24] Model diagram used for calculations. [Diagram 25] A diagram showing the calculation results. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and any deviation from the spirit and scope of the present invention is not permitted. It will be easily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0024] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0026] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0027] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0028] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It is possible.

[0029] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via a "device that has some electrical function." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0030] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. I will explain this in more detail.

[0031] <Configuration Example of Semiconductor Device> FIG. 1(A) and FIG. 1(B) show a bottom gate structure as an example of a semiconductor device. FIG. 1(A) is a plan view of a channel-etch transistor. FIG. 1(B) is a cross-sectional view taken along the line AB in FIG. 1(A). ) in order to avoid complication, some of the components of the transistor 110 (e.g., The protective insulating film 109, etc. are omitted.

[0032] The transistor 110 shown in FIG. 1A and FIG. 1B is a transistor including a substrate 100 having an insulating surface. On the top, a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, and a gate insulating film 1 The oxide semiconductor film 1 is provided in a region that is in contact with the gate electrode 102 and overlaps with at least the gate electrode 101. 03, a source electrode 105a and a drain electrode electrically connected to the oxide semiconductor film 103 105b, covering the oxide semiconductor film 103, the source electrode 105a and the drain electrode 105b. The protective insulating film 109 is included.

[0033] The thickness of the oxide semiconductor film 103 is greater than 5 nm and less than or equal to 200 nm. The oxide semiconductor film 103 is single crystal or microcrystalline. It is preferable to have a structure having any one of these crystallinities.

[0034] In this embodiment, the oxide semiconductor film 103 is a CAAC-OS (C Axis Al ignited Crystalline Oxide Semiconductor film It is preferable that there is.

[0035] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often small enough to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by a microscope, the boundary between the amorphous region and the crystalline region in the CAAC-OS film was clearly visible. In addition, grain boundaries were not clearly observed in the CAAC-OS film by TEM. Therefore, the CAAC-OS film does not show any electron transfer due to grain boundaries. The decline in activity is suppressed.

[0036] The crystals in the CAAC-OS film have c-axes aligned along the surface on which the CAAC-OS film is formed or along the surface of the CAAC-OS film. Atomic arrangement aligned perpendicularly and in a triangular or hexagonal shape when viewed perpendicular to the ab plane When viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. The a-axis and b-axis directions of different crystal parts may be different. In this specification, when the term "perpendicular" is used, it includes the range of 85° to 95°. It will be included.

[0037] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may become high in the vicinity of the

[0038] The c-axis of the crystal part in the CAAC-OS film is aligned along the surface on which the CAAC-OS film is formed or along the surface of the CAAC-OS film. Since the CAAC-OS film is aligned in the vertical direction, the shape of the CAAC-OS film (the cross-sectional shape of the surface on which it is formed or the cross-sectional shape of the surface) Depending on the shape, the c-axes of the crystals may be oriented in different directions. The direction is perpendicular to the surface on which the AAC-OS film is formed. The film is formed by forming a film or by performing a crystallization process such as a heat treatment after the film is formed. can be.

[0039] Transistors using CAAC-OS films show excellent photoinduced ... It is possible to reduce the fluctuation of electrical characteristics. Also, it is possible to suppress the fluctuation and variation of the threshold voltage. Therefore, the transistor is highly reliable.

[0040] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced. Furthermore, by improving the flatness of the surface of the crystalline oxide semiconductor film, The transistors using amorphous oxide semiconductors are more In order to improve the flatness of the surface of the oxide semiconductor film, It is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra ) is preferably formed on the surface having a thickness of 0.15 nm or less, and more preferably 0.1 nm or less.

[0041] Note that Ra is defined in JIS B0601:2001 (ISO4287:1997). This is a three-dimensional extension of the arithmetic mean roughness, which is currently used, so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from the reference surface to the specified surface" and is defined by the following formula. .

[0042]

number

[0043] Here, the specified surface is the surface to be measured for roughness, and has coordinates ((x1, y1, f(x1, y1)), (x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),( The specified surface is the xy plane, and the rectangular area is represented by four points, x2, y2, f(x2, y2), The area of ​​the rectangle projected onto the surface is S0, and the height of the reference surface (the average height of the specified surface) is Z0. a is taken with an atomic force microscope (AFM). It is measurable.

[0044] As shown in FIG. 1B, the oxide semiconductor film 103 has an end portion with a tapered angle of 20° to 50°. When the edge of the oxide semiconductor film 103 is vertical, the oxide semiconductor Oxygen is easily removed from the conductive film 103, which easily causes oxygen vacancies. By providing a taper at the portion, the occurrence of oxygen vacancies is suppressed, and the leakage current of the transistor 110 is reduced. The occurrence of can be reduced.

[0045] The oxide semiconductor used for the oxide semiconductor film 103 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. In addition, a stabilizer for reducing variations in electrical characteristics of a transistor using the oxide semiconductor is provided. In addition to these, gallium (Ga), tin (Sn), hafnium (Hf), Zirconium (Zr), Titanium (Ti), Scandium (Sc), Yttrium (Y), Lanthanides (e.g., cerium (Ce), neodymium (Nd), gadolinium (Gd)) It is preferable that one or more selected from the following are included.

[0046] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides In-Ti-Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, I n-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In -Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In- Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Y b-Zn oxide, In-Lu-Zn ​​oxide, and oxides of quaternary metals In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn based oxides can be used.

[0047] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. Metal elements may also be included.

[0048] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. Indicates one or more metal elements, or the above-mentioned elements as stabilizers In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0049] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In In:Ga:Zn oxides with an atomic ratio of Ga:Zn=2:1:3 and oxides with similar compositions It is a good idea to use compounds.

[0050] The gate insulating film 102 is preferably made of an oxide insulating film having sufficient voltage resistance and insulating properties. When the gate insulating film 102 has a single-layer structure, for example, silicon oxide is used. An insulating film containing an oxide containing silicon may be used.

[0051] The gate insulating film 102 may have a stacked structure. In the case of gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxynitride, Oxide on aluminum, yttrium oxide, lanthanum oxide or silicon oxynitride, etc. Silicon can be layered. Hafnium oxide and hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0) Silicon oxide can be layered on top of high-k materials such as silicon dioxide. By using this, the gate leakage current can be reduced.

[0052] By using an oxide insulating film as the gate insulating film 102, the oxide insulating film can be heated. Since part of oxygen can be released by the above reaction, oxygen can be released from the oxide semiconductor film 103. By supplying oxygen, oxygen vacancies in the oxide semiconductor film 103 can be compensated for. It is preferred that oxygen be present in the film 102 (bulk) in an amount at least greater than the stoichiometric ratio. For example, the gate insulating film 102 is made of SiO 2+α (where α>0) It is preferable to use a silicon oxide film. By using the oxide semiconductor film 103 as the oxide semiconductor film 2, oxygen can be supplied to the oxide semiconductor film 103. The transistor characteristics of the transistor 110 using the semiconductor film 103 can be improved. do.

[0053] However, when a silicon oxide film is used as the gate insulating film 102, Silicon in the oxide semiconductor film 102 may be taken into the oxide semiconductor film 103 as an impurity. By incorporating silicon or the like as impurities into the nitride semiconductor film 103, In addition, impurities in the vicinity of the surface where the oxide semiconductor film 103 is formed may affect the characteristics of the capacitor. When impurity elements are introduced, the crystallization of the oxide semiconductor film is inhibited by the impurity elements. As a result, an amorphous region remains in the vicinity of the surface where the oxide semiconductor film is to be formed. In addition, in the case where the oxide semiconductor film 103 is a CAAC-OS film, It becomes difficult to form crystal parts.

[0054] In particular, the oxide semiconductor film 103 is covered with the gate insulating film 102 at a portion where the oxide semiconductor film 103 and the gate insulating film 102 are in contact with each other. Impurities such as silicon are easily introduced into the oxide semiconductor film 103 in the vicinity of the formation surface. Since the channel formation region of the transistor 110 is formed near the formation surface, If impurities such as silicon are introduced nearby, the characteristics of the transistor 110 will change. There is a risk of injury.

[0055] Here, the oxide semiconductor film 103 is formed of SiO2, which is an oxide containing silicon as an impurity. The structural changes that occur when the compound is added are investigated using classical molecular dynamics calculations. The results of the calculation will be explained with reference to Figs. 21 to 25. The molecular dynamics calculation software used was Fujitsu Ltd.'s SCIGRESS ME. In classical molecular dynamics, we define an empirical potential that characterizes the interatomic interactions. By numerically solving Newton's equations of motion, we can evaluate the forces acting on each atom. , the motion (time evolution) of each atom can be tracked deterministically.

[0056] The calculation model and calculation conditions are described below. The r-Huggins potential was used.

[0057] As a calculation model, a single crystal structure of 1680 atoms of InGaZnO4 (see Figure 21(A)) And 20 atoms each of In, Ga, and Zn of 1680 atoms of InGaZnO4 are silicided. A structure was created in which the cations were replaced with Si atoms (see FIG. 21(B)). In the silicon (Si) substitution model, silicon (Si) is 3.57 atom% (2. 34% by weight. The density of the single crystal model shown in FIG. 21(A) is 6.36 g / cm m 3 The density of the silicon (Si) substituted model shown in FIG. 21(B) is 6.08 g / c m 3 It is.

[0058] For the calculation model shown in Fig. 21(A) and Fig. 21(B), At 1727°C, which is lower than the melting point (estimated to be about 2000°C by classical molecular dynamics calculations), At a constant pressure (1 atm), the time interval was 150 psec (time step width 0.2 fsec x 750,000 The structure was relaxed by classical molecular dynamics calculations (step). The radial distribution function g(r) was calculated for the ion-distribution function g(r). This function expresses the probability density that another atom exists at a distance r from the atom. As the correlation between the two decreases, g(r) approaches 1.

[0059] The above two calculation models were obtained by performing classical molecular dynamics calculations for 150 psec. The final structures are shown in Figures 22(A) and 22(B), respectively. The radial distribution function g(r) in is shown in FIG.

[0060] The single crystal model shown in Figure 22(A) is stable and maintains its crystalline structure in the final structure. The silicon (Si) substitution model shown in FIG. 22(B) is unstable, and the crystal structure changes over time. It can be seen that the structure of the crystalline structure collapses and changes to an amorphous structure. By comparing the radial distribution function g(r) of each structural model, the single crystal model shows that the On the other hand, in the silicon (Si) substituted model, , the peak disappears around 0.6 nm, indicating that there is no long-range order.

[0061] These calculation results show that the inclusion of silicon (Si) in InGaZnO4 results in It was suggested that the amorphization of InGaZnO4 was likely to occur. Even if aZnO4 containing silicon (Si) is heated at high temperatures, InGaZnO4 It was confirmed that no crystallization occurred.

[0062] Next, what kind of structural change occurs when carbon atoms (C) are added to the oxide semiconductor film 103? The results of the classical molecular dynamics calculations are shown in Fig. 21(A) and Fig. 2 4 and 25. In order to perform the above calculations, classical molecular dynamics calculation software is used. The software used was SCIGRESS ME manufactured by Fujitsu Ltd.

[0063] The calculation model and the calculation results are described below. The r-Huggins potential was used. In addition, the interatomic interaction with the carbon atom (C) was used the Lennard-Jones potential.

[0064] As a calculation model, a single crystal structure of 1680 atoms of InGaZnO4 (see Figure 21(A)) and 1680 atoms of InGaZnO4, 20 atoms each of In, Ga, and Zn are carbon. The structure in which 80 oxygen (O) atoms have been replaced with carbon atoms (C) (Figure 24( In the carbon (C) substitution model shown in FIG. 24(A), the carbon atom ( C) is 8.33 atom %. The density of the single crystal model shown in FIG. 21(A) is 6.36g / cm 3 The density of the carbon (C) substitution model shown in FIG. 24(A) is 5.8 9g / cm 3 It is.

[0065] For the calculation models shown in Fig. 21(A) and Fig. 24(A), At 1727°C, which is lower than the melting point (estimated to be about 2000°C by classical molecular dynamics calculations), The pressure was constant (1 atm) for 140 psec (time step width 0.2 fsec x 750,000 steps). The structure was relaxed by classical molecular dynamics calculations (step 1). The radial distribution function g(r) was calculated by the following equation. This is a function that represents the probability density of the existence of another atom at a distance r. As the correlation disappears, g(r) approaches 1.

[0066] The above two calculation models were obtained by performing classical molecular dynamics calculations for 150 psec. The final structures are shown in FIG. 22(A) and FIG. 24(B), respectively. The radial distribution function g(r) in the structure is shown in FIG.

[0067] The single crystal model shown in Figure 22(A) is stable and maintains its crystalline structure in the final structure. However, the carbon (C) substitution model shown in FIG. 24(B) is unstable, and the crystal structure collapses over time. It can be seen that the structure changes to an amorphous structure. Comparing the radial distribution function g(r) of the structural models, the single crystal model has a peak even at long distances. On the other hand, in the carbon (C) substituted model, the order is 0.6 nm. The peak disappears near the center, indicating the absence of long-range order.

[0068] These calculation results show that the inclusion of carbon (C) in InGaZnO4 results in It was suggested that GaZnO4 becomes more likely to become amorphous. Even if InGaZnO4 contains carbon (C) and is heated at high temperatures, it will not crystallize. It was confirmed that there was no

[0069] As described above, the incorporation of impurities into the oxide semiconductor film Therefore, in the semiconductor device described in this embodiment, The incorporation of impurities such as silicon into the vicinity of the surface on which the compound semiconductor film is to be formed is suppressed. As a result, in the oxide semiconductor film 103, the oxide semiconductor A region in which silicon is distributed at a concentration of 1.0 atomic % or less is formed toward the film 103. The region is indicated as region 103a. The concentration of silicon contained in region 103a is 0.1 atomic percent. It is more preferable that the concentration of the oxide is less than 10%. The thickness of these layers is in the range of 5 nm or less.

[0070] Note that a region other than the region 103a of the oxide semiconductor film 103 is denoted as a region 103b. The concentration of silicon contained in the region 103b is smaller than the concentration of silicon contained in the region 103a. It becomes smaller.

[0071] Furthermore, when the gate insulating film 102 contains impurities such as carbon, these also become undesirable due to the presence of silicon. Similarly, there is a risk that the oxide semiconductor film 103 may be taken in as an impurity. The carbon concentration in 03a is 1.0×10 20 atoms / cm 3 More preferably, 1.0×10 19 atoms / cm 3 The following applies.

[0072] In this way, impurities such as silicon are taken into the region 103a of the oxide semiconductor film 103. By reducing the concentration of, it is possible to suppress the fluctuation of the characteristics of the transistor 110. In addition, the oxide semiconductor film 103 can be crystallized up to the vicinity of the surface where the oxide semiconductor film 103 is to be formed. When the compound semiconductor film 103 is a CAAC-OS film, the crystal part is formed up to the vicinity of the surface on which the film is to be formed. By manufacturing a transistor using such an oxide semiconductor film, As a result, a semiconductor device having stable electrical characteristics can be obtained.

[0073] Note that the details of the other components will be described in the manufacturing method of the transistor 110 described later. This will be described with reference to FIG. 4(A) to FIG. 4(E).

[0074] Note that a planarization insulating film may be further provided over the transistor 110. In order to electrically connect the source electrode 105a and the drain electrode 105b to the wiring, An opening may be formed in the insulating film 102, the protective insulating film 109, etc. A second gate electrode is formed in a region above the semiconductor film 103 that overlaps with the gate electrode 101. The electrode may have a pole.

[0075] 2(A) and 2(B) show the transistor 1 shown in FIG. 1(A) and FIG. 1(B). 2A shows a plan view of a transistor 120, and FIG. ) is a cross-sectional view of the CD cross section in FIG. 2(A). In order to prevent this, some of the components of the transistor 120 (for example, the protective insulating film 1 09, etc.) are omitted.

[0076] The transistor 120 shown in FIG. 2A and FIG. 2B is a transistor including a substrate 100 having an insulating surface. On the top, a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, and a gate insulating film 1 The oxide semiconductor film 1 is provided in a region that is in contact with the gate electrode 102 and overlaps with at least the gate electrode 101. 03, a source electrode 105a and a drain electrode electrically connected to the oxide semiconductor film 103 105b, covering the oxide semiconductor film 103, the source electrode 105a and the drain electrode 105b. The transistor 120 includes a protective insulating film 109. The point is that the protective insulating film 109 is made of an oxide containing silicon, similar to the gate insulating film 102. The insulating film 109 is formed by using an insulating film containing a fluorine atom and a fluorine atom. It is a point having area 103c nearby.

[0077] The oxide semiconductor film 103 of the transistor 120 includes regions 103a to 103c. The region 103a is a region in the oxide semiconductor film 103 that is adjacent to the interface with the gate insulating film 102. This region is one in which silicon is distributed toward the nitride semiconductor film 103 at a concentration of 1.0 atomic % or less. The region 103a is present in a range of 5 nm or less from the interface with the gate insulating film 102. In addition, the region 103c is preferably a region that is adjacent to the protective insulating film 1 in the oxide semiconductor film 103. Silicon is distributed from the interface with the oxide semiconductor film 109 toward the oxide semiconductor film 103 at a concentration of 1.0 atomic % or less. The region 103c is a region in which the thickness from the interface with the protective insulating film 109 is 5 nm or less. In addition, the region 103a and the region 103b of the oxide semiconductor film 103 are preferably in the range of 103a. The area other than the area 103c is referred to as an area 103b.

[0078] The concentration of silicon contained in the region 103b is different from the concentration of silicon contained in the region 103a. The concentration of silicon in the region 103a is less than 0.1 atomic percent. It is more preferable that:

[0079] Here, the concentration of silicon contained in the region 103a is set to 1.0 atomic % or less, preferably 0.1 % or less, and the concentration of silicon contained in the region 103c is also 1.0 atomic % or less, preferably The concentration of silicon in the region 103b is set to 0.1 atomic % or less. , the concentration of silicon contained in the region 103a and the region 103c is smaller than that of the silicon contained in the region 103a and the region 103c.

[0080] In this manner, even in the region 103c corresponding to the back channel of the oxide semiconductor film 103, By reducing the concentration of impurities such as silicon, the electrical characteristics of the transistor 120 can be improved. Fluctuations can be suppressed.

[0081] The other components are similar to those of the semiconductor device shown in FIG. 1(A) and FIG. 1(B). For details, please refer to the descriptions of Figures 1(A) and 1(B).

[0082] The transistors shown in FIGS. 1 and 2 are so-called channel-etched transistors. However, the semiconductor device described in this embodiment is not limited to this. 3(B) shows a channel stop type transistor different from the transistors shown in Figs. 3A shows a configuration example of the resistor 130. FIG. 3A is a plan view, and FIG. 3B shows the configuration example of the resistor 130 shown in FIG. 3A is a cross-sectional view of the E-F cross section in FIG. Therefore, some of the components of the transistor 130 (such as the protective insulating film 109) are omitted. In addition, in FIG. 3(A), the shape of the channel protective film 108 is illustrated in order to facilitate understanding. It is shown three-dimensionally.

[0083] The transistor 130 shown in FIG. 3A and FIG. 3B is a transistor including a substrate 100 having an insulating surface. On the top, a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, and a gate insulating film 1 The oxide semiconductor film 1 is provided in a region that is in contact with the gate electrode 102 and overlaps with at least the gate electrode 101. 03, a channel protective film 108 provided on and in contact with the oxide semiconductor film 103, A source electrode 105a and a source electrode 105b are provided on the film 108 and electrically connected to the oxide semiconductor film 103. and the drain electrode 105b, and the oxide semiconductor film 103, the source electrode 105a, and The oxide semiconductor film 103 includes a protective insulating film 109 that covers the drain electrode 105b. The transistor 110 has a region 103a and a region 103b. The transistor 130 differs from the transistor 110 in that it has a channel protection film 108. .

[0084] The channel protection film 108 is preferably an inorganic insulating film containing oxygen. For example, , silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film Insulating films such as a gallium oxide film and a hafnium oxide film can be used. The thickness of the protective film 108 is preferably 5 nm or more and 300 nm or less.

[0085] In this manner, by providing the channel protective film 108 on and in contact with the oxide semiconductor film 103, The source electrode 105a and the drain electrode 105b are etched to form the oxide semiconductor film 1 Damage to the back channel side of 03 (e.g., plasma or etchant during etching) This prevents damage caused by the adhesive. can be made stable.

[0086] As shown in FIG. 3B, the channel protection film 108 has an inclination angle of 10° to 60° at the end. It is preferable that the channel protection film 108 has a taper. This can reduce the electric field concentration in the vicinity of the bottom end of the channel protection film 108. .

[0087] The other components are similar to those of the semiconductor device shown in FIG. 1(A) and FIG. 1(B). For details, please refer to the descriptions of Figures 1(A) and 1(B).

[0088] <Example of the transistor manufacturing process> Hereinafter, an example of a manufacturing process of the transistor shown in FIGS. 1 to 3 will be described with reference to FIGS. He explains.

[0089] <Fabrication process of transistor 110> An example of a manufacturing process of the transistor 110 shown in FIG. 1 will be described with reference to FIGS. 4A to 4E. We will explain about this.

[0090] First, a substrate 100 having an insulating surface is prepared. There is no particular restriction on the substrate that can be used, but it must be at least heat-resistant enough to withstand the subsequent heat treatment. For example, barium borosilicate glass and aluminoborose glass are Substrates such as glass substrates such as fluorine glass, ceramic substrates, quartz substrates, and sapphire substrates are used. In addition, a single material such as silicon or silicon carbide can be used as long as it has an insulating surface. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, S An OI substrate or the like can also be used.

[0091] A flexible substrate may be used as the substrate 100. A transistor including the oxide semiconductor film 103 may be directly formed on a substrate. A transistor including an oxide semiconductor film 103 is formed on a substrate, and then the transistor is peeled off and transferred to a flexible substrate. In order to separate and transfer the film from the formation substrate to the flexible substrate, the formation substrate and the oxide film may be A peeling layer may be provided between the transistor including the semiconductor film 103 and the semiconductor film 103 .

[0092] An insulating film serving as a base film may be provided between the substrate 100 and the gate electrode 101. It has a function of preventing the diffusion of impurity elements such as hydrogen and moisture from the substrate 100. a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film; can be formed by a laminated structure of a plurality of films.

[0093] Next, a gate electrode (including wiring formed in the same layer as the gate electrode) is formed on the substrate 100. The conductive film used for the gate electrode is, for example, molybdenum, Metals such as titanium, tantalum, tungsten, aluminum, copper, neodymium, and scandium The gate electrode may be made of a material selected from the group consisting of fluorine, fluorine-containing ... The conductive film may be formed using a conductive metal oxide. Examples include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and indium oxide (InO3). Indium tin oxide (In2O3-SnO2, sometimes abbreviated as ITO), In2O3-ZnO, or these metal oxide materials with silicon or The gate electrode can be made of the above materials. The method for forming the layer is not particularly limited, and examples thereof include a deposition method, Various film formation methods such as CVD, sputtering, and spin coating can be used. .

[0094] Next, a resist mask is formed on the conductive film by a photolithography process, and selectively etched. After etching is performed to form the gate electrode 101, the resist mask is removed. A resist mask for forming the gate electrode 101 may be formed by an ink-jet method. If the resist mask is formed by the inkjet method, no photomask is used, so manufacturing The cost can be reduced. The gate electrode 101 can be etched by dry etching or wet etching. Alternatively, wet etching may be used, or both may be used.

[0095] Next, a gate insulating film 102 is formed to cover the gate electrode 101 (see FIG. 4(A)). Here, the thickness of the gate insulating film 102 can be set to, for example, 1 nm or more and 500 nm or less. The method for forming the gate insulating film 102 is not particularly limited. For example, sputtering The gate insulating film is formed by using the appropriate method such as the annealing method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc. 102 can be created.

[0096] The gate insulating film 102 is preferably made of an oxide insulating film having sufficient voltage resistance and insulating properties. When the gate insulating film 102 has a single-layer structure, for example, silicon oxide is used. An insulating film containing an oxide containing silicon may be used.

[0097] The gate insulating film 102 may have a stacked structure. In the case of gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxynitride, Oxide on aluminum, yttrium oxide, lanthanum oxide or silicon oxynitride, etc. Silicon can be layered. Hafnium oxide and hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0) Silicon oxide can be layered on top of high-k materials such as silicon dioxide. By using this, the gate leakage current can be reduced.

[0098] By using an oxide insulating film as the gate insulating film 102, the Since part of oxygen in the oxide insulating film can be released, the oxide semiconductor film 103 can be deoxygenated. In particular, oxygen vacancies in the oxide semiconductor film 103 can be compensated for by supplying oxygen to the gate The presence of oxygen in the insulating film 102 (bulk) at least exceeds the stoichiometric ratio. For example, the gate insulating film 102 is preferably made of SiO 2+α (where α>0) It is preferable to use a silicon oxide film that can be used as a gate insulating film. By using the oxide semiconductor film 102 as the oxide semiconductor film 103, oxygen can be supplied to the oxide semiconductor film 103. The transistor characteristics of the transistor 110 using the nitride semiconductor film 103 can be improved. can.

[0099] In addition, before the oxide semiconductor film 103 is formed, the gate insulating film 102 is subjected to planarization treatment. The planarization process is not particularly limited, but may be a dry etching process, a plasma process, or the like. Treatment such as polishing (for example, chemical mechanical polishing) can be used.

[0100] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the oxide semiconductor film 103 is formed, powdery substances (particles) adhering to the film formation surface of the oxide semiconductor film 103 are removed. , also called garbage) can be removed.

[0101] As the planarization process, dry etching, plasma processing, and polishing may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. The thickness is not limited to a specific value and may be appropriately set depending on the unevenness of the surface on which the oxide semiconductor film 103 is formed.

[0102] In addition, in the process of forming the oxide semiconductor film 103, hydrogen or water is added to the oxide semiconductor film 103. In order to prevent the inclusion of as much as possible, the oxide semiconductor film 103 was formed by a pretreatment process. The substrate 100 on which the gate insulating film 102 is formed is preheated in a preheating chamber of the sputtering device. The substrate 100 and the gate insulating film 102 are heated to remove impurities such as hydrogen and moisture adsorbed thereon. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. It is nice.

[0103] Next, a film having a thickness of 5 nm or more and 200 nm or less, preferably 1 The oxide semiconductor film 103 is formed to a thickness of 0 nm to 30 nm (see FIG. 4B). The semiconductor film 103 preferably has a crystalline structure such as single crystal or microcrystal. The oxide semiconductor film 103 is preferably a CAAC-OS film. The oxide insulating film 102 and the oxide semiconductor film 103 were successively formed without being exposed to the air. It is preferable to do so.

[0104] In this embodiment, an In-Ga-Zn-based oxide target is used as the oxide semiconductor film 103. The oxide semiconductor film 103 is formed by a sputtering method using a rare gas (typically In general, the gas is heated in an atmosphere of argon, oxygen, or a mixture of rare gas and oxygen. It can be formed by a sputtering method.

[0105] In order to form an In-Ga-Zn-O film as the oxide semiconductor film 103 by a sputtering method, The target is, for example, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. The target has an atomic ratio of In:Ga:Zn=3:1:2, and the target has an atomic ratio of An oxide target with In:Ga:Zn=2:1:3 can be used. The target for forming the semiconductor film 103 by sputtering is one of these targets. The materials and compositions of the materials are not limited to those mentioned above.

[0106] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and 96% or less. By using an oxide target with a high relative density, the oxide film formed The compound semiconductor film 103 can be a dense film.

[0107] The sputtering gas used in forming the oxide semiconductor film 103 may be hydrogen, water, a hydroxyl group, or a fluorine-containing gas. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0108] In the case where a CAAC-OS film is used as the oxide semiconductor film 103, the CAAC-OS film There are three heat treatment methods for forming the film. The first is to set the film formation temperature at 200°C or higher. By forming the oxide semiconductor film at a temperature of 450° C. or lower, The second method is to form crystals whose c-axes are aligned perpendicular to the surface. After forming a thin film of the compound semiconductor, a heat treatment is performed at a temperature between 200 and 700°C. A crystal part in which the c-axis is aligned perpendicular to a surface or a surface of the oxide semiconductor film is formed. The third method is to deposit a thin oxide semiconductor film on the first layer and then heat it at 200°C or higher for 7 Then, a heat treatment is performed at 00° C. or less, and a second oxide semiconductor film is formed. A method for forming crystals whose c-axes are aligned perpendicular to the surface or surface of a semiconductor film. It is.

[0109] In addition, by forming the oxide semiconductor film 103 while heating the substrate 100, It is possible to reduce the concentration of impurities such as hydrogen and water contained in the material. This is preferable because it reduces damage caused by the

[0110] Note that the oxide semiconductor film 103 may be a crystalline oxide semiconductor film other than a CAAC-OS film. When a solid film (monocrystalline or microcrystalline) is formed, the film formation temperature is not particularly limited.

[0111] In the case where a CAAC-OS film is used as the oxide semiconductor film 103, for example, A semiconductor oxide sputtering target is used to form the film by sputtering. When ions collide with the sputtering target, the ions are released from the sputtering target. The crystal region cleaved from the ab plane forms a plate or pellet with a plane parallel to the ab plane. In this case, the plate-like sputtering particles may peel off. The ring particles reach the substrate while maintaining their crystalline state, forming a CAAC-OS film. It is possible.

[0112] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0113] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0114] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0115] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0116] As an example of a sputtering target, a polycrystalline In-Ga-Zn oxide target is used. The details are shown below.

[0117] The polycrystalline In-Ga-Zn oxide target is InO X powder, GaO Y Powder and Z nO Z The powders are mixed in a specified number of moles, pressurized, and then heated at a temperature between 1000°C and 1500°C. It can be obtained by heat treatment at 35°C. Note that X, Y, and Z are any positive numbers. , InO X powder, GaO Y Powder and ZnO Z The mole ratio of the powder is, for example, 2:2:1. , 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. The above can be changed as necessary.

[0118] Then, the remaining moisture in the film formation chamber is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. The oxide semiconductor film 103 is formed on the substrate 100 by using the above target. To remove residual moisture, adsorption-type vacuum pumps, such as cryopumps and ion pumps, are used. It is preferable to use a pump or a titanium sublimation pump as the exhaust means. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (preferably The oxide semiconductor film formed in the film formation chamber is The concentration of impurities such as hydrogen and water contained in the body membrane 103 can be reduced.

[0119] When the oxide semiconductor film 103 is formed by a sputtering method, When particles constituting the gate insulating film 103 collide with the gate insulating film 102, The elements constituting the oxide semiconductor film 103 are mixed with each other (mixing, mixing This mixing phenomenon occurs when the oxide semiconductor near the interface with the gate insulating film 102 is mixed with the This is particularly noticeable in the membrane 103, specifically in the above-mentioned region 103a. In the transistor described in the embodiments, the oxide semiconductor film 103 in the vicinity of the gate insulating film 102 Since the channel region is formed in the gate insulating film 102, the elements constituting the gate insulating film 102 do not become impurities in the region. By mixing it as a substance, it degrades the on-characteristics (e.g. on-current) of the transistor. This could be a factor in causing this.

[0120] Here, when the oxide semiconductor film 103 is formed on the gate insulating film 102, Regarding the possibility of mixing occurring in the vicinity of the interface between the oxide semiconductor film 102 and the oxide semiconductor film 103, The results of the investigation using classical molecular dynamics calculations are explained below. The molecular dynamics calculation software used was Fujitsu Ltd.'s SCIGRESS ME. Ta.

[0121] An amorphous silicon oxide film (hereinafter referred to as a-SiO2) is used as the gate insulating film. The model shown in Figure 6 was created. The size of the unit cell for calculation (calculation unit cell) is The x-axis and y-axis directions are 3 nm, 3 nm, and 7.5 nm, respectively. The z-axis is the direction parallel to the a-SiO2 film, and the z-axis is the thickness direction of the a-SiO2 film. In the calculation, periodic boundary conditions are applied in the x-axis and y-axis directions. We assumed that the membrane was sufficiently wide in the y-axis direction.

[0122] Next, indium atoms, gallium atoms, and Zinc atoms and oxygen atoms are arranged in a ratio of 1:1:1:4 (total of 840 atoms) from the top (Figure 6, original The temperature was set to 300°C and the time was set to 2 nsec (time step width Classical molecular dynamics calculations were performed with a time delay of 0.2 fs and a step number of 10 million.

[0123] The results of the above calculation are shown in Figures 7 and 8. Figure 7(A) shows the oxygen atom and The arrangement of silicon atoms is shown in Fig. 7(B), and the arrangement of oxygen atoms, silicon atoms, and gas atoms after 1 nsec is shown in Fig. 7(C). Fig. 7(C) shows the arrangement of oxygen, silicon, and zinc atoms after 2 nsec. FIG. 8(A) shows the arrangement of a Zn atom, a Ga atom, and a Zinc atom. The arrangement of oxygen atoms, silicon atoms, gallium atoms, and zinc atoms after the reaction is shown in FIG. 8(B). FIG. 8(C) shows the arrangement of only silicon atoms after 2 nsec. The arrangement of ammonium, gallium, and zinc atoms is shown.

[0124] The arrangement of silicon atoms only shown in FIG. 8(B) and the arrangement of indium and gallium atoms shown in FIG. 8(C) By comparing the arrangement of the silicon atoms with that of the zinc atoms, It was confirmed that aluminum atoms, gallium atoms, and zinc atoms had penetrated the material.

[0125] From the results of the above calculations, indium atoms, gallium atoms, and zinc atoms with energies of 1 eV By injecting electrons and oxygen atoms into the a-SiO2 film, the a-SiO2 film and the IGZ Between the O film and the silicon atoms, indium atoms, gallium atoms, zinc atoms, and oxygen atoms It was shown that a layer of mixed

[0126] From the above results, it was found that a layer in which the oxide semiconductor film 103 and the gate insulating film 102 were mixed was formed. In order to prevent this, the particles constituting the oxide semiconductor film 103 should be prevented from colliding with the gate insulating film 102. For example, the power for forming the oxide semiconductor film 103 is reduced. There is a method to increase the deposition pressure. Or, the distance between the target and the substrate (hereafter referred to as T- (also written as S distance.) may be widened.

[0127] As described above, the mixing by sputtering is performed near the interface with the gate insulating film 102. This may occur in the oxide semiconductor film 103 adjacent thereto. Sputtering is performed by weakening the force with which the particles collide with the gate insulating film 102. If the collision effect is reduced and the oxide semiconductor film is formed near the interface, the collision For example, the deposition power for the oxide semiconductor film 103 may be reduced to increase the velocity of the boundary. The oxide semiconductor film is formed near the surface, and then the film formation power is increased to form the oxide semiconductor film. In addition, the deposition pressure of the oxide semiconductor film 103 may be increased to prevent the oxide semiconductor film 103 from being formed in the vicinity of the interface. Alternatively, a silicon oxide film may be formed first, and then an oxide semiconductor film may be formed by lowering the film formation pressure. The distance between the TS of the oxide semiconductor film 103 is increased to form an oxide semiconductor film in the vicinity of the interface. Then, the TS distance may be narrowed and an oxide semiconductor film may be formed.

[0128] The specific value of the film formation power is 5 kW or less, preferably 1 kW or less, and more preferably It is desirable to set the film formation power to 500 W or less, and more preferably to 200 W or less. As the deposition power decreases, the deposition rate of the oxide semiconductor film 103 decreases. If it is too low, it will be difficult to generate plasma in the sputtering device, and film formation will not be performed normally. Therefore, the deposition power should be applied by the sputtering equipment used. It is desirable to set the power to 5% or more of the maximum power that can be used. In this case, the deposition is performed in a proper manner in consideration of the performance of a sputtering apparatus, the thickness of the oxide semiconductor film 103, and the like. The deposition time is the same as the manufacturing process (takt time) of the transistor 110. The implementer may select an appropriate optimum power value within a range that does not significantly affect the power consumption.

[0129] The specific value of the film formation pressure is 0.4 Pa or more, preferably 1.0 Pa or more. It is more preferable that the pressure is 2.0 Pa or more, and further preferably 5.0 Pa or more. In addition, the higher the deposition pressure, the worse the quality of the deposited film becomes (for example, the film becomes sparse). For this reason, it is desirable to keep the deposition pressure at 100 Pa or less. The extent to which the force should be increased depends on the characteristics required for the oxide semiconductor film 103 (e.g., The practitioner may select an appropriate pressure value in consideration of the characteristics of the electrode (e.g., field effect mobility, etc.).

[0130] The specific value of the distance between the TSs is 30 mm or more, preferably 50 mm or more. It is more preferable that the distance is 100 mm or more, and further preferably 300 mm or more. Note that the deposition rate of the oxide semiconductor film 103 decreases as the TS distance increases. For this reason, it is desirable to set the TS distance to 500 mm or less. The extent to which the film formation time is extended depends on the manufacturing process of the transistor 110 (takt time ) within the range that does not have a significant impact on the implementation, the implementer can select the optimal TS distance as appropriate. Good.

[0131] In addition, in order to reduce the force with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102, In order to achieve this, one of the conditions, deposition power, deposition pressure, or TS distance, must be within the above range. Alternatively, the oxide semiconductor film 103 may be formed under the above-mentioned conditions. A semiconductor film 103 may be formed.

[0132] The sputtering device used was a magnetron with a target and a substrate on which a film was to be formed, which were set approximately parallel to each other. When using a magnetron sputtering device (also simply called a magnetron sputtering device), In this case, the gate insulating film 102 contains not only particles constituting the oxide semiconductor film 103 but also plasma and Since secondary electrons and the like collide with each other, the elements constituting the gate insulating film 102 are Therefore, the oxide semiconductor film 103 is easily mixed into the oxide semiconductor film 103. The sputtering equipment used is a facing target type sputtering equipment (mirror tron ​​sputtering). The device is also called a target device. The substrate to be coated is placed in a space other than the space between the two targets. The targets are set almost perpendicular to the surface of the target. Plasma is generated, and the target (used for forming the oxide semiconductor film 103) is heated by the plasma. The surface of the target is sputtered to form an oxide semiconductor film 10 on the deposition substrate. Therefore, the substrate on which the film is to be formed is not directly exposed to plasma or secondary electrons. (or very little).

[0133] In addition, when the oxide semiconductor film 103 is formed by sputtering in a rare gas atmosphere, the oxide semiconductor film 103 is preferably formed in an argon atmosphere. Helium may be used instead of argon. Helium has a smaller atomic weight than argon. As a result, the force with which particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 is weakened. Furthermore, in the vicinity of the interface between the oxide semiconductor film 103 and the gate insulating film 102, After the deposition of the film was performed in a helium atmosphere, the deposition chamber was switched to an argon atmosphere. In this case, the deposition speed of the oxide semiconductor film 103 can be increased.

[0134] The oxide semiconductor film 103 is formed by ALD (Atomic Layer Deposition). The film may be formed by a method that causes less impact on the gate insulating film 102, such as a deposition method, a vapor deposition method, or a coating method. stomach.

[0135] As described above, the force with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 By forming the oxide semiconductor film 103 with the weaker heat treatment, the oxide semiconductor film 10 In FIG. 3, silicon is introduced from the interface with the gate insulating film 102 toward the oxide semiconductor film 103. A region 103a having a concentration of 1.0 atomic % or less and a region 103b having a concentration of 1.0 atomic % or less. Here, the region 103b is a region in the oxide semiconductor film having a low concentration of fluorine. The region other than the region 103a of 103. Also, silicon included in the region 103a The concentration is more preferably 0.1 atomic % or less.

[0136] In addition, by forming the oxide semiconductor film 103 in this manner, the oxide semiconductor film 103 contained in the gate insulating film 102 The incorporation of impurities such as carbon into the oxide semiconductor film 103 is also reduced. Thus, the carbon concentration in the region 103a is 1.0×10 20 atoms / cm 3 below, More preferably, 1.0×10 19 atoms / cm 3 The result is as follows.

[0137] In addition, a CAAC-OS film is formed as the oxide semiconductor film 103 while heating (first In the case of the above method, the amount of impurities such as silicon taken into the region 103a is reduced. In other words, the oxide semiconductor film is formed on the surface of the oxide semiconductor film or on the surface of the oxide semiconductor film. It is possible to form a crystal part in which the c-axis is aligned perpendicular to the surface.

[0138] In addition, the force with which particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 is weakened. The oxide semiconductor film 103 is formed by depositing the oxide semiconductor in the gate insulating film 102. This also prevents the elements constituting the gate insulating film 102 from being mixed in. In order to prevent this, a highly conductive element such as a metal element constituting the oxide semiconductor film 103 is mixed into the Since the above can be suppressed, a decrease in the resistivity of the gate insulating film 102 can be prevented.

[0139] After the oxide semiconductor film 103 is formed, the oxide semiconductor film 103 is subjected to heat treatment. The temperature of the heat treatment is set to 200° C. or higher and 700° C. or lower, or lower than the distortion point of the substrate. By carrying out this heat treatment, it is possible to remove excess hydrogen (including water and hydroxyl groups). be.

[0140] In addition, when the CAAC-OS film is formed by the second or third method, By performing the heat treatment, the c-axis of the oxide semiconductor film is perpendicular to the surface on which the oxide semiconductor film is formed or the surface of the oxide semiconductor film. In addition, the crystals in the region 1 of the oxide semiconductor film 103 are aligned in a vertical direction. In the oxide semiconductor film 103a, the concentration of impurities such as silicon is reduced. The crystal portion can be formed up to the vicinity of the surface on which the crystal is to be formed.

[0141] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element or the like and heating the workpiece in a nitrogen atmosphere. During this time, the oxide semiconductor film 103 is exposed to the air. Do not allow it to come into contact with water or hydrogen, and avoid contamination.

[0142] The heat treatment device is not limited to an electric furnace, and may be heat conducted from a medium such as a heated gas or heat radiation. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a light bulb. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. Inert gases such as rare gases or nitrogen that do not react with the workpiece during heat treatment are used. Used.

[0143] For example, the heat treatment may involve placing the workpiece in a heated inert gas atmosphere for several minutes. After heating, the workpiece may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA processing allows high-temperature heat treatment in a short time. The present invention can be applied even under temperature conditions exceeding 100°C. During the treatment, inert gas is used instead of oxygen. It is also possible to switch to a gas containing

[0144] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0145] After the oxide semiconductor film 103 is heated by the heat treatment, high-purity oxygen gas and Nitrous oxide gas, high purity nitrous oxide gas, or ultra dry air (CRDS (cavity reflow desiccant) When measured using a dew point meter using the down-down laser spectroscopy method, the moisture content was 20 ppm ( (-55°C in dew point equivalent) or less, preferably 1 ppm or less, more preferably 10 ppb or less Air) may be introduced. The oxygen gas or nitrous oxide gas must not contain water, hydrogen, etc. Alternatively, it is preferable that the oxygen gas or the nitrous oxide gas introduced into the heat treatment device is pure. The concentration is 6N or more, preferably 7N or more (i.e., impurities in oxygen gas or nitrous oxide gas) It is preferable to keep the concentration at 1 ppm or less, preferably 0.1 ppm or less. The oxide semiconductor that was reduced by the heat treatment was removed by the action of nitrous oxide gas. By supplying oxygen, which is the main component of the conductor, the oxide semiconductor film can be grown to a high purity. It can be made into type i (intrinsic) or type i (intrinsic).

[0146] In addition, when the CAAC-OS film is formed by the third method, an oxide semiconductor is further added. As a result, the oxide semiconductor film is aligned in a c-axis direction with respect to the surface on which the oxide semiconductor film is to be formed or the surface. The crystals aligned in the vertical direction are used as seeds, and the oxide semiconductor film formed thereon also has the same crystal structure. The oxide semiconductor film may have a portion.

[0147] Note that a crystalline oxide semiconductor film (single crystal or microcrystalline) other than the CAAC-OS film may be used. In the case of forming the oxide semiconductor film, the heat treatment can be performed to crystallize the oxide semiconductor film. In addition, the concentration of impurities such as silicon in the region 103a of the oxide semiconductor film 103 is Since the amount of the oxide semiconductor film is reduced, the oxide semiconductor film can be crystallized up to a surface where the oxide semiconductor film is formed.

[0148] Note that a structure in which heat treatment is performed before the oxide semiconductor film is processed into an island shape is described here. However, one embodiment of the disclosed invention is not limited thereto. The heat treatment may be carried out after processing.

[0149] Next, the oxide semiconductor film 103 is photolithographically separated into island-shaped oxide semiconductor films 1 In addition, the island-shaped oxide semiconductor film 103 is preferably processed into a rectangular shape (see FIG. 4C). A resist mask for forming the resist film may be formed by an ink-jet method. When formed using the inkjet method, no photomask is used, reducing manufacturing costs. Note that the oxide semiconductor film 103 can be etched by either dry etching or wet etching. Alternatively, either one or both may be used.

[0150] Here, as shown in FIG. 4C, the oxide semiconductor film 103 has an edge portion with a tilt angle of 20° to 50°. When the edge of the oxide semiconductor film 103 is vertical, the oxide Oxygen is easily released from the semiconductor film 103, and oxygen vacancies are easily generated. The tapered end portion suppresses the occurrence of oxygen vacancies and reduces the leakage current of the transistor 110. The occurrence of current can be reduced.

[0151] Next, a source electrode and a drain electrode (formed from the same layer as this) are formed on the oxide semiconductor film 103. The conductive film used for the source electrode and the drain electrode is deposited. Examples of the conductive film include aluminum, chromium, copper, tantalum, titanium, molybdenum, and tantalum. Metal film containing an element selected from tinsten, or a metal nitride containing the above-mentioned elements as components. Films such as titanium nitride film, molybdenum nitride film, and tungsten nitride film can be used. In addition, titanium, molybdenum, etc. may be applied to either or both of the upper and lower sides of the metal film such as aluminum or copper. High melting point metal films such as titanium and tungsten, or metal nitride films of these metals (titanium nitride film, A layered structure of a source electrode (a molybdenum nitride film, a tungsten nitride film, etc.) may also be used. The conductive film used for the source and drain electrodes may be formed of a conductive metal oxide. Metal oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide ( ZnO), indium tin oxide (In2O3-SnO2, abbreviated as ITO), The source and drain electrodes can be made of In2O3-ZnO. The conductive film used for the electrode can be formed as a single layer or a stacked layer using the above-mentioned materials. The method of formation is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, a spin coating method, etc. Various film formation methods can be used.

[0152] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the source electrode 105a and the drain electrode 105b by this process, the resist mask is removed. (See FIG. 4(D)). When forming a resist mask in the photolithography process, For the exposure, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. The lower end of the source electrode 105a and the drain electrode 105 adjacent to each other on the oxide semiconductor film 103 The channel length L of the transistor to be formed later is determined by the width of the gap between the bottom end of Therefore, when performing exposure with a channel length L of less than 25 nm, for example, a few nm to several 1 Extreme ultraviolet rays with an extremely short wavelength of 0 nm are used. It is recommended to use this light for exposure when forming a resist mask in the photolithography process. The exposure has high resolution and a large depth of focus. It is possible to miniaturize the channel length L, thereby increasing the operating speed of the circuit.

[0153] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0154] Note that when the conductive film is etched, the oxide semiconductor film 103 is etched and divided. It is desirable to optimize the etching conditions so as not to cause this. It is difficult to obtain a condition in which the oxide semiconductor film 103 is not etched at all. During etching of the conductive film, the oxide semiconductor film 103 is only partially etched. For example, 5% to 50% of the thickness of the oxide semiconductor film 103 is etched to form a groove (a recess). In some cases, the oxide semiconductor film 103 has a structure including a first insulating film and a second insulating film.

[0155] Next, a semiconductor film 104 is formed on the source electrode 105a and the drain electrode 105b. A protective insulating film 109 is formed so as to be in contact with a part of the insulating film 03 (see FIG. 4(E)). As the insulating film, it is preferable to use an inorganic insulating film, such as a silicon oxide film, a silicon oxynitride film, Aluminum oxide film, aluminum oxynitride film, gallium oxide film, hafnium oxide film, etc. The oxide insulating film may be formed as a single layer or a stack. Silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film, etc. Any nitride insulating film may be further formed as a single layer or a multilayer. For example, sputtering may be used. The silicon oxide film and the silicon nitride film are formed in the order from the source electrode 105a and the drain electrode 105b side by using a method. Then, a laminate of a silicon dioxide film and an aluminum oxide film is formed.

[0156] In addition, in this step, when the protective insulating film 109 is formed by a sputtering method, In the same manner as in the case of forming the oxide semiconductor film 103, the particles forming the protective insulating film 109 are It is effective to weaken the force of collision with the oxide semiconductor film 103. A region 103c is formed in the vicinity of the interface where the conductive film 103 and the protective insulating film 109 are in contact with each other. As a result, the transistor 120 shown in FIG. 2(A) and FIG. 2(B) is formed. The region 103c is a region in the oxide semiconductor film 103 extending from the interface with the protective insulating film 109 to the oxide semiconductor layer. This is a region where silicon is distributed at a concentration of 1.0 atomic % or less toward the conductor film 103. It is preferable that the thickness of 03c from the interface with the protective insulating film 109 is within a range of 5 nm or less. I wish.

[0157] Here, the protective insulating film 109 may be the same insulating film as the gate insulating film 102. In order to prevent impurities such as silicon from being mixed into the oxide semiconductor film 103, By suppressing mixing in the vicinity of the interface between the oxide semiconductor film 103 and the protective insulating film 109, Therefore, the silicon constituting the protective insulating film 109 is not uniformly distributed in the oxide semiconductor film during sputtering. For example, the deposition power for the protective insulating film 109 can be reduced. In order to prevent this, the deposition pressure of the protective insulating film 109 must be increased or the distance between the TSs must be increased. be.

[0158] In this manner, even in the region 103c corresponding to the back channel of the oxide semiconductor film 103, The concentration of impurities such as silicon can be reduced.

[0159] The transistor 120 is manufactured in the same manner as the transistor 110. can be done.

[0160] After the protective insulating film 109 is formed, the oxide semiconductor film 103 is preferably subjected to heat treatment. The temperature of the heat treatment is set to 300° C. or higher and 700° C. or lower, or lower than the distortion point of the substrate.

[0161] The heat treatment is carried out in a nitrogen, oxygen or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm). pm or less, preferably 10 ppb or less in air), or rare gases (argon, helium, etc. ) atmosphere, but it is also possible to carry out the treatment in an atmosphere of nitrogen, oxygen, ultra-dry air, or a rare gas. It is preferable that the gas does not contain water, hydrogen, etc. Also, the gas introduced into the heat treatment device should not contain nitrogen, oxygen, or The purity of the rare gas should be 6N (99.9999%) or more, preferably 7N (99.99999%). %) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). preferable.

[0162] The oxide semiconductor film is then heat-treated to form a film of the oxide semiconductor. However, the amount of oxygen in the silicon may decrease at the same time. The gate insulating film 102 is formed using an insulating film containing an oxide containing oxygen. Since the oxygen can be supplied to the oxide semiconductor film 103, oxygen vacancies in the oxide semiconductor film 103 can be compensated for. This can be done.

[0163] By performing the above-described heat treatment, the oxide semiconductor film 103 is free of impurities other than its main components. The oxide semiconductor film 103 can be highly purified so that it does not contain as much oxygen as possible. There are very few carriers derived from the donor (close to zero), and the carrier concentration is 1 × 1 0 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 In this manner, the oxide semiconductor film 103 which has been made i-type (intrinsic) is formed. can be formed.

[0164] Through the above steps, the transistor 110 is formed (see FIG. 4E). The concentration of impurities such as silicon taken into the region 103a of the oxide semiconductor film 103 is This allows the transistor 110 to have stable electrical characteristics. It is possible.

[0165] A planarization insulating film may be provided over the transistor 110. Acrylic resin, polyimide resin, benzocyclobutene resin, polyamide resin, epoxy resin In addition to the above organic materials, low dielectric constant organic materials such as cellulose, etc. can be used. Dielectric constant material (low-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus In addition, the insulating film formed from these materials can be used in multiple layers. Several layers may be stacked.

[0166] <Fabrication process of transistor 130> Next, a manufacturing process of the transistor 130 shown in FIG. An example will be described.

[0167] First, a gate electrode is formed on a substrate 100 in the same manner as for the transistor 110 up to the step shown in FIG. The gate electrode 101, the gate insulating film 102, and the region 103a and the region 103b are included. An oxide semiconductor film 103 is formed (see FIG. 5A). The details of the gate insulating film 102 and the oxide semiconductor film 103 are shown in FIGS. The description regarding (C) may be taken into consideration.

[0168] Next, the insulating film 107 used as the channel protective film is formed to a thickness of 5 nm to 300 nm. As the insulating film 107, an inorganic insulating film containing oxygen can be used. For example, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a nitriding film, etc. are preferable. An insulating film such as an aluminum oxide film, a gallium oxide film, or a hafnium oxide film can be used. The method for forming the insulating film 107 is not particularly limited. For example, the method may be a sputtering method, a M The film can be formed by appropriately using the BE method, the CVD method, the pulsed laser deposition method, the ALD method, etc. .

[0169] Next, a resist mask is formed on the insulating film 107 by a photolithography process, and then etching is performed. After forming the channel protection film 108 by etching, the resist mask is removed (FIG. 5(C) )). A resist mask for forming the channel protection film 108 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since the channel protection film 108 is not used, the manufacturing cost can be reduced. The etching may be dry etching or wet etching, or both may be used.

[0170] As shown in FIG. 5C, the channel protection film 108 is inclined at an angle of 10° to 60° to the edge. It is preferable that the channel protection film 108 has such a taper. This makes it possible to reduce the electric field concentration in the vicinity of the bottom end of the channel protection film 108. do.

[0171] In this manner, by providing the channel protective film 108 on and in contact with the oxide semiconductor film 103, The source electrode 105a and the drain electrode 105b are etched to form the oxide semiconductor film 1 Damage to the back channel side of 03 (e.g., plasma or etchant during etching) This prevents damage caused by acid and other chemicals, resulting in a stable electrical property. It is possible to provide a semiconductor device using a compound semiconductor.

[0172] Next, a source electrode and a drain electrode are formed on the channel protection film 108 and the oxide semiconductor film 103. A conductive film to be used for the electrodes (including wiring formed in the same layer) is formed, and then photolithography is performed. The conductive film is selectively etched by a etching process to form the source electrode 105a and the drain electrode 105b. An electrode 105b is formed (see FIG. 5(D)). This step is the same as the step shown in FIG. Since the method can be used, the source electrode 105a and the drain electrode 105b can be For details, please refer to the description of Figure 4(D).

[0173] Next, the source electrode 105a, the drain electrode 105b and the channel protective film 108 are A protective insulating film 109 is formed to cover the insulating film (see FIG. 5(E)). Since the protective insulating film 109 can be formed by the same method as that described above, the details of the protective insulating film 109 are shown in FIG. The statements in paragraph 4(E) may be taken into consideration.

[0174] By forming the oxide semiconductor film in the above manner, the oxide semiconductor film is formed near the surface on which the oxide semiconductor film is to be formed. In addition, the concentration of impurities in the oxide semiconductor film 103 can be reduced. Since the oxide semiconductor film 103 can be crystallized up to the vicinity of the deposition surface, the crystallinity of the oxide semiconductor film 103 can be improved. In addition, when the oxide semiconductor film 103 is a CAAC-OS film, The crystal portion can be formed up to the vicinity of the deposition surface of the oxide semiconductor film 103. An interface with the gate insulating film 102, or an interface between the oxide semiconductor film 103 and the protective insulating film 109 The c-axis is aligned perpendicular to the surface of the oxide semiconductor film. In this way, a semiconductor device having stable electrical characteristics can be provided.

[0175] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0176] (Embodiment 2) A semiconductor device having a display function (a display device) using the transistor described in Embodiment 1 as an example In addition, a part or the whole of a driver circuit including a transistor can be manufactured. A system-on-panel can be formed by forming the display panel and the pixel portion on the same substrate.

[0177] In FIG. 9A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the semiconductor device is sealed with a second substrate 4006. In A), a region surrounded by a sealant 4005 on a first substrate 4001 and The semiconductor layer is formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate in a different region. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted on the substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4002 are provided with Various signals and potentials are transmitted via FPC (Flexible Printed Circuit). t) Powered by 4018a and 4018b.

[0178] In FIG. 9B and FIG. 9C, a pixel portion 4002 is provided on a first substrate 4001. A sealant 4005 is provided so as to surround the scanning line driver circuit 4004 . In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are in a synchronous with the first substrate 4001. The display element is sealed by a sealing material 4005 and a second substrate 4006. In FIG. 9B and FIG. 9C, the first substrate 4001 is surrounded by a sealant 4005. A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region where the semiconductor device is mounted. A signal line driver circuit 4003 formed of a conductor film is mounted. In the above embodiment, a signal line driver circuit 4003 and a scanning line driver circuit 4004 are separately formed. Various signals and potentials applied to the pixel portion 4002 are supplied from an FPC 4018. .

[0179] In addition, in FIG. 9B and FIG. 9C, a signal line driver circuit 4003 is formed separately. In the illustrated example, the scanning line driver is mounted on a single substrate 4001, but the present invention is not limited to this configuration. Alternatively, a driving circuit may be formed separately and mounted, or a part of a signal line driving circuit or a scanning line driving circuit may be mounted. Only a part of it may be formed separately and mounted.

[0180] The method of connecting the separately formed drive circuit is not particularly limited, and may be any of the following: ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a utomated bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 9B shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 4003) is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0181] The display device includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above, are mounted.

[0182] In this specification, the term "display device" refers to an image display device, a display device, or an optical This refers to the source of light (including lighting equipment).

[0183] Also, connectors such as FPC or TAB tape or TCP are attached. Modules, modules with printed wiring boards attached to the ends of TAB tape or TCP, Also includes modules in which ICs (integrated circuits) are directly mounted on the display element using the COG method. This is included in the device.

[0184] In addition, the pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. To this end, the transistor described in Embodiment 1 can be applied.

[0185] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements ( The light-emitting element can be used as a light-emitting display element. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0186] One embodiment of a semiconductor device will be described with reference to FIGS. , which corresponds to the cross-sectional view taken along line MN in FIG. 9(B).

[0187] As shown in FIGS. 10 to 12, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 401. 6, and the connection terminal electrode 4015 and the terminal electrode 4016 are The terminals are electrically connected via an anisotropic conductive film 4019 .

[0188] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 denotes source and drain electrodes of the transistor 4010 and the transistor 4011. It is formed of the same conductive film as that of the first embodiment.

[0189] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 10 to 12, the transistors included in the pixel portion 4002 are A transistor 4010 and a transistor 4011 included in a scanning line driver circuit 4004 are shown as examples. It shows.

[0190] In this embodiment, the transistors 4010 and 4011 are the transistors The transistors shown in the following can be applied: transistor 4010, transistor 4 011 is electrically stable with the electrical characteristic fluctuations suppressed. As the semiconductor device of this embodiment shown in FIG. 12, a highly reliable semiconductor device can be provided. can.

[0191] The transistor 4011 included in the scanning line driver circuit 4004 is provided with a second This is a structure in which a gate electrode is provided. By controlling the voltage applied to the second gate electrode, This makes it possible to control the threshold voltage of the transistor 4011.

[0192] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. can be used.

[0193] FIG. 10 shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and The liquid crystal layer 4008 is sandwiched between insulating layers that function as alignment layers. The second electrode layer 4031 is provided on the second substrate 4. 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are disposed on the liquid crystal layer 4008 The structure is such that the electrodes are laminated via a gap.

[0194] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. The liquid crystal layer 4008 is provided to control the thickness (cell gap) of the liquid crystal layer 4008. A spacer of the above type may be used.

[0195] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0196] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing at least a few percent by weight of a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response speed of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since no film is required, rubbing is also unnecessary. This prevents electrostatic damage that may occur during the manufacturing process, reducing defects and damage to liquid crystal display devices. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0197] The specific resistivity of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 1 1 Ω cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistivity values ​​in the specification are those measured at 20°C.

[0198] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period of time, taking into consideration the current drain and other factors. By using a transistor having a semiconductor film, the liquid crystal capacitance of each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0199] The transistor including the purified oxide semiconductor film used in this embodiment is in an off state. Therefore, the current value (off-state current value) at the time of the image signal or other electric signals can be reduced. The retention time of the data can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, resulting in reduced power consumption. It plays a major role.

[0200] In addition, the transistor including the purified oxide semiconductor film used in this embodiment has a relatively Since a relatively high field effect mobility can be obtained, high speed driving is possible. By using the above transistor in the pixel portion, a high-quality image can be provided. In addition, the above transistors can be separately manufactured in a driver circuit portion and a pixel portion on the same substrate. This makes it possible to reduce the number of parts in the liquid crystal display device.

[0201] There are two types of LCD displays: TN (Twisted Nematic) and IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0202] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. This is a method of controlling the arrangement of crystal molecules, and it applies a In this method, the liquid crystal molecules are aligned vertically. There are several types of vertical alignment modes: For example, MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV mode (Advanced Super-View), etc. It is also possible to divide a pixel into several regions (subpixels) and display each region separately. Multi-domain or multi-domain design that is devised to tilt the molecule in the direction of The method mentioned above can be used.

[0203] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. Optical members (optical substrates) such as a prevention member are provided as appropriate. For example, a polarizing substrate and a retardation substrate Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0204] In addition, multiple light-emitting diodes (LEDs) are used as backlights to display the image in a time-division format. It is also possible to perform a field sequential drive method. By applying the color driving method, it is possible to display colors without using color filters. This can be done.

[0205] The display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is The color is not limited to the three colors red, green, and blue. For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may be applied to monochrome display devices. It is also possible.

[0206] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element utilizing electroluminescence is made of a light-emitting material They are classified according to whether they are organic or inorganic compounds. Generally, the former are called organic E The latter is called an inorganic EL element.

[0207] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0208] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0209] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission, bottom emission where the light is emitted from the surface on the substrate side, or the surface on the substrate side and the opposite side There are light-emitting devices with a double-sided emission structure that extracts light from the outside, and light-emitting devices with any emission structure can be used. It is possible.

[0210] FIG. 11 shows an example of a light-emitting device using a light-emitting element as a display element. The transistor 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second The electrode layer 4031 has a stacked structure, but is not limited to the structure shown in the figure. The structure of the light emitting element 4513 can be changed as appropriate according to the direction of extracted light.

[0211] The partition 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening is a continuous curved It is preferable to form the inclined surface so that the inclined surface is formed with a certain rate.

[0212] The electroluminescent layer 4511 may be composed of a single layer or may be composed of a plurality of layers stacked together. It doesn't matter whether it is done or not.

[0213] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective film may be formed on the barrier 4031 and the partition wall 4510. The protective film may be made of silicon nitride. A silicon nitride oxide film, a DLC film, etc. can be formed on the first substrate 400. The space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 is filled with a filler 45. 14 is provided and sealed. In this way, it is highly airtight and degassing is possible to prevent exposure to the outside air. Protective films with low damage (laminated films, UV-cured resin films, etc.) and covering materials It is preferable to package (enclose) the

[0214] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, poly Imide resin, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. For example, nitrogen is used as a filler. That's good.

[0215] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0216] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display) and is a paper-based display. It is possible to make a display that is as easy to read as a regular display, consumes less power than other displays, and is thinner and lighter in size. This has the advantage that

[0217] The electrophoretic display device may have various forms, but it has a first particle having a positive charge and A microcapsule containing a negatively charged second particle and a negatively charged second particle is introduced into a solvent or solute. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and they do not migrate in the absence of an electric field. The color of the first particle and the color of the second particle are different (including colorless). )

[0218] In this way, the electrophoretic display device is a so-called This is a display that utilizes the dielectrophoretic effect.

[0219] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0220] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0221] In addition, display devices using the twist ball display method can also be used as electronic paper. The twist ball display method uses black and white spherical particles as the display element. The insulating layer is disposed between a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer are electrically connected to each other. This is a method of displaying information by controlling the orientation of spherical particles by applying a potential difference to the electrode layer. be.

[0222] FIG. 12 shows an active matrix electronic paper as one mode of a semiconductor device. The electronic paper shown in FIG. 12 is an example of a display device that uses the twisting ball display method.

[0223] A first electrode layer 4030 connected to the transistor 4010 and a second electrode layer 4006 Between the second electrode layer 4031 and the black area 4615a and the white area 4615b, A spherical particle 4613 is provided that includes a cavity 4612 that is filled with liquid around it. The spherical particles 4613 are filled with a filler 4614 such as a resin. The second electrode layer 4031 corresponds to a common electrode (opposite electrode). are electrically connected.

[0224] In addition, in FIG. 10 to FIG. 12, the first substrate 4001 and the second substrate 4006 are In addition to the glass substrate, a flexible substrate can also be used. For example, a transparent plastic substrate can be used. As for plastic, FRP (Fibre Plastics) can be used. Ass-Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) A film, a polyester film or an acrylic resin film can be used. In addition, aluminum foil is sandwiched between PVF film or polyester film. Ports can also be used.

[0225] The insulating layer 4021 can be formed using an inorganic insulating material or an organic insulating material. , acrylic resin, polyimide resin, benzocyclobutene resin, polyamide resin, epoxy If a heat-resistant organic insulating material such as resin is used, it is suitable as a planarizing insulating film. In addition to the above organic insulating materials, low-k materials, siloxane resins, P SG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. The insulating layer may be formed by stacking a plurality of insulating films made of these materials.

[0226] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a sintering method, or the like, depending on the material. Pin coating method, dipping method, spray coating, droplet ejection method (inkjet method, etc.), printing Printing methods (screen printing, offset printing, etc.), roll coating, curtain coating Coating, knife coating, etc. can be used.

[0227] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating film, and conductive film provided on the elemental part are sensitive to light in the visible light wavelength range. It is translucent.

[0228] A first electrode layer 4030 and a second electrode layer 4031 (pixel electrode layer) for applying a voltage to a display element In the case of the layer (also called the common electrode layer, counter electrode layer, etc.), the direction of the light to be extracted and the electrode layer are provided. The light transmission or reflection can be selected depending on the location where the electrode layer is to be disposed and the pattern structure of the electrode layer.

[0229] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material that can be used.

[0230] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), Or, it can be formed by using one or more of its alloys or nitrides. .

[0231] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer or derivative thereof consisting of two or more of aniline, pyrrole and thiophene Examples include the body.

[0232] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0233] As described above, by using the transistor described in Embodiment 1 as an example, a highly reliable semiconductor device can be obtained. Note that the transistors exemplified in the first embodiment can be used in the same manner as in the above-mentioned embodiment. Not only semiconductor devices with display functions, but also power devices mounted on power circuits, LSIs, etc. semiconductor integrated circuits, semiconductor devices with image sensor functions that read information on objects, etc. The present invention can be applied to semiconductor devices having various functions.

[0234] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0235] (Embodiment 3) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. Cameras such as digital cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) (c) Portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the liquid crystal display device described in the above embodiment include: He explains.

[0236] FIG. 13A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in 1 or 2, a highly reliable notebook type personal computer can be manufactured. The input signal may be a computer.

[0237] FIG. 13B shows a portable digital assistant (PDA), which includes a display unit 3023 and a display unit 3024 on a main body 3021. An external interface 3025 and operation buttons 3024 are provided. The semiconductor device shown in the first or second embodiment has a stylus 3022 as an accessory. By applying this technology, a highly reliable personal digital assistant (PDA) can be created.

[0238] FIG. 13C shows an example of an electronic book. For example, an electronic book 2700 has a housing 27 The device is made up of two housings, housing 2701 and housing 2703. 3 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. With this configuration, it becomes possible to operate like a paper book.

[0239] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 13C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 13C). By applying the semiconductor device shown in 1 or 2, a highly reliable electronic book 2700 and It is possible.

[0240] FIG. 13C shows an example in which an operating unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The display may be configured with a keyboard or a pointing device on the front side. On the back and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion section, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. A configuration in which the above is also possible.

[0241] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0242] FIG. 13D shows a smartphone, which includes a housing 2800, a button 2801, and a micro A phone 2802, a display unit 2803 equipped with a touch panel, a speaker 2804, and a camera. The camera includes a lens 2805 and functions as a mobile phone. Or, by applying the semiconductor device shown in 2, a highly reliable smartphone can be obtained. It is possible.

[0243] The display direction of the display unit 2803 changes appropriately depending on the usage mode. The camera lens 2805 is located on the same surface as the speaker, so video calls are possible. The speaker 2804 and microphone 2802 are not limited to voice calls, but can also be used for video calls, recording, playback, etc. It is possible to live etc.

[0244] In addition, the external connection terminal 2806 can be used to connect various cables such as an AC adapter and a USB cable. It is possible to connect to a computer, charge the device, and communicate with a personal computer. A recording medium can be inserted into an external memory slot (not shown) to store and transfer a larger amount of data. It can handle.

[0245] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0246] FIG. 13(E) shows a digital video camera, which includes a main body 3051, a display unit (A) 3057, An eyepiece 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056, etc. By applying the semiconductor device shown in the first or second embodiment, This makes it possible to provide a more reliable digital video camera.

[0247] FIG. 13(F) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. By applying the semiconductor device shown in the first or second embodiment, The television device 9600 can be highly reliable.

[0248] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. The remote control can also be operated by the remote control. A display unit for displaying the output information may be provided.

[0249] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0250] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination. EXAMPLES

[0251] In this example, the concentration of silicon contained in the oxide target was measured by SIMS. The results will be explained.

[0252] First, the oxide target used in this example will be described.

[0253] Sample A was an In-Ga-Zn oxide target (atomic ratio of In:Ga:Zn =2:1:3, and as sample B, an In-Ga-Zn oxide target (atomic number The ratio is In:Ga:Zn=3:1:2), and sample B is an In-Sn-Zn oxide ( The atomic ratio of In:Sn:Zn=2:1:3 was used. Silicon-added In-Ga-Zn oxide target (atomic ratio In:Ga:Zn =1:1:1) was used.

[0254] SIMS measurements were performed on sample A, sample B, sample C, and standard sample D. The silicon concentration in each sample was examined by this method.

[0255] FIG. 14 shows the results of SIMS measurements of samples A to C and standard sample D. .

[0256] As shown in Figure 14, the concentration of silicon in sample A is 4 × 10 18 atoms / cm 3 , the silicon concentration of sample B is 3×10 17 atoms / cm 3 , Sample C's serial The concentration of kon is 2×10 17 atoms / cm 3 , the silicon concentration of standard sample D is 2×10 18 atoms / cm 3 It was found that Sample A to Sample B were The SIMS measurement results for C are quantified using standard sample D.

[0257] The above data was obtained using targets Samples A to C and Standard Sample D. When an oxide semiconductor film is formed, silicon other than silicon contained in the target (e.g. For example, silicon in the insulating film mixed in by mixing) is included in the oxide semiconductor film. This can be used as a basis for determining whether

[0258] For example, the target is sample A (In:Ga:Zn=2:1:3 (atomic ratio) In an oxide semiconductor film formed using an oxide target having a silicon concentration of 10 ... 4×10 18 atoms / cm 3 If it is higher, silicon from areas other than the target may be mixed in. It can be determined that it has been inserted. EXAMPLES

[0259] In the above-described embodiment, the inclusion of insulating film constituent elements in the oxide semiconductor film is The cause of this is mixing that occurs when forming the oxide semiconductor film. It is possible that the insulating film constituent elements are diffused into the oxide semiconductor by subsequently heating the substrate. In this embodiment, the incorporation of insulating film constituent elements into the oxide semiconductor film is considered to be caused by thermal We will explain the experiment that investigated whether diffusion is the cause.

[0260] The experiment consisted of three substrates with a structure in which an insulating film and an oxide semiconductor film were formed on the substrate. After the preparation, a sample that was not heat-treated (hereinafter referred to as sample E) was heat-treated at 450°C. The sample that was heat-treated at 650°C (hereinafter referred to as sample F) A sample (hereinafter referred to as sample G) was prepared. Time-of-Flight Mass Spectrometry (ToF-SIMS) Using a quantitative ion mass spectrometer (QES), The silicon concentration in the conductive film near the interface with the gate insulating film was measured.

[0261] First, the structure of the sample used in the ToF-SIMS measurement is shown in FIG.

[0262] The sample shown in FIG. 15 is prepared by forming a silicon oxide film 202 on a silicon substrate 200 and chemically Mechanical polishing (CMP:Chemical Mechanical Polishing) The surface was made flat by using a special tool, and then an IGZO film 204 was formed. Finally, a heat treatment was performed. It is.

[0263] The silicon oxide film 202 was formed using a sputtering device. The deposition conditions were: substrate temperature: 100°C, gas flow rate: Ar / O2=25sccm / 25scc m, deposition power: 1.5 kW (RF power source), deposition pressure: 0.4 Pa, film thickness: 300 nm A silicon oxide target was used as the sputtering target. Before forming the silicon oxide film 202, a dilute hydrofluoric acid is used to form a film on the surface of the silicon substrate 200. The oxide film was removed.

[0264] The IGZO film 204 was formed using a sputtering device. The conditions were: substrate temperature: 200°C, gas flow rate: Ar / O2=30sccm / 15sccm, film formation Power: 0.5 kW (DC power source), film formation pressure: 0.4 Pa, film thickness: 15 nm. The sputtering target is an oxide of In:Ga:Zn=3:1:2 [atomic ratio]. A solid target was used.

[0265] The heat treatment was performed by placing the substrate in an electric furnace using a resistance heating element or the like. For sample F, the heating temperature was 450°C and the heating time was 1 hour. For sample G, The heating temperature was 650°C and the heating time was 1 hour. In both cases, the atmosphere was a mixture of nitrogen and oxygen. Sample E was also heat-treated. do not have.

[0266] Next, for samples E to G, To F-SIMS measurements were performed to determine the amount of silicon in the IGZO film near the interface with the silicon oxide film. The concentrations were measured and the results are shown in FIG.

[0267] As shown in FIG. 16, in all samples, the silicon oxide film interface in the oxide semiconductor film was The silicon concentration was determined by using the In-Ga-Zn oxide target (atomic ratio: The silicon concentration in In:Ga:Zn=3:1:2 is 3×10 17 atom s / cm 3 It can be seen that the temperature is higher than that near the silicon oxide film interface. The silicon measured in the oxide semiconductor film next to the In-Ga-Zn oxide target It can be said that silicon is not the cause.

[0268] In addition, as shown in Figure 16, the sample that was not heat-treated (sample E) and the sample that was heat-treated In the samples (samples F and G) tested, The silicon concentration gradient in the IGZO film is unique. Therefore, the incorporation of insulating film constituent elements into the oxide semiconductor film is due to thermal diffusion. It can be said that this is not due to the mixing but rather due to the mixing. EXAMPLES

[0269] In this embodiment, the mixing of insulating film constituent elements into the oxide semiconductor film caused by mixing is prevented. This is a description of an experiment conducted to investigate whether the effect of reducing the power required for forming an oxide semiconductor film can be suppressed. Make a statement.

[0270] The experiment consisted of forming an insulating film on a substrate, and then applying four types of power to the insulating film to form an oxide semiconductor film. After deposition under the conditions (1kW, 5kW, 9kW and 1kW+5kW), each substrate was Four types of samples were prepared by heat treatment. The silicon concentration in the film near the interface with the gate insulating film was measured using the ToF-SIMS method. Measured.

[0271] First, the structure of the sample used in the ToF-SIMS measurement is shown in FIG.

[0272] The sample shown in FIG. 17 is a glass substrate 300 having a silicon oxynitride film 302 formed thereon. An IGZO film 304 was then formed on the substrate, and finally a heat treatment was performed.

[0273] The silicon oxynitride film 302 was formed using a high density plasma CVD apparatus. The deposition conditions for the silicon film 302 were: substrate temperature: 325° C., gas flow rate: SiH4 / N2O / Ar = 250sccm / 2500sccm / 2500sccm, deposition power: 5kW x 4 units (Ma The conditions were: microwave power source, deposition pressure: 30 Pa, and film thickness: 100 nm. Before forming the silicon film 302, the surface of the glass substrate 300 was cleaned to remove particles and the like. .

[0274] The IGZO film 304 was formed using a sputtering device. The conditions were: substrate temperature: 170°C, gas flow rate: Ar / O2=100sccm / 100sccm, Deposition pressure: 0.6 Pa, film thickness: 35 nm, 1 kW, 5 kW, 9 kW and 1 kW + 5 The deposition was carried out under four power conditions (AC power source was used for both). The target used was an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Ta.

[0275] The above-mentioned deposition power of "1kW + 5kW" means that the first 5 nm of deposition is performed with 1kW of power, The subsequent 30 nm film was formed at a power of 5 kW. The sample with the semiconductor film formed at 9 kW is sample H, and the sample with the semiconductor film formed at 5 kW is sample P. Sample I is a sample grown at 1kW, Sample J is a sample grown at 1kW + 5kW. It is called Sample K.

[0276] The heat treatment was performed by placing the substrate in an electric furnace using a resistance heating element or the like. First, the specimen was heated at 450°C in N2 atmosphere for 1 hour. Heating was performed for 1 hour under the conditions of heat temperature: 650°C, heating atmosphere: N2+O2.

[0277] Next, for samples H to K, To F-SIMS measurement was performed to determine the amount of silicon in the IGZO film near the interface with the silicon oxynitride film. The concentration of the com- pounds was measured. The results are shown in Figure 18. Note that Figure 18(B) is a part of Figure 18(A). This is an enlarged view.

[0278] As shown in Fig. 18, in all samples, the IGZO film near the silicon oxynitride film interface The silicon concentration was determined by using the In-Ga-Zn oxide target (atomic ratio: The silicon concentration in In:Ga:Zn=1:1:1 is 2×10 18 atom s / cm 3 Therefore, it can be confirmed that the silicon oxynitride film boundary is higher than that of the silicon nitride film. The silicon measured in the oxide semiconductor film near the surface was determined to be an In-Ga-Zn oxide target. It can be said that this is not silicon caused by the smear.

[0279] In addition, from Figure 18, the silicon concentration in the IGZO film near the silicon oxynitride film interface is It was confirmed that the decrease in the deposition power was accompanied by a decrease in the deposition power. By reducing the deposition power, the insulating film in the oxide semiconductor film caused by mixing is prevented from being mixed. It was confirmed that the contamination of the constituent elements could be suppressed.

[0280] In addition, the silicon concentration of sample J and sample K is almost the same, so that the initial stage of film formation In the first step, an oxide semiconductor film is formed at low power, and then the power is increased to form an oxide semiconductor film. Even if the oxide semiconductor film is formed, the inclusion of insulating film constituent elements into the oxide semiconductor film caused by mixing is suppressed. It was confirmed that this is possible. EXAMPLES

[0281] In this embodiment, the oxide semiconductor film is formed by mixing an insulating film component element into the oxide semiconductor film. The results of an investigation into the crystalline state in the semiconductor film will be explained.

[0282] First, two substrates on which oxide semiconductor films were formed using targets with different compositions were placed on the substrate. Each substrate was then divided into three parts. The three parts were then heat-treated under different conditions. By carrying out the above steps, a total of six samples with different conditions were created. The crystal state of the oxide semiconductor film was examined by X-ray diffraction (XRD). Measurements were taken using the on (on).

[0283] First, the structure of the sample used in the XRD measurement is shown in FIG.

[0284] The sample shown in FIG. 19(A) is an IGZO ( The IGZO film 402 was formed using a target of In:Ga:Zn=1:1:1 [atomic ratio]. After the coating, a heat treatment was performed.

[0285] The IGZO film 402 was formed using a sputtering device. The conditions were: substrate temperature: 200°C, deposition power: 100W, deposition pressure: 0.4Pa, gas flow rate: O 2=10sccm, film thickness: 100nm. The sputtering target was The target was In:Ga:Zn=1:1:1 [atomic ratio] with 2 wt% SiO2 added. and In:Ga:Zn=1:1:1 [atomic ratio] with 5 wt% SiO2 added. Before forming the IGZO film 402, the surface of the glass substrate 400 was The substrate was washed to remove particles and the like.

[0286] The heat treatment was performed by placing the substrate in an electric furnace using a resistance heating element. After deposition, the substrate was divided into three parts. One of the parts was heat-treated in a N2 atmosphere at 650°C for one hour. The heat treatment was carried out for 1 hour in an O2 atmosphere at 650°C. After heating for 1 hour in a N2 atmosphere at 0°C, the specimen was heated for 1 hour in an O2 atmosphere at 450°C. In addition, one of the three divided substrates was not subjected to heat treatment.

[0287] By adjusting the targets and heating conditions described above, samples L to S shown in Table 1 were obtained. Six types of samples of Sample Q were prepared.

[0288] [Table 1]

[0289] Next, XRD measurements were performed on the IGZO films of samples L to Q, and the crystal structure of each film was The crystal state was measured. The results are shown in Figure 20(A) and Figure 20(B). Figure 20(A) shows the FIG. 20(B) shows the XRD measurement results of Samples L to N, and FIG. 20(C) shows the XRD measurement results of Samples O to N. These are the XRD measurement results of Pull Q.

[0290] As shown in FIG. 20A, the heat treatment was performed at 650° C. within the temperature range described in the above embodiment. In sample L, a peak due to crystals was observed near 2θ = 31°. However, in Figure 20(B), no peaks due to crystals were observed in any of the samples. Therefore, the IGZO film contains excess silicon as an impurity, and as a result, It was confirmed that crystallization was inhibited.

[0291] Next, we investigated the effect of IGZO film deposition on the target containing 2 wt% silicon. In order to investigate the amount of silicon contained, X-ray photoelectron spectroscopy (XPS: Xr Using ay photoelectron spectroscopy, IGZO film The composition of the elements contained therein was measured.

[0292] The sample used for the XPS measurement was a silicon substrate 500 with an I This structure has a GZO film 502 formed thereon.

[0293] The IGZO film 502 was formed using a sputtering device. The conditions were: substrate temperature: 200°C, deposition power: 100W, deposition pressure: 0.4Pa, gas flow rate: O 2=10sccm, film thickness: 15nm. The sputtering target was A target with In:Ga:Zn=1:1:1 [atomic ratio] and 2wt% SiO2 added Before forming the IGZO film 502, the surface of the silicon substrate 500 was washed with dilute hydrofluoric acid. The oxide film formed on the surface was removed.

[0294] The results of XPS measurements showed that the IGZ film formed using a target containing 2 wt% silicon It was confirmed that the O film contained 1.1 atom % of silicon.

[0295] As described above, the oxide semiconductor film is mixed with the gate insulating film to form a silicide layer near the interface. When impurities such as silicon are mixed in, crystallization of the channel formation region of the oxide semiconductor film is inhibited. Therefore, it was found that the oxide semiconductor film and the gate insulating film were likely to be in contact with each other. In the above, it is important to reduce the silicon concentration as described above. It was shown. [Explanation of symbols]

[0296] 100 Substrates 101 Gate electrode 102 Gate insulating film 103 Oxide semiconductor film 103a area 103b area 103c area 105a Source electrode 105b Drain electrode 107 Insulating film 108 Channel protection film 109 Protective insulating film 110 Transistor 120 Transistor 130 Transistor 200 Silicon Substrate 202 Silicon oxide film 204 IGZO membrane 300 Glass Substrate 302 Silicon oxynitride film 304 IGZO membrane 400 Glass Substrate 402 IGZO membrane 500 Silicon substrate 502 IGZO membrane 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 2800 Chassis 2801 Button 2802 Microphone 2803 Display section 2804 Speaker 2805 Camera Lenses 2806 External connection terminal 3001 Main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main unit 3022 Stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main unit 3053 Eyepiece 3054 Operation switch 3056 Battery 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4019 Anisotropic conductive film 4021 Insulation layer 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4034 Insulating film 4510 Bulkhead 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling material 4612 Cavity 4613 Spherical particles 4614 Filling material 4615a Black area 4615b White area 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand

Claims

1. an insulating film and a gate electrode on a substrate; an oxide semiconductor film in contact with the insulating film; a source electrode and a drain electrode electrically connected to the oxide semiconductor film, the insulating film contains silicon and oxygen; the oxide semiconductor film has a first region and a second region, the first region has a thickness of 5 nm or less from an interface between the oxide semiconductor film and the insulating film; a concentration of silicon contained in the second region is lower than a concentration of silicon contained in the first region; In the first region, the carbon concentration is 1.0×10 １９ atoms / cm ３ is as follows: The oxide semiconductor film includes a crystal portion.

2. In claim 1, the crystal portion has a c-axis oriented along a direction perpendicular to a surface on which the oxide semiconductor film is to be formed, The term "perpendicular" includes a range of 85° to 95° inclusive.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor film is formed by an ALD method.

4. In any one of claims 1 to 3, The oxide semiconductor film may be formed of any of a variety of oxides, including indium oxide, tin oxide, zinc oxide, In—Zn-based, Sn—Zn-based, Al—Zn-based, Zn—Mg-based, Sn—Mg-based, In—Mg-based, In—Ga-based, In—Ga-Zn-based, In-Al—Zn-based, In—Sn—Zn-based, Sn—Ga-Zn-based, Al—Ga-Zn-based, Sn—Al—Zn-based, In—Hf—Zn-based, In—Zr—Zn-based, In—Ti-Zn-based, In—Sc-Zn-based, In-Y-Zn-based, In-La-Zn-based, In-Ce-Zn-based, and In-Pr-Zn-based. the semiconductor device is an In-Zn-based, In-Nd-Zn-based, In-Sm-Zn-based, In-Eu-Zn-based, In-Gd-Zn-based, In-Tb-Zn-based, In-Dy-Zn-based, In-Ho-Zn-based, In-Er-Zn-based, In-Tm-Zn-based, In-Yb-Zn-based, In-Lu-Zn-based, In-Sn-Ga-Zn-based, In-Hf-Ga-Zn-based, In-Al-Ga-Zn-based, In-Sn-Al-Zn-based, In-Sn-Hf-Zn-based, or In-Hf-Al-Zn-based oxide semiconductor film.

5. In any one of claims 1 to 4, The oxide semiconductor film has a carrier concentration of 1×10 １４ / cm ３ 4. A semiconductor device comprising:

Images