Partitioned Template Matching and Symbolic Peephole Optimization

Abstract

Systems and techniques are provided that facilitate partitioned template matching and / or symbolic peephole optimization. In various embodiments, the system can include a template component that can perform template matching on a Clifford circuit associated with a set of qubits. In various aspects, the system can include a partition component that can partition the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to template matching. In various instances, template matching can be performed on the computation stages.

Description

[Technical field]

[0001] The subject disclosure relates to Clifford circuits, and more particularly, to partitioned template matching and symbolic peephole optimization for Clifford circuits. [Background technology]

[0002] A quantum circuit is a transformation that operates on a set of quantum bits. Quantum circuits can be represented as unitary matrices (e.g., for any suitable positive integer n, a quantum circuit that operates on n quantum bits can be expressed as 2 n ×2 n The quantum state of a set of qubits can be represented by a quantum state vector (e.g., for n qubits, the quantum state vector is 2 n (which may have elements of x, y ...

[0003] The long-term success of quantum computing depends on achieving at least partial error tolerance. Clifford circuits are a particular type of quantum circuit that is integrated into error-tolerant quantum computing (e.g., the encoding circuits for many quantum error-correcting codes are Clifford circuits). Clifford circuits can be useful in quantum computing, so the synthesis of optimized Clifford circuits that implement a given Clifford operator may be desirable. Optimization of Clifford circuits aims to reduce the number of gates for a single qubit or two qubits or both in the Clifford circuit, so that the computation time and / or computational resources required to execute the Clifford circuit can be reduced.

[0004] Much work has been done on the synthesis of asymptotically optimized Clifford circuits (e.g., Clifford circuits that are optimal up to a certain factor and therefore not exactly optimal). Traditionally, the synthesis of exactly optimized Clifford circuits has been prohibitively expensive, even for small numbers of qubits (e.g., conventional techniques can generate exactly optimized Clifford circuits up to 4 qubits, and optimized Clifford circuits up to 5 qubits for input / output permutations). Conventional techniques for optimizing Clifford circuits include template matching and peephole optimization. Template matching involves exploiting a template (e.g., a string of gates known to be equal to an identity) to reduce the number of gates in a given circuit. Conventional template matching is a general technique that works for Clifford and non-Clifford circuits alike. Thus, conventional template matching does not exploit and / or does not exploit certain structural properties of Clifford circuits, which limits the extent to which the circuits can be optimized. Peephole optimization involves identifying subcircuits within an overall Clifford circuit and utilizing a library of known optimal circuits to optimize the subcircuit. A technical challenge with traditional peephole optimization is that it requires that the subcircuit be completely isolated from the rest of the Clifford circuit. In other words, if a subcircuit contains an entangling gate that links the subcircuit to the rest of the circuit, traditional peephole optimization cannot be used.

[0005] Systems and / or techniques that can mitigate and / or solve one or more of these technical challenges would be desirable. Summary of the Invention

[0006] The following summary is presented in order to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the scope of the claims. The summary's sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a device, system, computer-implemented method, apparatus, or computer program product, or combination thereof, is described that can facilitate partitioned template matching and symbolic peephole optimization for Clifford circuits.

[0007] According to one or more embodiments, a system is provided. The system may include a memory capable of storing computer-executable components. The system may further include a processor capable of operably coupling to the memory and executing the computer-executable components stored in the memory. In various embodiments, the computer-executable components may include a template component capable of performing template matching on a Clifford circuit associated with a set of qubits. In various aspects, the computer-executable components may further include a partition component capable of partitioning the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to template matching. In various cases, the template matching may be performed on the computation stage. In various embodiments, the computer-executable components may further include a symbolic component capable of selecting a subset of qubits from the set of qubits, reconnecting at least one entangling gate in the computation stage such that a target of the at least one entangling gate is within the subset of qubits, and replacing the at least one reconnected entangling gate with a symbolic Pauli gate. In various cases, the symbolic Pauli gate can be a Pauli gate controlled by a symbolic variable. In various embodiments, the computer-executable components can further include a peephole component that can perform peephole optimization on a subset of qubits using the symbolic Pauli gate by implementing a dynamic programming algorithm.

[0008] According to one or more embodiments, the above-described systems may be implemented as computer-implemented methods and / or computer program products.

[0009] According to one or more embodiments, a system is provided. The system may include a memory capable of storing computer-executable components. The system may further include a processor capable of operably coupling to the memory and executing the computer-executable components stored in the memory. In various embodiments, the computer-executable components may include a peephole component capable of performing a peephole optimization on a Clifford circuit associated with a set of qubits. In various cases, the computer-executable components may further include a symbolic component capable of selecting a subset of qubits from the set of qubits prior to the peephole optimization, rewiring at least one entangling gate in the Clifford circuit such that a target of the at least one entangling gate is within the subset of qubits, and replacing the at least one rewired entangling gate with a symbolic Pauli gate. In various aspects, the computer-executable components may further include a partition component capable of partitioning the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage. In various cases, the computer-executable components can further include a template component that can perform template matching for a computation stage prior to rewiring the at least one entangling gate.

[0010] According to one or more embodiments, the above-described systems may be implemented as computer-implemented methods and / or computer program products. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a block diagram of an example, non-limiting system that facilitates partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Diagram 2] FIG. 1 is a flow diagram of an example, non-limiting computer-implemented method for facilitating partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Diagram 3] FIG. 1 is a flow diagram of an example, non-limiting computer-implemented method for facilitating partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Figure 4] 1 is an example, non-limiting table and an example, non-limiting compilation algorithm according to one or more embodiments described herein. [Diagram 5] FIG. 1 is a block diagram of an example, non-limiting system including a compute stage, a Pauli stage, and a SWAP stage that facilitates partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Figure 6] FIG. 13 is a diagram of how a Pauli gate can be pushed to the end of a Clifford circuit in an example, non-limiting manner, according to one or more embodiments described herein. [Figure 7] FIG. 2 is a diagram of an example, non-limiting Clifford circuit that has been partitioned in accordance with one or more embodiments described herein. [Figure 8]FIG. 1 is a block diagram of an example, non-limiting system including a library of templates that facilitates partitioned template matching and / or symbolic peephole optimization, according to one or more embodiments described herein. [Figure 9] FIG. 1 is a diagram of an example, non-limiting template that can be utilized for template matching, according to one or more embodiments described herein. [Figure 10] FIG. 13 is a diagram of an example, non-limiting template that can be utilized for Hadamard and / or phase pushing during template matching, according to one or more embodiments described herein. [Figure 11] FIG. 1 is a block diagram of an example, non-limiting system including floating-gate transformation rules that facilitate partitioned template matching and / or symbolic peephole optimization, in accordance with one or more embodiments described herein. [Figure 12] FIG. 13 is a diagram of an example, non-limiting rule for transforming a Pauli operator back into the original Hadamard gate and / or phase gate after a floating gate push, according to one or more embodiments described herein. [Figure 13] FIG. 13 illustrates how a floating gate push can be used to remove a blocking gate from the template matching range in an example, non-limiting manner, according to one or more embodiments described herein. [Figure 14] FIG. 1 is a block diagram of an example, non-limiting system that includes a SWAP equivalence relation to facilitate partitioned template matching and / or symbolic peephole optimization, in accordance with one or more embodiments described herein. [Figure 15]FIG. 13 illustrates, in an exemplary, non-limiting manner, how a SWAP gate can be optimized at the cost of one entangling gate, in accordance with one or more embodiments described herein. [Figure 16] FIG. 1 is a block diagram of an example, non-limiting system including a symbolic Pauli gate to facilitate partitioned template matching and / or symbolic peephole optimization, in accordance with one or more embodiments described herein. [Figure 17] FIG. 13 illustrates how a straddling gate can be rewired in an example, non-limiting manner, according to one or more embodiments described herein. [Figure 18] FIG. 13 illustrates, in an exemplary, non-limiting manner, how a symbolic Pauli gate can be used to improve peephole optimization, in accordance with one or more embodiments described herein. [Figure 19] FIG. 1 is a block diagram of an example, non-limiting system including a library of optimal sub-circuits that facilitates partitioned template matching and / or symbolic peephole optimization, in accordance with one or more embodiments described herein. [Figure 20] FIG. 1 is a flow diagram of an example, non-limiting computer-implemented method for facilitating partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Figure 21] FIG. 1 is a flow diagram of an example, non-limiting computer-implemented method for facilitating partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. [Figure 22] FIG. 1 is a block diagram of an example, non-limiting operating environment capable of facilitating one or more embodiments described herein. [Diagram 23]FIG. 1 illustrates an example, non-limiting cloud computing environment in accordance with one or more embodiments described herein. [Figure 24] FIG. 1 is a diagram of an example, non-limiting abstract model layer, according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following detailed description is merely illustrative and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any stated or implied information presented in the preceding "Background" or "Summary" sections, or in the "Description of the Preferred Embodiments" section.

[0013] One or more embodiments will now be described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

[0014] As mentioned above, a quantum circuit is a transformation that operates on a set of quantum bits. For any suitable positive integer n, a quantum circuit that operates on n quantum bits can be constructed in 2 n ×2 n The quantum state of a set of n qubits can be expressed as a unitary matrix of 2 n A quantum circuit can be applied to a quantum state vector via matrix multiplication. Moreover, quantum circuits can be combined in series via matrix multiplication, or in parallel via tensor products (e.g., the Kronecker product), or both.

[0015] As explained above, Clifford circuits are an important type of quantum circuit (e.g., important for achieving quantum error tolerance). Thus, improved optimization techniques for Clifford circuits may be desirable, where the optimization involves reducing the gate count of a given Clifford circuit without changing the overall function / transformation implemented by that Clifford circuit.

[0016] Clifford circuits, also known as stabilizer circuits, can be constructed from Hadamard gates (H), phase gates (also known as S, P), controlled NOT gates (CNOT), and Pauli gates (X, Y, and Z), where:

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[0017] An important property of Clifford circuits is that the Clifford gates H, S, and CNOT can map a Pauli matrix (or a tensor product of Pauli matrices, or both) onto itself by conjugation. Equivalently, this can be written as a Pauli gate being "pushed" through such Clifford gates H, S, and CNOT. That is, HX=ZH;HY=-YH;HZ=XH;SX=YS;SY=-XS;SZ=ZS CNOT 1,2 X1=X1X2CNOT 1,2 ;CNOT 1,2 X2=X2CNOT 1,2 ; CNOT 1,2 Z2=Z1Z2CNOT 1,2 ;CNOT 1,2 Z1=Z1CNOT 1,2 where the subscripts define the control and target qubits. For ease of explanation, these equations can be referred to as the Pauli push equations. As shown in each of these Pauli push equations, a given Pauli gate implemented on the left-hand side of a Clifford gate is equivalent to some potentially different Pauli gate implemented on the right-hand side of the same Clifford gate. Thus, a Pauli can be "pushed" from one side of a Clifford gate to the other.

[0018] As mentioned above, optimization of the Clifford circuit is conventionally done via template matching and peephole optimization, which are briefly described below.

[0019] First, consider template matching. For any suitable positive integer m, a template of size m is a sequence of m gates that realizes the identity function: T=G0G1...G m-1 =I where T represents the template and G j represents one gate for all non-negative integers j.

[0020] To see how the template can be used to reduce the number of gates, let us consider a subsequence of the template G j ...G j+p-1(mod m)For some index j, and for some 0≦p≦m, we observe whether p matches a gate in the circuit, and if the gates in the circuit can be moved together (e.g., made contiguous), then these gates in the circuit can be replaced by the inverse of other mp gates in the template. The larger the length p of the sequence, the more useful it is to perform the replacement, and the more efficient it becomes.

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[0021] In various cases, a template T of size m can be independent of templates of smaller size (e.g., application of a smaller template cannot reduce the number of gates in T or make it equal to another template). Circuit optimization using template matching is an iterative procedure in which, at each step, the optimization starts with a given gate in the circuit and attempts to match the given template as far back or as far forward, or both. If the matched gates can be moved together and a substitution would be beneficial, the template can be applied as defined above. However, if the matched gates cannot be moved together and / or cannot be made contiguous, the template cannot be applied. If the matched gates are not contiguous, one can say that there is at least one blocking gate between the matched gates. Equivalently, one can say that there is at least one blocking gate in the template matching range. In various cases, the steps can be repeated for all templates, or for all gates in the circuit, or both, until a given convergence criterion (e.g., a suitable predefined convergence criterion) is met. As a result, the circuit gate count can be reduced (eg, optimized).

[0022] As explained above, such conventional template matching is generally defined for quantum circuits. Thus, while conventional template matching is applicable to Clifford circuits, it does not exploit the specific properties of Clifford circuits for optimization. As described herein, the inventors of various embodiments of the present invention have devised techniques for improving template matching (e.g., making template matching more efficient) that works by exploring the specific structure of Clifford circuits.

[0023] Next, we consider peephole optimization. Similar to template matching, peephole optimization is an iterative procedure that optimizes circuits by considering subcircuits for a small subset of qubits, which we can call A, and then tries to replace such subcircuits with optimized versions from a database / library of precomputed optimal circuits. At each step, for a given gate, all subcircuits for a fixed small number of qubits (e.g., |A|=4) that contain that gate are considered. For each subcircuit, its cost can be calculated, and thus the optimal cost of the unitary implementation can be calculated (e.g., this optimal cost can be retrieved from a database of precomputed optimal circuits). If a replacement is beneficial, the subcircuit is replaced with the optimal implementation. The steps can be repeated for all gates until any suitable predefined convergence criterion is met.

[0024] As explained above, such traditional peephole optimization only works when the sub-circuit is completely decoupled from the rest of the circuit (e.g., the sub-circuit cannot include a straddling two-qubit gate that couples the sub-circuit to the rest of the circuit). As described herein, the inventors of various embodiments of the present invention have devised techniques to allow peephole optimization to be performed on a sub-circuit even when the sub-circuit is not completely decoupled from the rest of the circuit.

[0025] Various embodiments of the present invention may address one or more of these technical challenges. In particular, various embodiments of the present invention may provide systems and / or techniques that may facilitate partitioned template matching and / or symbolic peephole optimization, thereby optimizing Clifford circuits more efficiently than conventional template matching and / or conventional peephole optimization. In various aspects, the teachings described herein amount to a heuristic approach to Clifford circuit optimization that may bridge the gap between non-scalable methods for the synthesis of accurately optimized Clifford circuits and suboptimal (albeit asymptotically optimal) and inexpensive synthesis techniques. In various instances, embodiments of the present invention may be considered as computer-implemented tools (e.g., computer-implemented software programs) that may receive suboptimal Clifford circuits as inputs and produce optimized versions of these suboptimal Clifford circuits as outputs more efficiently and / or effectively than conventional systems and / or techniques can.

[0026] In various embodiments, such computer-implemented tools can apply partitioned template matching to the input Clifford circuit, which can be thought of as an improved version of template matching that leverages / takes advantage of the unique properties / structure of Clifford circuits. Specifically, partitioned template matching leverages the observation that in a Clifford circuit, Pauli gates can always be "pushed" to the end of the circuit (e.g., via the Pauli push equation described above) without changing the non-Pauli Clifford gates (e.g., H, S, CNOT). In various embodiments, partitioned template matching can include three steps. First, the Clifford circuit can be partitioned into computation stages, Pauli stages, and SWAP stages by "pushing" every Pauli gate and every SWAP gate in the Clifford circuit to the end of the Clifford circuit (one skilled in the art will appreciate that SWAP gates can be "pushed" through the Clifford circuit in the same and / or similar manner that Pauli gates can be "pushed" through the Clifford circuit). In various cases, a computation stage may contain only H, S, and CNOT gates, a Pauli stage may contain only Pauli gates, and a SWAP stage may contain only SWAP gates. Second, template matching can be applied to the computation stage to reduce the gate count (e.g., it may be easier to apply templates because Pauli and SWAP are pushed to the end of the circuit during partitioning; in other words, Pauli and SWAP are excluded from the computation stage). Third, the SWAP stage can be optimized by exploiting the fact that a SWAP gate can be implemented for the effective cost of a two-qubit gate if it can be "aligned" with another two-qubit gate.In some cases, if application of a template or SWAP optimization results in a Pauli gate in a computation stage, such a Pauli gate can be pushed through the Pauli stage (e.g., the circuit can be repartitioned). In some aspects, application of a template to a computation stage can be hindered by a blocking gate. As described herein, the inventors have devised a novel floating gate technique that removes the blocking gate, thereby enabling application of the template. In other words, the inventors have devised a procedure that allows application of the template to a sequence of discontinuous gates that cannot be moved together directly. Such a procedure attempts to move (e.g., "float") a single qubit gate that blocks application of the template elsewhere by decomposing the single qubit gate into a linear combination of Pauli operators and "pushing" the Pauli operator until it can be combined with the original single qubit gate that no longer blocks application of the template.

[0027] In other words, while traditional template matching simply applies a template directly to a given Clifford circuit, partitioned template matching can include: (1) partitioning a given Clifford circuit into three stages (e.g., computation, Pauli, and SWAP) by "pushing" any Pauli and / or SWAP gates in the given Clifford circuit to the end of the given Clifford circuit; (2) applying a template to one of the three partitions (e.g., computation stage); and (3) implementing SWAP optimization by aligning SWAP to two-qubit gates. As mentioned above, various embodiments of the present invention can implement floating gate techniques that allow for the application of templates to non-contiguous sequences of gates. As described herein, floating gate techniques can include rewriting blocking gates as linear combinations of Paulis and "pushing" the Paulis out of the desired template matching range, thereby allowing for the application of the desired template. Conventional template matching simply does not include such partitioning or floating gate techniques.

[0028] In various instances, computer-implemented tools according to various embodiments of the present invention can apply symbolic peephole optimization to a given circuit, which can be thought of as an improved version of peephole optimization that can work even when the subcircuits are not completely isolated. Specifically, when considering a subcircuit that is coupled / entangled with the rest of the circuit by a straddling gate, such a straddling gate can be rewritten such that the target of the straddling gate is within the subcircuit (e.g., this can typically be done by application of various Hadamard gates and / or phase gates), and then the rewritten straddling gate can be replaced and / or represented by a symbolic Pauli gate as defined herein. As described below, a symbolic Pauli gate is a Pauli gate that is controlled by a symbolic variable rather than another qubit. A symbolic Pauli gate is obtained from a two-qubit gate by removing the control and replacing the target with a Pauli gate as desired. Therefore, a symbolic Pauli gate can be treated as a single qubit gate. Subcircuits with symbolic Pauli gates can then be optimized using dynamic programming and / or a library of precomputed optimal circuits. That is, when a symbolic Pauli gate is implemented, the subcircuit can effectively be treated as if it were completely decoupled from the rest of the circuit, despite the fact that the subcircuit is not completely decoupled from the rest of the circuit.

[0029] In other words, while traditional peephole optimization simply involves identifying fully decoupled subcircuits and replacing all or part of the fully decoupled subcircuits with precomputed optimal circuits, symbolic peephole optimization can include: (1) identifying suitable subcircuits that are fully decoupled or not; (2) rewriting suitable straddling gates so that the target of the straddling gate is within the subcircuit (e.g., so that the control of the rewritten straddling gate is within the remainder of the circuit); (3) replacing each rewritten straddling gate in the subcircuit with a symbolic Pauli gate (e.g., a Pauli gate controlled by a symbolic variable); and (4) replacing all or part of the subcircuit that has a symbolic Pauli gate with a precomputed optimal circuit. Traditional peephole optimization simply cannot handle straddling gates.

[0030] In various cases, partitioned template matching and symbolic peephole optimization may be sequentially combined for improved optimization of the Clifford circuit (e.g., a computer-implemented tool as described herein may receive a Clifford circuit as input, may apply partitioned template matching to the input Clifford circuit, and may then apply symbolic peephole optimization, thereby providing an optimized Clifford circuit as output).

[0031] Various embodiments of the invention may be employed to use hardware and / or software to solve technical problems that are advanced in nature (e.g., facilitating partitioned template matching and / or symbolic peephole optimization), are not abstract, and cannot be performed as a set of mental acts by a human. Furthermore, some of the processes performed may be performed by specialized computers (e.g., performing template matching on a Clifford circuit associated with a set of qubits by a device operatively coupled to a processor; partitioning the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to template matching, where template matching is performed on the computation stage by the device; partitioning the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage, where template matching is performed on the computation stage by replacing blocking gates with linear combinations of Pauli operators in the computation stage); (e.g., pushing a subset of qubits out of a switching range; selecting, by the device, a subset of qubits from the set of qubits; reconnecting, by the device, at least one entangling gate in a computation stage such that a target of the at least one entangling gate is among the subset of qubits; replacing, by the device, the at least one reconnected entangling gate with a symbolic Pauli gate, where the symbolic Pauli gate is a Pauli gate controlled by a symbolic variable; performing, by the device, a peephole optimization on the subset of qubits with the symbolic Pauli gate). Such defined tasks are typically not performed manually by a human.Moreover, neither the human mind nor a human with pen and paper can electronically optimize a Clifford circuit by electronically partitioning it into three separate stages, by applying template matching to one of these stages, or by electronically replacing the Stradling gates with symbolic Pauli gates, or by any combination thereof. Instead, various embodiments of the invention are intrinsically and intimately related to computer technology and cannot be implemented outside of a quantum computing environment (e.g., various embodiments of the invention are directed to systems and / or computer-implemented methods that can more efficiently optimize an input Clifford circuit; such systems and / or computer-implemented methods would be extremely useful in the field of quantum computing, but cannot actually be implemented in any sensible way outside of a computing environment).

[0032] In various instances, various embodiments of the present invention may integrate the disclosed teachings regarding partitioned template matching and symbolic peephole optimization into practical applications. Indeed, various embodiments of the present invention, which may take the form of systems and / or computer-implemented methods as described herein, may be thought of as computerized tools that can receive a Clifford circuit as input and generate an optimized (e.g., reduced gate count) version of the Clifford circuit as output. More specifically, such computerized tools may facilitate such optimization by implementing partitioned template matching (as opposed to conventional template matching) and by implementing symbolic peephole optimization (as opposed to conventional peephole optimization). Electronic generation of optimized Clifford circuits is certainly a useful and practical application of computers, especially in view of the importance of Clifford circuits to error-tolerant quantum computing. Moreover, as noted above, various embodiments of the present invention may solve / address some of the technical challenges experienced by the prior art. Specifically, while conventional template matching is a general procedure, partitioned template matching can be thought of as a Clifford-specific version of template matching that optimizes Clifford circuits more efficiently than conventional template matching allows. In addition, while conventional peephole optimization does not work when the subcircuit under consideration is not completely isolated from the rest of the circuit (e.g., it does not work when there are straddling gates), symbolic peephole optimization can be thought of as an improved version of peephole optimization that works despite the absence of complete isolation. Overall, such systems and / or techniques clearly constitute concrete, tangible technological improvements in the field of Clifford circuit optimization.

[0033] Moreover, various embodiments of the present invention can control real-world devices based on the disclosed teachings. For example, embodiments of the present invention can receive as input a real-world sub-optimal Clifford circuit by implementing partitioned template matching and symbolic peephole optimization, and generate as output a real-world optimized version of the sub-optimal Clifford circuit. In some cases, embodiments of the present invention can run such a real-world optimized version of the sub-optimal Clifford circuit on a real-world quantum computing device.

[0034] It should be appreciated that the drawings and disclosure herein are illustrative and not limiting.

[0035] FIG. 1 is a block diagram of an example, non-limiting system 100 that can facilitate partitioned template matching and / or symbolic peephole optimization according to one or more embodiments described herein. As shown, a Clifford optimization system 102 can receive a sub-optimal Clifford circuit 104 as an input and electronically generate an optimized Clifford circuit 106 as an output via any suitable wired and / or wireless electronic connection. In various aspects, the optimized Clifford circuit 106 can be functionally equivalent to the sub-optimal Clifford circuit 104 (e.g., the same overall transformation can be implemented as the sub-optimal Clifford circuit 104), but can have a reduced gate count than the sub-optimal Clifford circuit 104. In various aspects, the sub-optimal Clifford circuit 104 can perform operations on any suitable number of quantum bits. If the sub-optimal Clifford circuit 104 operates on n quantum bits for any suitable positive integer n, then the optimized Clifford circuit 106 can also perform operations on n quantum bits.

[0036] In various embodiments, the Clifford optimization system 102 can include a processor 108 (e.g., a computer processing unit, microprocessor) and a computer-readable memory 110 operatively coupled to the processor 108. The memory 110 can store computer-executable instructions that, when executed by the processor 108, cause the processor 108 or other components of the Clifford optimization system 102 (e.g., the partition component 112, the template component 114, the floating component 116, the SWAP component 118, the symbolic component 120, the peephole component 122), or combinations thereof, to perform one or more operations. In various embodiments, the memory 110 can store and the processor 108 can execute the computer-executable components (e.g., the partition component 112, the template component 114, the floating component 116, the SWAP component 118, the symbolic component 120, the peephole component 122).

[0037] In various embodiments, the Clifford optimization system 102 can include a partition component 112. In various aspects, the partition component 112 can partition (e.g., segment) the sub-optimal Clifford circuit 104 into computational stages, Pauli stages, and SWAP stages. In various cases, the partition component 112 can “push” any Pauli gates (e.g., X, Y, or Z, or combinations thereof) to the end of the sub-optimal Clifford circuit 104 via the Pauli push equations referenced above. Similarly, the partition component 112 can “push” any SWAP gates in the sub-optimal Clifford circuit 104 to the end of the sub-optimal Clifford circuit 104 via similar push equations applicable to SWAP gates. As a result, all SWAP gates are now located in one portion of the suboptimal Clifford circuit 104, now referred to as the SWAP stage, all Pauli gates are now located in a different portion of the suboptimal Clifford circuit 104, now referred to as the Pauli stage, and the remaining Clifford gates (e.g., H, S, CNOT) can be located in yet another portion of the suboptimal Clifford circuit 104, now referred to as the computation stage. In other words, the partition component 112 can move different operators / gates of the suboptimal Clifford circuit 104 to different positions in the suboptimal Clifford circuit 104 without functionally changing the overall transformation implemented by the suboptimal Clifford circuit 104.

[0038] In various embodiments, the Clifford optimization system 102 can include a template component 114. In various aspects, the template component 114 can store, maintain, and / or have any suitable form of access to a library of templates. In various cases, the template can be any suitable string of quantum gates that implement an identity transformation and / or are equivalent to an identity transformation. In various cases, the template component 114 can facilitate template matching to a computational stage of the sub-optimal Clifford circuit 104 by utilizing a library of templates. In other words, the template component 114 can apply one or more templates from the library of templates to a computational stage of the sub-optimal Clifford circuit 104 to reduce the gate count of the sub-optimal Clifford circuit 104. It should be noted that in some cases, applying a template to a computational stage is easier and / or more efficient / effective than applying a template to a non-partitioned version of the sub-optimal Clifford circuit 104. That is, all Pauli gates and / or SWAP gates in the sub-optimal Clifford circuit 104 are "pushed" toward the end of the sub-optimal Clifford circuit 104 by the partition component 112 so that these Pauli gates and / or SWAP gates are no longer present in the computation stage and therefore cannot block and / or impede the application of the template to the computation stage (e.g., without partitioning, Pauli gates and / or SWAP gates may be located in the middle of the template matching range and therefore may block / prevent the application of the template).

[0039] In various embodiments, the Clifford optimization system 102 can include a floating component 116. In various aspects, the floating component 116 can store, maintain, or have any suitable form of access to, or combinations of, various floating gate transformation rules. In various cases, as mentioned above, a gate in a computation stage may block or hinder the application of a template, or both (e.g., an undesirable H gate or an undesirable S gate or both may be present within the template matching range). Traditionally, nothing is done and a different template is tried. However, in various aspects, the floating component 116 can solve this problem. Specifically, in various cases, the floating component 116 can utilize floating gate transformation rules to rewrite and / or transform a blocking gate into a linear combination of Pauli gates (e.g., H can be expressed as a linear combination of Pauli gates, and S can be expressed as a linear combination of Pauli gates). The floating component 116 can then "push" the linear combination of Pauli gates out of the template matching range via the Pauli push equation. Thus, the blocking gates are removed from the matching range and the template can be applied. In some cases, the floating component 116 can convert the linear combination of the moved Pauli operators back to the original single qubit gate using floating gate transformation rules. In other words, the partition component 112 can move the Pauli gates out of the template matching range, and the floating component 116 can move the Hadamard gates and / or phase gates out of the template matching range.

[0040] In various embodiments, the Clifford optimization system 102 can include a SWAP component 118. In various aspects, the SWAP component 118 can store, maintain, or have any suitable form of access to or combination of various SWAP equivalence relations. In various aspects, the SWAP gate can be implemented at the practical cost of a two-qubit gate (e.g., CNOT) by pushing / merging the SWAP gate back into the computation stage and combining it with a two-qubit gate according to a known equation / formula. The SWAP equivalence relations can be known equations / formulas. That is, the SWAP equivalence relations can be various equations that indicate the resulting circuit and / or resulting gate string that is realized when the SWAP gate is implemented consecutively with a CNOT gate and / or a CZ gate. In this manner, the SWAP component 118 can replace a SWAP gate in the SWAP stage of the suboptimal Clifford circuit 104.

[0041] In various embodiments, the Clifford optimization system 102 can include a symbolic component 120. In various aspects, the symbolic component 120 can perform various actions that can prepare a partitioned, template-matched version of the suboptimal Clifford circuit 104 for peephole optimization. Specifically, the symbolic component 120 can select any suitable subcircuit in a computation stage (e.g., a subcircuit that operates on two qubits or three qubits or both). In various cases, the symbolic component 120 can then rewrite any straddling gates so that their targets are in the subcircuit, or are operated on by the subcircuit, or both. In various cases, the straddling gates can be two-qubit gates (e.g., CNOT and / or CZ) that have only one of the target qubit or control qubit in the subcircuit. If the target qubit of the stradling gate is in and / or is manipulated by the subcircuit, the control qubit of the stradling gate is in and / or is manipulated by the rest of the circuit. On the other hand, if the control qubit of the stradling gate is in and / or is manipulated by the subcircuit, the target qubit of the stradling gate is in and / or is manipulated by the rest of the circuit. Thus, the stradling gate couples the subcircuit to the rest of the circuit. In various embodiments, the symbolic component 120 can use any suitable mathematical equation / formula to rewire the stradling gate such that the target qubit of the stradling gate is in the subcircuit.In various instances, the symbolic component 120 can then replace the rewired straddling gates in the subcircuit with symbolic Pauli gates. Like entangling gates (e.g., CNOT and / or CZ), the symbolic Pauli gates can be control Pauli gates (e.g., X, Y, or Z or combinations thereof). However, unlike entangling gates, the symbolic Pauli gates can be controlled by symbolic variables rather than by another qubit. In various embodiments, the value of the symbolic variable can be 0 or 1, and the symbolic variable can be the exponent of the symbolic Pauli gate. Thus, when the symbolic variable has a value of 1, the symbolic Pauli gate can implement the underlying Pauli. However, when the symbolic variable has a value of 0, the symbolic Pauli gate can implement the identity transformation instead. In this way, the symbolic Pauli gate can mimic the behavior of a control Pauli (e.g., CNOT and / or CZ) but can be treated as a single-qubit gate (e.g., as a non-entangling gate) for the purposes of peephole optimization.

[0042] In various embodiments, the Clifford optimization system 102 can include a peephole component 122. In various aspects, the peephole component 122 can store, maintain, or have any suitable form of access to a library of optimal circuits, or a combination thereof. In various aspects, the peephole component 122 can leverage the library of optimal circuits to perform peephole optimization on subcircuits having symbolic Pauli gates (e.g., precomputed optimal circuits in the library can replace all and / or a portion of the gates in the subcircuit, thereby reducing the gate count). As mentioned above, conventional peephole optimization techniques simply cannot be performed on subcircuits that are not fully decoupled. However, with symbolic Pauli gates, symbolic peephole optimization can be performed on subcircuits that are not fully decoupled.

[0043] In various embodiments, the Clifford optimization system 102 may iteratively execute all or some or both of the partition component 112, the template component 114, the floating component 116, the SWAP component 118, the symbolic component 120, and / or the peephole component 122, thereby resulting in an optimized Clifford circuit 106.

[0044] 2-3 are flow diagrams of example, non-limiting computer-implemented methods 200 and 300 that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. In some cases, computer-implemented methods 200 and 300 can be facilitated by system 100.

[0045] Consider first the computer-implemented method 200. In various embodiments, operation 202 may include receiving, by a device operatively coupled to the processor, a sub-optimal Clifford circuit (e.g., 104). In some embodiments, the sub-optimal Clifford circuit may be received and optimized directly, while other embodiments may include receiving a Clifford unitary, compiling the Clifford unitary by a technique based on Gaussian elimination on symplectic matrices (e.g., sometimes referred to as baseline compilation), and optimizing the compiled circuit.

[0046] In various embodiments, operation 204 can include partitioning the sub-optimal Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage by “pushing” a Pauli gate or a SWAP gate, or both, onto the end of the sub-optimal Clifford circuit, by a device (e.g., 112).

[0047] In various cases, operation 206 can include performing, by the device, template matching (e.g., via 114) and / or SWAP optimization (e.g., via 118) passes through the computation stages until a convergence criterion is reached. In some cases, this operation can include repartitioning a suboptimal Clifford circuit each time applying a template and / or merging SWAP gates produces Pauli gates and / or SWAP gates during a computation stage.

[0048] In various cases, act 208 may include performing, by a device (e.g., 120 and 122), symbolic peephole optimization passes over the computation stages in a random order.

[0049] In some embodiments, operation 210 may include performing, by a device (e.g., 114), another template matching pass through the computation stages to further reduce the single qubit gate count.

[0050] In various cases, operation 212 may include outputting, by the device, an optimized Clifford circuit (eg, 106) that implements the sub-optimal Clifford circuit.

[0051] Consider now the computer-implemented method 300. In various embodiments, operation 302 may include receiving, by a device operably coupled to the processor, a sub-optimal Clifford circuit (e.g., 104).

[0052] In various embodiments, operation 304 may include synthesizing, by the device, a sub-optimal Clifford circuit using a baseline compiler (e.g., Gaussian elimination for symplectic matrices).

[0053] In various cases, operation 306 may include performing, by the device, operations 204-210 of the computer-implemented method 200.

[0054] In various cases, act 308 may involve the device iteratively repeating acts 304-306 any suitable number of times and selecting the best circuit obtained by the device.

[0055] In various aspects, operation 310 may include outputting, by the device, an optimized Clifford circuit (eg, 106) that implements the sub-optimal Clifford circuit.

[0056] As described herein, various embodiments of the present invention can facilitate partitioned template matching and symbolic peephole optimization, which can be thought of as two novel algorithms for Clifford circuit optimization. In some cases, these novel algorithms can be applied in at least two ways. First, if the input is Clifford unitary, optimization begins by synthesizing the circuit using a baseline compiler (discussed with respect to FIG. 4), where optimization involves reducing the gate count by applying partitioned template matching or symbolic peephole optimization, or both. Second, if the input is not Clifford unitary, but is instead a Clifford circuit, optimization can begin by resynthesizing the circuit, or by directly applying partitioned template matching or symbolic peephole optimization, or both. In some cases, both of these methods can be performed in parallel, and the best result can be chosen. As mentioned above, in some cases, gate count can be further reduced by iteratively repeating the baseline compilation and optimization any suitable number of times and then choosing the best result.

[0057] 4 is a diagram of an example, non-limiting table 402 and an example, non-limiting compilation algorithm / circuitry 404, according to one or more embodiments described herein. In other words, FIG. 4 illustrates how a baseline compiler can function.

[0058] Let PL(n) denote the group of Pauli operators for n qubits, and CL(n) denote the group of Clifford operators for n qubits. The Clifford operator D∈CL(n) is D -1 OD=X1 and D -1We say that we separate a pair of Pauli operators O,O'∈PL(n) if O'D = Z1. Note that this is possible only if OO' = -O'O. Then, the following holds: A pair of anticommutative Pauli operators O,O'∈PL(n) can be separated by some Clifford operator D with CNOT cost ≤ (3 / 2)n + O(1), where the operator D can be computed in time O(n) (e.g., in capital O notation). This can be referred to as Lemma 1.

[0059] Let the goal be to compile a given Clifford operator C∈CL(n) using single-qubit gates and CNOT gates. For each qubit j∈[n], O j =CX j C -1 And O' j =CZ j C -1 Let us assume that. j and O' j Note that D is anticommutative. j ∈CL(n), O j and O' j Let D be the Clifford operator that separates pairs of j Pick a qubit j such that j has the minimum number of CNOT gates, or pick a random qubit if using a randomized version of the compilation algorithm. Define j as follows:

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[0060] The proof of Lemma 1 is as follows. In particular, a separation operator D can be explicitly constructed such that D maps the anticommutative Pauli pairs O and O' to X1 and Z1, respectively, as shown below. The objective is to minimize the CNOT cost of D.

[0061] The Pauli operators O and O' are in standard form if their action on every qubit j fits one of the five cases shown in table 402 of FIG. 4. Recall that the single-qubit Clifford group CL(1) acts by permutation on the Pauli operators X, Y, and Z. Therefore, every Pauli pair O and O' can be converted to standard form by applying a layer of single-qubit Clifford operators. This partitions the n qubits into five disjoint subsets [n]=ABCDE. A has odd size because otherwise O and O' would commute. Let A(j) be the jth qubit of A. Now apply the algorithm / circuit 404 shown in FIG. 4. Let D be the operator realized by the compilation algorithm / circuit 404 combined with an initial layer of single-qubit Clifford operators. Direct inspection shows that D has the desired separation property described above, up to the sign coefficient. The sign coefficients can be fixed by applying Pauli X1 or Y1 or Z1 as the final gate of D. The resulting circuit has some CNOT number such that at most (3 / 2)|A|+|B|+|C|+|D|+O(1)≦(3 / 2)n+O(1).

[0062] Note that the above proof uses the symbol D in two separate senses, as a way to denote a separate circuit (e.g., shown as algorithm / circuit 404) and as a way to denote a subset of qubits (e.g., [n]=ABCDE). Those skilled in the art will appreciate these separate uses of the symbol D.

[0063] 5 is a block diagram of an example, non-limiting system 500 including a computation stage, a Pauli stage, and a SWAP stage that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 500 can, in some cases, include the same components as system 100 and can further include a computation stage 502, a Pauli stage 504, and a SWAP stage 506.

[0064] In various embodiments, the partition component 112 can partition the sub-optimal Clifford circuit 104 into a computation stage 502, a Pauli stage 504, and a SWAP stage 506. As explained above, a Clifford gate can turn a tensor product of Pauli matrices into a tensor product of Pauli matrices (e.g., via the Pauli push equation). The partition component 112 can take advantage of this fact. Specifically, the partition component 112 can utilize the Pauli push equation to "push" and / or move any Pauli operator in the sub-optimal Clifford circuit 104 to a specified location in the circuit, referred to as a Pauli stage 504. In a similar fashion, the partition component 112 can "push" and / or move the SWAP gate in the sub-optimal Clifford circuit 104 to a different designated location in the circuit referred to as the SWAP stage 506 (e.g., one skilled in the art will appreciate that the SWAP can be "pushed" and / or moved around the circuit via an equation similar to the Pauli push equation). As a result, the Pauli stage 506 can be a portion of the sub-optimal Clifford circuit 104 that includes only Pauli gates (e.g., X, Y, Z), the SWAP stage 506 can be a portion of the sub-optimal Clifford circuit 104 that includes only SWAP gates, and the computation stage 502 can be the remaining portion of the sub-optimal Clifford circuit 104 that includes the remaining Clifford gates (e.g., H, S, CNOT). FIGS. 6-7 help illustrate such partitioning.

[0065] 6 is a diagram of how a Pauli gate can be "pushed" onto the end of a Clifford circuit in an example, non-limiting manner in accordance with one or more embodiments described herein. As shown, FIG. 6 depicts a two-qubit circuit 602 and an equivalent two-qubit circuit 604. As shown, the two-qubit circuit 602 is coupled to a Clifford operator 608 (e.g., CNOT in the example shown) and a Pauli operator 606 applied to the left of the Clifford operator 608 (e.g., CNOT in the example shown).

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[0066] Those skilled in the art will appreciate that SWAP gates can be "pushed" in a similar manner.

[0067] FIG. 7 is a diagram of an example, non-limiting Clifford circuit 700 that has been partitioned according to one or more embodiments described herein. In other words, FIG. 7 illustrates an example, non-limiting result that can be obtained by partitioning with the partition component 112. The circuit 700 can be thought of as an example, non-limiting partitioned version of the suboptimal Clifford circuit 104. As shown, the Pauli push equation (and the similar SWAP push equation) can be utilized to partition the suboptimal Clifford circuit 104 into three different stages. Specifically, all Pauli operators in the suboptimal Clifford circuit 104 can be "pushed" and / or relocated by the partition component 112 to a specific location, referred to as the Pauli stage 504. Similarly, all SWAP gates in the suboptimal Clifford circuit 104 can be "pushed" and / or relocated by the partition component 112 to a different specific location, referred to as the SWAP stage 506. In various embodiments, the remainder of the sub-optimal Clifford circuit 104 may be referred to as a computation stage 502. As shown, the computation stage 502 may optionally include only H-gates, S-gates, and / or CNOT-gates, the Pauli stage 504 may optionally include only X-gates, Y-gates, and Z-gates, and the SWAP stage 506 may optionally include only SWAP gates.

[0068] 8 is a block diagram of an example, non-limiting system 800 including a library of templates that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 800 can, in some cases, include the same components as system 500 and can further include a library of templates 802.

[0069] In various embodiments, the template component 114 can electronically store, maintain, and / or have access to a library of templates 802. As described above, the templates can be any suitable string of gates that implement an identity transformation. In various aspects, the template component 114 can perform template matching for the computation stage 502 by utilizing the library of templates 802. As described above, template matching involves matching a subsequence of gates in the template to a corresponding subsequence of gates in the circuit. As long as the corresponding subsequence of gates in the circuit is contiguous (e.g., there are no blocking gates in the template matching range), the subsequence of gates in the circuit can be replaced with the inverse of the remaining gates in the template, thereby reducing the number of gates in the circuit. FIG. 9 illustrates various exemplary, non-limiting templates that may be present in the library of templates 802. In some cases, the template component 114 can simplify template matching (e.g., at the cost of introducing an extra Hadamard) by converting all 2-qubit gates in the computation stage 502 to CZ gates before performing template matching.

[0070] In various embodiments, the template component 114 can implement Hadamard and / or phase pushing through two-qubit gates to further reduce the number of single-qubit gates and increase the opportunities for template application. Suppose computation stage 502 is optimized using templates. The idea is to "push" the Hadamard and phase gates as far as possible to one of the two-qubit gates. "Pushing" a single-qubit gate through a two-qubit gate can be understood in terms of template application where a fixed subsequence must match. FIG. 10 illustrates exemplary, non-limiting templates that can be used to "push" Hadamard and phase. Consider template (a) of FIG. 10. Template (a) of FIG. 10 can be used to "push" the H gate to the right of the CNOT gate. Here, H and CNOT of template (a) of FIG. 10 must be matched in the circuit (indicated by the dashed lines), and then the remainder of template (a) of FIG. 10 may need to be replaced by its inverse. In the notation of the above discussion of template matching, the dashed lines can be understood to restrict the application of template (a) of FIG. 10 (which may be called, for example, a "Hadamard pushing template") to i=0 and p=2. Note that if the circuit is already optimized in terms of the number of two-qubit gates, template matching can be applied to reduce the number of single-qubit gates, specifically by restricting the templates used to a subset that allows the number of single-qubit gates to be reduced without also reducing the number of two-qubit gates. Such a subset of templates can include single-qubit templates and templates with an even number of two-qubit gates (when applied to replace half of the entangling gates with the remainder).

[0071] 11 is a block diagram of an example, non-limiting system 1100 including floating gate transformation rules that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 1100 can, in some cases, include the same components as system 800 and can further include floating gate transformation rules 1102.

[0072] As explained above, conventional template matching requires that matched gates in a circuit can be made contiguous by swapping. If the matched gates are not contiguous, then a blocking gate can be said to be within the template matching range, which may prevent the application of the template under consideration. In various embodiments, the floating component 116 can address this issue. Specifically, if the template component 114 cannot directly apply a template from the library of templates 802 for a blocking gate, the floating component 116 can take action. In various embodiments, the floating component 116 can iteratively attempt to move a single qubit gate that is within the template matching range elsewhere (e.g., attempt to remove the blocking gate). In various embodiments, this action includes moving the blocking gate to the left of the leftmost matched gate in the circuit or to the right of the rightmost matched gate in the circuit until all blocking gates have been moved out of the template matching range or until the matched gates can be moved together.

[0073] In various embodiments, the floating component 116 can electronically store, maintain, or have access to, or a combination of, floating gate transformation rules 1102. In various embodiments, the floating gate transformation rules 1102 can include rules (e.g., equivalence relations, equations, or formulas, or a combination thereof) for transforming phase gates and / or Hadamard gates into linear combinations of Pauli operators, or can include rules for transforming linear combinations of Pauli operators back to single qubit gates, or both. Specifically, the floating gate transformation rules 1102 include:

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[0074] 13 is a diagram of how a floating gate push can be used to remove a blocking gate from a template matching range in an example, non-limiting manner according to one or more embodiments described herein. In other words, FIG. 13 illustrates an example of how the floating component 116 can function.

[0075] As shown, FIG. 13 depicts an example, non-limiting template 1302, and an example, non-limiting circuit 1304. Note that template 1302 can be equivalent to template (e) of FIG. 9. As can be seen, the first three gates (e.g., CNOT gates in top-to-bottom qubit order) of template 1302 are 2,1 , CNOTT 3,1 , and CNOT 3,2 ) matches that in circuit 1304 (e.g., circuit 1304 also matches that in 2,1 , CNOTT 3,1 , and CNOT 3,2 Therefore, the circuit 1304 can potentially be optimized by the template 1302. However, the CNOT of the circuit 1304 2,1 and CNOT 3,1, the template 1302 cannot be directly applied to the circuit 1304. In such a case, the S gate can be considered as a blocking gate (e.g., the S gate is between the matched gates in the circuit 1304 such that the matched gates in the circuit 1304 are not contiguous; equivalently, one can say that the S gate is within the template matching range). Conventional template matching does not provide a solution to this problem, and instead, different templates are tried. However, the floating component 116 can solve this problem. Specifically, the floating component 116 can transform the S gate (e.g., a non-limiting example of a blocking gate) into a linear combination of Pauli operators according to the above equation (e.g., according to the floating gate transformation rule 1102). The floating component 116 can then independently push the linear combination of Pauli operators out of the template matching range (e.g., so that the S gate is no longer CNOT) via the Pauli push equation. 2,1 , CNOTT 3,1 , and CNOT 3,2 , and so pushing can continue until the linear combination of Pauli operators becomes a single-qubit gate acting on the same qubit. At such point, floating component 116 can use floating gate transformation rules 1102 (e.g., table 1202, since the S gate is being floated in this example) to transform the linear combination of moved Pauli operators back into a single-qubit gate. Circuit 1306 is the result of floating the S gate of circuit 1304 in this manner. As shown in circuit 1306, the CNOT 2,1 , CNOTT 3,1 , and CNOT 3,2 is now continuous, which allows the application of template 1302. In this case, the floating of the S gate is 3,1 and CNOT 3,2If only one qubit passed through, this example would not be a 1-qubit gate, so the floating of the S gate would be a 4th gate (e.g., CNOT 1,3 ) (e.g., again, one skilled in the art would understand how to accomplish such floating via the Pauli push equation). In various embodiments, a matched gate (e.g., CNOT 2,1 , CNOTT 3,1 , and CNOT 3,2 ) are contiguous in the circuit 1306, the template 1302 can be applied to reduce the gate count. That is, the matched gates (e.g., CNOT 2,1 , CNOTT 3,1 , and CNOT 3,2 ) may be replaced with the inverse of the remaining gates in template 1302. The result may be an optimized circuit 1308, which may have a smaller gate count than circuit 1304, as shown.

[0076] 14 is a block diagram of an example, non-limiting system 1400 including a SWAP equivalence relation that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 1400 can include, in some cases, the same components as system 1100 and can further include a SWAP equivalence relation 1402.

[0077] In various embodiments, the SWAP component 118 can optimize the SWAP stage 506 (e.g., after the template component 114 and / or the floating component 116 facilitate template matching for the computation stage 502). In various aspects, the SWAP component 118 can electronically store, maintain, and / or have access to SWAP equivalence relations 1402, which can be used to facilitate SWAP optimization. Specifically, one of ordinary skill in the art can

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[0078] FIG. 15 is a diagram of how a SWAP gate can be optimized at the cost of one entangling gate in an example, non-limiting manner according to one or more embodiments described herein. As shown, FIG. 15 depicts an example circuit 1502 and an equivalent example circuit 1504. In various aspects, the circuit 1502 includes a CZ gate aligned with a SWAP gate (e.g., the CZ gate and the SWAP gate are adjacent and operate on the same qubit). In various aspects, application of an equivalence relation with respect to the SWAP gate (e.g., application of the SWAP equivalence relation 1402) can transform the circuit 1502 into the circuit 1504. As shown, the circuit 1504 does not have a SWAP gate, but does have a second CZ gate (e.g., a second two-qubit gate). As another example, FIG. 15 depicts an example circuit 1506 and an equivalent example circuit 1508. In various embodiments, the circuit 1506 includes a CNOT gate aligned with a SWAP gate (e.g., the CNOT gate and the SWAP gate are adjacent and operate on the same qubit). In various embodiments, application of an equivalence relation with respect to the SWAP gate (e.g., application of the SWAP equivalence relation 1402) can transform the circuit 1506 into a circuit 1508. As shown, the circuit 1508 does not have a SWAP gate, but does have a second CNOT gate (e.g., a second two-qubit gate). In this manner, the SWAP gate can be merged from the SWAP stage 506 back into the original computation stage 502 and replaced at the cost of an additional two-qubit gate via the SWAP equivalence relation 1402.

[0079] 16 is a block diagram of an example, non-limiting system 1600 including a symbolic Pauli gate that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 1600 can, in some cases, include the same components as system 1400 and can further include a symbolic Pauli gate 1602.

[0080] As described above, conventional peephole optimization techniques rely on a database of optimal few-qubit Clifford circuits that are used to optimize larger Clifford circuits. However, such conventional peephole optimization techniques are limited to few-qubit subcircuits that are completely decoupled from the remaining qubits. In various embodiments, the symbolic component 120 can solve this problem (e.g., can facilitate peephole optimization even for few-qubit subcircuits that are not completely decoupled from the remaining qubits). The symbolic component 120 does so by creating symbolic Pauli gates 1602 in the suboptimal Clifford circuit 104 (e.g., in the computation stage 502 after performing partitioned template matching).

[0081] Standard gate set: C={I,X,Y,Z,H,S,CNOT} Consider a Clifford circuit for n qubits, expressed using the formula: Note that if the circuit contains CZ gates, we can convert them to CNOT gates by introducing Hadamard gates, as mentioned above. n Let denote the set of all n-qubit circuits that can be represented using a set of gates C. The cost of each gate can be defined as: $(CNOT)=1 and $(X)=$(Y)=$(Z)=$(H)=$(S)=0 The cost of a circuit can be expressed as the combined cost of all gates that appear in the circuit. Symbolic peephole optimization is n Given an input, implement the same Clifford operator as U (modulo the global topology), and find an optimized circuit U'∈C such that $(U')≤$(U). nTherefore, note that symbolic peephole optimization focuses on reducing the number of two-qubit gates (e.g., only CNOT gates have nonzero cost as defined above). This conveniently complements partitioned template matching, which can reduce the number of single-qubit gates as discussed above.

[0082] We next consider the symbolic peephole optimization in more detail. We define a circuit U∈C such that a database of optimized Clifford circuits for |A| qubits is available. n and a small subset of qubits A ⊆ [n]. The goal is to be able to meaningfully define and optimize constraints on U with respect to A, focusing on situations where A is not completely decoupled from the rest of the circuit.

[0083] Let B=[n]\A be the complement of A. A CNOT gate can be said to be entangling and / or straddling if it connects A and B. Without loss of generality, assume that an entangling / straddling CNOT has its target qubit in A. If this is not the case, an entangling / straddling CNOT gate can be rewired and / or rewritten such that its control qubit and target qubit can swap places by adding an extra Hadamard gate. An exemplary, non-limiting illustration of this is shown in FIG. 17.

[0084] As shown in FIG. 17, example circuit 1702 is equivalent to example circuit 1704. Note that the CNOT gate in circuit 1702 has its control qubit in A and its target qubit in B. As shown, the control qubit and target qubit can be swapped if Hadamards are implemented in parallel both before and after the CNOT gate. This allows circuit 1704 to have a CNOT gate whose control qubit is in B and whose target qubit is in A. Thus, symbolic component 120 can rewrite / rewire any straddling gate such that the target qubit of the straddling gate is in A (e.g., the desired subcircuit) via Hadamard addition.

[0085] Once all straddling gates have been rewired so that their targets are in A, the symbolic component 120 can partition the entangling / straddling CNOT gates into groups, such that all CNOTs in a group have the same control bit. Let k be the number of groups. Each entangling / straddling CNOT can be

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[0086] In various aspects, the symbolic component 120, with the following considerations, can optimize the family U A = {U A (v)} v of Clifford circuits for |A| qubits. First, U A should be expressed using the gate set of Clifford + symbolic Pauli gates. The cost $(U A ) should be defined as the sum of the number of CNOTs in U A and the number of symbolic Pauli gates in U A . Second, the optimization should respect the temporal order of the symbolic Pauli gates present in U A . That is, if i < j, then v iAll symbolic Pauli gates controlled by v j should be applied prior to any symbolic Pauli gate controlled by . Third, the optimization is performed on the phase factor

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[0087] In various aspects, the symbolic component 120 can select the subset A to be optimized. In some cases, the performance of the symbolic peephole optimization can be sensitive to the order of the qubit subsets. From numerical experiments, the inventors of various embodiments of the present invention have found that the most successful strategy is random subset assignment. Specifically, the symbolic component 120 selects the subset A to be optimized.

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[0088] FIG. 18 is an illustration of a simple example of how symbolic peephole optimization can be facilitated. As shown, FIG. 18 depicts an example circuit 1802 operating on n=2 qubits. Let A be a subset containing only the first qubit, whereby B is the complement of A and contains only the second qubit. As shown, circuit 1802 can have two straddling CNOT gates connecting A and B. Also as shown, these two straddling CNOT gates can have their target qubit in A. As explained above, if this is not the case, symbolic component 120 can rewire / rewrite the straddling CNOT gates via application of a Hadamard gate such that the target is in A. In various embodiments, symbolic component 120 can replace each straddling CNOT gate with a symbolic Pauli gate, thereby providing circuit 1804. As shown, circuit 1804 no longer has any straddling CNOT gates. Instead, subcircuit A of circuit 1804 now contains a symbolic Pauli X gate (e.g., X v ). Moreover, the remainder B of the circuit 1804 includes non-unitary gates (e.g., U B (v) (e.g., as explained above, this can include various projectors based on the symbolic variable v). As shown, the subcircuit U A ={X v HX v H} vhas one control bit (e.g., k=1) and contains two symbolic Pauli gates. Therefore, $(U A )=2. Using identity 1806 (e.g., identity 1806 can be retrieved from any suitable library / database of precomputed optimal circuits), symbolic component 120 calculates $(U' A )=1 for the subcircuit U A ={X v HX v H} v Functionally U A Equivalent subcircuit U' A = {HSX v i v} v can be transformed into the phase factor i v can be implemented by symbolic component 120 via a single-qubit S gate acting on B. Symbolic component 120 then computes U' A (e.g., replacing every symbolic Pauli gate with a straddling CNOT), thereby giving the optimized circuit 1808.

[0089] 19 is a block diagram of an example, non-limiting system 1900 including a library of optimal sub-circuits that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein. As shown, system 1900 can, in some cases, include the same components as system 1600 and can further include a library of optimal circuits 1902.

[0090] As described above, the symbolic component 120 can prepare the sub-optimal Clifford circuit 104 for peephole optimization by rewiring straddling gates and / or implementing a symbolic Pauli gate 1602. Also, in various embodiments, the peephole component 122 can perform peephole optimization on a sub-circuit that includes a symbolic Pauli gate 1602 by utilizing a library of optimal circuits 1902 (e.g., the peephole component 122 can electronically store, maintain, and / or have any suitable form of access to the library of optimal circuits 1902).

[0091] In various embodiments, the peephole component 122 and / or the symbolic component 120 can implement dynamic programming to optimize a sub-circuit that includes the symbolic Pauli gate 1602. In various embodiments, such dynamic programming can ensure finding a maximum optimization for a given fixed set of qubits (e.g., for a sub-circuit). Such dynamic programming is now described in detail.

[0092] Let PL(n) denote the group of Pauli operators for n qubits, and CL(n) denote the group of Clifford operators for n qubits. Clifford gate C and symbolic Pauli gate P v Consider a quantum circuit containing the n-qubit Clifford + symbolic Pauli gate operator P1,...,P k ∈PL(n) and Clifford operator R∈CL(n), so

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[0093] Clifford operators C0,...,C that satisfy the above conditions k It may be desirable to minimize the function $(C) for all pairs of C. To perform this minimization efficiently, a change of variables is performed: B j =C k ...C j However, 1≦j≦k. In this case, for 1≦j≦k,

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[0094] Let LOC(n) ⊆ CL(n) be a product subgroup of the Clifford group generated by single-qubit Clifford gates. j Multiply if ∈LOC(n) B j ←B j L j It is easy to check that F is invariant under j *Depends only on LOC(n). Fix the canonical representation of each left coset, REP(n) ⊂ CL(n) Let be the set of standard representations. By definition, all Clifford groups are disjoint unions of

number

[0095] Next, we use a dynamic programming method and a cost function $(B) with B ∈ REP(n) to compute the function F using a precomputed lookup table for B1,...,B k ∈REP(n), i.e., the intermediate objective functions f1,...,f k Define REP(n) → Z + However, Z + teeth,

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[0096] Functions f1,...,f k The lookup tables for can be computed one by one. Building each lookup table requires REP(n) iterations. This can be done for n=2,3. Note that by relying on a dynamic programming algorithm to ensure that all possible optimizations actually occur, symbolic peephole optimization can be more resource intensive compared to traditional peephole optimization. That is, symbolic peephole optimization requires |REP(n)| iterations per subcircuit considered, compared to once for traditional peephole optimization. 2 The size of the lookup table can be |REP(n)| = 6720 for n = 3. However, the symbolic peephole optimization gives the advantage that the subcircuit being tested does not need to be completely isolated.

[0097] We now consider the following proof of Lemma 2. The above algorithm for computing the lexicographically minimal elements of a coset can work for a particular choice of ordering, as explained below. A symplectic matrix C of size 2n has 4n elements that form an integer int(C). 2 It can be parameterized by bits. Here is the bit ordering in int(C) for n=2,3,4:

number

[0098] 20-21 are flow diagrams of example, non-limiting computer-implemented methods 2000 and 2100 that can facilitate partitioned template matching and / or symbolic peephole optimization in accordance with one or more embodiments described herein.

[0099] Consider first the computer-implemented method 2000. In various embodiments, operation 2002 includes performing template matching, by a device (e.g., 114) operably coupled to the processor, against a Clifford circuit (e.g., 104) associated with the set of qubits.

[0100] In various embodiments, operation 2004 can include partitioning, by a device (e.g., 112), the Clifford circuit into computational stages (e.g., 502), Pauli stages (e.g., 504), and SWAP stages (e.g., 506) prior to template matching, which can be performed on the computational stages (e.g., an example of partitioning shown in FIG. 7).

[0101] In various cases, operation 2006 may include selecting, by a device (eg, 120), a subset of qubits (eg, A) from the set of qubits.

[0102] In various cases, operation 2008 may include having a device (e.g., 120) rewire at least one entangling gate (e.g., CNOT or CZ or both) in a computation stage such that the target of at least one entangling gate is among a subset of the qubits (e.g., via applying a Hadamard as shown in FIG. 17).

[0103] In various embodiments, operation 2010 can include replacing, by a device (e.g., 120), at least one of the reconnected entangling gates with a symbolic Pauli gate (e.g., 1602), which is a Pauli gate controlled by a symbolic variable (e.g., an example of such a replacement is shown in FIG. 18).

[0104] In various cases, operation 2012 may include performing peephole optimization on a subset of qubits by implementing a dynamic programming algorithm using symbolic Pauli gates (e.g., by leveraging a library of optimal circuits 1902) with a device (e.g., 122). For a fixed set of qubits that experience peephole optimization, the optimization itself may be guided by the dynamic programming algorithm described above.

[0105] Although not shown in FIG. 20, the computer-implemented method 2000 may optionally further include, by a device (e.g., 116), pushing a blocking gate (e.g., S in FIG. 13) out of the template matching range by replacing the blocking gate with a linear combination of Pauli operators in a computation stage.

[0106] Although not shown in FIG. 20, the computer-implemented method 2000 may optionally further include, by a device (e.g., 112), repartitioning the Clifford circuit if performing template matching in a computation stage results in a Pauli gate or a SWAP gate in the computation stage.

[0107] Consider now the computer-implemented method 2100. In various embodiments, operation 2102 can include performing, by a device (e.g., 122) operably coupled to the processor, a peephole optimization on a Clifford circuit (e.g., 104) associated with the set of qubits.

[0108] In various aspects, operation 2104 may include selecting, by a device (eg, 120), a subset of qubits from the set of qubits.

[0109] In various cases, operation 2106 may include having a device (e.g., 120) rewire at least one entangling gate (e.g., CNOT or CZ or both) in the Clifford circuit such that the target of the at least one entangling gate is among a subset of the qubits (e.g., via applying a Hadamard filter as shown in FIG. 17).

[0110] In various cases, operation 2108 can include having the device (e.g., 120) replace at least one rewired entangling gate with a symbolic Pauli gate (e.g., 1602, for example, shown in FIG. 18) prior to peephole optimization.

[0111] In various embodiments, operation 2110 can include partitioning, by a device (e.g., 112), the Clifford circuit into a computation stage (e.g., 502), a Pauli stage (e.g., 504), and a SWAP stage (e.g., 506).

[0112] In various cases, operation 2112 can include performing template matching by a device (eg, 114) on a computation stage prior to rewiring at least one entangling gate.

[0113] Although not shown in FIG. 21, the computer-implemented method 2100 may optionally further include, by a device (e.g., 116), pushing a blocking gate (e.g., S in FIG. 13) out of the template matching range by replacing the blocking gate with a linear combination of Pauli operators in a computation stage.

[0114] Although not shown in FIG. 21, the computer-implemented method 2100 may optionally further include, by a device (e.g., 112), repartitioning the Clifford circuit if performing template matching in a computation stage results in a Pauli gate or a SWAP gate in the computation stage.

[0115] The inventors of various embodiments of the present invention have conducted various experiments and / or numerical simulations, the results of which demonstrate that embodiments of the present invention are superior to conventional Clifford optimization techniques. The experiments / simulations involved generating 993 uniformly sampled random Clifford unitaries with CNOT costs between 5 and 15. For costs between 5 and 14, the inventors considered 99 circuits for each cost value. At cost=15, there are only three Clifford circuits (left and right single qubit Clifford modulo, and modular qubit permutations). For each Clifford unitary, the inventors synthesized it using the baseline compiler and nine randomized compilers described above, for a total of 10 different initial circuits. Optimizations (e.g., partitioned template matching and symbolic peephole optimization) were then performed on these 10 circuits to pick out the best results. The inventors found that the exact optimal cost was achieved for 90.2% of the circuits, and on average introduced only about 1% overhead into the CNOT cost.

[0116] The inventors also applied the described optimization techniques to encoding circuits for quantum error correcting codes (QECC) to see how embodiments of the present invention work in the real world with practically relevant circuits. Encoding circuits for QECC were obtained by starting with a code stabilizer generator and generating corresponding circuits using the Clifford circuit synthesis algorithm. These circuits were recompiled using the baseline compiler and then optimizations (e.g., partitioned template matching and symbolic peephole optimization) were performed. The inventors found that the introduction of floating gate technology resulted in an average improvement of about 2.6% in the number of 2-qubit gates due to the additional template application enabled by the floating gate technology. Moreover, an average improvement of 64.5% over the reference circuit and 35.4% over the circuit synthesized using the baseline compiler was achieved. The inventors further noted that the quality of the improvement produced by various embodiments of the present invention does not decrease with problem size (e.g., the improvement over the baseline compiler remains about 35% even when the number of qubits is greater than 12). The inventors have also found that the combined algorithms described herein take only a few seconds for small numbers of qubits (e.g., average runtime 2.42 seconds for n=5), and up to tens of minutes for large numbers of qubits.

[0117] Overall, various embodiments of the present invention can be thought of as two novel algorithms for optimization of Clifford circuits: (1) partitioned template matching, and (2) symbolic peephole optimization. Partitioned template matching can be thought of as a Clifford-specific extension of traditional template matching that leverages Clifford-specific properties to further reduce gate count. Specifically, partitioned template matching can include partitioning the Clifford circuit into three separate stages (e.g., computation, Pauli, and SWAP), performing template matching on one of these separate stages (e.g., computation), and eliminating the SWAP gate by aligning it with another two-qubit gate. Moreover, various embodiments of the present invention can include a floating gate technique that can be used to remove blocking gates from the desired template matching range. Symbolic peephole optimization can be thought of as an improved version of peephole optimization that does not require complete decoupling to function. Specifically, symbolic peephole optimization can involve identifying a desired subcircuit, rewiring any straddling gates so that their targets are within the subcircuit, and then replacing the rewired straddling gates with symbolic Pauli gates that are controlled by symbolic variables rather than other qubits.

[0118] Throughout this disclosure, various variables, symbols, and / or mathematical notations are used to aid in the description of embodiments of the present invention. In some cases, the same variable / symbol may have different meanings when used in different parts of this specification (e.g., in some places, i is used to represent an imaginary number, and in other places, i is used to represent a subscript; in some places, D is used to represent a particular algorithm and / or function, and in other places, D is used to represent a subset of qubits; in some places, C is used to represent various Clifford circuits and / or Clifford gate sets, and in other places, C is used to represent a subset of qubits, etc.). Those skilled in the art will appreciate that the same variable / symbol may have different meanings when used in different contexts / ways.

[0119] To provide further context for the various embodiments described herein, Figure 22 and the following discussion are intended to provide a brief, general description of a suitable computing environment 2200 in which various embodiments of the embodiments described herein may be implemented. Although the embodiments are described in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will appreciate that the embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0120] Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

[0121] The illustrated embodiments of the present disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0122] A computing device typically includes a variety of media, which may include computer-readable storage media, machine-readable storage media, or communication media, or a combination thereof, and these two terms are used differently from each other in this specification as follows. A computer-readable storage medium or machine-readable storage medium can be any available storage medium that can be accessed by a computer, and includes both volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, a computer-readable storage medium or machine-readable storage medium can be implemented in conjunction with any method or technology for storage of information, such as computer-readable or machine-readable instructions, program modules, structured or unstructured data, etc.

[0123] A computer-readable storage medium may include, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disk (BD) or other optical disk storage device, magnetic cassette, magnetic tape, magnetic disk storage device or other magnetic storage device, solid state drive or other solid state storage device, or other tangible and / or non-transitory medium that may be used to store the desired information. In this regard, it should be understood that the terms "tangible" or "non-transitory" as applied herein to storage, memory, or computer-readable medium are intended as qualifiers to exclude only propagating transitory signals per se, and are not intended to waive any right to all standard storage, memory, or computer-readable media other than propagating transitory signals per se.

[0124] The computer-readable storage medium can be accessed by one or more local or remote computing devices for a variety of operations concerning the information stored by the medium, e.g., via access requests, queries, or other data retrieval protocols.

[0125] Communication media typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, such as a modulated data signal, e.g., carrier wave or other transport mechanism, and includes any information transmission or transport media. The term "modulated data signal" or signal refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal or signals. By way of example, and not limitation, communication media include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

[0126] Referring again to FIG. 22, an exemplary environment 2200 for implementing various embodiments of the aspects described herein includes a computer 2202 including a processing unit 2204, a system memory 2206, and a system bus 2208. The system bus 2208 couples system components including, but not limited to, the system memory 2206 to the processing unit 2204. The processing unit 2204 can be any of a variety of commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 2204.

[0127] The system bus 2208 may be any of several types of bus structures that may be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 2206 includes a ROM 2210 and a RAM 2212. A basic input / output system (BIOS) may be stored in a non-volatile memory, such as a ROM, an erasable programmable read-only memory (EPROM), or an EEPROM, such a BIOS containing basic routines that help transfer information between elements within the computer 2202, such as during start-up. The RAM 2212 may also include a high-speed RAM, such as a static RAM for caching data.

[0128] The computer 2202 further includes an internal hard disk drive (HDD) 2214 (e.g., EIDE, SATA), one or more external storage devices 2216 (e.g., a magnetic floppy disk drive (FDD) 2216, a memory stick or flash drive reader, a memory card reader, etc.), and a drive 2220, such as a solid state drive, optical disk drive, etc., that can read from and write to a disk 2222, such as a CD-ROM disk, DVD, BD, etc. Alternatively, if a solid state drive is included, the disk 2222 is not included unless separate. Although the internal HDD 2214 is illustrated as being disposed within the computer 2202, the internal HDD 2214 may also be configured for external use within a suitable chassis (not shown). Additionally, although not shown in the environment 2200, a solid state drive (SSD) may be used in addition to or in place of the HDD 2214. The HDD 2214, external storage device 2216, and drive 2220 can be connected to the system bus 2208 by a HDD interface 2224, an external storage interface 2226, and a drive interface 2228, respectively. The interface 2224 for external drive implementations can include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0129] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. For the computer 2202, the drives and storage media accommodate the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to a particular type of storage device, those skilled in the art will appreciate that other types of computer-readable storage media, whether now existing or later developed, may also be used in the exemplary operating environment, and further, any such storage media may include computer-executable instructions for performing the methods described herein.

[0130] A number of program modules can be stored in the drives and RAM 2212, including an operating system 2230, one or more application programs 2232, other program modules 2234 and program data 2236. All or portions of the operating system, applications, modules and / or data can also be cached in RAM 2212. The systems and methods described herein can be implemented using a variety of commercially available operating systems or combinations of operating systems.

[0131] The computer 2202 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate a hardware environment for the operating system 2230, where the emulated hardware may optionally be different than the hardware illustrated in FIG. 22. In such an embodiment, the operating system 2230 may include one of a number of virtual machines (VMs) hosted on the computer 2202. Additionally, the operating system 2230 may provide a runtime environment, such as the Java® Runtime Environment or the .NET Framework, for the application 2232. The runtime environment is a consistent execution environment that allows the application 2232 to run on any operating system that includes the runtime environment. Similarly, the operating system 2230 may support containers, and the application 2232 may be in the form of a container, which is a lightweight, standalone, executable package of software that includes, for example, code, runtime, system tools, system libraries, and settings for the application.

[0132] Additionally, computer 2202 can be enabled with a security module, such as a Trusted Processing Module (TPM). For example, with a TPM, a boot component can temporally hash the next boot component and wait for the result to match a secure value before loading the next boot component. This process can occur at any layer in the code execution stack of computer 2202, for example, at the application execution level or at the operating system (OS) kernel level, thereby enabling security at any level of code execution.

[0133] A user may enter commands and information into the computer 2202 through one or more wired / wireless input devices, such as a keyboard 2238, a touch screen 2240, and a pointing device, such as a mouse 2242. Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, a joystick, a virtual reality controller and / or headset, a game pad, a stylus pen, an image input device, such as a camera, a gesture sensor input device, a visual motion sensor input device, an emotion or face detection device, a biometric input device, such as a fingerprint or iris scanner. These and other input devices are often connected to the processing unit 2204 through an input device interface 2244, which may be coupled to the system bus 2208, but may not be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a gaming port, a USB port, an IR interface, a BLUETOOTH® interface, etc.

[0134] A monitor 2246 or other type of display device can also be connected to the system bus 2208 via an interface, such as a video adapter 2248. In addition to the monitor 2246, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0135] The computer 2202 can operate in a networked environment using logical connections via wired and / or wireless communications to one or more remote computers, such as a remote computer 2250. The remote computer 2250 may be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment device, a peer device or other shared network node, and typically includes many or all of the elements described relative to the computer 2202, but for simplicity, only a memory / storage device 2252 is illustrated. The logical connections depicted include wired / wireless connections to a local area network (LAN) 2254 or a wide area network (WAN) 2256 or both. Such LAN and WAN networking environments are commonplace in offices and companies, facilitating enterprise-wide computer networks, such as intranets, all of which may connect to a global communications network, such as the Internet.

[0136] When used in a LAN networking environment, the computer 2202 can be connected to the local network 2254 through a wired and / or wireless communication network interface or adapter 2258. The adapter 2258 facilitates wired or wireless communication to the LAN 2254, which may also include a wireless access point (AP) disposed therein for communicating with the adapter 2258 in a wireless mode.

[0137] When used in a WAN networking environment, the computer 2202 may include a modem 2260 or may be connected to a communications server on the WAN 2256 via other means for establishing communications over the WAN 2256, such as using the Internet. The modem 2260, which may be an internal or external device and may be a wired or wireless device, may be connected to the system bus 2208 via the input device interface 2244. In a networked environment, program modules depicted relative to the computer 2202, or portions thereof, may be stored in the remote memory / storage device 2252. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

[0138] When used in either a LAN or WAN networking environment, the computer 2202 can access a cloud storage system or other network-based storage system, such as, but not limited to, a network virtual machine that implements one or more aspects of information storage or processing, in addition to or instead of the external storage device 2216 described above. In general, a connection between the computer 2202 and the cloud storage system can be established over the LAN 2254 or WAN 2256, for example, by an adapter 2258 or a modem 2260, respectively. When the computer 2202 is connected to an associated cloud storage system, the external storage interface 2226, aided by the adapter 2258 and / or the modem 2260, can manage the storage provided by the cloud storage system as if it were any other type of external storage. For example, the external storage interface 2226 can be configured to provide access to cloud storage sources as if those sources were physically connected to the computer 2202.

[0139] The computer 2202 is operable to communicate with any wireless device or entity operatively disposed within a wireless network, such as, for example, a printer, a scanner, a desktop or portable computer or both, a portable data assistant, a communications satellite, fixtures or locations associated with a wireless detectable tag (e.g., a kiosk, a newsstand, a store shelf, etc.), and a telephone. This includes Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. Thus, the communication can be of a predefined structure, as with a conventional network, or can simply be an ad-hoc communication between at least two devices.

[0140] Referring now to FIG. 23, an exemplary cloud computing environment 2300 is depicted. As shown, the cloud computing environment 2300 includes one or more cloud computing nodes 2302 that can communicate with local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or cell phone 2304, a desktop computer 2306, a laptop computer 2308, and / or an automobile computer system 2310. The nodes 2302 can communicate with each other. They can be physically or virtually grouped in one or more networks, such as a private, community, public, or hybrid cloud, or combination thereof, as described herein above (not shown). This allows the cloud computing environment 2300 to provide infrastructure, platform, and / or software as a service without the cloud consumer having to maintain resources on a local computing device. It will be understood that the types of computing devices 2304-2310 shown in FIG. 23 are intended to be merely exemplary, and that the computing node 2302 and cloud computing environment 2300 can communicate with any type of computerized device over any type of network or over a network-addressable connection (e.g., using a web browser), or both.

[0141] Referring now to FIG. 24, a set of functional abstraction layers provided by the cloud computing environment 2300 (FIG. 23) is shown. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. It should be understood in advance that the components, layers, and functions shown in FIG. 24 are intended to be merely illustrative, and embodiments of the present invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0142] The hardware and software layer 2402 includes hardware and software components. Examples of hardware components include: mainframe 2404, reduced instruction set computer (RISC) architecture based servers 2406, servers 2408, blade servers 2410, storage devices 2412, and networks and networking components 2414. In some embodiments, software components include network application server software 2416, and database software 2418.

[0143] The virtualization layer 2420 provides an abstraction layer over which the following examples of virtual entities may be provided: virtual servers 2422 , virtual storage 2424 , virtual networks including virtual private networks 2426 , virtual applications and operating systems 2428 , and virtual clients 2430 .

[0144] In one example, the management layer 2432 can provide the functions described below. Resource provisioning 2434 provides dynamic procurement of computing resources and other resources utilized to perform tasks within the cloud computing environment. Metering and billing 2436 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, and protection for data and other resources. User portal 2438 provides consumers and system administrators with access to the cloud computing environment. Service level management 2440 provides allocation and management of cloud computing resources such that required service levels are met. Service level agreement (SLA) planning and fulfillment 2442 provides advance agreement for cloud computing resources in anticipation of future demands and procurement of cloud computing resources according to SLAs.

[0145] Workload layer 2444 provides examples of functionality for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this layer include: mapping and navigation 2446, software development and lifecycle management 2448, virtual classroom instruction delivery 2450, data analytics processing 2452, transaction processing 2454, and differential privacy federated learning processing 2456. Various embodiments of the present invention may utilize the cloud computing environment described with reference to Figures 23 and 24 to perform one or more differential privacy federated learning processes in accordance with various embodiments described herein.

[0146] The present invention may be a system, method, apparatus, or computer program product, or combinations thereof, at any possible level of technical detail of integration. The computer program product may include a computer readable storage medium having computer readable program instructions for causing a processor to perform aspects of the present invention. The computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may further include: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or grooved structures having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being ephemeral signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a wave guide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through electrical wires.

[0147] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to an individual computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface of each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the individual computing / processing device. The computer readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state configuration data, configuration data for an integrated circuit, or object oriented programming languages ​​such as Smalltalk®, C++, and procedural or similar programming languages ​​such as the "C" programming language. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server.In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the present invention.

[0148] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to make a machine, such that the instructions, which execute via a processor of the computer or other programmable data processing apparatus, create means for implementing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored in a computer-readable storage medium having instructions stored thereon to instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium having the instructions stored thereon comprises an article of manufacture including instructions for implementing aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to create a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, causing the computer, other programmable apparatus, or other device to perform a series of operable functions.

[0149] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block of the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special-purpose hardware-based system that performs the specified functions or actions or executes a combination of special-purpose hardware and computer instructions.

[0150] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one or more computers, those skilled in the art will appreciate that the present disclosure can also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the computer-implemented methods of the present invention can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable home or commercial electronic devices, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be practiced with stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0151] As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to or include computer-related entities or entities related to a machine operable with one or more specialized functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution, and a component can be localized on one computer or distributed between two or more computers, or both. In another example, individual components can execute from various computer-readable media having various data structures stored thereon. Components may communicate through local and / or remote processes, such as by following a signal having one or more data packets (e.g., data from one component interacts with another component within a local system, within a distributed system, or across networks, or a combination thereof, such as the Internet, which interacts with other systems via signals). As another example, a component may be a device having special functionality imparted by mechanical parts operated by electrical or electronic circuits, and operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component can be a device that provides special functionality through electronic components without mechanical parts, where the electronic components can include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic components. In one aspect, a component can emulate an electronic component via a virtual machine, for example, within a cloud computing system.

[0152] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from the context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, then "X utilizes A or B" is satisfied under any of the foregoing cases. Moreover, as used within the specification of the subject matter and the accompanying drawings, the articles "a" and "an" should be construed generally to mean "one or more" unless otherwise stated or clear from the context to cover the singular form. As used herein, the terms "example, illustrative, exemplary" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0153] As employed in the subject specification, the term "processor" may refer to substantially any computing processing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreaded execution capability, a multi-core processor, a multi-core processor with software multithreaded execution capability, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space usage or improve the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory component" entity embodied in a "memory" or a component that includes a memory. It should be appreciated that the memory and / or memory components described herein can be either volatile memory or non-volatile memory, or can include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM, which may act as external cache memory. By way of example, and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of the systems or computer-implemented methods herein are intended to include, but are not intended to be limited to, these and any other suitable types of memory.

[0154] What has been described above includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Moreover, to the extent that the terms "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to how the term "comprising" is interpreted when employed as a transitional phrase in a claim.

[0155] Although the description of various embodiments has been presented for illustrative purposes, it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used in this specification is chosen to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to allow others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A system comprising: A processor executing computer-executable components stored in a computer-readable memory, the computer-executable components comprising: a template component that performs template matching on a Clifford circuit associated with a set of qubits; a partition component that partitions the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to the template matching, the partition component performing the template matching on the computation stages; The processor comprising: A system comprising:

2. A floating component that pushes blocking gates out of the template matching range in the computation stage by replacing the blocking gates with a linear combination of Pauli operators. The system of claim 1 further comprising:

3. 3. The system of claim 1, wherein the partition component repartitions the Clifford circuit if performing template matching in the computation stage results in a Pauli gate or a SWAP gate in the computation stage.

4. a symbolic component for selecting a subset of qubits from the set of qubits, reconnecting at least one entangling gate in the computation stage such that a target of the at least one entangling gate is within the subset of qubits, and replacing the at least one reconnected entangling gate with a symbolic Pauli gate, the symbolic Pauli gate being a Pauli gate controlled by a symbolic variable. The system of claim 1 , further comprising:

5. a peephole component that performs a peephole optimization on the subset of qubits using the symbolic Pauli gates by implementing a dynamic programming algorithm. The system of claim 4 further comprising:

6. 1. A computer-implemented method comprising: performing, by a device operatively coupled to the processor, template matching against a Clifford circuit associated with the set of qubits; partitioning, by the device, the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to the template matching, the template matching being performed on the computation stages; 4. A computer-implemented method comprising:

7. 1. A computer program for facilitating partitioned template matching and symbolic peephole optimization, comprising: To the processor performing template matching on a Clifford circuit associated with the set of qubits; partitioning the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to the template matching, the template matching being performed on the computation stage; A computer program for executing the above.

8. 1. A system comprising: A processor executing computer-executable components stored in a computer-readable memory, the computer-executable components comprising: a Peephole component that performs a Peephole optimization on a Clifford circuit associated with the set of qubits; a symbolic component that, prior to said peephole optimization, selects a subset of qubits from said set of qubits, rewires at least one entangling gate in said Clifford circuit such that a target of said at least one entangling gate is within said subset of qubits, and replaces said at least one rewired entangling gate with a symbolic Pauli gate; The processor comprising: A system comprising:

9. 9. The system of claim 8, wherein the symbolic Pauli gate is a Pauli X-gate controlled by a symbolic variable, the value of the symbolic variable being 0 or 1.

10. a partition component that partitions the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage; a template component that performs template matching on the computation stage prior to reconnecting the at least one entangling gate; The system of claim 8 or 9, further comprising:

11. A floating component that pushes blocking gates out of the template matching range in the computation stage by replacing the blocking gates with a linear combination of Pauli operators. The system of claim 10 further comprising:

12. 12. The system of claim 10 or 11, wherein the partition component repartitions the Clifford circuit if performing template matching in the computation stage results in a Pauli gate or a SWAP gate in the computation stage.

13. 1. A computer-implemented method comprising: performing, by a device operatively coupled to the processor, a peephole optimization on a Clifford circuit associated with the set of qubits; selecting, by the device, a subset of qubits from the set of qubits; reconnecting, with the device, at least one entangling gate in the Clifford circuit such that a target of the at least one entangling gate is within the subset of qubits; replacing the at least one rewired entangling gate with a symbolic Pauli gate prior to the peephole optimization by the device; 4. A computer-implemented method comprising:

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