MEMORY SYSTEM AND CONTROL METHOD - Patent application

Abstract

To provide a memory system and a control method capable of protecting a signal line even when an input / output port is in an open state, in the memory system that is connectable to a host device.SOLUTION: A memory system of an embodiment includes a non-volatile memory that stores data. The memory system includes: a connector part connectable to a host; and a memory controller that executes instructions for the memory received from the host via the connector part. The memory controller includes: a signal line that transmits a signal sent from the host via the connector part; a resistor electrically connected between the signal line and wiring serving as a reference potential of the memory system; a switch connected in series with the resistor and capable of opening and closing the connection between the signal line and the wiring serving as the reference potential; and a switch control circuit that opens the switch when there is a change in a potential state of the signal line and closes the switch when there is no change in the potential state of the signal line.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a memory system and a control method. [Background technology]

[0002] A memory system connectable to a host device communicates with the host device via signal lines conforming to a certain interface standard. In addition to signal lines for high-speed communication, such signal lines may include optional signal lines for low-speed communication. The optional signal lines may include, for example, signal lines for transferring clock signals and data signals. The host device may not include a circuit for processing the optional signal lines. In such a memory system connected to a host device, the circuit for processing the optional signal lines is in an unconnected state, and the input / output ports of the circuit are in an open state.

[0003] Even if an input / output port is in an open state, it is not desirable for the potential of the signal line to be indefinite. For this reason, the interface standard specifies that the memory system connects the optional signal line to a reference potential such as a power line or a ground line via a resistor or the like. The interface standard also specifies that the input / output port of the circuit that processes the optional signal line provided in the host device is pulled up (connected to a positive power line via a resistor or the like) or pulled down (connected to a ground line or a negative power line via a resistor or the like). In other words, when a host device equipped with a circuit including a pulled up or pulled down input / output port is connected, the potential state of the circuit connected to that circuit is protected in the memory system. Some kind of protection means is also required in memory systems that are connected to host devices that do not have such circuits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,551,897 [Patent Document 2] U.S. Patent No. 10,719,435 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a memory system and a control method capable of protecting signal lines even when an input / output port is in an open state in a memory system connectable to a host device. [Means for solving the problem]

[0006] A memory system according to an embodiment is a memory system that includes a non-volatile memory and a memory controller connected to the memory and is connectable to a host. The memory controller is capable of executing instructions for the memory received from the host, and includes a signal line for transmitting a signal sent from the host, a resistive element electrically connected between the signal line and a wiring to which a reference potential of the memory system is applied, a switching element connected in series with the resistive element and capable of controlling a connection between the signal line and the wiring, and a control circuit that controls the switching element to change the connection between the signal line and the wiring from a connected state to a disconnected state based on a change in the potential on the signal line from a first potential corresponding to a logical H level to a second potential corresponding to a logical L level or from the second potential to the first potential. After the connection between the signal line and the wiring is changed to a disconnected state, inside the memory controller, there is no connection of the resistive element between the signal line and the wiring, and the potential of the signal line is a potential corresponding to the host reference potential applied through the host resistive element to the host wiring electrically connected to the signal line inside the host. the signal lines include a clock signal line that transmits a clock signal and a data signal line that transmits a data signal, and the control circuit controls the switching element to change the connection between the clock signal line and the wiring or the connection between the data signal line and the wiring from a connected state to a disconnected state when there is a change from a first potential to a second potential on the clock signal line or the data signal line. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing a configuration of a memory system according to an embodiment connected to a host device. [Diagram 2]2 is a block diagram showing a part of a configuration of a host interface in the memory system according to the first embodiment. [Diagram 3] 1 is a block diagram showing a configuration in a state in which a host interface in a memory system according to a first embodiment is connected to a host device. [Figure 4] 2 is a block diagram showing a configuration in a state in which a host interface in a memory system according to a first embodiment is connected to another host device. FIG. [Diagram 5] 5 is a flowchart showing the operation of a host interface in the memory system according to the first embodiment. [Figure 6] FIG. 11 is a block diagram showing a part of the configuration of a host interface in a memory system according to a second embodiment. [Figure 7] FIG. 11 is a block diagram showing a configuration in a state in which a host interface in a memory system according to a second embodiment is connected to a host device. [Figure 8] 1 is a diagram showing an example of a data format of a serial bus in a memory system according to an embodiment; [Figure 9] 10 is a flowchart showing the operation of a host interface in a memory system according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (Configuration of the first embodiment) 1 is a diagram showing an example of a configuration of a memory system 1 according to an embodiment. As shown in FIG. 1, the memory system 1 can be connected to a host device 30 via a bus 100 that complies with a certain interface standard. The host device 30 is, for example, a server, a personal computer, or a mobile information processing device. The memory system 1 functions as an external storage device for the host device 30. The host device 30 can issue requests to the memory system 1. The requests include read requests and write requests.

[0009] The memory system 1 includes a NAND flash memory 10, a controller (an example of a memory controller) 20, and a RAM (Random Access Memory) 220. The NAND flash memory 10 includes one or more memory chips 11. The memory chip 11 includes a plurality of memory cell transistors and can store data in a non-volatile manner. The memory chip 11 is connected to the controller 20 by a NAND bus 40.

[0010] The controller 20 includes a host interface (HOST I / F) 210, a CPU (Central Processing Unit) 230, a buffer memory (Buffer) 240, a NAND interface (NAND I / F) 250, and a RAM interface (RAM I / F) 260. Each of these components is connected to each other via an internal bus so as to be able to communicate with each other.

[0011] The controller 20 performs program processing, read processing, erase processing, etc. on the NAND flash memory 10. The controller 20 is a semiconductor circuit configured as, for example, a System-On-a-Chip (SoC). The controller 20 may be configured as a Field-Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). The controller 20 may be configured by multiple chips. Each function of the controller 20 may be realized by a CPU 230 that executes software (firmware), dedicated hardware, or a combination of these.

[0012] The host interface 210 is connected to the host device 30 via a bus 100 that complies with an interface standard such as the SATA (Serial Advanced Technology Attachment) standard, the SAS (Serial Attached SCSI) (registered trademark) standard, the PCI (Peripheral Components Interconnect) Express (registered trademark) (PCIe) standard, or the SMBus (System Management Bus) (registered trademark) standard, and performs communication between the controller 20 and the host device 30.

[0013] The memory system 1 has an input / output port 35 used for connection to the host device 30. The input / output port 35 has a function of relaying between the host device 30 and the host interface 210, and is, for example, a connector. The input / output port 35 may be compliant with two or more interface standards, namely, high-speed communication (PCIe, SATA, etc.) and low-speed communication (SMBus, etc.). The input / output port 35 supports one or more of the interface standards supported by the bus 100.

[0014] The NAND interface 250 is connected to the memory chip 11 of the NAND flash memory 10 via the NAND bus 40, and executes communication between the controller 20 and the memory chip 11. The RAM interface 260 is connected to the RAM 220, and executes communication between the controller 20 and the RAM 220.

[0015] The CPU 230 controls the operation of the controller 20 .

[0016] The RAM 220 provides a working area to the CPU 230 via a RAM interface 260. The buffer memory 240 temporarily holds data to be transmitted to the memory chip 11 of the NAND flash memory 10 and data received from the memory chip 11. The RAM 220 and the buffer memory 240 may be realized by, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination of these. Note that the types of memory constituting the RAM 220 and the buffer memory 240 are not limited to these. The buffer memory 240 may be implemented outside the controller 20.

[0017] (Interface standard that the host interface complies with) Various specifications have been established from the viewpoints of hardware and software for the interface standard connecting the host device 30 and the memory system 1. In the interface standard connecting a main device such as the host device 30 and a secondary device such as the memory system 1, in addition to high-speed communication such as PCIe, a data signal line for transmitting data for low-speed communication and a clock signal line for transmitting a clock signal are specified.

[0018] In order to stabilize the operation of the device and protect the device from excessive input from the outside, the data signal lines and the clock signal lines in the host device 30 and the memory system 1 need to be pulled up or down when the terminals (input / output ports) connected to those signal lines are not connected (open). Pulling up refers to connecting the target data signal line or clock signal line to a positive reference potential line via a resistor or the like with a certain resistance value. Pulling down refers to connecting the target data signal line or clock signal line to a negative reference potential line via a resistor or the like with a certain resistance value. In the following description, connecting to a positive power supply line via a resistor is called pull up, and connecting to a ground line via a resistor is called pull down. The ground line may be common to the negative power supply line or may be different.

[0019] Interface standards for connecting a primary device and a secondary device usually stipulate that the data signal line and the clock signal line must be pulled up or down on the primary device side, but this alone does not protect the data signal line and the clock signal line of the secondary device.

[0020] In recent years, it has become common for one I / O port to comply with multiple interface standards. In this case, since not all host devices are compatible with all of the interface standards supported by the I / O port, it is possible that some of the data signal lines and clock signal lines of the slave device will not be protected.

[0021] In the memory system 1 of the embodiment, the host interface 210 has a characteristic configuration to protect the memory system 1. Hereinafter, with reference to FIG. 2, a part of the configuration of the host interface 210 in the memory system 1 of the first embodiment will be described in detail.

[0022] The host interface 210 of the embodiment complies with the PCIe standard as an example of an interface standard for high-speed communication, and the SMBus standard as an example of an interface standard for low-speed communication. 2 SMBus is a serial bus standard derived from the PCI Express (registered trademark) standard. The SMBus standard uses an SCL line for transmitting a clock signal and an SDA line for transmitting a data signal as transmission lines. The host interface 210 of this embodiment has a host interface 210a that complies with the SMBus standard for low-speed communication and a host interface 210b that complies with the PCIe standard for high-speed communication.

[0023] As shown in Fig. 2, in the memory system 1, the input / output port 35 and the host interface 210a are connected via an SCL line and an SDA line that comply with the SMBus standard. The input / output port 35 and the host interface 210b are connected via a plurality of signal lines that comply with the PCIe standard. In the example shown in Fig. 2, the input / output port 35 is compatible with the PCIe standard for high-speed communication and the SMBus standard for low-speed communication, but is not limited thereto. For example, the input / output port 35 may also be compatible with the USB standard or the like.

[0024] The host interface 210a has an input buffer 211 that receives a clock signal from the SCL line, and an input buffer 213 that receives a data signal from the SDA line. The input buffer 211 sends the received clock signal to other functional elements of the controller 20. The input buffer 213 sends the received data signal to other functional elements of the controller 20.

[0025] The host interface 210a also has an output buffer 212 that transmits a clock signal received from another functional element of the controller 20 to the host device 30 via the SCL line. Similarly, the host interface 210a has an output buffer 214 that transmits a data signal received from another functional element of the controller 20 to the host device 30 via the SDA line.

[0026] The host interface 210a further includes a resistor R C , resistor R D , switch C , and switch SW D The resistor R C One end is connected to the ground line and the other end is connected to the switch SW C and the other end connected to the switch SW C is the SCL line connected to the input / output port 35 and resistor R C Resistor R D One end is connected to the ground line and the other end is connected to the switch SW D and the other end connected to the switch SW Dis the SDA line connected to the input / output port 35 and the resistor R D The ground line is a reference potential line and may be a negative power supply line. C and switch SW D is composed of, for example, an electronic switch or a transistor, and its opening and closing is controlled by a switch control circuit 215.

[0027] The SCL line connected to the input / output port 35 is connected to the input of the input buffer 211, the output of the output buffer 212, and the switch SW C The switch SW C The other end of the resistor R C The output of the input buffer 211 and the input of the output buffer 212 are connected to other functional elements of the controller 20.

[0028] The SDA line connected to the input / output port 35 is connected to the input of the input buffer 213, the output of the output buffer 214, and the switch SW D The switch SW D The other end of the resistor R D The output of the input buffer 213 and the input of the output buffer 214 are connected to other functional elements of the controller 20.

[0029] The switch control circuit 215 controls the switch SW C and switch SW D The opening and closing condition is based on whether the host device 30 is connected to the memory system 1. More specifically, the switch control circuit 215 controls the opening and closing of the switch SW C and switch SW D is closed, if the SCL line or the SDA line is at the same potential as the power supply line of the host device 30 (or the memory system 1), the switch SW C and switch SW D otherwise, switch SW C and switch SW DThe potentials of the SCL and SDA lines can be detected by the switch control circuit 215 monitoring the outputs of the input buffers 211 and 213.

[0030] That is, first, the switch control circuit 215 controls the switch SW C and switch SW D Close the resistor R C and resistor R D In this state, the switch control circuit 215 detects that the host device 30 is not connected to the input / output port 35 of the memory system 1 and the SCL and SDA lines are in a floating state. In this case, the switch control circuit 215 detects that the host device 30 is not connected to the input / output port 35 of the memory system 1 and the SCL and SDA lines are in a floating state. C and switch SW D Keep the SCL and SDA lines connected to resistor R C and resistor R D The signal line is kept pulled down to the ground line via the host interface 210a. Here, the signal line being in a "floating state" means that the outside of the input / output port 35 (i.e., the host device 30 side) is not electrically connected to a reference potential line having a reference potential such as a positive power supply line, a negative power supply line, or a ground line, and the potential of the signal line is in an undefined state (undefined state) unless the signal line is pulled down within the host interface 210a.

[0031] On the other hand, when the host device 30 is connected to the input / output port 35 of the memory system 1 and the SCL line or the SDA line has a potential equivalent to that of the positive power supply line, the switch control circuit 215 turns on the switch SW C and switch SW D This releases the pull-down state of the SCL and SDA lines within the host interface 210a.

[0032] The SCL and SDA lines conforming to the SMBus standard can be wired-ORed with multiple devices via the bus 100. Therefore, the pull-down in the host interface 210a is performed via a relatively large value resistor.

[0033] 3 shows a state in which a host device 30 is connected to the memory system 1 via an input / output port 35 in this embodiment. As shown in FIG. 3, the host device 30 has an interface section IF in which the SCL line and the SDA line are connected to resistors R HC and resistor R HD Through the power line V DD This is because if the SCL line serving as the clock signal line and the SDA line serving as the data signal line are left floating without being connected to the power supply line or ground line, not only will normal signal transmission be impossible, but there is also a risk of damaging the elements of the host device 30.

[0034] Usually, in the interface standard to which the host device 30 conforms, the data signal line and the clock signal line are pulled up to the power supply line, and the resistance value of the resistor for the pull-up is also predetermined. HC and resistor R HD The resistance value is the specified value.

[0035] The switch control circuit 215 of the controller 20 supplies the power supply voltage V DD When a voltage equal to that of the switch SW C and switch SW D This opens the SCL and SDA lines through resistor R C and resistor R D The SCL and SDA lines are disconnected from the power supply line V of the host device 30. DD It is pulled up only to

[0036] As shown in FIG. 3, the SCL and SDA lines of the host device 30 are connected to the power supply line V DD When the host device 30 is connected to the memory system 1, the SCL and SDA lines are pulled up to the power supply line V DDIn the memory system of the embodiment, the power supply potential (e.g., 1.8V) appearing on the SCL line or the SDA line is detected to detect that the host device 30 is connected to the memory system 1. This makes it possible to detect whether the host device 30 is connected or not without providing any special additional function to the interface standard.

[0037] (The meaning of the switch) Here, the switch SW in the host interface 210a C and switch SW D Let us consider the significance of the switch SW C and switch SW D When the host device 30 is not connected, the resistor R C and resistor R D This pulls down the SCL and SDA lines to protect them.

[0038] On the other hand, when the host device 30 is connected to the I / O port 35 as shown in FIG. 3, the potentials of the SCL and SDA lines are HC and resistor R C The potential divided and dropped by resistor R HD and resistor R D In this case, the potential levels of the SCL and SDA lines are stable, but the potentials of the resistors R HD and resistor R HC and a resistor R C and resistor R D Generally, the resistance of the resistor R in the host interface 210a is not very accurate, so it is difficult to obtain a desired potential level. C and resistor R DThe disadvantage is that the data waveform is deformed (distortion occurs due to a delay in the rising edge of the waveform or a steep rising edge). For this reason, the SCL line and the SDA line are connected to a resistor R HD and resistor R HC Other than that, switch SW C and switch SW D Therefore, resistor R C and resistor R D It is desirable to separate the

[0039] When the host device 30 is connected to the memory system 1 via the input / output port 35, the potential levels of the SCL and SDA lines are, strictly speaking, HC and resistor R C The potential divided by the resistor R HD and resistor R D Here, the potential is divided by the pull-down resistor R C and resistor R D The resistance value of the pull-up resistor R HC and resistor R HD This allows the host interface 210a to detect the potential levels of the SCL and SDA lines at the power supply voltage V DD It is easy to determine whether the value is equivalent to the value of the

[0040] Here, an example in which the SCL and SDA lines are in a floating state will be described with reference to Fig. 4. Consider a case in which the memory system 1 is connected to a host device 31 as shown in Fig. 4. The host device 31 does not comply with the SMBus standard for low-speed communication, and the bus 100a does not include a signal line of the SMBus standard. In other words, the host device 31 complies with the USB standard and the PCI Express standard, but does not comply with the SMBus standard. In this case, even though the host device 31 is connected to the memory system 1 via the input / output port 35, the SCL and SDA lines of the host interface 210a will be in a floating state.

[0041] The memory system 1 of the embodiment includes a switch SW C and S.W. D and a switch control circuit 215. Therefore, even if the input / output port 35 on the host device 31 side is not connected to a terminal conforming to the SMBus standard, it is possible to prevent the signal line from going into a floating state.

[0042] (Operation of the first embodiment) Next, the operation of the memory system 1 of this embodiment will be described with reference to Fig. 5. In an initial state in which the host device 30 is not connected to the input / output port 35, the switch control circuit 215 turns on the switch SW C and switch SW D This is the state shown in FIG. 2, where the SCL and SDA lines of the host interface 210a are maintained in a closed state by resistors R C and resistor R D (S510). As a result, the inputs of the input buffers 211 and 213 and the outputs of the output buffers 212 and 214 are both fixed to the potential of the ground line, stabilizing the operation of the host interface 210a and protecting the circuitry.

[0043] Switch control circuit 215 monitors the potential of the input signals on the SCL and SDA lines (S520) via input buffers 211 and 213. If there is no change in the levels of the SCL and SDA lines (if the potential of the ground line is detected), monitoring continues (No in S530).

[0044] Power supply line V DD When a potential equivalent to the potential of the switch SW C and switch SW D As a result, the SCL and SDA lines are connected to the resistor R C and resistor R D The SCL or SDA line is released from the pull-down state by the power supply line V DD The detection of the potential of resistor R HC or resistor R HD The SCL or SDA line becomes the power supply line V DD This means that the signal has been pulled up to the input / output port 35, so it is understood that the host device 30 is connected to the input / output port 35 (S550).

[0045] Through this series of operations, the data signal line (SDA line) and the clock signal line (SCL line) of the interface line connecting the host device 30 and the memory system 1 are always at the same voltage as the power supply line V DD The input terminals are pulled up to the positive terminal or pulled down to the ground line, ensuring stable operation of the circuit and protecting the circuit.

[0046] According to the memory system 1 of the embodiment, when the host device 30 is connected, the pull-down of the data signal line and the clock signal line in the memory system 1 is released. That is, the resistor R HC and resistor R HD This causes the power line V DDOn the other hand, when the host device 30 is disconnected from the memory system 1, the data signal line and the clock signal line are pulled down in the memory system 1. This operation stabilizes the input / output elements of the host interface 210a and can protect them from destruction.

[0047] (Configuration of the second embodiment) Next, a memory system according to a second embodiment will be described with reference to Figures 6 and 7. The memory system 1 according to the first embodiment shown in Figures 2 and 3 includes switches and resistors that pull down the SCL and SDA lines, whereas the memory system 2 according to the second embodiment shown in Figures 6 and 7 includes switches and resistors that pull up the SCL and SDA lines. In the following description, functional elements common to the first embodiment are denoted by common reference numerals, and duplicated description will be omitted.

[0048] 6 and 7, the memory system 2 according to the second embodiment includes a controller 20a, which includes a host interface 210c. The host interface 210c includes a host interface 210d that complies with the SMBus standard for low-speed communication and a host interface 210b that complies with the PCIe standard for high-speed communication.

[0049] The host interface 210d has an input buffer 211 that receives a clock signal from the SCL line, and an input buffer 213 that receives a data signal from the SDA line. The input buffer 211 sends the received clock signal to other functional elements of the controller 20a. The input buffer 213 sends the received data signal to other functional elements of the controller 20a. The host interface 210d also has an output buffer 212 that sends the clock signal received from other functional elements of the controller 20a to the host device 30 via the SCL line. Similarly, the host interface 210d has an output buffer 214 that sends the data signal received from other functional elements of the controller 20a to the host device 30 via the SDA line.

[0050] The host interface 210d further includes a resistor R Ca , resistor R Da , switch Ca , and switch SW Da It has a switch SW Ca is the power line V DD One end connected to resistor R Ca and the other end connected to resistor R Ca indicates the SCL line connected to the input / output port 35 and the switch SW Ca The switch SW Da is the power line V DD One end connected to resistor R Da and the other end connected to resistor R Da is the SDA line connected to the input / output port 35 and the switch SW Da The switch SW Ca and switch SW Da is composed of, for example, an electronic switch or a transistor, and its opening and closing is controlled by a switch control circuit 215a.

[0051] The SCL line connected to the input / output port 35 is connected to the input of the input buffer 211, the output of the output buffer 212, and a resistor R Ca It is connected to one end of resistor R Ca The other end of the switch SW Ca Through the power line V DD The output of the input buffer 211 and the input of the output buffer 212 are connected to other functional elements of the controller 20a.

[0052] The SDA line connected to the input / output port 35 is connected to the input of the input buffer 213, the output of the output buffer 214, and a resistor R Da It is connected to one end of resistor R Da The other end of the switch SW Da Through the power line V DDThe output of the input buffer 213 and the input of the output buffer 214 are connected to other functional elements of the controller 20a.

[0053] The switch control circuit 215a controls the switch SW Ca and switch SW Da The opening and closing condition is based on whether or not communication between the host device 30 and the memory system 2 has started. More specifically, the switch control circuit 215a opens and closes the switch SW Ca and switch SW Da When the start of transmission of a clock signal or a data signal is detected from the SCL line or the SDA line with the switch SW Ca and switch SW Da otherwise, switch SW Ca and switch SW Da Keep the door closed.

[0054] That is, first, the switch control circuit 215a controls the switch SW Ca and switch SW Da Close the resistor R Ca and resistor R Da Through the power line V DD In this state, the switch control circuit 215a detects that the host device 30 is not connected to the input / output port 35 of the memory system 2 and the SCL and SDA lines are in a floating state. In this case, the switch control circuit 215a controls the switch SW Ca and switch SW Da Keep the SCL and SDA lines connected to resistor R Ca and resistor R Da In the memory system 2, the power supply line V DD When the host device 30 is connected to the input / output port 35 of the memory system 2 and detects the start of transmission of a clock signal or a data signal from the SCL line or the SDA line, the switch control circuit 215a controls the switch SW Ca and switch SW DaThis releases the pull-up state of the SCL and SDA lines in the memory system 2.

[0055] 7 shows a state in which the host device 30 is connected to the memory system 2 via an input / output port 35 in the second embodiment. As shown in FIG. 7, the host device 30 has an interface section IF in which the SCL line and the SDA line are connected to resistors R HC and resistor R HD This causes the power line V DD Pulled up to .

[0056] When the switch control circuit 215a detects the start of transmission of a clock signal or a data signal on the SCL line or the SDA line, the switch control circuit 215a controls the switch SW Ca and switch SW Da This opens the resistor R Ca and resistor R Da is the power line V DD The SCL and SDA lines are disconnected from the power supply line V of the host device 30. DD It is pulled up only to

[0057] (Detection of start of signal transmission) As shown in FIG. 7, the SCL and SDA lines of the host device 30 are connected to the power supply line V DD When the host device 30 is connected to the memory system 2, the SCL and SDA lines are pulled up to the power supply line V DD The SCL and SDA lines when no signal is present are in a state in which the host device 30 has not started to transmit a clock signal or a data signal to the SCL or SDA line. On the other hand, when the host device 30 starts to transmit a clock signal or a data signal to the SCL or SDA line, the potential of the SCL or SDA line becomes "L."

[0058] FIG. 8 shows a data waveform conforming to the SMBus standard in the embodiment. As shown in FIG. 8, the waveform of data transmitted according to this standard (data signal flowing on the SDA line based on the clock signal flowing on the SCL line) is a data string consisting of a 7-bit slave address, a 1-bit command, and a 1-bit ACK, a data string consisting of an 8-bit register address, a 1-bit ACK, and a data string consisting of an 8-bit data string, and a 1-bit ACK, in this order. These data strings start with the transition of the SCL line and the SDA line from the "H" potential to the "L" potential at the start S, and end with the transition of the SCL line and the SDA line from the "L" potential to the "H" potential at the stop P. The switch control circuit 215a according to the second embodiment detects the transition of the SCL line or the SDA line from the "H" level to the "L" level at the start S.

[0059] Here, the "H" level (or potential) refers to the logical value "H" and is generally the power supply line V DD The potential of the power supply line V is referred to as an "L" level (or potential), which generally means a logic value of "L", but is not limited to this. For example, an "H" level is the potential of the power supply line V DD The "L" level may be a potential having a height equivalent to the potential of the ground line. The potential of the ground line may also be the potential of the negative power supply line. Specifically, 70 to 100% of the potential of the power supply line VDD may be the "H" level, and 30% to 0% of the potential of the power supply line VDD (ground potential or negative potential of the power supply line) may be the "L" level.

[0060] That is, the memory system 2 according to the second embodiment detects a change in potential from "H" level to "L" level that occurs immediately before the transmission of a data string by a clock signal or a data signal flowing through the SCL line or the SDA line, and turns on the switch SW Ca and switch SW Da Therefore, when transmitting a clock signal or a data signal, the SCL line and the SDA line are in a pulled-up state only within the host device 30, making it possible to carry out stable signal transmission.

[0061] 8, when data transmission starts, the potential transition from "H" level to "L" level on the SDA line occurs earlier than the potential transition from "H" level to "L" level on the SCL line. Therefore, it is preferable for the switch control unit 215a to detect the potential transition from "H" level to "L" level that appears on the SDA line.

[0062] In the memory system 2 according to the modified embodiment, the host device 30 detects the start of transmission in optional low-speed communication (e.g., SMBus) by detecting a transition of the potential appearing on the SCL line or the SDA line from "H" level to "L" level. This makes it possible to detect the presence or absence of connection of the host device 30 without providing any special additional function to the interface standard.

[0063] (Operation of the second embodiment) Next, the operation of the memory system 2 of this embodiment will be described with reference to Fig. 9. Since the memory system 2 according to the second embodiment is a modified version of the memory system 1 according to the first embodiment, common operations are denoted by common reference symbols and duplicated descriptions will be omitted.

[0064] In an initial state in which the host device 30 is not connected to the input / output port 35, the switch control circuit 215a controls the switch SW Ca and switch SW Da This is the state shown in FIG. 6, where the SCL and SDA lines of the host interface 210d are maintained in a closed state by resistors R Ca and resistor R Da Through the power line V DD As a result, the inputs of the input buffers 211 and 213 and the outputs of the output buffers 212 and 214 are both pulled up to the power supply line V DD , and the elements of the host interface 210d are protected.

[0065] The switch control circuit 215a of the host interface 210d monitors the potentials of the input signals on the SCL and SDA lines via the input buffers 211 and 213 (S520). If there is no change in the levels of the SCL and SDA lines, the monitoring continues (No in S535). At this point, the host device 30 is connected to the memory system 2 via the input / output port 35, but communication via the SCL and SDA lines has not yet started.

[0066] When a potential change from "H" to "L" of the clock signal or data signal is detected on the SCL line or the SDA line (Yes in S535), the switch control circuit 215a controls the switch SW Ca and switch SW Da As a result, the SCL and SDA lines are connected to the resistor R Ca and resistor R Da On the other hand, when a potential change from "H" to "L" is detected on the SCL or SDA line, the resistor R HC or resistor R HD The SCL or SDA line becomes the power supply line V DD This means that the signal has been pulled up to the high level (and as a result, data transmission or the like has started), so it can be seen that the host device 30 has started transmission in the optional low-speed communication (for example, SMBus) (S550).

[0067] The switch control circuit 215a of the host interface 210d monitors the potential of the input signal on the SCL line and the SDA line via the input buffers 211 and 213 (S560). Specifically, the switch control circuit 215a monitors the potential of the input signal related to stop P, which indicates that transmission in low-speed communication is completed. If there is no change in the potential of the input signal, monitoring continues (No in S570). After transmission in low-speed communication is completed, when a transition from the "L" potential to the "H" potential of the SCL line and the SDA line at stop P is detected (Yes in S570), the switch control circuit 215a controls the switch SW Ca and switch SW DaThis operation closes the SCL and SDA lines of the host interface 210d, and the resistor R Ca and resistor R Da Through the power line V DD As a result, the inputs of the input buffers 211 and 213 and the outputs of the output buffers 212 and 214 are both pulled up to the power supply line V DD , and the elements of host interface 210d are protected.

[0068] Through this series of operations, the data signal line (SDA line) and the clock signal line (SCL line) of the interface line connecting the host device 30 and the memory system 2 are always connected to the power supply line V DD This ensures stable operation of the circuit and protects the circuit.

[0069] In the memory system 2 according to the second embodiment, even when the host device 30 is connected to the input / output port 35 and there is no data transmission on the SCL and SDA lines, the SCL and SDA lines are pulled up in the memory system 2. That is, the pull-up is performed both in the host device 30 and in the memory system 2, but the potentials of the SCL and SDA lines are stable, so that there is no problem in protecting the elements included in the host interface 210d. In addition, after the start of data transmission, the pull-up in the memory system 2 is released, so there is no problem in data transmission. The significance of the switch is the same as in the memory system 1 according to the first embodiment.

[0070] According to the memory system 2 according to the modified embodiment, when the host device 30 starts data transmission in optional low-speed communication (e.g., SMBus), the pull-up of the data signal line and the clock signal line in the memory system 2 is released. That is, the resistor R HC and resistor R HD Only the power line V DDOn the other hand, when data transmission from the host device 30 to the memory system 2 is completed, the data signal line and the clock signal line are pulled up in the host device 30 and in the memory system 2. This series of operations makes it possible to protect the elements included in the host interface 210d.

[0071] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0072] 1,2…Memory system, 10...NAND flash memory, 11…Memory chip, 20, 20a…controller, 210, 210a, 210b, 210c, 210d...host interfaces, 220…RAM, 230…CPU, 240…buffer, 250…NAND interface, 260...RAM interface 30, 31...host device, 35...input / output port, 40…NAND bus, 100,100a...bus.

Claims

1. A memory system comprising a non-volatile memory and a memory controller connected to the memory, the memory system being connectable to a host, the memory system comprising: The memory controller includes: Executing instructions for the memory received from the host; a signal line for transmitting a signal sent from the host; a resistance element electrically connected between the signal line and a wiring to which a reference potential of the memory system is applied; a switching element connected in series with the resistive element and capable of controlling a connection between the signal line and the wiring; a control circuit that controls the switching element to change the connection between the signal line and the wiring from a connected state to a disconnected state based on a change in a potential on the signal line from a first potential corresponding to a logical H level to a second potential corresponding to a logical L level or a change from the second potential to the first potential; Equipped with After the connection between the signal line and the wiring is changed to the disconnected state, Inside the memory controller, there is no connection of a resistive element between the signal line and the wiring, the potential of the signal line becomes a potential corresponding to a reference potential of the host, which is applied to a host wiring electrically connected to the signal line inside the host through a host resistance element; the signal lines include a clock signal line for transmitting a clock signal and a data signal line for transmitting a data signal; The control circuit controls the switching element so as to change the connection between the clock signal line and the wiring or the connection between the data signal line and the wiring from the connected state to the disconnected state when a change from the first potential to the second potential occurs on the clock signal line or the data signal line. Memory system.

2. the reference potential is a ground potential of the memory system; 2. The memory system of claim 1, wherein the control circuit controls the switching element so as to change the connection between the signal line and the wiring from the connected state to the disconnected state when there is a change from the second potential to the first potential on the signal line.

3. the reference potential is a positive power supply potential of the memory system; 2. The memory system of claim 1, wherein the control circuit controls the switching element so as to change the connection between the signal line and the wiring from the connected state to the disconnected state when there is a change from the first potential to the second potential on the signal line.

4. 2. The memory system of claim 1, wherein the memory system is compliant with the SMBus(TM) standard.

5. 2. The memory system according to claim 1, wherein the memory system complies with a plurality of interface standards different from each other.

6. 6. The memory system according to claim 5, wherein the plurality of interface standards include an SMBus(TM) standard and a PCIe(TM) standard.

7. A method for controlling a memory system that includes a non-volatile memory and a memory controller connected to the memory and is connectable to a host, the memory controller being capable of executing an instruction for the memory received from the host, and including a resistive element electrically connected between a signal line that transmits a signal sent from the host and a wiring to which a reference potential of the memory system is applied; controlling a connection between the signal line and the wiring based on a change in a potential on the signal line from a first potential corresponding to a logical H level to a second potential corresponding to a logical L level or from the second potential to the first potential; After the connection between the signal line and the wiring is changed from a connected state to a disconnected state, Inside the memory controller, there is no connection of a resistive element between the signal line and the wiring, the potential of the signal line becomes a potential corresponding to a reference potential of the host, which is applied to a host wiring electrically connected to the signal line inside the host through a host resistance element; the signal lines include a clock signal line for transmitting a clock signal and a data signal line for transmitting a data signal; when a change occurs from the first potential to the second potential on the clock signal line or the data signal line, controlling a connection between the clock signal line and the wiring or a connection between the data signal line and the wiring to be changed from the connected state to the disconnected state. A method for controlling a memory system.

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