Semiconductor device and manufacturing method thereof

Abstract

To provide a manufacturing method of a channel lamination type GAA-FET element.SOLUTION: A manufacturing method includes: a step of forming an alternate layer 110 in which a silicon germanium layer and a silicon layer are alternately laminated on a substrate; a step of forming a silicon nitride film 112 on a front surface and a side wall of the alternate layer having a fin structure after the alternate layer is patterned and etched to form the fin structure projected onto the substrate; a step of forming a gate spacer 115 to the side wall of a dummy gate after the dummy gate 113 and a silicon oxide film 114 are sequentially formed on the alternate layer while nipping the silicon nitride film; a step of etching the alternate layer by using the silicon oxide film as a hard mask after the silicon oxide film exposed to an upper part is etched; and a step of selectively forming an inner spacer on the side wall of the silicon germanium layer of the silicon layer and the silicon germanium layer of the etched alternate layer.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device designed with a Gate-All-Around (GAA) Field Effect Transistor (FET) and a method for manufacturing the same. [Background technology]

[0002] To overcome the structural limitations of planar semiconductor devices, a three-dimensional Fin-FET technology has been introduced. Fin-FET is a compound word of fin and FET, and has a structure in which the gate surrounds some (e.g., three) sides of the channel. This structure increases the contact area between the gate and the channel, improving operating speed and productivity and reducing power consumption without increasing the size of the device. Fin-FET technology also makes it easier to adjust the size of CMOS (complementary metal-oxide-semiconductor).

[0003] In terms of CMOS architecture and foundry, Fin-FET technology is evolving into an improved Gate All Around (GAA)-FET technology. GAA-FET has a structure in which the gate surrounds the entire surface (e.g., four sides) of the channel, and the contact area is increased compared to Fin-FET, so it has the advantage of providing better current driving capability while being smaller in size compared to Fin-FET technology, and significantly reducing leakage current when power is off.

[0004] Manufacturing such GAA-FET devices is extremely difficult. In particular, manufacturing a GAA-FET device in which a channel having a thickness of less than a few tens of nanometers is stacked requires an extremely difficult process, but research and development in this field is still insufficient. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Publication Number: 10-2016-0099445 (Publication Date: August 22, 2016, Title of Invention: TACKED GATE-ALL-AROUND FINFET AND METHOD FORMING THE SAME) Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE PRESENT EMBODIMENT In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device, more specifically, a method for manufacturing a channel-stacked type GAA-FET device which requires an extremely difficult process. [Means for solving the problem]

[0007] In order to achieve the above object, a method for manufacturing a semiconductor device according to an aspect of the present invention includes the steps of forming alternating layers in which silicon germanium layers and silicon layers are alternately stacked on a substrate, patterning and etching the alternating layers to form a fin structure protruding from the substrate, and then forming a silicon nitride film on a surface and a sidewall of the alternating layers having the fin structure, sequentially forming a dummy gate and a silicon oxide film on the alternating layers with the silicon nitride film sandwiched therebetween, and then forming a gate spacer on a sidewall of the dummy gate, etching the silicon nitride film exposed at an upper portion, and then etching the alternating layers using the silicon oxide film as a hard mask, and selectively forming an inner spacer on a sidewall of the silicon germanium layer of the etched silicon and silicon germanium layers of the alternating layers.

[0008] A semiconductor device according to another aspect of the present invention includes a plurality of source / drains arranged on a substrate, a silicon layer arranged on the substrate and serving as a channel layer, the silicon layer being stacked between adjacent source / drains, a gate electrode arranged on an upper portion of the silicon layer and in a space formed between the silicon layers, an internal spacer supporting the space, and an insulator arranged on the upper portion of the silicon layer to prevent a short circuit between the gate electrode and the source / drains. Effect of the Invention

[0009] According to the present invention, a defect-free single crystal silicon layer can be laminated by using a low-temperature repeated cooling process as a method for reducing stress generated in the process of repeatedly growing a silicon germanium layer used as a sacrificial layer and a silicon layer used as a channel layer, thereby increasing the number of silicon layers used as a channel layer, improving the driving current, and reducing the leakage current.

[0010] Also, by forming inner spacers on both side walls of the silicon germanium layer used as a sacrificial layer, it is possible to support the space between the silicon layers formed by removing the silicon germanium layer.

[0011] Furthermore, the inner spacer can be easily formed by a thermal oxidation process, so that the channel length can be easily adjusted.

[0012] Furthermore, the mole fraction of the silicon germanium layer increases due to the condensation of germanium caused by the thermal oxidation process, which makes it easier to selectively etch the silicon germanium layer.

[0013] In addition, in the process of removing the silicon nitride film formed on the silicon layer, the silicon nitride film is not completely removed and both ends of the silicon nitride film are maintained, so that the short circuit between the gate electrode and the source / drain can be easily prevented by both ends of the silicon nitride film. [Brief description of the drawings]

[0014] [Figure 1] 1 is a perspective view showing a three-dimensional structure of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Diagram 3] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 4] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Diagram 5] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 6] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 7] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 8] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 9] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 10] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 11] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 12] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 13] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 14] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 15] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 16] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 17] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 18] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 19] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 20] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 21] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. [Figure 22] 2 is a cross-section taken along the lines A-A' and B-B' shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The advantages and features of the present invention, and the method of achieving them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the present invention of the scope of the invention, and the present invention is defined only by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

[0016] As used herein, when a film, such as a layer or film, is referred to as being "on" another film or substrate, it means that the film may be formed directly on the other film or substrate, or there may be another film of material interposed therebetween.

[0017] Furthermore, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe material films or process steps, but this is merely used to distinguish a particular material film or process step from other material films or other process steps, and should not be construed as being limited by these terms.

[0018] The terms used in the present specification are for the purpose of describing the embodiments and are not intended to limit the present invention. In the present specification, the singular form includes the plural form unless otherwise specified in the text. When used in the specification, "comprises" and / or "comprising" means that the mentioned components, steps, operations and / or elements do not exclude the presence or addition of one or more other components, steps, operations and / or elements.

[0019] In addition, the embodiments described herein are described with reference to perspective views and / or cross-sectional views which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for the effective explanation of technical contents. Therefore, the shapes of the exemplary views may vary depending on manufacturing techniques and / or tolerances. Therefore, the embodiments of the present invention are not limited to the specific shapes shown in the drawings, but also include changes in shapes generated by the manufacturing process. For example, an etching region shown with a right angle may be rounded or have a shape with a predetermined curvature. Therefore, the regions illustrated in the drawings have schematic attributes, and the shapes of the regions illustrated in the drawings are intended to illustrate specific shapes of the regions of the element, and are not intended to limit the scope of the invention.

[0020] FIG. 1 is a perspective view showing a three-dimensional structure of a semiconductor device according to an embodiment of the present invention.

[0021] Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention may be a channel-stacked GAA (Gate-All-Around)-FET device evolved from a fin-FET device.

[0022] The semiconductor device designed as a GAA-FET device includes a substrate 101, a plurality of source / drains 117 disposed on the substrate 101, a plurality of silicon layers 103, 105, 107, 109 stacked between adjacent source / drains 117 as channel layers disposed on the substrate 101, a gate electrode 120 disposed on the silicon layers 103, 105, 107, 109 and in a space formed between the silicon layers 103, 105, 107, 109, an inner spacer 116' supporting the space, and an insulator 112 for blocking (preventing) a short circuit between the gate electrode 120 and the source / drains 117 disposed on the silicon layers 103, 105, 107, 109.

[0023] The gate electrode 120 is disposed on the silicon layers 103, 105, 107, and 109 and in the spaces formed between the silicon layers 103, 105, 107, and 109, thereby surrounding the silicon layers 103, 105, 107, and 109 used as channel layers.

[0024] A gate electrode 120 is formed by a GAA-FET element by sharing adjacent source / drains 117. The GAA-FET element is isolated from other GAA-FET elements by a shallow trench isolation (STI) film (STI film) 111.

[0025] The inner spacer 116' supporting the spaces formed between the silicon layers 103, 105, 107, and 109 may be a silicon oxide film (third silicon oxide film), and the insulator 112 blocking a short circuit between the gate electrode 120 and the source / drain 117 may be a silicon nitride film. The insulator 112 is processed from a plate-shaped thin film to a line-shaped thin film by an etching process to be described later.

[0026] Meanwhile, in Fig. 1, reference numeral 118 denotes a silicon oxide film (fourth silicon oxide film) covering the entire surface of the substrate 101, which is shown in a transparent configuration in Fig. 1 to clearly show the internal three-dimensional structure of the semiconductor device. In Fig. 1, reference numeral 119 denotes a gate dielectric layer. The gate dielectric layer 119 is disposed between the gate electrode 120 and the silicon layers 103, 105, 107, and 109 used as channel layers.

[0027] Hereinafter, a method for manufacturing the semiconductor device shown in Fig. 1 will be described in detail with reference to Fig. 2 to Fig. 22. It should be noted that while four silicon layers 103, 105, 107, and 109 are shown in Fig. 1, for the sake of simplicity of the drawings, only three silicon layers 103, 105, and 107 are shown in Fig. 2 to Fig. 22.

[0028] 2 to 22 are cross-sectional views taken along the cutting lines AA' and BB' shown in FIG.

[0029] First, referring to FIG. 2, a process of forming alternating layers 110 in which silicon germanium layers 102 and silicon layers 103 are alternately stacked on a substrate 101 is performed.

[0030] The substrate 101 may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc. Also, the substrate 101 may include a silicon substrate, a Si-On-Insulator (SOI) substrate, which may be p-type or n-type, or an intrinsic silicon substrate.

[0031] A silicon germanium layer 102 and a silicon layer 103 are successively grown on a substrate 101. The silicon germanium layer 102 and the silicon layer 103 may be thin films having a thickness of a few tens of nanometers or less. For example, the thickness of the silicon germanium layer 102 and the silicon layer 103 may range between about 5 nm and about 8 nm. The germanium percentage (atomic percentage) of the silicon germanium layer 102 may be in the range between about 25 percent and about 35 percent, although higher or lower germanium percentages may be used.

[0032] The silicon germanium layer 102 and the silicon layer 103 are formed in the same chamber by an epitaxial growth process using the substrate 101 as a seed layer. In this case, the silicon germanium layer 102 is SiGe (Si 1-x Ge x ;x is 0 to 1) is called an epitaxial layer (epi layer), and the silicon layer 103 is called a Si epi layer.

[0033] The epitaxial growth process includes, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a molecular beam epitaxy (MBE) process.

[0034] The silicon germanium layer 102 is used as a sacrificial layer that is selectively etched in a subsequent process, and the silicon layer 103 is used as a channel layer of the GAA-FET device. In this case, the number of times that the silicon germanium layer 102 and the silicon layer 103 are repeatedly grown is the same as the number of channel layers of the GAA-FET device. The silicon layer 103 used as the channel layer is sometimes called a semiconductor layer.

[0035] The difference in lattice constant between silicon and germanium is about 4.3%. This causes stress during repeated growth of the silicon germanium layer 102 and silicon layer 103. When the silicon germanium layer 102 and silicon layer 103 exceed a critical thickness in this state, the accumulated strain energy is released and the stress is relieved. During this process, interfacial dislocations are generated, which reduces the performance of the device and generates leakage current.

[0036] The more the number of times the silicon germanium layer 102 and the silicon layer 103 are repeatedly grown, the greater the stress applied to the silicon germanium layer 102 and the silicon layer 103 becomes, and the greater the dislocation density becomes, which causes a problem of limiting the number of silicon channels in the GAA-FET element.

[0037] In order to solve this problem, in this embodiment, a low-temperature recurring cooling process is proposed as a method for reducing stress generated during repeated growth of the silicon germanium layer 102 and the silicon layer 103.

[0038] The low-temperature repeated cooling process is a process in which a silicon germanium layer 102 and a silicon layer 103 are successively grown at a first temperature, the grown silicon germanium layer 102 and silicon layer 103 are cooled to a second temperature lower than the first temperature, and another silicon germanium layer 104 and another silicon layer 105 are successively grown at the first temperature again. That is, the low-temperature repeated cooling process means repeating the growth and cooling of a silicon germanium layer and a silicon layer.

[0039] Such a low-temperature repeated cooling process utilizes the difference in thermal expansion coefficient between silicon and germanium, and is effective in alleviating stress between SiGe and silicon. Here, the first temperature, which is a growth temperature, may be, for example, 500°C to 800°C, and the second temperature, which is a cooling temperature, may be, for example, 300°C to 400°C.

[0040] The growth of the silicon germanium layer and the silicon layer is preferably carried out by a CVD process using radiant heat by lamp heating, and rapid cooling and heating are possible by lamp heating.

[0041] When the growth of SiGe and silicon is performed by an ALD process or an MBE process rather than a CVD process, rapid cooling and heating can be performed using an RTA (Rapid Thermal Annealing) device after the epitaxial growth is completed.

[0042] In this way, in the present invention, in order to reduce the stress generated during the repeated growth of the silicon germanium layer and the silicon layer, the silicon germanium layer and the silicon layer are repeatedly grown using a low-temperature repeated cooling process, thereby making it possible to stack a single crystal silicon layer without defects and to increase the number of stacked silicon layers, thereby improving the drive current and reducing the leakage current.

[0043] 2 shows a case where the silicon germanium layer and the silicon layer are repeatedly grown three times, but the present invention is not limited to this case, and therefore the number of times that the silicon germanium layer and the silicon layer are repeatedly grown may be four or more.

[0044] 3 to 6, after a process of patterning and etching the alternating layer 110 to form a fin structure protruding from the substrate 101 (FIGS. 3, 4, and 5), a process of forming a silicon nitride film on the surface and sidewalls of the alternating layer 110 having the fin structure (FIG. 6) is performed.

[0045] 3, the fin structure can be achieved by patterning and etching the alternating layer 110 to form a trench 30. The trench 30 is formed by sequentially performing a photolithography process, an etching process, and an ashing process for removing a photoresist film formed in the photolithography process, which are performed after selecting a position of the trench.

[0046] Next, referring to FIG. 4, an STI process is performed to cover the alternating layers and to form a shallow trench isolation film (STI film) 111 in the trench 30.

[0047] The STI process includes a deposition process for filling the trench 30 with an isolation film, and a planarization process (Chemical Mechanical Polishing: CMP) for removing surface steps of the isolation film 111. The deposition process may be CVD, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), High Density or Plasma CVD. The planarization process is performed to remove surface steps of the isolation film 111 to such a level that the surface of the alternating layer 110 is not exposed. The surface of the alternating layer 110 is the surface of the uppermost silicon layer 107 in the alternating layer 110. The isolation film 111 is a silicon oxide film (SiO 2 ) may also be used.

[0048] 5, a process of removing the isolation film 111 is performed to expose the sidewalls of the alternating layers 110. For this purpose, a wet etching process can be used.

[0049] Next, referring to FIG. 6, a silicon nitride film (Si 3 N 4 A process of forming a silicon nitride film 112 (SiN or SiN) is performed. The silicon nitride film 112 is formed by a deposition process including CVD, APCVD, LPCVD, or PECVD. The silicon nitride film 112 plays an important role in preventing a short circuit between the gate electrode and the source / drain in a subsequent process and in a selective etching process for forming a channel by the silicon layers 103, 105, and 107.

[0050] 7 to 9, a dummy gate 113 and a first silicon oxide film 114 are sequentially formed on the alternating layer 110 with the silicon nitride film 112 therebetween (FIGS. 7 and 8), and then a process of forming gate spacers on sidewalls of the dummy gate 113 (FIG. 9) is performed.

[0051] Specifically, referring to FIG. 7, a dummy gate 113 is formed on the entire surface of the silicon nitride film 112. Thus, the dummy gate 113 is formed on the alternating layer 110 with the silicon nitride film 112 sandwiched therebetween. The dummy gate 113 is formed by a deposition process including CVD, APCVD, LPCVD, or PECVD. The dummy gate 113 may be polysilicon (Poly-Si), silicon germanium (SiGe), amorphous silicon, or other material having a high etching selectivity with respect to the first silicon oxide film 114. Next, a first silicon oxide film 114 is formed on the entire surface of the dummy gate 113. The first silicon oxide film 114 is formed by a deposition process including CVD, APCVD, LPCVD, or PECVD.

[0052] 8, a process is performed to etch the dummy gate 113 and the first silicon oxide film 114 corresponding to the remaining regions of the silicon layers 103, 105, and 107 excluding the regions used as channel layers. The dummy gate 113 and the first silicon oxide film 114 corresponding to the remaining regions are etched by, for example, a photolithography process and a dry etching process. The etching width W of the dummy gate 113 and the first silicon oxide film 114 as viewed from the viewpoint of the cutting line A-A' is 1 is the etching width W of the dummy gate 113 and the first silicon oxide film 114 as viewed from the viewpoint of the cutting line B-B′. 2 is set larger.

[0053] 9, a process of forming gate spacers 115 on sidewalls of the dummy gate 113 exposed by the etching process of FIG. 8 is performed. The gate spacers 115 are formed by, for example, a thermal oxidation process. The gate spacers 115 may be a silicon oxide film. The silicon oxide film that is the gate spacer 115 is called a second silicon oxide film to distinguish it from the first silicon oxide film 114 formed on the dummy gate 113. The width of the gate spacer 115 can be set in consideration of the channel width of the silicon layers 103, 105, and 107.

[0054] 10 and 11, after forming a gate spacer 115 on the sidewall of the dummy gate 113, the silicon nitride film 112 exposed at the top is selectively etched (FIG. 10), and then a process of etching the alternating layer 110 using a first silicon oxide film 114 formed on the dummy gate 113 as a hard mask is performed (FIG. 11).

[0055] 10, the silicon nitride film 112 is etched by, for example, a dry or wet etching process, preferably a dry etching process, and a partial surface of the alternating layer 110 is exposed on the top by etching the silicon nitride film 112. The partial surface of the alternating layer 110 means a partial surface of the silicon layer 107 arranged in the uppermost stage.

[0056] 11, a process of etching the alternating layer 110 is performed without a photolithography process, using the first silicon oxide film 114 formed on the dummy gate 113 as a hard mask. At this time, the gate spacer 115, which is a second silicon oxide film formed on the sidewall of the dummy gate 113, is also used as a hard mask. As a result, the sidewall of the dummy gate 113 is not exposed when the alternating layer 110 is etched.

[0057] 12 and 13, a process of selectively forming inner spacers 116' on sidewalls of the silicon germanium layers 102, 104, and 106 among the silicon layers 103, 105, and 107 and the silicon germanium layers 102, 104, and 106 of the etched alternating layer 110 is performed.

[0058] 12, a process of forming a silicon oxide film 116 on the sidewalls of the silicon germanium layers 102, 104, and 106 and the silicon layers 103, 105, and 107 of the etched alternating layer 110 is performed. At this time, a silicon oxide film 116 is also formed on the substrate 101 by the same process. For the sake of terminology, the silicon oxide film formed on the sidewalls of the silicon germanium layers 102, 104, and 106 and the silicon layers 103, 105, and 107 and on the substrate 101 is referred to as a "third silicon oxide film."

[0059] The third silicon oxide film 116 is formed by a thermal oxidation process. The thermal oxidation process may be a wet oxidation process or a dry oxidation process, and is preferably a wet oxidation process. The wet oxidation process is performed at a temperature of 800° C. or less, and preferably at 700° C. to 800° C., in order to precisely adjust the widths of the silicon layers 103, 105, and 107 and the silicon germanium layers 102, 104, and 106.

[0060] In the dry oxidation process, there is almost no difference in the oxidation rate between the silicon layers 103, 105, 107 and the silicon germanium layers 102, 104, 106. However, in the wet oxidation process, the oxidation rate of the silicon germanium layers 102, 104, 106 is higher than that of the silicon layers 103, 105, 107. This is due to the germanium component contained in the silicon germanium layers 102, 104, 106, and the higher the mole fraction of germanium, the higher the growth rate of the third silicon oxide film 116. In the oxidation process of the silicon germanium layer, the germanium component does not participate in the oxidation process. Therefore, the germanium component is condensed in the silicon germanium layer, and as the oxidation process proceeds, the germanium mole fraction of the silicon germanium layer increases.

[0061] As a result, the third silicon oxide film 116 formed on the sidewalls of the silicon germanium layers 102, 104, and 106 at the same time has a first width W 1 The third silicon oxide film 116 formed on the side walls of the silicon layers 103, 105, and 107 is grown to have the first width W 1 Shorter second width W 2 Grows into.

[0062] In the wet oxidation process, the growth rate of the third silicon oxide film 116 growing on the sidewalls of the silicon layers 103, 105, and 106 is different from the growth rate of the third silicon oxide film 116 growing on the sidewalls of the silicon germanium layers 102, 104, and 106, but each silicon oxide film 116 is formed to a very accurate width. Therefore, the wet oxidation process is more advantageous than the dry oxidation process in that the widths of the silicon layers 103, 105, and 107 and the silicon germanium layers 102, 104, and 106 remaining after the silicon oxide film 116 is grown can be precisely controlled. In addition, the wet oxidation process is more advantageous than the dry oxidation process in that the boundary between the silicon layer and the silicon germanium layer can be prevented from becoming unclear due to the diffusion of germanium.

[0063] 13, if the third silicon oxide film 116 grows to different widths on the sidewalls of the silicon layers 103, 105, and 107 and the silicon germanium layers 102, 104, and 106, a process of etching the third silicon oxide film 116 is performed until the sidewalls of the silicon layers 103, 105, and 107 are exposed. That is, the etching process of the third silicon oxide film 116 is stopped in a state where the third silicon oxide film formed on the sidewalls of the silicon germanium layers 102, 104, and 106 remains. Here, the third silicon oxide film 116 remaining on the sidewalls of the silicon germanium layers 102, 104, and 106 with the sidewalls of the silicon layers 103, 105, and 107 exposed becomes the inner spacer 116'.

[0064] The etching process of the third silicon oxide film 116, which is performed until the sidewalls of the silicon layers 103, 105, and 106 are exposed, may be, for example, a dry etching process or a wet etching process, and preferably a wet etching process.

[0065] The etching process of the third silicon oxide film 116 is performed at a level that does not completely remove the gate spacer 115, which is the second silicon oxide film formed on the sidewall of the dummy gate 113. Also, the etching process of the third silicon oxide film 116 is performed at a level that does not completely remove the first silicon oxide film 114 formed on the dummy gate 113.

[0066] The inner spacer 116' determines a channel length through the silicon layers 103, 105, and 107 in a subsequent process of removing the silicon germanium layers 102, 104, and 106, which are used as sacrificial layers.

[0067] In addition, the inner spacer 116' plays a role in supporting the silicon layers 103, 105, and 107 used as channel layers. That is, the inner spacer 116' is used as a structure to support the spaces (19 in FIG. 19) between the silicon layers formed by a subsequent process (FIG. 19) of removing the silicon germanium layers 102, 104, and 106.

[0068] Meanwhile, in an etching process of the third silicon oxide film 116 formed on the sidewalls of the silicon layers 103, 105, and 107 and the silicon germanium layers 102, 104, and 106, the silicon nitride film 112 is hardly etched due to its high etching selectivity with respect to the first silicon oxide film 114 and the third silicon oxide film 116. As a result, when viewed from the viewpoint of the cutting line AA, both ends 13 of the silicon nitride film 112 that are not etched protrude from the sidewalls of the silicon layers 103, 105, and 107. The protruding both ends 13 of the silicon nitride film are used as insulators that prevent (block) a short circuit between a gate electrode and a source / drain to be formed in a subsequent process.

[0069] Referring to FIG. 14, after forming the inner spacer 116', a process of forming source / drain (S / D) 117 on both sides of the alternating layers including the silicon layers 103, 105, 107 and the silicon germanium layers 102, 104, 106 is performed using the silicon layers 103, 105, 107 and the silicon substrate 101 as seed layers.

[0070] The source / drain 117 is formed by a selective epitaxial growth process, which may include, for example, an ion implantation process for doping with n-type or p-type impurities depending on the device type (n-type or p-type FET).

[0071] Materials for selectively growing the source / drain 117 can be, for example, silicon, silicon germanium (SiGe) and / or silicon carbide (SiC). In addition, the source / drain 117 according to the embodiment of the present invention grows in a form where the growth starts at different growth points and meets each other because the silicon layers 103, 105, and 107 and the silicon substrate 101 are used as seed layers. Therefore, the source / drain 117 can grow in a polycrystalline form.

[0072] 15, a process of forming a silicon oxide film 118 covering the source / drain and the dummy gate 113 is performed. The silicon oxide film 118 is referred to as a fourth silicon oxide film to distinguish it from the first silicon oxide film 114, the second silicon oxide film used as the gate spacer 115, and the third silicon oxide film used as the inner spacer 116'. The fourth silicon oxide film 118 is formed by a deposition process, for example, a physical vapor deposition (PVD) process, a CVD process, or an atomic layer deposition (ALD) process. Here, the PVD process includes thermal evaporation, e-bean evaporation, and sputtering, and the CVD process includes thermal CVD, plasma enhanced (PE) CVD, atmospheric pressure (AP) CVD, and low pressure (LP) CVD.

[0073] 16, a process of polishing the fourth silicon oxide film 118 is performed to expose a surface of the dummy gate 113. The fourth silicon oxide film 118 is polished by a CMP process.

[0074] 17, a process of removing the exposed dummy gate 113 is performed. The dummy gate 113 is removed by an etching process having a high etching selectivity with respect to the fourth silicon oxide film 118 and the silicon nitride film 112. The etching process may be, for example, a wet etching process or a dry etching process.

[0075] 18, an etching process is performed to remove the silicon nitride film 112 exposed on the upper side due to the removal of the dummy gate 113. The silicon nitride film 112 is removed by an etching process having a high etching selectivity with respect to the fourth silicon oxide film 118. At this time, both ends 13 of the silicon nitride film 112 covered by the fourth silicon oxide film 118 are not etched by the fourth silicon oxide film 118. Both ends 13 of the silicon nitride film 112 that are not removed by the etching process protrude into the fourth silicon oxide film 118. The protruding both ends 13 of the silicon nitride film 112 serve to maintain the distance between the gate electrode (120 in FIG. 22) and the source / drain 117 to be formed in a subsequent process, and also serve as an insulator to prevent a short circuit between the gate electrode (120 in FIG. 22) and the source / drain 117. Meanwhile, the etching process for removing the silicon nitride film 112 may be, for example, a dry etching process or a wet etching process. In order to precisely control the distance between the gate electrode (120 in FIG. 22) and the source / drain 117, it is preferable to remove the silicon nitride film 112 using a dry etching process that is advantageous for precise etching.

[0076] 19, after the removal of the silicon nitride film 112 is completed, a process of selectively removing the silicon germanium layers (102, 104, 106 in FIG. 18) formed between the silicon layers 103, 105, 107 is performed. The silicon germanium layers (102, 104, 106 in FIG. 18) are removed by an etching process including, for example, a dry etching process or a wet etching process. The etching process of the silicon germanium layers (102, 104, 106 in FIG. 18) is performed by an etching material (e.g., an etching solution or an etching gas) that is introduced through a space 20 formed between the sidewalls of the silicon layers 103, 105, 107 and the sidewall of the fourth silicon oxide film 118 when viewed from the viewpoint of the cutting line B-B'.

[0077] 20, after the removal of the silicon germanium layers (102, 104, 106 in FIG. 18) is completed, a process of forming a gate dielectric layer 119 on all surfaces of the silicon layers 103, 105, 107 exposed by the removal of the fourth silicon oxide film 118, the silicon germanium layers (102, 104, 106 in FIG. 18), and the inner sidewalls of the inner spacers 116' is performed. The gate dielectric layer 119 may be silicon oxide, silicon nitride, or a high-k dielectric material (Hf, Zr, Al, La, Mg, Ba, Ti, Pb, or a combination of metal oxides and silicates). The gate dielectric layer 119 is formed by a deposition process including, for example, an atomic layer deposition (ALD) process.

[0078] 21, after the formation of the gate dielectric layer 119 is completed, a process of forming a gate electrode 120 on the gate dielectric layer 119 is performed. The material of the gate electrode 120 may be, for example, Ti, Al, Cu, W, and combinations thereof. The gate electrode 120 is formed, for example, by an ALD process or an electro / electroless deposition process.

[0079] 22, after the formation of the gate electrode 120 is completed, a CMP process is performed to form the gate electrode 120 and the fourth silicon oxide film to the same thickness. For example, the CMP process can be stopped when the surface of the fourth silicon oxide film 118 is exposed. Upon completion of the CMP process for the gate electrode 120, the GAA-FET device is completed.

[0080] The semiconductor devices manufactured by the manufacturing methods according to the above-described embodiments can be realized in various types of semiconductor packages. For example, semiconductor devices according to embodiments of the present invention may be packaged in a variety of formats, including package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flatpack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), etc.

[0081] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, but rather it is possible to use the invention in various other combinations, modifications, and environments without departing from the spirit and scope of the invention. The appended claims should be construed to include other embodiments.

Claims

1. 1. A method for manufacturing a semiconductor device, the method comprising: forming alternating layers of silicon germanium and silicon layers on a substrate (FIG. 2); patterning and etching the alternating layers to form a fin structure protruding above the substrate, and then forming a silicon nitride film on a surface and sidewalls of the alternating layers having the fin structure; forming a dummy gate and a silicon oxide film on the alternating layers with the silicon nitride film therebetween, and then forming a gate spacer on a sidewall of the dummy gate; etching the silicon nitride film exposed at the top, and then etching the alternating layer using the silicon oxide film as a hard mask; and selectively forming an inner spacer on a sidewall of the silicon germanium layer of the etched alternating silicon and silicon germanium layers.

2. The step of forming the alternating layers includes: Sequentially growing the silicon germanium layer and the silicon layer at a first temperature by an epitaxial growth process; a cooling step for cooling the silicon germanium layer and the silicon layer to a second temperature lower than the first temperature; growing another silicon germanium layer and another silicon layer sequentially on the silicon layer at the first temperature by the epitaxial growth process; cooling the other silicon germanium layer and the other silicon layer to the second temperature by the cooling step; The method for manufacturing a semiconductor device according to claim 1 , comprising:

3. 3. The method of claim 2, wherein the first temperature is between 500.degree. C. and 800.degree. C., and the second temperature is between 300.degree. C. and 400.degree.

4. 2. The method of claim 1, wherein the silicon nitride film functions to prevent a short circuit between a gate electrode and a source / drain in a subsequent process.

5. The step of forming the gate spacer comprises:

2. The method of claim 1, further comprising forming a gate spacer on a sidewall of the dummy gate by a thermal oxidation process.

6. The step of forming the inner spacer comprises: forming a silicon oxide film on sidewalls of the etched silicon germanium and silicon layers of the alternating layers; Etching the silicon oxide film until a sidewall of the silicon layer is exposed; forming the silicon oxide film remaining on the sidewall of the silicon germanium layer as the inner spacer while the sidewall of the silicon layer is exposed; The method for manufacturing a semiconductor device according to claim 1 , comprising:

7. The step of forming a silicon oxide film on sidewalls of the silicon germanium layer and the silicon layer includes:

7. The method of claim 6, further comprising growing the silicon oxide film on sidewalls of the silicon germanium layer and the silicon layer by a thermal oxidation process.

8. The step of forming a silicon oxide film on sidewalls of the silicon germanium layer and the silicon layer includes:

7. The method of claim 6, further comprising growing the silicon oxide film on sidewalls of the silicon germanium layer and the silicon layer by a wet oxidation process.

9. 9. The method of claim 8, wherein the silicon oxide film formed on the sidewalls of the silicon germanium layer grows to a first width toward a center of the silicon germanium layer, and the silicon oxide film formed on the sidewalls of the silicon layer grows to a second width smaller than the first width toward the center of the silicon layer.

10. The method of claim 8 , wherein the wet oxidation process is performed at a temperature of 800° C. or less.

11. The step of etching the silicon oxide film includes:

7. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of etching the silicon oxide film by a wet etching process.

12. In the step of etching the silicon oxide film until the sidewall of the silicon layer is exposed, an etching selectivity of the silicon nitride film to the silicon oxide film is 7. The method of claim 6, wherein the silicon nitride film is hardly etched due to a selective etching process, and both ends of the silicon nitride film that are not etched protrude from sidewalls of the silicon layer.

13. 13. The method of claim 12, wherein both ends of the protruding silicon nitride film are used as an insulator to prevent a short circuit between a gate electrode and a source / drain formed in a subsequent process.

14. 2. The method of claim 1, wherein in the forming of the inner spacer, the inner spacer serves as a structure supporting a space between the silicon layers formed by a subsequent process of removing the silicon germanium layer used as a sacrificial layer.

15. 2. The method of claim 1, wherein in the step of forming the inner spacer, the inner spacer is a silicon layer included in the alternating layer and serves as a structure that determines a channel length of the silicon layer used as a channel layer.

16. After the step of selectively forming an inner spacer, forming a source / drain using the silicon layer and the substrate as a seed layer; forming a silicon oxide film covering the source / drain and the dummy gate; polishing the silicon oxide film to expose a surface of the dummy gate; removing the exposed dummy gate; removing the silicon nitride film exposed by removing the dummy gate; selectively removing the silicon germanium layer formed between the silicon layers; forming a gate dielectric layer on a surface of the silicon oxide film, on sidewalls of the silicon oxide film exposed by removal of the dummy gate, and on all sides of each of the silicon layers exposed by removal of the silicon germanium layer; forming a gate electrode over the gate dielectric layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

17. 17. The method of claim 16, wherein in the step of etching and removing the silicon nitride film, both ends of the silicon nitride film protruding into the silicon oxide film are not removed by the silicon oxide film.

18. Both ends of the silicon nitride film are The method for manufacturing a semiconductor device according to claim 17 , further comprising: maintaining a distance between the gate electrode and the source / drain.

19. Both ends of the silicon nitride film are The method of claim 17, further comprising: forming a gate electrode that acts as an insulator to prevent short circuits between the gate electrode and the source / drain.

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