Semiconductor device, semiconductor memory, photoelectric conversion device, mobile body, method for manufacturing photoelectric conversion device, and method for manufacturing semiconductor memory

Abstract

To improve transistor characteristics.SOLUTION: A semiconductor device includes a first conductivity type first transistor and a second conductivity type second transistor, and the first transistor is arranged in an active region of a semiconductor substrate, has a portion where a gate electrode and an active region overlap in a plan view, and is located between the source and the drain of the first transistor of the semiconductor substrate. In the channel width direction, the impurity concentration of the second conductivity type is higher in the end portion than that in the central portion side of the portion.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a semiconductor memory, a photoelectric conversion device, a mobile object, a method for manufacturing a photoelectric conversion device, and a method for manufacturing a semiconductor memory. [Background technology]

[0002] Patent Document 1 discloses a technique for ensuring circuit operation stability by using different transistor thresholds in an SRAM (Static Random Access Memory) type semiconductor memory. Patent Document 2 describes changing the shape of the gate electrode and the thickness of the gate insulating film to reduce transistor noise. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-058675 A [Patent Document 2] JP 2017-069231 A Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 describes using different transistor threshold values, but does not provide a detailed discussion of how to change the size of the transistor. Transistor miniaturization is necessary for high integration of SRAM-type semiconductor memories.

[0005] In addition, there is a demand for reducing noise caused by transistors in semiconductor circuits. However, changing the shape of the gate electrode or the thickness of the gate insulating film as described in Patent Document 2 increases the area of ​​the transistor and increases the number of manufacturing steps.

[0006] An object of the present invention is to provide a technique for improving the size, noise, and other characteristics of transistors used in semiconductor devices. [Means for solving the problem]

[0007] One aspect of the present invention is a semiconductor memory having an SRAM (Static Random Access Memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being arranged in an active region of a semiconductor substrate, the active region including a portion overlapping a gate electrode of the first transistor and located between a source and a drain of the first transistor, the portion being arranged across a first position, a second position, and a third position which are aligned in order along a channel width direction of the first transistor, the portion including a first semiconductor region of a second conductivity type arranged at the first position and a second semiconductor region of a second conductivity type arranged at the second position, and an impurity concentration of the first semiconductor region being higher than an impurity concentration of the second semiconductor region.

[0008] Another aspect of the present invention is a manufacturing method for a semiconductor memory having an SRAM (Static Random Access Memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the method comprising the steps of: preparing a semiconductor substrate having a first region and a second region; using a first mask pattern to form a first trench in the first region and a second trench in the second region; forming a second mask pattern on the first mask pattern, the second mask pattern having an opening that covers the first trench and exposes the second trench; using the first mask pattern and the second mask pattern, implanting impurity ions of a first conductivity type into the semiconductor substrate through the second trench; filling the first trench and the second trench with an insulator to form a first element isolation portion having the first trench and a second element isolation portion having the second trench; and forming the first transistor in the first region and the second transistor in the second region.

[0009] Another aspect of the present invention is a manufacturing method for a semiconductor memory having an SRAM (Static Random Access Memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the method comprising the steps of: preparing a semiconductor substrate having a first region and a second region; using a first mask pattern to form a first trench in the first region and a second trench in the second region; forming a second mask pattern on the first mask pattern, the second mask pattern having an opening that covers the first trench and exposes the second trench; using the first mask pattern and the second mask pattern, implanting impurity ions of a first conductivity type into the semiconductor substrate through the second trench; filling the first trench and the second trench with an insulator to form a first element isolation portion having the first trench and a second element isolation portion having the second trench; and forming the first transistor in the first region and the second transistor in the second region.

[0010] Another aspect of the present invention is a semiconductor device having a CMOS circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being arranged in an active region of a semiconductor substrate, the first transistor having a portion where a gate electrode of the first transistor and the active region overlap and which is located between a source and a drain of the first transistor in the semiconductor substrate, a first semiconductor region of a second conductivity type being arranged at a first position along a channel width direction of the first transistor, and a second semiconductor region of the second conductivity type being arranged at a second position between the first position and a third position, and an impurity concentration of the first semiconductor region being higher than an impurity concentration of the second semiconductor region.

[0011] Another aspect of the present invention includes a unit cell portion in which a unit cell having a photoelectric conversion element is arranged, and a signal readout portion for reading out a signal from the unit cell portion, the signal readout portion having at least one first transistor of a first conductivity type, the first transistor being arranged in an active region of a semiconductor substrate, the active region including a first portion overlapping with a gate electrode of the first transistor and located between a source and a drain of the first transistor, the first portion being arranged across a first position, a second position, and a third position which are aligned in order along a channel width direction of the first transistor, the first portion including a first semiconductor region of a second conductivity type arranged at the first position and a second semiconductor region of a second conductivity type arranged at the second position, and an impurity concentration of the first semiconductor region is higher than an impurity concentration of the second semiconductor region. Effect of the Invention

[0012] The present invention makes it possible to improve the characteristics of a transistor. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is an equivalent circuit diagram for explaining a unit cell of the semiconductor memory according to the first embodiment. [Diagram 2] FIG. 2 is a schematic plan view illustrating a unit cell of the semiconductor memory according to the first embodiment. [Diagram 3] 1A is a schematic cross-sectional view of a transistor according to a first embodiment; FIG. 1B is a schematic cross-sectional view of a transistor according to a first embodiment; FIG. 1C is a graph showing impurity concentrations of the transistor according to the first embodiment; [Figure 4] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a second embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a second embodiment. [Figure 7] 11A to 11C are schematic cross-sectional views illustrating a method for manufacturing a photoelectric conversion device according to a third embodiment. [Figure 8]FIG. 11 is a cross-sectional view illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 9] FIG. 13A is a schematic cross-sectional view of a transistor according to a fifth embodiment, and FIG. 13B is a graph showing the impurity concentration of the transistor according to the fifth embodiment. [Figure 10] FIG. 1 is a block diagram showing a configuration of a photoelectric conversion device. [Figure 11] FIG. 11 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 12] FIG. 13 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a sixth embodiment. [Figure 13] FIG. 13 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a seventh embodiment. [Figure 14] 13 is a table for explaining a photoelectric conversion device according to Example 8. [Figure 15] FIG. 13 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a ninth embodiment. [Figure 16] FIG. 1 is a perspective view illustrating a stacked type photoelectric conversion device. [Figure 17] FIG. 1 is a diagram showing the configuration of an imaging system. [Figure 18] FIG. 1A is a diagram showing a configuration of a moving body; FIG. [Figure 19] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Each embodiment will be described below with reference to the drawings. In the description of each embodiment, the description of the same configuration as in other embodiments may be omitted. The polarity of N-type or P-type in the following description can be changed. In that case, it can be applied by changing the polarity of the semiconductor region, changing the potential of the control signal, etc. In the following description, electrically connecting means connecting to a common node. Also, in the connection relationship between circuit elements, it is possible to make appropriate changes such as inserting another element (switch, buffer, etc.) between them.

[0015] Example 1 1 is an equivalent circuit diagram illustrating a unit cell of a semiconductor memory according to this embodiment. The semiconductor memory according to this embodiment is a static random access memory (hereinafter, SRAM). In the SRAM, a unit cell 100 is a bit cell that holds a 1-bit signal. In the SRAM, a plurality of unit cells 100 are arranged.

[0016] The unit cell 100 has at least six transistors M1 to M6. The two transistors M1 and M2 are P-type MOS transistors and can function as load transistors of the SRAM. The two transistors M3 and M4 are N-type MOS transistors and can function as driver transistors of the SRAM. The two transistors M5 and M6 are N-type MOS transistors and can function as transfer transistors of the SRAM. The connections of the transistors are as follows:

[0017] The sources of the two transistors M1 and M2 are electrically connected to a power supply voltage node VDD. The sources of the two transistors M3 and M4 are electrically connected to a power supply voltage node GND, which is the ground. Two transistors M1 and M3 with different polarities form one inverter, and two transistors M2 and M4 with different polarities form one inverter. Specifically, the drain of the transistor M1 is electrically connected to the drain of the transistor M3, and the gate electrodes of the transistor M1 and the transistor M3 are electrically connected. Similarly, the drain of the transistor M2 is electrically connected to the drain of the transistor M4, and the gate electrodes of the transistor M2 and the transistor M4 are electrically connected. Furthermore, these two inverters form one flip-flop. The gate electrode of the transistor M1 is electrically connected to the drain of the transistor M2, and the gate electrode of the transistor M2 is electrically connected to the drain of the transistor M1.

[0018] The transistor M5 can control conduction between one flip-flop and one bit line BL. The transistor M6 can control conduction between one flip-flop and one bit line BLB. The gate electrodes of the two transistors M5 and M6 are electrically connected to one word line WL. In the first embodiment, these six transistors constitute an SRAM unit cell 100.

[0019] FIG. 2 is a schematic plan view illustrating a unit cell 100 corresponding to FIG. 1. FIG. 2 shows the arrangement of transistors projected onto the surface of a semiconductor substrate. The surface of the semiconductor substrate includes an X direction and a Y direction perpendicular to the X direction. The unit cells 100 are arranged in two regions 210 and 220. The region 210 is an area where an N-type semiconductor region is provided, and the region 220 is an area where a P-type semiconductor region is provided. These semiconductor regions can also be called wells. Two transistors M1 and M2 are arranged in the region 210, and four transistors M3 to M6 are arranged in the region 220.

[0020] In the region 210, an element isolation region 211 and an active region 212 are provided on the surface of the semiconductor substrate. In Fig. 2, a transistor M1 is arranged in one active region 212, and a transistor M2 is arranged in another active region 212. However, the transistors M1 and M2 may be arranged in the same active region 212. The transistor M1 has a gate electrode 231 and P-type semiconductor regions 250 and 251 which serve as a source and drain. The transistor M2 has a gate electrode 230 and P-type semiconductor regions 252 and 253 which serve as a source and drain.

[0021] In the region 220, an element isolation region 221 and an active region 222 are provided on the surface of the semiconductor substrate. In FIG. 2, transistors M3 and M5 are arranged in one active region 222, and transistors M4 and M6 are arranged in another active region 222. However, the transistors M3 to M6 may be arranged in the same active region 222. The transistor M3 has a gate electrode 231 and N-type semiconductor regions 254 and 255 which are a source and a drain. The transistor M4 has a gate electrode 230 and N-type semiconductor regions 256 and 257 which are a source and a drain. The transistor M5 has a gate electrode 232 and N-type semiconductor regions 255 and 258 which are a source and a drain. The transistor M6 has a gate electrode 232 and N-type semiconductor regions 256 and 259 which are a source and a drain. Here, the gate electrode 232 can function as the word line WL in FIG. 1 while functioning as the gate electrodes of the transistors M5 and M6. Here, the legend in FIG. 2 shows ACT indicating an active region, GATE indicating a gate electrode, FIELD indicating an element isolation region, and CNT indicating the position of a contact plug.

[0022] The gate electrodes 230, 231, and 232 are formed of, for example, polysilicon, and can function as gate electrodes of transistors in the portions overlapping with the active regions 212 and 222. Here, the gate electrode 231 is disposed in common to the two transistors M1 and M3, the gate electrode 230 is disposed in common to the two transistors M2 and M4, and the gate electrode 232 is disposed in common to the two transistors M5 and M6. The gate electrodes 230 and 231 extend from the element isolation region 211 to the active region 212, the element isolation region 211, the element isolation region 221, the active region 222, and the element isolation region 221. In the case of the sources and drains other than the gate electrodes, if the sources and drains of the transistors are common nodes, they may be formed of one semiconductor region.

[0023] Here, the high integration of the unit cell of the SRAM will be explained. In the SRAM, the unit cells are repeatedly arranged. By reducing the area of ​​the unit cell even slightly, the high integration of the SRAM is possible. In order to reduce the area of ​​the unit cell, it is effective to reduce the size of the transistors constituting the unit cell. However, in order to stabilize the operation as an SRAM, it is necessary to set the current ratio of each transistor to a desired value, and all of the transistors constituting the unit cell cannot be formed with the minimum size. If all of the transistors constituting the unit cell are formed with the minimum size, the current ratio will change, causing a decrease in the speed of the write and read operations and operation failure. By designing the size of the load transistor to be the smallest among the transistors constituting the unit cell, the size of the other transistors can also be reduced, and the desired current ratio will be achieved, resulting in stable operation. In other words, it is effective to reduce the area of ​​the unit cell by minimizing the channel width that defines the size of the load transistor. Here, the width of the channel of the transistor is generally defined as the width of the active region between the element isolation. Therefore, the spacing between the element isolation is determined by the rules of the semiconductor process. Therefore, in this embodiment, a semiconductor region of the opposite conductivity type to the polarity of the load transistor is provided around the element isolation section in which the load transistor is provided. By providing such a semiconductor region, the effective channel width of the transistor can be made smaller than the spacing between the element isolation sections. Therefore, it is possible to relatively reduce the design values ​​of the channel widths of the drive transistor and transfer transistor compared to the case in which the channel width of the load transistor is set to the minimum value stipulated by the process rules. This makes it possible to reduce the area of ​​the unit cell.

[0024] A specific configuration of the transistor of this embodiment will be described with reference to FIG. 3. FIGS. 3(a) and 3(b) are schematic cross-sectional views of a transistor M1, which is a load transistor. FIGS. 3(a) and 3(b) are schematic views in which the configuration of contact plugs and the like is omitted, focusing on a part of the transistor. FIG. 3(a) is a cross-sectional view of the transistor M1 along the X direction in FIG. 2, and shows a cross-sectional view of the transistor M1 in the channel length direction. FIG. 3(a) shows the semiconductor regions 250 and 251 of the transistor M1 and a gate electrode 231 provided on a gate insulating film 602. The transistor M1 is provided in an N-type semiconductor region 58b. The transistor M1 has a portion 601 located between the semiconductor region 250 and the semiconductor region 251. The portion 601 is a portion where the gate electrode 231 and the active region 212 overlap in a plan view.

[0025] FIG. 3(b) is a cross section of the transistor M1 along the Y direction in FIG. 2, and is a cross section in the channel width direction of the transistor M1. An active region 212 in which the transistor M1 is disposed is disposed between two element isolation regions 211. The element isolation region 211 is provided with an element isolation portion 31. The element isolation portion 31 has a trench isolation structure in which an insulator formed in a groove (trench) is disposed, for example. Examples of the trench isolation structure include an STI structure (shallow trench isolation structure) and a DTI (deep trench isolation structure). In this embodiment, the element isolation portion 31 is an STI. The gate electrode 231 extends from the element isolation region 211 to the active region 212. The gate electrode 231 extends from above the element isolation portion 31 to above the gate insulating film 602. Here, the portion 601 is the active region 212 overlapped with the gate electrode 231 in the Z direction. This portion 601 is generally a region in which a channel of a transistor can be formed.

[0026] In this embodiment, an N-type semiconductor region 52 is provided along the side and bottom of the groove of the element isolation portion 31. The N-type semiconductor region 52 has a higher impurity concentration than the N-type semiconductor region 58b. In FIG. 3(b), n+ is indicated for the semiconductor region 52, and n is indicated for the semiconductor region 58b. The N-type semiconductor region 52 reduces the channel width of the transistor M1 that can actually be formed, that is, the effective channel width. If the width of the region between the element isolation portions 31, that is, the width of the portion 601, is set to width W1, the effective channel width is width W2. It can be said that the effective channel width is determined by the semiconductor region 52. For example, when the width W1 is 80 nm or more and 120 nm or less, the width W2 can be, for example, 60 nm or more and 100 nm or less. The width W2 is not limited to this value and can be set appropriately depending on the semiconductor region 52.

[0027] The line segment AB in FIG. 3(b) is a line segment along the gate width direction, and is located at the end of the portion 601. The line segment AB has positions P1, P2, and P3 on the line segment. The position P2 is a position between the positions P1 and P3. The semiconductor region 52 is provided at the positions P1 and P3, and the semiconductor region 58b is provided at the position P2. FIG. 3(c) is a diagram showing the impurity concentration of the N-type semiconductor region at the line segment AB in FIG. 3(b). The impurity concentration here indicates the NET concentration. In FIG. 3(b), the positions P1 and A are the same position, and the positions P2 and B are the same position, but in reality, the positions P1 to P3 exist between the positions A and B. The concentration at the position P1 is C1, the concentration at the position P2 is C2, and the concentration at the position P3 is C3. In this case, C1=C3>C2. That is, it is understood that the impurity concentration increases from the center of portion 601 toward the boundary between element isolation portion 31 and portion 601 .

[0028] With this configuration, when the gate electrode 231 is turned on, a channel is formed at position P2, but no channel is formed at positions P1 and P3. That is, the threshold value of the transistor is higher at positions P1 and P3 than at position P2. Therefore, the effective channel width of the transistor is smaller than the spacing between the element isolation parts. With this impurity concentration profile, the effective channel width can be made smaller than the spacing between the element isolation parts 31.

[0029] In this embodiment, the concentrations C1 and C3 are equal, but they may be different. In addition, the concentrations C1 and C3 are preferably at least twice the concentration C2. More preferably, the concentrations C1 and C3 are at least 10 times the concentration C2. With such a concentration relationship, the effective channel width can be reliably reduced in the operating voltage range.

[0030] In this embodiment, the semiconductor region 58b in the portion 601 is described as being N-type, but it may be P-type as long as the transistor M1 operates. That is, among the impurity concentrations at the positions P1, P2, and P3, donor concentrations are D1, D2, and D3, and acceptor concentrations are A1, A2, and A3. Here, the concentrations D1, D2, D3, A1, A2, and A3 have values ​​equal to or greater than 0. In this case, the relationship of the concentrations at each position is D1-A1>D2-A2 and D3-A3>D2-A2.

[0031] Moreover, position P1 is between the side surface of the trench of element isolation portion 31 and position P2, and can also be said to be adjacent to element isolation portion 31. Position P3 is between the side surface of the trench of element isolation portion 31 and position P2, and can also be said to be adjacent to element isolation portion 31. In this embodiment, at the depth of line segment AB, semiconductor region 52 extends to a position of, for example, 20 nm from the side surface of the trench.

[0032] In this embodiment, the present invention is applied to the load transistors of an SRAM type semiconductor memory, but it may be applied to other transistors depending on the characteristics. By applying a transistor with such a configuration to an SRAM type semiconductor memory, it becomes possible to miniaturize the unit cell.

[0033] Example 2 In this embodiment, a photoelectric conversion device 300 using the semiconductor memory of the first embodiment will be described. In this embodiment, the photoelectric conversion device has an SRAM and a photoelectric conversion unit in which a photoelectric conversion element is arranged on the same semiconductor substrate. Here, the photoelectric conversion unit is a CCD sensor, a CMOS sensor, or the like. The photoelectric conversion unit of this embodiment is a CMOS sensor having a photodiode as a photoelectric conversion element, a transfer transistor, and an amplification transistor.

[0034] A method for manufacturing the photoelectric conversion device of this embodiment will be described with reference to Figs. 4 to 6. Figs. 4 to 6 are schematic cross-sectional views for explaining a method for manufacturing the photoelectric conversion device 300. The region 310 is a region in which an SRAM is formed, and includes the regions 210 and 220 described in the first embodiment. The region 330 is a region in which pixels of the photoelectric conversion unit are arranged. The pixels include at least a photodiode and a transfer transistor. The region 340 is arranged with a processing circuit unit including a circuit for operating the pixels and a circuit for signal processing. The processing circuit unit includes, for example, a logic circuit and is also called a peripheral circuit in an imaging device. The region 340 has a region 350 and a region 360. The region 350 indicates a region in which an N-type transistor is arranged, and the region 360 indicates a region in which a P-type transistor is arranged.

[0035] The process shown in FIG. 4(a) will be described. First, a substrate 30 is prepared. The substrate 30 is, for example, a silicon single crystal substrate, but may be a substrate after processing. The substrate 30 has a region 310, a region 330, and a region 340. Next, a mask pattern 32 is formed on the substrate 30. The mask pattern 32 is a mask pattern for forming a groove that will become an element isolation portion. The mask pattern 32 has openings at arbitrary positions in each of the regions 220, 210, 330, and 340. The openings of the mask pattern 32 expose the portions of the surface S1 of the substrate 30 where the grooves will be formed later. Then, the substrate 30 is etched using the mask pattern 32 as a mask to form grooves 31a to 31d corresponding to the respective openings. The region 220 has a groove 31a, the region 210 has a groove 31b, the region 330 has a groove 31c, and the region 340 has a groove 31d. Here, the mask pattern 32 is made of an inorganic material such as a silicon nitride film or a silicon oxide film. The mask pattern 32 can be formed by forming a film of an inorganic material on the substrate 30, forming a pattern of an organic material on the film of the inorganic material, and removing a part of the film of the inorganic material by etching using the pattern as a mask. In this embodiment, a silicon nitride film is used as the inorganic material. The pattern of an organic material is, for example, a photoresist pattern.

[0036] In FIG. 4(b), a mask pattern 33 is formed on the mask pattern 32. The mask pattern 33 is a mask pattern for forming an N-type semiconductor region on the side and bottom of the groove in the region 210. The mask pattern 33 covers the regions 220, 330, and 340, and exposes the region 210. That is, the mask pattern 33 covers the grooves 31a, 31c, and 31d, and exposes the groove 31b. The mask pattern 33 has an opening 51 that exposes the region 210. The opening 51 only needs to expose at least the groove 31b in the region 210. Here, as described in the first embodiment, the region 210 is a portion where a load transistor of an SRAM is formed, and is a region where a P-type transistor is formed. The mask pattern 33 is formed of a photoresist. The mask pattern 33 is formed by forming a film made of a photoresist on the mask pattern 32, and then performing exposure, development, and the like. Then, ion implantation 40 is performed on the substrate 30 using the mask patterns 32 and 33 as masks. By the ion implantation 40, an N-type semiconductor region 52 is formed along the side and bottom of the trench. The ion species of the ion implantation 40 is impurity ions for forming an N-type semiconductor region, such as phosphorus (P) or arsenic (As). The implantation angle of the ion implantation 40 can be selected arbitrarily. In this embodiment, the ion implantation is performed obliquely with respect to the surface S1 of the substrate 30, and it is preferable to select the ion implantation angle of about 10 degrees. Here, the ion implantation angle is the angle formed by the perpendicular line to the surface S1 and the ion implantation direction. By having such an implantation angle, ions can be efficiently implanted into the side of the trench. In addition, the ion implantation 40 can be performed by rotating 360 degrees in the direction of the surface S1, so that ions can be implanted into all the side surfaces of the trench. Thereafter, the mask pattern 33 is removed (not shown) while leaving the mask pattern 32.

[0037] In FIG. 4(c), a mask pattern 34 is formed on the mask pattern 32. The mask pattern 34 is a mask pattern for forming a P-type semiconductor region on the side and bottom of the trench in the region 330. The mask pattern 34 covers the regions 210, 220, and 340, and exposes the region 330. That is, the mask pattern 34 covers the trenches 31a, 31b, and 31d, and exposes the trench 31c. The mask pattern 34 has an opening 53 that exposes the region 330. The opening 53 only needs to expose at least the trench 31c in the region 330. The mask pattern 34 is formed of a photoresist. The mask pattern 34 is formed by forming a film made of a photoresist on the mask pattern 32, and then performing exposure, development, and the like. Then, ion implantation 41 is performed on the substrate 30 using the mask pattern 32 and the mask pattern 34 as masks. The ion implantation 41 forms a P-type semiconductor region 54 along the side and bottom of the trench. The ion species of the ion implantation 41 is an impurity ion for forming a P-type semiconductor region, such as boron (B) or boron fluoride (BF2). The implantation angle of the ion implantation 41 can be selected arbitrarily, but it is preferable to select about 10 degrees with respect to the surface S1 of the substrate 30. With such an implantation angle, ions can be efficiently implanted into the side surface of the trench. Moreover, by performing the ion implantation 41 while rotating it 360 degrees in the direction of the surface S1, ions can be implanted into all the side surfaces of the trench.

[0038] Then, the mask pattern 32 is left and the mask pattern 34 is removed. Then, the mask pattern 32 is removed, and an insulator is filled into the grooves 31a to 31d to form the element isolation portion. The insulator is, for example, silicon oxide or silicon nitride. For example, after the mask pattern 34 is first removed, a heat treatment is performed to reduce damage caused to the grooves before forming an insulator film. At that time, a film due to thermal oxidation may be formed on the inner wall of the groove. An insulator film is formed so as to cover the grooves 31a to 31d by a high density plasma CVD method or the like, and the excess insulator film is removed by a polishing technique such as etching or CMP, to form the element isolation portion 31. In the region 210, the element isolation portion 31 is formed with the semiconductor region 52 formed therearound, and in the region 330, the element isolation portion 31 is formed with the semiconductor region 54 formed therearound. In the region 220 and the region 340, neither the semiconductor region 52 nor the semiconductor region 54 is formed around the element isolation portion 31. In addition, a silicon oxide film (not shown) is formed on the surface S1 for a later process.

[0039] In FIG. 5(a), a mask pattern 35 is formed on the surface S1 of the substrate 30. The mask pattern 35 is a mask pattern for forming P-type semiconductor regions in the regions 220, 330, and 350. The P-type semiconductor regions can function as wells in which elements are formed, for example. The mask pattern 35 covers the regions 210 and 360 and exposes the regions 320, 330, and 350. That is, the mask pattern 35 has openings 55a, 55c, and 55d that expose the regions 320, 330, and 350. The mask pattern 35 is formed of photoresist by the same method as other mask patterns. Then, ion implantation 42 is performed on the substrate 30 using the mask pattern 35 as a mask. P-type semiconductor regions 56a, 56c, and 56d are formed by the ion implantation 42. The ion species of the ion implantation 42 is the same as that of the ion implantation 41. The implantation angle of the ion implantation 42 can be selected arbitrarily. Since the region 330 is a region where a photoelectric conversion element is formed, additional ion implantation may be performed to form a well appropriate for the photoelectric conversion element, or the well in the region 330 may be formed in a process different from that for the regions 220 and 340. Thereafter, the mask pattern 35 is removed (not shown).

[0040] In FIG. 5(b), a mask pattern 36 is formed on the surface S1 of the substrate 30. The mask pattern 36 is a mask pattern for forming N-type semiconductor regions in the regions 210 and 360. The N-type semiconductor regions can function as wells in which elements are formed, for example. The mask pattern 36 covers the regions 220, 330, and 350, and exposes the regions 210 and 360. The mask pattern 36 has openings 57b and 57d that expose the regions 210 and 360. The mask pattern 36 is formed of photoresist by the same method as other mask patterns. Then, ion implantation 43 is performed on the substrate 30 using the mask pattern 36 as a mask. N-type semiconductor regions 58b and 58d are formed by the ion implantation 43. The ion species of the ion implantation 43 is the same as that of the ion implantation 40. The implantation angle of the ion implantation 43 can be selected arbitrarily. Thereafter, the mask pattern 36 is removed (not shown).

[0041] In FIG. 5(c), a mask pattern 37 is formed on the surface S1 of the substrate 30. The mask pattern 37 is a mask pattern for forming a P-type semiconductor region 60 in the region 210. This P-type semiconductor region 60 can be provided for adjusting the threshold value of a transistor. The mask pattern 37 covers the region 220, the region 330, and the region 340, and exposes the region 210. The mask pattern 37 has an opening 59 for exposing the region 210. The mask pattern 37 is formed of photoresist by a method similar to that of other mask patterns. Then, ion implantation 44 is performed on the substrate 30 using the mask pattern 37 as a mask. The P-type semiconductor region 60 is formed by the ion implantation 44. The ion species of the ion implantation 44 is the same as that of the ion implantation 41. The implantation angle of the ion implantation 44 can be selected arbitrarily. Thereafter, the mask pattern 37 is removed (not shown).

[0042] In FIG. 6(a), a mask pattern 38 is formed on the surface S1 of the substrate 30. The mask pattern 38 is a mask pattern for forming an N-type semiconductor region 62 in the region 220. This N-type semiconductor region 62 can be provided for adjusting the threshold value of a transistor. The mask pattern 38 covers the region 210, the region 330, and the region 340, and exposes the region 220. The mask pattern 38 has an opening 61 for exposing the region 210. The mask pattern 38 is formed of photoresist by a method similar to that of other mask patterns. Then, ion implantation 45 is performed on the substrate 30 using the mask pattern 38 as a mask. An N-type semiconductor region 62 is formed by the ion implantation 45. The ion species of the ion implantation 45 is the same as that of the ion implantation 40. The implantation angle of the ion implantation 45 can be selected arbitrarily. Thereafter, the mask pattern 38 is removed (not shown).

[0043] Generally, the circuit formed in region 340 uses transistors with a low threshold voltage to increase the speed of operation. On the other hand, the circuit formed in region 310, i.e., SRAM, uses transistors with a relatively high threshold voltage to stabilize the circuit operation. Therefore, in this embodiment, by adding the steps shown in FIG. 5(c) and FIG. 6(a), it is possible to manufacture the transistors in region 310 and region 340 in the same process. This manufacturing method makes it possible to manufacture a photoelectric conversion device at low cost. The steps shown in FIG. 5(c) and FIG. 6(a) may also be applied to the transistors in region 330 and region 340.

[0044] FIG. 6(b) shows a state in which an element is formed after the process described in FIG. 6(a). A P-type transistor is formed in region 210, an N-type transistor is formed in region 220, an N-type transistor and a photoelectric conversion element are formed in region 330, and an N-type transistor and a P-type transistor are formed in region 340. The transistor and the photoelectric conversion element can be formed by forming a gate electrode and ion implantation. After that, an interlayer insulating film, a contact plug, and a wiring layer are formed, and a color filter, a microlens, and the like are formed to form a photoelectric conversion device. In addition, when the photoelectric conversion device is a backside illumination type, the substrate 30 may be thinned, and element isolation may be formed on the backside. As described above, a photoelectric conversion device is formed by the process shown in FIG. 4 to FIG. 6.

[0045] Here, the conditions of ion implantation related to the characteristics of the transistor in region 210 will be described. The ion implantation 40 and ion implantation 44 have a large effect on the transistor characteristics. Here, the dose of ion implantation 40 is greater than the dose of ion implantation 44. This is to satisfy the above-mentioned relationship of impurity concentrations. With this manufacturing method, a channel is not formed in the semiconductor region 52 located under the gate electrode of the transistor, and the effective channel width of the transistor can be narrowed.

[0046] The mask pattern 32 shown in Fig. 4(a) may be formed of photoresist. In that case, for example, the mask pattern 32 made of photoresist is irradiated with ultraviolet light to harden the photoresist. By forming the mask pattern 32 from photoresist in this manner, in the step of Fig. 4(b), the mask pattern 33 can be removed while leaving the mask pattern 32. By forming the mask pattern 32 from photoresist, it is possible to reduce the time required for dry etching or the like to remove the mask pattern 32, compared to when the mask pattern 32 is formed from an inorganic material.

[0047] Example 3 In this embodiment, a modified example of the photoelectric conversion device 300 using the semiconductor memory of the second embodiment will be described with reference to Fig. 7. Fig. 7 is a schematic cross-sectional view illustrating a method for manufacturing the photoelectric conversion device of this embodiment.

[0048] In this embodiment, the polarity of the photoelectric conversion element in the second embodiment is changed. That is, the semiconductor region 54 in FIG. 6(b) is an N-type semiconductor region having the same polarity as the semiconductor region 52. With this configuration, as shown in FIG. 7, the process of forming the semiconductor region 52 and the semiconductor region 54 can be integrated into one process. The forming process includes the process of forming a mask pattern and ion implantation. According to this embodiment, the photoelectric conversion device having an SRAM can be formed in fewer processes.

[0049] Example 4 In this embodiment, a modified example of the photoelectric conversion device 300 using the semiconductor memory of the second embodiment will be described. FIG. 8 is a schematic cross-sectional view of the photoelectric conversion device of this embodiment. In this embodiment, an N-type semiconductor region 801 is provided for the transistor in the region 360. The semiconductor region 801 has the same function as the semiconductor region 52 of the second embodiment. This configuration allows the transistor to be miniaturized. Furthermore, this transistor configuration reduces noise such as random telegraph noise (hereinafter referred to as RTN) caused by the channel of the transistor. In addition to photoelectric conversion devices, the present invention can be applied to CMOS circuits in which RTN should be taken into consideration.

[0050] Example 5 In this embodiment, a photoelectric conversion device to which a suitable transistor is applied will be described. Before describing the photoelectric conversion device, a transistor with reduced noise will be described in detail with reference to FIGS.

[0051] FIG. 9 is a schematic diagram for explaining an example in which the semiconductor region 52 shown in FIG. 3(b) is not included. FIG. 9(a) is a schematic cross-sectional view of a transistor corresponding to FIG. 3(b). FIG. 9(b) corresponds to FIG. 3(c) and is a diagram showing the impurity concentration of the N-type semiconductor region along the line segment AB in FIG. 9(a). In FIG. 9, the same components as those in FIG. 3 are given the same reference numerals and will not be described. The transistor of the comparative example shown in FIG. 9(a) does not have the semiconductor region 52 shown in FIG. 3(b). Therefore, the impurity concentration along the line segment AB in FIG. 9(a) shown in FIG. 9(b) is constant at a concentration C2. The difference between the maximum and minimum of the change in the impurity concentration of the P-type semiconductor region 58b along the line segment AB in FIG. 9(a) is smaller than the difference between the maximum and minimum of the change in the impurity concentration of the P-type semiconductor region along the line segment AB in FIG. 3(b). The difference between the maximum and minimum of the change in the impurity concentration of the P-type semiconductor region along the line segment AB in FIG. 3(b) can also be said to be the difference in the impurity concentration between the semiconductor region 52 and the semiconductor region 58b. Here, the effective channel width of the transistor of the comparative example is width W3. The effective channel width of the transistor described in FIG. 3 is width W2, whereas the effective channel width of the transistor of the comparative example is width W3. The relationship of the widths is W3=W1>W2. In the following description, if the transistor shown in FIG. 3 is a type 1 transistor, the transistor shown in FIG. 9 is a type 2 transistor.

[0052] A transistor arranged close to the element isolation section 31 of the STI structure may have an inverse narrow channel effect. The inverse narrow channel effect means the following transistor operation. The channel end along the channel width direction of the transistor is adjacent to the STI structure. The electric field generated by the gate electrode is concentrated at this channel end. As a result, the threshold value of the transistor is lowered at the channel end. Here, when the transistor is driven, a drain current flows. That is, in the configuration of FIG. 9, the drain current is concentrated at the channel end with a low threshold. Also, oxygen vacancies are generated in the semiconductor substrate near the element isolation section 31. In the oxygen vacant region, trapping and emission of electrons, which are carriers, may occur frequently. When the drain current is concentrated at the channel end, that is, near the element isolation section 31, the value of RTN may increase, that is, may worsen. That is, in the second type transistor shown in FIG. 9, RTN may be superimposed on the signal depending on the place of use. In the case of a photoelectric conversion device, such a current situation may cause a decrease in image quality, for example, in which the image appears to have linear scratches due to noise. The first type transistor has improved RTN characteristics compared to the second type transistor, and the second type transistor can be manufactured with fewer steps compared to the first type transistor, and has a long effective channel length, which allows for improved driving force. Next, a preferred arrangement of transistors in a photoelectric conversion device will be described.

[0053] FIG. 10 is a block diagram showing the configuration of a photoelectric conversion device. A unit cell section 1000 has a plurality of unit cells 1001. The unit cells 1001 are arranged two-dimensionally. The unit cells 1001 may be referred to as pixels in a photoelectric conversion device. The unit cells 1001 have the pixel configuration of, for example, a CMOS type photoelectric conversion device. A vertical scanning circuit 1002 outputs a control signal for driving each unit cell 1001. A control line 1012 electrically connects the vertical scanning circuit 1002 and each unit cell 1001, and supplies a control signal to an element of each unit cell 1001. In FIG. 10, one control line 1012 is arranged for the plurality of unit cells 1001 arranged in each row, but in reality, a plurality of control lines 1012 are arranged in each row. The number of lines is the number necessary to control the unit cells 1001. A signal line 1013 outputs a signal from the unit cell 1001. At least one signal line 1013 is electrically connected to the unit cells 1001 arranged in each column. The signal line 1013 is electrically connected to a signal readout unit 1014.

[0054] The signal readout unit 1014 includes a current source circuit 1003, a signal amplifier circuit 1004, an AD conversion circuit 1005, and a memory circuit 1007. The current source circuit 1003 supplies a constant current to a signal line 1013 for reading out a signal from the unit cell 1001. The signal line 1013 is electrically connected to the signal amplifier circuit 1004. The signal amplifier circuit 1004 amplifies a signal input from the signal line 1013. The AD conversion circuit 1005 converts an analog signal from the signal amplifier circuit 1004 into a digital signal. The ramp generation circuit 1006 generates a reference signal to be compared with a signal to be AD converted by the AD conversion circuit 1005. The counter circuit 1008 outputs a count value. The memory circuit 1007 holds the count value output from the counter circuit 1008. The horizontal scanning circuit 1015 supplies a control signal for transferring the value held in the memory circuit 1007 to the signal processing circuit 1010. The signal output circuit 1011 outputs the signal processed by the signal processing circuit 1010 to the outside of the photoelectric conversion device. The driving of these circuits is controlled based on a control signal from a timing generator (TG) 1009. Note that circuits such as the signal amplifier circuit 1004 and the AD conversion circuit 1005 can be omitted or modified as appropriate. Here, the portion in which circuits other than the unit cell section 1000 are arranged may be referred to as a peripheral circuit section.

[0055] FIG. 11 is an equivalent circuit diagram for explaining a photoelectric conversion device. FIG. 11 shows a readout path of the photoelectric conversion device. FIG. 11 shows the configuration of the unit cell 1001, the current source circuit 1003, the signal amplifier circuit 1004, and the AD conversion circuit 1005 shown in FIG. 10. The unit cell 1001 includes a photodiode (hereinafter, PD) 1101, a transfer transistor 1102, a floating diffusion section (hereinafter, FD) 1104, a reset transistor 1103, an amplifier transistor 1105, and a selection transistor 1106. The PD 1101 functions as a photoelectric conversion section that photoelectrically converts light incident through an optical system. The anode of the PD 1101 is grounded, and the cathode is connected to the source of the transfer transistor 1102. The transfer transistor 1102 is driven by a control signal TX input to its gate, and transfers the charge generated in the PD 1101 to the FD 1104. The FD 1104 temporarily stores electric charge and functions as a charge-voltage converter that converts the stored electric charge into a voltage signal. The amplifier transistor 1105 and the current source circuit 1003 form a source follower amplifier. An electric signal converted into a voltage by the FD 1104 is input to the gate of the amplifier transistor 1105. The drain of the amplifier transistor 1105 is connected to a power supply voltage VDD, and the source of the amplifier transistor 1105 is connected to a selection transistor 1106. The reset transistor 1103 electrically connects the FD 1104 to the power supply voltage VDD. When the reset transistor 1103 is turned on by a control signal RES, the electric charge of the FD 1104 is discharged to the power supply voltage VDD and reset. Here, the power supply voltage VDD can be said to be a reference voltage. The selection transistor 1106 electrically connects the amplifier transistor 1105 to a signal line 1107. When a corresponding row is selected at a certain time, the control signal SEL becomes high level. The selection transistor 1106, to which a high-level control signal SEL is supplied, becomes conductive, and a signal from the amplification transistor 1105 is output to a signal line 1107. These transistors in the unit cell 1001 are N-type transistors. A constant current is supplied to the signal line 1107, forming a source follower amplifier.

[0056] The current source circuit 1003 includes three N-type transistors 1108 to 1110. The three transistors 1108 to 1110 are provided so as to be directly connected between a signal line 1107 and a ground voltage GND. The transistors 1109 and 1110 are cascode-connected and function as a current source. The transistor 1108 functions as a switch for turning the current source on and off. A control signal V1108 is supplied to the gate of the transistor 1108. When the control signal V1108 is at a high level, a constant current is supplied to the signal line 1107, and when the control signal V1108 is at a low level, the supply of the constant current to the signal line 1107 is stopped. The control signal V1109 is supplied to the gate of the transistor 1109, and the control signal V1110 is supplied to the gate of the transistor 1110. The control signal V1109 and the control signal V1110 are fixed bias voltages that determine the operating points of the transistors 1109 and 1110, respectively.

[0057] The output of the source follower amplifier constituted by the amplifying transistor 1105 is input to a signal amplifying circuit 1004. The signal amplifying circuit 1004 includes an inverting amplifier 1112, an input capacitance 1111, a feedback capacitance 1114, a switch 1113, and a switch 1115. The amplification degree of the signal can be changed by using the switch 1113 to select or deselect the feedback capacitance 1114 and change the capacitance value. The amplification degree of the signal may also be changed by changing the position of the switch 1113 to change the capacitance value of the input capacitance 1111. The switch 1115 resets the inverting amplifier 1112, the input capacitance 1111, and the feedback capacitance 1114. The signal amplified by the signal amplifying circuit 1004 is AD converted in the AD converting circuit 1005.

[0058] Here, we will explain the relationship between the current flowing through the signal line 1107 and the signal. First, find the amount of change ΔVvl in the voltage Vvl of the signal line 1107 when the current Ivl flowing through the signal line 1107 changes by ΔIvl. If β is a current parameter of the amplifying transistor 1105, Vvl and ΔVvl are expressed by equations (1) and (2). Vvl=Vfd-Vth-√2Ivl / β...Equation (1) ΔVvl=-√2ΔIvl / β...Equation (2) From equation (2), it can be seen that when the current Ivl of the signal line 1107 changes, the voltage Vvl changes. In other words, the current Ivl is a factor of the fluctuation of the voltage Vvl. Here, since the optical signal from the PD 1101 and the reference reset signal appear in the voltage Vvl, it is desirable that the voltage Vvl does not fluctuate due to other factors. If the voltage Vvl fluctuates, the fluctuation is superimposed on the voltage indicating the signal, resulting in noise. In other words, it is desirable that the current Ivl is a constant current with little fluctuation. Therefore, as described with reference to FIG. 3 and FIG. 9, it is desirable to apply a first-class N-type transistor with a constant drain current to the transistors 1109 and 1110 constituting the current source. With such a configuration, it is possible to reduce the current ΔIvl and the voltage ΔVvl and reduce the degradation of the signal due to RTN.

[0059] Example 6 The photoelectric conversion device of this embodiment will be described with reference to FIG. 12. FIG. 12 is an equivalent circuit diagram for explaining the photoelectric conversion device of this embodiment. FIG. 12 shows the inverting amplifier 1112 of the signal amplifier circuit 1004 shown in FIG. 10 and FIG. 11. The inverting amplifier 1112 includes at least five transistors 1201 to 1205. The P-type transistor 1202 and the P-type transistor 1203 are cascode-connected to form a current source circuit. This current source passes a constant current of, for example, 6 μA. The control signal V1202 and the control signal V1203 are supplied to the gates of the transistors 1202 and 1203, respectively, and are fixed bias voltages that determine the operating points of each transistor. The P-type transistor 1201 functions as a switch for turning the current source circuit on or off. The control signal V1201 is supplied to the gate of the transistor 1201 to control the on / off of the transistor 1201. The N-type transistor 1204 is a gate-grounded transistor. The control signal V1204 is a fixed bias voltage that determines the operating point. The N-type transistor 1205 is a common-source transistor. An input signal Vampi, not a control signal, is input to the gate of the transistor 1205. The output signal Vampo of the inverting amplifier 1112 is output to a common node of the transistors 1204 and 1203.

[0060] Here, the gain Ao of the inverting amplifier 1112 is expressed by equation (3).

[0061]

number

[0062] Here, the mutual conductance gm and the output resistance R of the N-type transistor 1205 with the source grounded are assumed. If the RTN deteriorates in the transistor 1202 or the transistor 1203, the drain current of the transistor 1205 changes, and the mutual conductance gm of the transistor 1205 changes. As a result, the gain Ao changes as shown in the formula (3). This is because, if a constant signal is input, the magnitude of the signal amplified by one inverting amplifier 1112 may vary depending on the timing (time) of the amplification. In addition, if there are multiple inverting amplifiers 1112, even if a constant signal is input, the magnitudes of the multiple amplified signals may vary. Therefore, it is desirable to use P-type type 1 transistors for the P-type transistor 1202 and the P-type transistor 1203 that constitute the current source circuit. In addition, control signals V1204 and V1205 that determine the operating point are input to the gates of the transistors 1204 and 1205. Even in such transistors, since a variation in drain current causes a variation in operation, it is preferable to use a type 1 transistor. That is, it is preferable to use N-type type 1 transistors for the N-type transistor 1204 and the N-type transistor 1205. As in this embodiment, by using type 1 transistors for at least the transistors 1202 and 1203 in the signal amplifier circuit 1004, it is possible to suppress signal degradation.

[0063] Example 7 The photoelectric conversion device of this embodiment will be described with reference to FIG. 13. FIG. 13 is an equivalent circuit diagram for explaining the photoelectric conversion device of this embodiment. FIG. 13 shows the AD conversion circuit 1005 shown in FIG. 10 and FIG. 11. The AD conversion circuit 1005 includes at least a comparator 1300. The comparator 1300 includes transistors 1301 to 1307. A P-type transistor 1301 and a P-type transistor 1302 are cascode-connected to configure a current source circuit. A P-type transistor 1303 can function as a switch for turning on or off the current source circuit. A control signal V1303 is supplied to the gate of the transistor 1303 to control the conduction of the transistor 1303. A P-type transistor 1304 functions as an input transistor. A ramp signal output from the ramp generation circuit 1006 shown in FIG. 10 is input to the gate of the transistor 1304. A P-type transistor 1305 functions as an input transistor. The amplified signal Vampo output from the signal amplifier circuit 1004 shown in FIG. 10 is input to the gate of the transistor 1305. In FIG. 13, the gate of the transistor 1304 is indicated as the input terminal INN, and the gate of the transistor 1305 is indicated as the input terminal INP. The drain of the transistor 1304 is electrically connected to the drain of the N-type transistor 1306, and the drain of the transistor 1305 is electrically connected to the drain of the N-type transistor 1307. The comparator 1300 of such a circuit outputs a result of comparing the signal voltage Vampo caused by the optical signal with a ramp signal serving as a reference signal. The output is output to a node where the transistors 1305 and 1307 are connected, and the comparison result may be affected by a change in the current value in the current source circuit via a capacitance, a latch circuit, and a logic circuit. Therefore, it is desirable to apply a first-class transistor to at least the transistors 1301 and 1302 of the comparator 1300. Also, the first-class transistors may be applied to the transistors 1304 to 1307. As in this embodiment, by using type 1 transistors at least for the transistors 1202 and 1203 in the AD conversion circuit 1005, it is possible to suppress signal degradation.

[0064] Example 8 In each of the fifth to seventh embodiments, the details of the circuit in which it is desirable to provide the first-class transistor in the photoelectric conversion device are described. In this embodiment, it is described which part of the photoelectric conversion device is provided with the first-class transistor. FIG. 14 is a table for explaining the photoelectric conversion device according to this embodiment. FIG. 14 shows the part in each block of the photoelectric conversion device shown in FIG. 10 to which the first-class transistor is desirable to be applied. If the block described in the column of the block name includes the first-class transistor, a "◯" is added to the column of the first-class transistor, and if it does not include the first-class transistor, a "×" is added to the column of the first-class transistor. First, by applying the first-class transistor to the unit cell section 1000, it is possible to reduce the influence of the dark current (leak current) generated around the element isolation section on the PD. Furthermore, as described in the fifth to seventh embodiments, it is desirable to apply the first-class transistor to a part where noise may be superimposed on the signal of at least one of the current source circuit 1003, the signal amplifier circuit 1004, and the AD conversion circuit 1005 in the signal readout section. It is preferable to use type 1 transistors in locations where noise may be superimposed on the signals of the three circuits.

[0065] On the other hand, in the circuit of the signal readout section, it is preferable to apply a type 2 transistor, not a type 1 transistor, to a transistor used in a completely on state, for example, a transistor functioning as a switch. The control signal for turning on and off a transistor functioning as a switch is, for example, a ground voltage GND in the case of a P-type transistor, and a power supply voltage Vdd in the case of an N-type transistor. Since a uniform inversion region occurs in the channel of a transistor to which such a control signal is supplied, current is unlikely to concentrate and flow at the channel end near the element isolation part. Therefore, it is possible to apply a type 2 transistor, not a type 1 transistor, because RTN is unlikely to increase. In a type 2 transistor, the semiconductor region 52 and the semiconductor region 54 of the opposite conductivity type to the polarity of the transistor are not provided. In other words, a PN junction interface is not formed between the semiconductor region 52 and the semiconductor region 54 of the opposite conductivity type to the source and drain of the transistor. Therefore, it is possible to suppress the decrease in the breakdown voltage due to the PN junction. In addition, if the effective channel width of the transistor becomes small, the resistance when the transistor is on may increase, causing a decrease in the driving speed. Therefore, in a circuit requiring high-speed driving, it is preferable to apply a type 2 transistor, not a type 1 transistor. The circuits requiring high speed driving include the vertical scanning circuit 1002, the ramp generating circuit 1006, the memory circuit 1007, the horizontal scanning circuit 1015, the counter circuit 1008, the TG 1009, the signal processing circuit 1010, the signal output circuit 1011, and the like.

[0066] As shown in this embodiment, in a device such as a photoelectric conversion device in which it is desired to reduce noise superimposed on a signal, by using a type 1 transistor in at least one circuit of the readout circuit unit, it is possible to reduce the noise superimposed on the signal.

[0067] Example 9 This embodiment shows a modification of the inverting amplifier 1112 in FIG. 11 described in the fifth embodiment. In this embodiment, the inverting amplifier 1112 is changed from a single-input amplifier to a differential amplifier. The other configurations of this embodiment are the same as those described in the fifth embodiment.

[0068] FIG. 15 is an equivalent circuit diagram for explaining the photoelectric conversion device according to this embodiment. FIG. 15 shows an inverting amplifier 1112. The inverting amplifier 1112 is a differential amplifier. A P-type transistor 1501, a P-type transistor 1502, an N-type transistor 1503, and an N-type transistor 1504 form a differential pair. An N-type transistor 1506 forms a current source circuit. An N-type transistor 1505 functions as a switch for turning a current on or off. A signal is input as a voltage Vampi to an input terminal, which is the gate of the transistor 1504. A reference signal Vref is input to the other input terminal. The difference between the voltages input to the two input terminals is amplified and output as a voltage Vampo from the output terminal. Here, as described in the fifth embodiment, if the RTN of the transistor deteriorates, the amount of current in the differential amplifier fluctuates. At that time, if the balance of the current flowing through the differential pair is lost, the voltage Vampo, which is the output signal, fluctuates. Here, by configuring the differential amplifier with a first-class transistor, the RTN can be reduced and the quality of the signal can be improved. In addition, the transistor 1505 functioning as a switch is preferably a type 2 transistor.

[0069] The configuration of this embodiment also makes it possible to provide a photoelectric conversion device with reduced noise.

[0070] Example 10 In this embodiment, an example of a photoelectric conversion device will be described. The photoelectric conversion device of this embodiment is configured by stacking at least two semiconductor substrates for stacking in an electrically connected state. Such a photoelectric conversion device is also called a stacked type photoelectric conversion device. Here, the semiconductor substrate may be called a member or a chip.

[0071] FIG. 16 is a schematic diagram of the photoelectric conversion device 3000 of this embodiment, and is an exploded perspective view of the photoelectric conversion device 3000. A pixel region 3011 is provided on one semiconductor substrate 3010. A control unit 3021 and a signal processing unit 3022 are provided on another semiconductor substrate 3020. The pixel region 3011 is a photoelectric conversion unit in which unit cells including photoelectric conversion elements are arranged. The signal processing unit 3022 is provided with the semiconductor memory described in the first embodiment and the like. The orthogonal projections of the control unit 3021 and the signal processing unit 3022 onto the semiconductor substrate 3010 are at least partially overlapped with the pixel region 3011. The photoelectric conversion device 3000 of this embodiment may further include a semiconductor substrate having another processing circuit, or may include three or more stacked semiconductor substrates.

[0072] The control unit 3021 may include a vertical scanning circuit that supplies driving signals to the pixels, a power supply circuit, a timing generation circuit for driving the photoelectric conversion device, a reference signal supply circuit that supplies a reference signal to the conversion circuit, an amplifier circuit, or a horizontal scanning circuit for sequentially reading out signals from the conversion circuit.

[0073] The signal processing unit 3022 processes an electric signal based on a signal charge generated in the pixel region. The signal processing unit 3022 may include a noise elimination circuit, an amplification circuit, a conversion circuit, and an image signal processing circuit. The noise elimination circuit is, for example, a correlated double sampling (CDS) circuit. The amplification circuit is, for example, a column amplifier circuit. The conversion circuit is, for example, an analog-to-digital conversion (ADC) circuit composed of a comparator and a counter. The image signal processing circuit includes, for example, a memory and a processor, and generates image data from the analog-to-digital converted digital signal and performs image processing on the image data.

[0074] The present invention is also applicable to a photoelectric conversion device in which a plurality of semiconductor substrates are stacked as in this embodiment.

[0075] Example 11 Fig. 17 is a block diagram showing the configuration of an imaging system 3100 according to this embodiment. The imaging system 3100 of this embodiment includes the photoelectric conversion device 3104 described in the above embodiment. Here, any of the photoelectric conversion devices described in the above embodiment can be applied to the photoelectric conversion device 3104. Specific examples of the imaging system 3100 include a digital still camera, a digital camcorder, and a surveillance camera. Fig. 10 shows an example of the imaging system 3100 as a digital still camera.

[0076] 10 includes a photoelectric conversion device 3104, a lens 3102 that forms an optical image of a subject on the photoelectric conversion device 3104, an aperture 3103 that varies the amount of light passing through the lens 3102, and a barrier 3101 that protects the lens 3102. The lens 3102 and the aperture 3103 form an optical system that focuses light on the photoelectric conversion device 3104.

[0077] The imaging system 3100 has a signal processing unit 3105 that processes an output signal output from the photoelectric conversion device 3104. The signal processing unit 3105 performs signal processing operations such as performing various corrections and compression on an input signal as necessary and outputting the signal. The imaging system 3100 further has a buffer memory unit 3106 for temporarily storing image data, and an external interface unit (external I / F unit) 3109 for communicating with an external computer or the like. The imaging system 3100 further has a recording medium 3111 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 3110 for recording or reading out the recording medium 3111. The recording medium 3111 may be built into the imaging system 3100 or may be removable. In addition, communication from the recording medium control I / F unit 3110 to the recording medium 3111 and communication from the external I / F unit 3109 may be performed wirelessly.

[0078] Furthermore, the imaging system 3100 has an overall control / calculation unit 3108 that performs various calculations and controls the entire digital still camera, and a timing generation unit 3107 that outputs various timing signals to the photoelectric conversion device 3104 and the signal processing unit 3105. Here, the timing signals and the like may be input from the outside, and the imaging system 3100 only needs to have at least the photoelectric conversion device 3104 and the signal processing unit 3105 that processes the output signal output from the photoelectric conversion device 3104. Note that, as described in the sixth embodiment, the timing generation unit 3107 may be mounted on the photoelectric conversion device. The overall control / calculation unit 3108 and the timing generation unit 3107 may be configured to implement a part or all of the control functions of the photoelectric conversion device 3104.

[0079] The photoelectric conversion device 3104 outputs an image signal to the signal processing unit 3105. The signal processing unit 3105 performs a predetermined signal processing on the image signal output from the photoelectric conversion device 3104, and outputs image data. The signal processing unit 3105 generates an image using the image signal. The signal processing unit 3105 and the timing generating unit 3107 may be mounted on the photoelectric conversion device. That is, the signal processing unit 3105 and the timing generating unit 3107 may be provided on a substrate on which pixels are arranged, or may be provided on a separate substrate as shown in FIG. 16. By configuring an imaging system using the photoelectric conversion device of each of the above-mentioned embodiments, an imaging system capable of acquiring a better quality image can be realized.

[0080] Example 12 The moving body of this embodiment will be described with reference to Figs. 18 and 19. Fig. 18 is a schematic diagram showing a configuration example of the moving body of this embodiment. Fig. 19 is a flow diagram showing the operation of an imaging system mounted on the moving body of this embodiment. In this embodiment, an example of an on-vehicle camera is shown as the imaging system. In the following description, the imaging device refers to any of the photoelectric conversion devices of the above-mentioned embodiments.

[0081] FIG. 18(a) shows an example of a vehicle system and an imaging system mounted thereon. The imaging system 3201 includes an imaging device 3202, an image pre-processing unit 3215, an integrated circuit 3203, and an optical system 3214. The optical system 3214 forms an optical image of a subject on the imaging device 3202. The imaging device 3202 converts the optical image of the subject formed by the optical system 3214 into an electrical signal. The image pre-processing unit 3215 performs predetermined signal processing on the signal output from the imaging device 3202. The function of the image pre-processing unit 3215 may be incorporated in the imaging device 3202. The imaging system 3201 includes at least two sets of the optical system 3214, the imaging device 3202, and the image pre-processing unit 3215, and the output from each set of the image pre-processing unit 3215 is input to the integrated circuit 3203.

[0082] The integrated circuit 3203 is an integrated circuit for use in an imaging system, and includes an image processing unit 3204 including a memory 3205, an optical distance measuring unit 3206, a parallax calculation unit 3207, an object recognition unit 3208, and an abnormality detection unit 3209. The image processing unit 3204 performs image processing such as development processing and defect correction on the output signal of the image pre-processing unit 3215. The memory 3205 temporarily stores the captured image and stores the defective positions of the captured pixels. The optical distance measuring unit 3206 performs focusing and distance measurement of the subject. The parallax calculation unit 3207 calculates parallax information (phase difference of parallax images) from multiple image data acquired by multiple imaging devices 3202. The object recognition unit 3208 recognizes subjects such as cars, roads, signs, and people. When the abnormality detection unit 3209 detects an abnormality in the imaging device 3202, it notifies the main control unit 3213 of the abnormality.

[0083] The integrated circuit 3203 may be realized by dedicated hardware, a software module, or a combination of these. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or a combination of these.

[0084] The main control unit 3213 supervises and controls the operations of the imaging system 3201, the vehicle sensor 3210, the control unit 3220, etc. Note that instead of having the main control unit 3213, a method may be adopted in which the imaging system 3201, the vehicle sensor 3210, and the control unit 3220 each have their own communication interface and each transmits and receives control signals via a communication network (for example, CAN standard).

[0085] The integrated circuit 3203 has a function of receiving a control signal from the main control unit 3213 or transmitting a control signal or a setting value to the imaging device 3202 by its own control unit.

[0086] The imaging system 3201 is connected to a vehicle sensor 3210, and can detect the vehicle's driving state, such as vehicle speed, yaw rate, and steering angle, as well as the state of the environment outside the vehicle, other vehicles, and obstacles. The vehicle sensor 3210 is also a distance information acquisition means for acquiring distance information to an object from a parallax image. The imaging system 3201 is also connected to a driving assistance control unit 3211 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the imaging system 3201 and the vehicle sensor 3210. This allows for avoidance control when a collision is estimated, and activation of a safety device when a collision occurs.

[0087] The imaging system 3201 is also connected to an alarm device 3212 that issues an alarm to the driver based on the result of the determination by the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 3213 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 3212 warns the user by sounding an alarm, displaying alarm information on a display screen such as a car navigation system or a meter panel, vibrating a seat belt or steering wheel, etc.

[0088] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are photographed by the imaging system 3201. Fig. 18B shows an example of the arrangement of the imaging system 3201 when the imaging system 3201 photographs the area in front of the vehicle.

[0089] The two imaging devices 3202 are disposed in front of the vehicle 3200. Specifically, if the center line of the vehicle 3200 with respect to its forward / backward direction or outer shape (for example, vehicle width) is regarded as an axis of symmetry, and the two imaging devices 3202 are disposed in line symmetry with respect to the axis of symmetry, this is preferable for obtaining distance information between the vehicle 3200 and an object to be photographed and for determining the possibility of a collision. In addition, the imaging devices 3202 are preferably disposed so as not to obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 3200 from the driver's seat. The alarm device 3212 is preferably disposed so as to be easily within the driver's field of vision.

[0090] Next, the operation of detecting a fault in the image capturing device 3202 in the image capturing system 3201 will be described with reference to Fig. 19. The operation of detecting a fault in the image capturing device 3202 is performed in accordance with steps S3310 to S3380 shown in Fig. 19.

[0091] Step S3310 is a step for performing startup settings of the imaging device 3202. That is, settings for the operation of the imaging device 3202 are transmitted from outside the imaging system 3201 (e.g., the main control unit 3213) or from inside the imaging system 3201, and the imaging operation and failure detection operation of the imaging device 3202 are started.

[0092] Next, in step S3320, pixel signals are obtained from the effective pixels. In addition, in step S3330, output values ​​are obtained from failure detection pixels provided for failure detection. These failure detection pixels have a photoelectric conversion unit, just like the effective pixels. A predetermined voltage is written to this photoelectric conversion unit. The failure detection pixels output a signal corresponding to the voltage written to this photoelectric conversion unit. Note that steps S3320 and S3330 may be reversed.

[0093] Next, in step S3340, a judgment is made as to whether the output expected value of the fault detection pixel corresponds to the actual output value from the fault detection pixel. If the result of the judgment in step S3340 indicates that the output expected value and the actual output value correspond, the process proceeds to step S3350, where it is judged that the imaging operation is performed normally, and the process proceeds to step S3360. In step S3360, the pixel signal of the scanning row is sent to the memory 3205 and temporarily stored. Thereafter, the process returns to step S3320, and the fault detection operation is continued. On the other hand, if the result of the judgment in step S3340 indicates that the output expected value and the actual output value do not correspond, the process proceeds to step S3370. In step S3370, it is judged that there is an abnormality in the imaging operation, and an alarm is issued to the main control unit 3213 or the alarm device 3212. The alarm device 3212 displays the detection of the abnormality on the display unit. Thereafter, in step S3380, the image capturing device 3202 is stopped, and the operation of the image capturing system 3201 is terminated.

[0094] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S3370 may be notified to the outside of the vehicle via a wireless network.

[0095] In addition, in this embodiment, the control to prevent collision with other vehicles has been described, but the control can also be applied to automatic driving control to follow other vehicles, automatic driving control not to go out of the lane, etc. Furthermore, the imaging system 3201 is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system 3201 is not limited to moving bodies, but can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0096] The photoelectric conversion device of the present invention may further include a color filter or a microlens, and may be configured to be capable of acquiring various information such as distance information. For example, a plurality of photoelectric conversion elements may be provided for one input node, or a single microlens common to a plurality of photoelectric conversion elements may be provided. The amplifying transistor may be a part of a source follower circuit, but may also be a part of an AD converter. Specifically, the amplifying transistor may constitute a part of a comparator included in the AD converter. A part of the comparator may be provided on another semiconductor substrate. The unit circuit may not include a transfer transistor, and the photoelectric conversion element may be directly connected to the input node. Furthermore, a charge discharge unit such as an overflow drain may be provided.

[0097] The present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention. Although the above-mentioned embodiments are described using examples such as a semiconductor memory and a photoelectric conversion device, the structure related to the transistor of the present invention can be applied to other devices. The above-mentioned embodiments are merely examples of the embodiment of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these examples. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0098] M1 Transistor 31 Element isolation section 231 Gate electrode 601 parts 602 Gate insulating film 52 Second conductivity type semiconductor region 58b Second conductivity type semiconductor region

Claims

1. a unit cell portion in which unit cells each having a photoelectric conversion element are arranged; a signal readout unit disposed at a position different from the unit cell unit for reading out a signal from the unit cell unit; the signal readout unit includes a signal amplifier circuit, at least one of an AD converter circuit, and a current source circuit; at least one of the signal amplifier circuit and the AD converter circuit has at least one first transistor of a first conductivity type; the first transistor is disposed in an active region of a semiconductor substrate; the active region includes a first portion overlapping a gate electrode of the first transistor and located between a source and a drain of the first transistor; the first portion is disposed across a first position, a second position, and a third position which are aligned in order along a channel width direction of the first transistor; the first portion includes a first semiconductor region of a second conductivity type arranged at the first position and a second semiconductor region of the second conductivity type arranged at the second position; A photoelectric conversion device, wherein the first semiconductor region has an impurity concentration higher than an impurity concentration of the second semiconductor region.

2. 2. The photoelectric conversion device according to claim 1, wherein, in a plan view, the active region is adjacent to an element isolation portion having a trench.

3. The photoelectric conversion device according to claim 2 , wherein the first position is between a side surface of the trench and the second position.

4. The photoelectric conversion device according to claim 2 , wherein the gate electrode of the first transistor extends over the element isolation portion.

5. the isolation portion includes a side portion and a bottom portion; 5. The photoelectric conversion device according to claim 2, wherein the bottom and the first semiconductor region are adjacent to each other along a depth direction of the semiconductor substrate.

6. The photoelectric conversion device according to claim 5 , wherein the bottom portion is disposed at a position overlapping at least a portion of the first semiconductor region in a plan view.

7. The photoelectric conversion device according to claim 5 , wherein the side portion and the bottom portion are in contact with the first semiconductor region.

8. a channel of the first transistor is formed at the second location; 8. The photoelectric conversion device according to claim 1, wherein a channel of the first transistor is not formed at the first position.

9. a third semiconductor region of a second conductivity type is disposed at the third position in the first portion; 9. The photoelectric conversion device according to claim 1, wherein the third semiconductor region has an impurity concentration higher than an impurity concentration of the second semiconductor region.

10. 10. The photoelectric conversion device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type.

11. 11. The photoelectric conversion device according to claim 1, wherein, when a gate electrode of the first transistor is turned on, the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region are such that a channel is formed at the second position and a channel is not formed at the first position.

12. The photoelectric conversion device according to any one of claims 1 to 11, characterized in that, when an impurity concentration of the first semiconductor region is C1 and an impurity concentration of the second semiconductor region is C2, the impurity concentrations of the first semiconductor region and the second semiconductor region satisfy C1 ≧ 2 × C2.

13. 13. The photoelectric conversion device according to claim 12, wherein the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region satisfy C1≧10×C2.

14. 14. The photoelectric conversion device according to claim 1, comprising a plurality of the unit cells.

15. 15. The photoelectric conversion device according to claim 1, wherein the current source circuit includes the first transistor.

16. the signal readout unit includes at least an AD conversion circuit, 16. The photoelectric conversion device according to claim 1, wherein the AD conversion circuit includes a comparator having another current source circuit, and the current source circuit and the other current source circuit include the first transistor.

17. the signal readout unit has at least one second transistor of the first conductivity type, the second transistor is disposed in another active region of the semiconductor substrate; the active region includes a second portion overlapping a gate electrode of the second transistor and located between a source and a drain of the second transistor; the second portion is disposed across a fourth position, a fifth position, and a sixth position which are aligned in order along a channel width direction of the second transistor; the second portion includes a fourth semiconductor region of the second conductivity type arranged at the fourth position and a fifth semiconductor region of the second conductivity type arranged at the fifth position; 17. The photoelectric conversion device according to claim 1, wherein the fourth semiconductor region and the fifth semiconductor region have the same impurity concentration.

18. the signal readout unit has at least one second transistor of the first conductivity type, the second transistor is disposed in another active region of the semiconductor substrate; the active region includes a second portion overlapping a gate electrode of the second transistor and located between a source and a drain of the second transistor; the second portion is disposed across a fourth position, a fifth position, and a sixth position which are aligned in order along a channel width direction of the second transistor; the second portion includes a fourth semiconductor region of the second conductivity type arranged at the fourth position and a fifth semiconductor region of the second conductivity type arranged at the fifth position; 17. The photoelectric conversion device according to claim 1, wherein the second conductivity type is P type, and a difference between the maximum and minimum impurity concentrations of the first semiconductor region and the second semiconductor region is smaller than a difference between the impurity concentrations of the first semiconductor region and the second semiconductor region.

19. the unit cell includes a transfer transistor that transfers charges from the photoelectric conversion element and an amplification transistor that outputs a signal based on the charges; 19. The photoelectric conversion device according to claim 1, wherein the transfer transistor and the amplification transistor are the first transistor.

20. The plurality of unit cells further include a signal line electrically connectable thereto, 20. The photoelectric conversion device according to claim 1, wherein the signal amplifier circuit processes the signal read out from the unit cell via the signal line.

21. The photoelectric conversion device according to any one of claims 1 to 20, a signal processing unit that processes a signal from the photoelectric conversion device.

22. The photoelectric conversion device according to any one of claims 1 to 20, a distance information acquisition means for acquiring distance information to an object from parallax information based on a signal from the photoelectric conversion device, A moving body further comprising a control means for controlling the moving body based on the distance information.

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