MEMORY STRUCTURE AND METHOD FOR OPERATING SAME - Patent application

Abstract

To provide a memory structure and a method for operating the memory structure.SOLUTION: A memory structure 10 includes: first to third gate structures 112, 114, 116 arranged along a first direction and separated from each other; a channel bodies 120 having first ends 120a and second ends 120b; a plurality of source regions 101 that are separated from each other, have first conduction types, and each being connected to the first end of the channel body; drain regions 102 that are separated from each other, have second conduction types, and each being connected to the second end of the channel body; and first side plugs 131 disposed along a second direction, extending along a third direction, and being electrically connected to the source regions and the channel bodies. The first gate structure includes island structures 1121 arranged along the second direction and extending along the third direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor structures and methods for operating same, and more particularly to memory structures and methods for operating same. [Background technology]

[0002] With the advent of big data and artificial intelligence innovation, the amount of data generated by human activities has been exploding. There is an increasing need for memory devices with large capacity and high computing speed to store and process large amounts of data. However, in existing processing systems based on the Von Neumann architecture, the data processing unit (e.g., central processing unit) and the data storage unit (e.g., memory) are separated, and the data processing unit receives data from the data storage unit, processes it, and the result is sent to the data storage unit for storage. Data must be frequently transferred between the data processing unit and the data storage unit. In the Von Neumann architecture, the transfer speed between the data processing unit and the data storage unit limits the data storage speed and computing speed, and thus such an architecture has difficulty loading large amounts of data processing.

[0003] It is desirable to provide in the art improved memory structures and methods for operating the same that have large capacity, high computational speed, and high durability. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a memory structure is provided. The memory structure includes a first gate structure, a second gate structure, a third gate structure, a plurality of channel bodies, a plurality of source regions, a plurality of drain regions, and a plurality of first side plugs. The first gate structure, the second gate structure, and the third gate structure are disposed along a first direction and are separated from each other. The plurality of channel bodies are separated from each other and pass through the first gate structure, the second gate structure, and the third gate structure along the first direction. Each of the plurality of channel bodies has a first end and a second end separated from the first end. The plurality of source regions are separated from each other and have a first conductivity type. The plurality of source regions are respectively connected to the first ends of the plurality of channel bodies. The plurality of drain regions are separated from each other and have a second conductivity type. The plurality of drain regions are respectively connected to the second ends of the plurality of channel bodies. The first conductivity type is different from the second conductivity type. The plurality of first side plugs are disposed along the second direction and extend along the third direction. The plurality of first side plugs are separated from one another and electrically connected to the plurality of source regions and the plurality of channel bodies. The first direction, the second direction, and the third direction are orthogonal to one another. The first gate structure includes a plurality of island structures separated from one another. The plurality of island structures are disposed along the second direction and extend along the third direction.

[0005] According to another embodiment of the present disclosure, a method for operating a memory structure is provided, the method including a forward propagation step and a reverse propagation step. The forward propagation step includes inputting a plurality of input signals to a plurality of memory cells of the memory structure via a plurality of bit lines; generating a plurality of cell currents by the plurality of memory cells for a plurality of source lines based on a plurality of weights stored in the plurality of memory cells; calculating a sum of the plurality of cell currents of each source line to obtain a plurality of source line currents; and converting the plurality of source line currents into an output signal. The reverse propagation step includes inputting a plurality of error input signals to the plurality of memory cells of the memory structure via a plurality of word lines; generating a plurality of error cell currents by the plurality of memory cells for the plurality of bit lines based on the plurality of error input signals; calculating a sum of the plurality of error cell currents of each bit line to obtain a plurality of error bit line currents; converting the plurality of error bit line currents into an error output signal; and updating the plurality of weights of the plurality of memory cells based on the error output signal.

[0006] According to another embodiment of the present disclosure, a method for operating a memory structure is provided, the method including a forward propagation step including: inputting a plurality of first input signals to a first memory cell array of the memory structure via a plurality of first bit lines; generating a plurality of first cell currents by the first memory cell array for a plurality of first source lines based on a plurality of first weights stored in the first memory cell array; calculating a sum of the plurality of first cell currents of each first source line to generate a plurality of first source line currents; inputting a plurality of second input signals to a second memory cell array of the memory structure via a plurality of second bit lines; generating a plurality of second cell currents by the second memory cell array for a plurality of second source lines based on a plurality of second weights stored in the second memory cell array; calculating a sum of the plurality of second cell currents of each second source line to obtain a plurality of second source line currents; and converting the plurality of first source line currents and the plurality of second source line currents into an output signal. The plurality of first weights are positive weights and the plurality of second weights are negative weights.

[0007] These and other embodiments of the present disclosure will be better understood with respect to the following detailed description of non-limiting embodiments, the following description being made with reference to the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] 1 shows a schematic diagram of a memory structure according to one embodiment of the present disclosure.

[0009] [Diagram 2] The results of operating the memory structure shown in FIG. 1 are shown.

[0010] [Diagram 3] 1 illustrates an equivalent circuit diagram of a memory structure according to one embodiment of the present disclosure.

[0011] [Figure 4]The results of operating the memory structure shown in FIG. 1 are shown. [Diagram 5] The results of operating the memory structure shown in FIG. 1 are shown. [Figure 6] The results of operating the memory structure shown in FIG. 1 are shown.

[0012] [Figure 7] 1 illustrates an equivalent circuit diagram of a memory structure according to one embodiment of the present disclosure.

[0013] [Figure 8] 1 illustrates an equivalent circuit diagram of a memory structure according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Various embodiments are described more fully below with reference to the accompanying drawings, which are provided for purposes of illustration and description, and not for purposes of limitation. For clarity, elements may not be drawn to scale. Additionally, some elements and / or reference numbers may be omitted from some of the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0015] The embodiments of the present disclosure may be applied to various types of three-dimensional stacked semiconductor devices, including, but not limited to, a semiconductor device including stacked chips or a semiconductor package including stacked chips.

[0016] The present disclosure provides a three-dimensional memory structure that includes three transistors (3T).

[0017] Please refer to FIG. 1. FIG. 1 shows a schematic diagram of a memory structure 10 according to an embodiment of the present disclosure. In this embodiment, the X direction may represent a first direction, the Y direction may represent a second direction, and the Z direction may represent a third direction. The first direction, the second direction, and the third direction are orthogonal to each other. The memory structure 10 includes a first gate structure 112, a second gate structure 114, a third gate structure 116, a plurality of channel bodies 120, a plurality of source regions 101, a plurality of drain regions 102, a plurality of dielectric films 122, a plurality of first side plugs 131, a plurality of second side plugs 132, and a plurality of side pads 133.

[0018] The first gate structure 112, the second gate structure 114, and the third gate structure 116 are arranged along the X direction (e.g., the first direction) and are separated from each other. The first gate structure 112, the second gate structure 114, and the third gate structure 116 may extend in a plane defined by the Y direction (e.g., the second direction) and the Z direction (e.g., the third direction). The second gate structure 114 is between the first gate structure 112 and the third gate structure 116. The first gate structure 112 includes a first island structure 1121, a second island structure 1122, and a third island structure 1123 arranged along the Y direction (e.g., the second direction) and separated from each other. The first island structure 1121, the second island structure 1122, and the third island structure 1123 may extend along the Z direction (e.g., the third direction). The third gate structure 116 includes a fourth island structure 1161, a fifth island structure 1162, and a sixth island structure 1163 arranged along the Y direction (e.g., the second direction) and separated from each other. The fourth island structure 1161, the fifth island structure 1162, and the sixth island structure 1163 may extend along the Z direction (e.g., the third direction). The first island structure 1121, the second island structure 1122, the third island structure 1123, the fourth island structure 1161, the fifth island structure 1162, and the sixth island structure 1163 are independently controllable. In one embodiment, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may include a semiconductor material or a metal material. For example, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may comprise monocrystalline silicon, or polycrystalline silicon, or a metal.

[0019] The channel bodies 120 are separated from each other. Each channel body 120 extends along the X direction (e.g., a first direction) and passes through the first gate structure 112, the second gate structure 114, and the third gate structure 116. Each channel body 120 has a first end 120a and a second end 120b separated from the first end 120a. The first end 120a of the channel body 120 and the second end 120b of the channel body 120 are respectively at two opposite end portions of the channel body 120 along the X direction (e.g., the first direction). The channel body 120 includes a first group of channel bodies, a second group of channel bodies, and a third group of channel bodies arranged along the Y direction (e.g., a second direction). The second group of channel bodies is between the first group of channel bodies and the third group of channel bodies.

[0020] The first group of channel bodies includes a plurality of channel bodies 120 arranged along the Z direction (e.g., the third direction) and arranged at different levels (in the embodiment shown in FIG. 1, the first group of channel bodies includes four channel bodies, but the disclosure is not limited thereto). The first group of channel bodies passes through the first island structure 1121 of the first gate structure 112, the second gate structure 114, and the fourth island structure 1161 of the third gate structure 116. The second group of channel bodies includes a plurality of channel bodies 120 arranged along the Z direction (e.g., the third direction) and arranged at different levels (in the embodiment shown in FIG. 1, the second group of channel bodies includes four channel bodies, but the disclosure is not limited thereto). The second group of channel bodies passes through the second island structure 1122 of the first gate structure 112, the second gate structure 114, and the fifth island structure 1162 of the third gate structure 116. The third group of channel bodies includes a plurality of channel bodies 120 arranged along the Z direction (e.g., a third direction) and arranged at different levels (in the embodiment shown in FIG. 1, the third group of channel bodies includes four channel bodies, but the present disclosure is not limited thereto). The third group of channel bodies passes through the third island structure 1123 of the first gate structure 112, the second gate structure 114, and the sixth island structure 1163 of the third gate structure 116.

[0021] A dielectric film 122 is between the first gate structure 112 and the channel body 120, between the second gate structure 114 and the channel body 120, and between the third gate structure 116 and the channel body 120. The dielectric film 122 may be on an outer surface of the channel body 120. The dielectric film 122 surrounds the channel body 120. In one embodiment, the first gate structure 112 is electrically insulated from the channel body 120 by the dielectric film 122, the second gate structure 114 is electrically insulated from the channel body 120 by the dielectric film 122, and the third gate structure 116 is electrically insulated from the channel body 120 by the dielectric film 122. In one embodiment, the dielectric films surrounding the different channel bodies 120 are connected to each other and cover the first gate structure 112, the second gate structure 114, and the third gate structure 116. In one embodiment, the channel body 120 can be formed by an epitaxial growth process. In one embodiment, the channel body 120 may include a semiconductor material such as single crystal silicon. During operation of the memory structure 10 (e.g., during a programming or erasing operation), the channel body 120 may be used to store carriers (e.g., electrons or holes). The dielectric film 122 does not need to have the function of storing carriers (e.g., electrons or holes). The dielectric film 122 may not include a charge storage structure, such as an oxide-nitride-oxide (ONO) structure. In other words, there may be no ONO structure between the channel body 120 and the gate structures (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116). In one embodiment, the dielectric film 122 may include a dielectric material such as an oxide. In one embodiment, the dielectric film 122 may be a single layer structure. In one embodiment, the dielectric film 122 may include a material with a high dielectric constant (high-k material).

[0022] In this embodiment, the first gate structure 112, the second gate structure 114, and the third gate structure 116 surround the dielectric film 122 and the respective channel bodies 120, so that the memory structure 10 may be understood as a gate-all-around (GAA) structure. Each channel body 120 may be controlled by three gates (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116). The channel bodies 120 of the first group of channel bodies may be controlled by a first island structure 1121 of the first gate structure 112, a second gate structure 114, and a fourth island structure 1161 of the third gate structure 116. The channel bodies 120 of the second group of channel bodies may be controlled by the second island structure 1122 of the first gate structure 112, the second gate structure 114, and the fifth island structure 1162 of the third gate structure 116. The channel bodies 120 of the third group of channel bodies may be controlled by the third island structure 1123 of the first gate structure 112, the second gate structure 114, and the sixth island structure 1163 of the third gate structure 116. At each intersection of the channel bodies 120 and the gate structures, a transistor is formed.

[0023] The source regions 101 are separated from each other. Each source region 101 extends along an X-direction (e.g., a first direction). The source regions 101 may be connected to a first end 120a of the channel body 120. The drain regions 102 are separated from each other. Each drain region 102 extends along an X-direction (e.g., a first direction). The drain regions 102 may be connected to a second end 120b of the channel body 120. Each channel body 120 may be connected to a corresponding source region 101 at the first end 120a and to a corresponding drain region 102 at the second end 120b. In one embodiment, the source region 101 and the drain region 102 may include a semiconductor material, such as single crystal silicon. The source region 101 may have a first conductivity type. The drain region 102 may have a second conductivity type. The first conductivity type is different from the second conductivity type. In one embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type. In one embodiment, the source region 101 may be heavily doped N-type (N+) and the drain region 102 may be heavily doped P-type (P+).

[0024] The first side plugs 131 are arranged along a Y direction (e.g., a second direction) and are separated from each other. Each of the first side plugs 131 extends along a Z direction (e.g., a third direction). The first side plugs 131 and the first gate structure 112 are at both ends of the source region 101 along the X direction. The first side plugs 131 may be electrically connected to the source region 101 and the channel body 120. One of the first side plugs 131 may be electrically connected to a first group of channel bodies and a source region 101 corresponding to the first group of channel bodies, another one of the first side plugs 131 may be electrically connected to a second group of channel bodies and a source region 101 corresponding to the second group of channel bodies, and another one of the first side plugs 131 may be electrically connected to a third group of channel bodies and a source region 101 corresponding to the third group of channel bodies.

[0025] The second side plugs 132 are arranged along the Y direction (e.g., the second direction) and are separated from each other. Each of the second side plugs 132 extends along the Z direction (e.g., the third direction). The second side plugs 132 and the third gate structure 116 are at both ends of the drain region 102 along the X direction. The side pads 133 are arranged along the Z direction (e.g., the third direction) and are separated from each other. The side pads 133 are at different levels. The side pads 133 are electrically connected to the drain region 102. The second side plugs 132 may be electrically connected to the side pads 133 at different levels. For example, in this embodiment, one of the second side plugs 132 (e.g., the shortest second side plug 132 in FIG. 1 ) is electrically connected to the drain region 102 at the top level and the channel body 120 at the top level through one of the side pads 133 (e.g., the side pad 133 at the top level in FIG. 1 ); one of the second side plugs 132 (e.g., the longest second side plug 132 in FIG. 1 ) is electrically connected to the drain region 102 at the bottom level and the channel body 120 at the bottom level through one of the side pads 133 (e.g., the side pad 133 at the bottom level in FIG. 1 ); the other second side plugs 132 are similarly electrically connected to the other side pads 133. In this embodiment, the side pads 133 may form a staircase structure, but the present disclosure is not limited thereto. In an embodiment, the first side plug 131, the second side plug 132, and the side pads 133 may include a semiconductor material or a metal material. For example, the first side plug 131, the second side plug 132, and the side pad 133 may include single crystal silicon, or polycrystalline silicon, or a metal.

[0026] The memory structure 10 may include an upper conductive structure 140 on the channel body 120. The upper conductive structure 140 includes a contact 1401 on the first gate structure 112, a first conductive layer 1411 (e.g., metal layer ML1) on the contact 1401, a via 1421 on the first conductive layer 1411, and a second conductive layer 1431 (e.g., metal layer ML2) on the via 1421. The first gate structure 112, the contact 1401, the first conductive layer 1411, the via 1421, and the second conductive layer 1431 are electrically connected to each other. The upper conductive structure 140 includes a contact 1402 on the second gate structure 114, and a first conductive layer 1412 (e.g., metal layer ML1) on the contact 1402. The second gate structure 114, the contact 1402, and the first conductive layer 1412 are electrically connected to each other. The upper conductive structure 140 includes a contact 1403 on the third gate structure 116, a first conductor layer 1413 (e.g., metal layer ML1) on the contact 1403, a via 1423 on the first conductor layer 1413, and a second conductor layer 1433 (e.g., metal layer ML2) on the via 1423. The third gate structure 116, the contact 1403, the first conductor layer 1413, the via 1423, and the second conductor layer 1433 are electrically connected to each other.

[0027] The upper conductive structure 140 includes a contact 1404 on the first side plug 131, a via 1424 on the contact 1404, a via 1434 on the via 1424, and a third conductive layer 1444 (e.g., metal layer ML3) on the via 1434. The first side plug 131, the via 1424, the via 1434, and the third conductive layer 1444 are electrically connected to each other. The upper conductive structure 140 includes a contact 1405 on the second side plug 132, a via 1425 on the contact 1405, a via 1435 on the via 1425, and a third conductive layer 1445 (e.g., metal layer ML3) on the via 1435. The second side plug 132, the via 1425, the via 1435, and the third conductive layer 1445 are electrically connected to each other. In one embodiment, contacts 1401, 1402, 1403, 1404, and 1405, first conductor layers 1411, 1412, and 1413, vias 1421, 1423, 1424, 1425, 1434, and 1435, second conductor layers 1431 and 1433, and third conductor layers 1444 and 1445 may include semiconductor materials and metal materials.

[0028] In one embodiment, the memory structure 10 may include insulating materials. For example, the insulating materials may include insulating materials between the first gate structure 112, the second gate structure 114, and the third gate structure 116, insulating materials between the first island structure 1121, the second island structure 1122, and the third island structure 1123, insulating materials between the fourth island structure 1161, the fifth island structure 1162, and the sixth island structure 1163, insulating materials between the first side plugs 131, insulating materials between the second side plugs 132, and insulating materials between the side pads 133.

[0029] In one embodiment, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may each function as a word line (WL). In one embodiment, a transistor formed at each intersection of the first gate structure 112 including the island structure and the channel body 120 may function as a string select transistor; a transistor formed at each intersection of the third gate structure 116 including the island structure and the channel body 120 may function as a string select transistor. In one embodiment, the memory structure 10 may include a plurality of source lines (SL) and a plurality of bit lines (BL) that are orthogonal to each other. For example, the source lines may extend along the Z direction and the bit lines may extend along the Y direction; the present disclosure is not limited thereto. The source lines may be electrically connected to the source region 101 through a first side plug 131. The bit lines may be electrically connected to the drain region 102 through a second side plug 132. In this embodiment, each channel body 120 and the corresponding source region 101 and drain region 102 of the channel body 120 may function as a thyristor. In one embodiment, the memory structure of the present disclosure may function as a dynamic random access memory (DRAM) having a three-dimensional structure, and the operating mechanism of the memory structure is based on a thyristor. In one embodiment, the bit lines and source lines are orthogonal to each other, so that the memory structure can perform multiply-accumulate operations.

[0030] In one embodiment, the memory structure 10 may be formed by a stacked gate-all-around nanosheet CMOS process. The memory structure 10 with a lateral channel (i.e., the channel body 120) may have more layers of the channel body 120 stacked along the Z direction, so that more bits can be formed, and the memory structure 10 with a lateral channel may have a higher density of memory cells, which is more beneficial to the miniaturization of the memory structure. In one embodiment, the memory structure 10 may have more channel bodies 120 arranged along the Y direction, and the first gate structure and the third gate structure may include more island structures, so that more bits can be formed, and the memory structure 10 with a lateral channel may have a higher density of memory cells, which is more beneficial to the miniaturization of the memory structure.

[0031] Please refer to FIG. 2. FIG. 2 shows the results of operating the memory structure 10 shown in FIG. 1. The X-axis shows the bit line bias voltage (V BL ) in volts (V); the Y-axis represents the bit line current (I BL ) in amperes (A). The dotted curve represents a programming operation of the memory structure 10 in which the memory cells of the memory structure 10 are programmed to a data state of "1" (i.e., logic "1"). The solid curve represents an erasing operation of the memory structure 10 in which the memory cells of the memory structure 10 are programmed to a data state of "0" (i.e., logic "0"). The distance between the solid curve and the dotted curve under the same bit line bias voltage represents the ratio of the currents in the on state and the off state (on / off ratio). As shown in FIG. 2, when the bit line bias voltage is 1.8V, the memory structure 10 of the present disclosure has a current of 10 6 It has a larger on / off ratio R, which means that the on and off states of the memory structure 10 are easier to distinguish, and the memory structure 10 has a larger memory window.

[0032] Please refer to Figures 1 and 3. Figure 3 shows an equivalent circuit diagram of a memory structure 10 according to one embodiment of the present disclosure. Figure 3 shows a schematic diagram of four adjacent channel bodies 120 of Figure 1, for example, four channel bodies 120 passing through a first island structure 1121 and a second island structure 1122 of the first gate structure 112, a second gate structure 114, and a fourth island structure 1161 and a fifth island structure 1162 of the third gate structure 116.

[0033] The transistors T1 and T11 are formed at different levels at the intersection of the first island structure 1121 and the channel body 120. The transistors T4 and T41 are formed at different levels at the intersection of the second island structure 1122 and the channel body 120. The transistors T2, T21, T5, and T51 are formed at the intersection of the second gate structure 114 and the four channel bodies 120. The transistors T3 and T31 are formed at different levels at the intersection of the fourth island structure 1161 and the channel body 120. The transistors T6 and T61 are formed at different levels at the intersection of the fifth island structure 1162 and the channel body 120. The transistors T1, T2, and T3 are formed by the same channel body 120. The transistors T1, T2, and T3 together form a memory cell CA. The transistors T4, T5, and T6 are formed by the same channel body 120. The transistors T4, T5, and T6 together form a memory cell CC. The transistors T11, T21, and T31 are formed by the same channel body 120. The transistors T11, T21, and T31 together form a memory cell CB. The transistors T41, T51, and T61 are formed by the same channel body 120. The transistors T41, T51, and T61 together form a memory cell CD. The transistors T1, T2, and T3 (memory cells CA) are electrically connected to the source line SL1 and the bit line BL1. The transistors T4, T5, and T6 (memory cells CC) are electrically connected to the source line SL2 and the bit line BL1. The transistors T11, T21, and T31 (memory cells CB) are electrically connected to the source line SL1 and the bit line BL2. The transistors T41, T51, and T61 (memory cells CD) are electrically connected to a source line SL2 and a bit line BL2.

[0034] In one embodiment, a method for operating a memory structure according to the present disclosure includes a matrix multiplication operation. For example, when the matrix multiplication operation is performed in the memory structure 10, a plurality of input signals can be input to a plurality of memory cells via a plurality of bit lines electrically connected to the memory cells; the memory cells can generate a plurality of cell currents to a plurality of source lines based on a plurality of weights stored in the memory cells and the input signals. For example, the input signals can be converted to corresponding voltages via a conversion unit, or the input signals are in the form of voltages, and a multiplication operation is performed in the memory cells based on the voltages (or input signals) and the weights to obtain the cell currents. In this embodiment, the weights stored in the memory cells can be understood as the conductance of the memory cells, and the product of the weights and the voltages is output as a current. The source line currents output from the respective source lines can be obtained by summing the cell currents of the respective source lines. The obtained source line currents are the results of the operation. In one embodiment, the obtained source line currents can be converted to output signals.

[0035] For example, in the equivalent circuit diagram shown in Figure 3, the weight w CA is stored in memory cell CA, and weight w CC is stored in memory cell CC, and weight w CB is stored in memory cell CB, and weight w CD is stored in the memory cell CD; the input signal V in the form of a voltage BL1 is input to the memory cells CA and CC via the bit line BL1, and an input signal V BL2 is input to the memory cells CB and CD via the bit line BL2; the memory cell CA generates a cell current V based on the weight stored in the memory cell CA and the input signal. BL1 ×w CA to the source line SL1; the memory cell CC generates a cell current V BL1 ×w CC to the source line SL2; the memory cell CB generates a cell current VBL2 ×w CB to the source line SL1; the memory cell CD generates a cell current V BL2 ×w CD is generated for the source line SL2. The source line current I SL1 and the source line current I SL2 can be expressed by the following equations (1) and (2): In this way, the matrix multiplication operation is realized.

number

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[0036] In one embodiment, a method for operating a memory structure according to the present disclosure includes a forward propagation phase and / or a reverse propagation phase. The forward propagation phase includes: A plurality of input signals are input to a plurality of memory cells via a plurality of bit lines electrically connected to the memory cells (the bit lines are at the same potential as the drain regions); the input signals can be converted to corresponding voltages or are in the form of voltages; based on the plurality of weights stored in the memory cells and the input signals, the memory cells generate a plurality of cell currents for a plurality of source lines (at the same potential as the source regions); the sum of the cell currents of each source line is calculated to obtain a source line current; the source line currents are converted to an output signal. During the forward propagation phase, a positive voltage of the input signal corresponding to a positive voltage can be applied to the bit lines, and the source lines can be grounded. During the forward propagation phase, the cell current input from each memory cell can be the product of the corresponding cell current (or may be understood as the corresponding voltage applied to the memory cell) and the corresponding weight (the weight stored in the memory cell). The reverse propagation phase includes: A plurality of error input signals are input to the memory cell through a plurality of word lines electrically connected to the first gate structure; the error input signals can be converted to corresponding error voltages or the error input signals are in the form of voltages; based on the error input signals, the memory cell generates a plurality of error cell currents to the bit lines; the sum of the error cell currents of the respective bit lines is calculated to obtain a plurality of error bit line currents; the error bit line currents are converted to error output signals; the weights stored in the memory cell are updated based on the error output signals. During the reverse propagation phase, the source line can be grounded, a voltage between -1V and 2V is applied to the word lines electrically connected to the first gate structure, and a positive voltage is applied to the bit lines. The above phase of reverse propagation can obtain the correct current direction and reduce or avoid the body effect.

[0037] In one embodiment, the forward propagation and back propagation steps can be used to train a neural network.

[0038] One of the forward propagation steps applicable to the memory structure of the present disclosure and one of the backward propagation steps applicable to the memory structure of the present disclosure are described below with reference to Figures 1 and 4-6, although the present disclosure is not limited thereto.

[0039] 4-5 are diagrams showing the relationship between bit line current and bit line bias voltage obtained by performing a forward propagation step in the memory structure 10 shown in FIG. 1. In FIG. 4, the X-axis represents the bit line bias voltage in volts (v); the Y-axis represents the bit line current in microamperes (μA). In FIG. 5, the X-axis represents the bit line bias voltage in volts (v); the Y-axis represents the bit line current in amperes (A). In this embodiment, the voltage applied to the second gate structure 114 and the third gate structure 116 is 3V, the voltage applied to the first gate structure 112 is −1V, the voltage applied to the source line (equal to the source region 101) is 0V (ground), and the voltage applied to the bit line (equal to the drain region 102) is 0V-2V. 4-5, the bitline current increases exponentially as the bitline bias voltage increases due to the presence of PN diodes in memory structure 10. As shown in Figures 4-5, suitable bitline bias voltages for the forward propagation phase can range from 1V (corresponding to a bitline current of 100 nanoamps (nA)) to 2V (corresponding to a bitline current of 10 microamps (μA)).

[0040] FIG. 6 is a diagram showing the relationship between the bit line current and the first gate bias voltage (the voltage applied to the first gate structure) obtained by performing the reverse propagation step in the memory structure 10 shown in FIG. 1. In FIG. 6, the X-axis represents the first gate bias voltage in volts (v); the Y-axis represents the bit line current in microamperes (μA). In this embodiment, the voltage applied to the second gate structure 114 and the third gate structure 116 is 3V, the voltage applied to the bit line (equal to the drain region 102) is 1.2V, the voltage applied to the source line (equal to the source region 101) is 0V (ground), and the voltage applied to the first gate structure 112 is −2V to 2V. As shown in FIG. 6, as the first gate bias voltage increases, the bit line current increases linearly. As shown in FIG. 6, the first gate bias voltage suitable for the reverse propagation step can be in the range of −1V to 2V.

[0041] In one embodiment, a method for operating a memory structure according to the present disclosure includes storing positive and negative weights in different memory cell arrays of the memory structure, and then performing a forward propagation step and / or a backward propagation step. One of the operating methods applicable to the memory structure of the present disclosure is described below with reference to Figures 7-8. The present disclosure is not limited thereto. Figures 7-8 show an equivalent circuit diagram of a memory structure 20 according to an embodiment of the present disclosure. The memory structure 20 may have a structure similar to the memory structure 10 shown in Figure 1.

[0042] The memory structure 20 includes a first memory cell array R1 and a second memory cell array R2. The first memory cell array R1 and the second memory cell array R2 include different memory cells. In the first memory cell array R1, transistors TP1, TP4, TP7, and TP10 are formed at the intersections of two island structures and four channel bodies of a first gate structure, transistors TP2, TP5, TP8, and TP11 are formed at the intersections of two island structures and four channel bodies of a second gate structure, and transistors TP3, TP6, TP9, and TP12 are formed at the intersections of two island structures and four channel bodies of a third gate structure. The transistors TP1, TP2, and TP3 are formed by the same channel body. The transistors TP1, TP2, and TP3 together form a memory cell CP33. The transistors TP4, TP5, and TP6 are formed by the same channel body. The transistors TP4, TP5, and TP6 together form a memory cell CP34. The transistors TP7, TP8, and TP9 are formed by the same channel body. The transistors TP7, TP8, and TP9 together form a memory cell CP43. The transistors TP10, TP11, and TP12 are formed by the same channel body. The transistors TP10, TP11, and TP12 together form a memory cell CP44. The memory cell CP33 is electrically connected to the bit line BL3 and the source line SL3. The memory cell CP34 is electrically connected to the bit line BL3 and the source line SL4. The memory cell CP43 is electrically connected to the bit line BL4 and the source line SL3. The memory cell CP44 is electrically connected to the bit line BL4 and the source line SL4.In the second memory cell array R2, transistors TN1, TN4, TN7, and TN10 are formed at the intersections of two island structures and four channel bodies of the first gate structure, transistors TN2, TN5, TN8, and TN11 are formed at the intersections of two island structures and four channel bodies of the second gate structure, and transistors TN3, TN6, TN9, and TN12 are formed at the intersections of two island structures and four channel bodies of the third gate structure. The transistors TN1, TN2, and TN3 are formed by the same channel body. The transistors TN1, TN2, and TN3 together form a memory cell CN35. The transistors TN4, TN5, and TN6 are formed by the same channel body. The transistors TN4, TN5, and TN6 together form a memory cell CN36. The transistors TN7, TN8, and TN9 are formed by the same channel body. The transistors TN7, TN8, and TN9 together form a memory cell CN45. The transistors TN10, TN11, and TN12 are formed by the same channel body. The transistors TN10, TN11, and TN12 together form a memory cell CN46. The memory cell CN35 is electrically connected to a bit line BL5 and a source line SL5. The memory cell CN36 is electrically connected to a bit line BL5 and a source line SL6. The memory cell CN45 is electrically connected to a bit line BL6 and a source line SL5. The memory cell CN46 is electrically connected to a bit line BL6 and a source line SL6.

[0043] In the memory structure 20, the weight w 33 , w 34 , w 43 , and w 44 (e.g., a first weight) is stored in memory cells CP33, CP34, CP43, and CP44, respectively, and weights w 33 , w 34 , w 43 , and w 44 is a positive weight. In the memory structure 20, the weights w 35 , w36 , w 45 , and w 46 (e.g., second weights) are stored in memory cells CN35, CN36, CN45, and CN46, respectively, and weights w 35 , w 36 , w 45 , and w 46 are negative weights.

[0044] The method of operation may include performing a forward propagation step in the memory structure 20, which includes the steps of: BL3 and V BL4 (e.g., a first input signal) is input to the first memory cell array R1 via bit lines BL3 and BL4 (e.g., first bit lines). The input signal V BL5 and V BL6 (e.g., a second input signal) is input to the second memory cell array R2 via bit lines BL5 and BL6 (e.g., second bit lines). BL3 and the input signal V BL5 can be the same as the input signal V BL4 and the input signal V BL6 The weights w stored in the first memory cell array R1 can be the same. 33 , w 34 , w 43 , and w 44 Based on the weights (e.g., first weights) and the input signal, a multiplication operation is performed in the memory cells CP33 and CP43 of the first memory cell array R1 to generate a corresponding first cell current for the source line SL3 (e.g., first source line), and a multiplication operation is performed in the memory cells CP34 and CP44 of the first memory cell array R1 to generate a corresponding first cell current for the source line SL4 (e.g., first source line). The first cell currents of the source lines SL3 and SL4 are summed to generate a first source line current O1. + and O2 + The weights w stored in the second memory cell array R2 are obtained. 35 , w 36 , w 45 , and w 46Based on the weights (e.g., second weights) and the input signal, a multiplication operation is performed in the memory cells CN35 and CN45 of the second memory cell array R2 to generate a corresponding second cell current for the source line SL5 (e.g., second source line), and a multiplication operation is performed in the memory cells CN36 and CN46 of the second memory cell array R2 to generate a corresponding second cell current for the source line SL6 (e.g., second source line). The second cell currents of the source lines SL5 and SL6 are summed to generate a second source line current O1. - and O2 - The first source line current O1 is obtained. + and O2 + , and the second source line current O1 - and O2 - can be converted to an output signal via converter 71 and converter 72. Specifically, the output signal includes a first output signal and a second output signal, and the first output signal is converted to a first source line current O1 via converter 71. + and the second source line current O1 - The second output signal is formed by converting the first source line current O2 through the converter 72. + and the second source line current O2 - The operation in the forward propagation stage can be expressed by the following equation (3):

number

[0045] The method of operation may include performing a reverse propagation step in the memory structure 20, which includes the following steps: Error input signals δ1 and δ2 (e.g., first error input signals) in the form of voltages are input to the first memory cell array R1 via word lines WL1 and WL2 (e.g., first word lines) electrically connected to the first gate structure; Error input signals δ3 and δ4 (e.g., second error input signals) in the form of voltages are input to the second memory cell array R2 via word lines WL3 and WL4 (e.g., second word lines) electrically connected to the first gate structure; The error input signals δ1 and δ3 may be the same; The error input signals δ2 and δ4 may be the same. Based on the weights stored in the first memory cell array R1 and the error input signals δ1 and δ2, the memory cells CP33 and CP34 of the first memory cell array R1 generate corresponding first error cell currents for the bit line BL3, and the memory cells CP43 and CP44 of the first memory cell array R1 generate corresponding first error cell currents for the bit line BL4. The first error bit line current σ1 is generated by summing the first error cell currents for the bit lines BL3 and BL4. + and σ2 + Based on the weights stored in the second memory cell array R2 and the error input signals δ3 and δ4, the memory cells CN35 and CN36 of the second memory cell array R2 generate corresponding second error cell currents for the bit line BL5, and the memory cells CN45 and CN46 of the second memory cell array R2 generate corresponding second error cell currents for the bit line BL6. The second error bit line current σ1 is obtained by summing the second error cell currents for the bit lines BL5 and BL6. - and σ2 - The first error bit line current σ + and σ2 + , and the second error bit line current σ - and σ2 -can be converted to an error output signal via converter 81 and converter 82. Specifically, the error output signal includes a first error output signal and a second error output signal, and the first error output signal is converted to a first error bit line current σ1 via converter 81. + and the second error bit line current σ - The second error output signal is formed by converting the first error bit line current σ2 through converter 82. + and the second error bit line current σ - The operation in the backpropagation stage can be expressed by the following equation (4):

number

[0046] The operation method is as follows: 33 , w 34 , w 43 , and w 44 (for example, the first weight), and the weight w 35 , w 36 , w 45 , and w 46 This may include updating the second weight (e.g., the second weight).

[0047] In the comparative example, the positive weights and the negative weights are stored in the same memory cell array. Compared with the comparative example, the present disclosure stores the positive weights and the negative weights in different memory cell arrays, which can avoid the problem that the weight matrix of the forward propagation stage and the weight matrix of the backward propagation stage cannot be transposed to each other.

[0048] In one embodiment, a method for operating a memory structure according to the present disclosure includes using a shifter and an adder to increase the number of bits stored in each memory cell from a single bit (i.e., a single memory cell can be programmed to a logic "1" or logic "0") to multiple bits. Thus, the weight stored in each memory cell can be increased from a single level to multiple levels.

[0049] According to the above-mentioned embodiment, the memory structure of the present disclosure includes memory cells electrically connected to different source lines (e.g., the memory cells are electrically connected to different source lines separated from each other through the first side plug 131); such a configuration allows the output value of each source line to be calculated separately, allowing the memory structure of the present disclosure to perform matrix multiplication operations, thus allowing the memory structure of the present disclosure to be applied in the field of neural devices or artificial intelligence (AI). The memory structure of the present disclosure and the method for operating the memory structure can perform computing-in-memory operations and does not need to transfer data between a data processing unit and a data storage unit, thus the memory structure of the present disclosure and the method for operating the memory structure can significantly improve the operation speed and the ability to process a large amount of data compared with the Von Neumann architecture. The present disclosure provides a DRAM having a three-dimensional structure capable of performing computing-in-memory operations, and the operating mechanism of the memory structure is based on thyristors, thereby exhibiting the characteristics of large capacity, high storage density, high scalability, high durability, long data retention time, and fast operation speed. Furthermore, due to the above characteristics, the present disclosure is applicable to artificial intelligence training involving large-scale data calculation, which can solve the problems of insufficient memory capacity and transmission bandwidth in artificial intelligence training, and greatly improve the efficiency of artificial intelligence training.

[0050] It should be noted that the above-mentioned elements and methods are provided for illustration. The present disclosure is not limited to the configurations and procedures disclosed above. Other embodiments with different configurations of known elements are applicable, and the illustrated elements can be adjusted and changed based on the actual needs of practical applications. Of course, it should be noted that the configurations in the figures are drawn for illustration only, and not for limitation. Therefore, it is known to those skilled in the art that the relevant elements and layers in a semiconductor device, the shape or positional relationship of the elements, and the details of the procedures can be adjusted or changed according to the actual requirements and / or manufacturing stages of practical applications.

[0051] While the present disclosure has been described by way of example and in terms of exemplary embodiments, it is to be understood that the disclosure is not limited thereto, but is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims should therefore be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. (Other possible items) [Item 1] a first gate structure, a second gate structure, and a third gate structure disposed along a first direction and spaced apart from one another; a plurality of channel bodies spaced apart from one another and passing through the first gate structure, the second gate structure, and the third gate structure along the first direction, each of the plurality of channel bodies having a first end and a second end spaced apart from the first end; a plurality of source regions separated from one another and having a first conductivity type, wherein the plurality of source regions are respectively connected to the first ends of the plurality of channel bodies; a plurality of drain regions separated from one another and having a second conductivity type, where the plurality of drain regions are respectively connected to the second ends of the plurality of channel bodies, and the first conductivity type is different from the second conductivity type; and a plurality of first side plugs disposed along a second direction and extending along a third direction, wherein the plurality of first side plugs are separated from one another and electrically connected to the plurality of source regions and the plurality of channel bodies, and the first direction, the second direction, and the third direction are orthogonal to one another; Equipped with The first gate structure has a plurality of island structures separated from one another, the plurality of island structures being arranged along the second direction and extending along the third direction. Memory structures. [Item 2] 2. The memory structure of claim 1, further comprising a plurality of second side plugs arranged along the second direction and extending along the third direction, the plurality of second side plugs being separated from one another and electrically connected to the plurality of drain regions and the plurality of channel bodies. [Item 3] a plurality of source lines electrically connected to the plurality of source regions through the plurality of first side plugs; and a plurality of bit lines electrically connected to the plurality of drain regions via the plurality of second side plugs; 3. The memory structure of claim 2, further comprising: wherein the source lines and the bit lines are orthogonal to one another. [Item 4] 2. The memory structure of claim 1, further comprising a plurality of side pads arranged along the third direction and separated from one another, the plurality of side pads connected to the plurality of drain regions. [Item 5] 5. The memory structure of any one of items 1 to 4, wherein the first conductivity type is N-type and the second conductivity type is P-type. [Item 6] applying a plurality of input signals to a plurality of memory cells in the memory structure via a plurality of bit lines; generating a plurality of cell currents to a plurality of source lines by the plurality of memory cells based on a plurality of weights stored in the plurality of memory cells; calculating a sum of the plurality of cell currents on each source line to generate a plurality of source line currents; and converting the plurality of source line currents into output signals. a forward propagation stage having applying a plurality of error input signals via a plurality of word lines to the plurality of memory cells in the memory structure; generating, by the plurality of memory cells, a plurality of error cell currents on the plurality of bit lines based on the plurality of error input signals; calculating a sum of the plurality of error cell currents on each bit line to obtain a plurality of error bit line currents; converting the plurality of error bit line currents into an error output signal; and updating the weights in the memory cells based on the error output signal. A backpropagation stage having 16. A method for operating a memory structure comprising: [Item 7] 7. The method of claim 6, wherein during the reverse propagation step, the plurality of source lines are grounded. [Item 8] 7. The method of claim 6, wherein a voltage between -1V and 2V is applied to the word lines during the reverse propagation phase. [Item 9] 7. The method of claim 6, wherein a positive voltage is applied to the bit lines during the reverse propagation phase. [Item 10] 7. The method of claim 6, wherein during the forward propagation phase, a positive voltage is applied to the bit lines and the source lines are grounded. [Item 11] 7. The method of claim 6, wherein the memory structure is a dynamic random access memory (DRAM). [Item 12] 7. The method of claim 6, wherein the operating mechanism of the memory structure is based on thyristors. [Item 13] 13. The method of any one of items 6 to 12, wherein during the forward propagation stage, each memory cell performs a multiplication operation based on a corresponding input signal and a corresponding weight to generate a corresponding cell current. [Item 14] inputting a plurality of first input signals to a first array of memory cells of the memory structure via a plurality of first bit lines; generating, by the first memory cell array, a plurality of first cell currents to a plurality of first source lines based on a plurality of first weights stored in the first memory cell array; calculating a sum of the plurality of first cell currents on respective first source lines to generate a plurality of first source line currents; inputting a plurality of second input signals to a second array of memory cells in the memory structure via a plurality of second bit lines; generating, by the second memory cell array, a plurality of second cell currents to a plurality of second source lines based on a plurality of second weights stored in the second memory cell array; calculating a sum of the plurality of second cell currents on each second source line to obtain a plurality of second source line currents; and Converting the plurality of first source line currents and the plurality of second source line currents into an output signal. A forward propagation stage having wherein the plurality of first weights are positive weights and the plurality of second weights are negative weights. [Item 15] 15. The method of claim 14, wherein the output signal includes a first output signal and a second output signal, the first output signal being formed by converting a portion of the plurality of first source line currents and a portion of the plurality of second source line currents, and the second output signal being formed by converting another portion of the plurality of first source line currents and another portion of the plurality of second source line currents. [Item 16] Item 15. The method of item 14, wherein the memory structure is a dynamic random access memory. [Item 17] Item 15. The method of item 14, wherein the operating mechanism of the memory structure is based on thyristors. [Item 18] applying a plurality of first error input signals to the first array of memory cells in the memory structure via a plurality of first word lines; generating, by the first memory cell array, a plurality of first error cell currents to the plurality of first bit lines based on the plurality of first error input signals; calculating a sum of the plurality of first error cell currents on each first bit line to obtain a plurality of first error bit line currents; applying a plurality of second error input signals to the second array of memory cells in the memory structure via a plurality of second word lines; generating, by the second memory cell array, a plurality of second error cell currents to the plurality of second bit lines based on the plurality of second error input signals; calculating a sum of the plurality of second error cell currents on each second bit line to obtain a plurality of second error bit line currents; converting the plurality of first error bit line currents and the plurality of second error bit line currents into an error output signal; and updating the plurality of first weights in the first memory cell array and the plurality of second weights in the second memory cell array based on the error output signal. A backpropagation stage having 18. The method of any one of items 14 to 17, further comprising: [Item 19] 20. The method of claim 18, wherein the error output signal includes a first error output signal and a second error output signal, the first error output signal being formed by converting a portion of the plurality of first error bit line currents and a portion of the plurality of second error bit line currents, and the second error output signal being formed by converting another portion of the plurality of first error bit line currents and another portion of the plurality of second error bit line currents. [Item 20] 20. The method of claim 18, wherein the memory structure is a dynamic random access memory and the operating mechanism of the memory structure is based on thyristors.

Claims

1. a first gate structure, a second gate structure, and a third gate structure disposed along a first direction and spaced apart from one another; a plurality of channel bodies separated from one another, each of the plurality of channel bodies passing through the first gate structure, the second gate structure, and the third gate structure along the first direction, each of the plurality of channel bodies having a first end and a second end opposite the first end along the first direction; a plurality of source regions separated from one another and having a first conductivity type, wherein the plurality of source regions are respectively connected to the first ends of the plurality of channel bodies; a plurality of drain regions separated from one another and having a second conductivity type, wherein the plurality of drain regions are respectively connected to the second ends of the plurality of channel bodies, and the first conductivity type is different from the second conductivity type; a plurality of first side plugs disposed along a second direction and extending along a third direction, wherein the plurality of first side plugs are separated from one another and electrically connected to the plurality of source regions and the plurality of channel bodies, and the first direction, the second direction, and the third direction are orthogonal to one another; a plurality of second side plugs separated from one another and electrically connected to the plurality of drain regions and the plurality of channel bodies; a plurality of source lines electrically connected to the plurality of source regions through the plurality of first side plugs; and a plurality of bit lines electrically connected to the plurality of drain regions via the plurality of second side plugs; Equipped with the first gate structure has a plurality of island structures separated from one another, the plurality of island structures being arranged along the second direction and extending along the third direction; the plurality of source lines and the plurality of bit lines are orthogonal to each other; Memory structures.

2. The memory structure of claim 1, wherein the plurality of second side plugs are arranged along the second direction and extend along the third direction.

3. 2. The memory structure of claim 1, further comprising a plurality of side pads disposed along said third direction and spaced apart from one another, said plurality of side pads being connected to said plurality of drain regions.

4. 4. The memory structure of claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type.

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