PIXEL STRUCTURE, ARRAY SUBSTRATE AND MANUFACTURING METHOD

Abstract

The present disclosure provides a pixel structure, an array substrate and a manufacturing method thereof in the field of display technology. The pixel structure includes a gate (611) disposed on a base substrate (1) and a gate insulating layer (62) covering the gate (611), on which a source (613), an active region (612), a drain (614), a first doped region (63) and a sub-electrode metal layer (65) are disposed, and a second doped region (64) disposed on both ends of the upper surface of the active region (612) is connected at one end to the source (613) and at the other end to the drain (614), the doping concentration of the first doped region is smaller than that of the second doped region (64), and each surface is covered with a passivation layer (66) on which a main pixel electrode (41) connected to the drain (614) and a sub-pixel electrode (51) connected to the sub-electrode metal layer (65) are disposed. The present disclosure controls an 8-domain VA display with only one thin film transistor, reducing complexity and manufacturing costs.

Description

[Technical field]

[0001] This disclosure claims priority to a Chinese patent application filed with the China Patent Office on April 29, 2022, application number 202210463909.5, entitled "Pixel structure, array substrate and manufacturing method," the entire contents of which are incorporated herein by reference. The present disclosure relates to the technical field of display technology, and in particular to a pixel structure, an array substrate and a manufacturing method. [Background technology]

[0002] Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) have various common display modes, such as Twisted Nematic (TA) display mode, Vertically Aligned (VA) display mode, Fringe Field Switching (FFS) display mode, and In-Plane Switching (IPS) display mode, where the VA mode has better dark state performance and better contrast compared to other display modes, but its viewing angle is relatively low.

[0003] Currently, the viewing angle of VA display is generally improved by dividing a pixel into a plurality of domains, for example, 8Domain (liquid crystal has eight directions) and 4Domain (liquid crystal has four directions). 4Domain is generally formed by forming slits in the pixel electrode and protrusions on the color film substrate. Liquid crystal molecules have pretilt angles in different directions when no voltage is applied, and after voltage is applied, the liquid crystal layer can be divided into four liquid crystal microdomains each having a different tilt direction. This realizes wide viewing angle display characteristics. 8Domain is generally formed by dividing a pixel into one main subpixel and one subsubpixel based on the above four domains, and the main subpixel and the subsubpixel each have four domains, and the driving voltages of the main subpixel and the subsubpixel are different, so that the liquid crystal rotation angles are different and the liquid crystal rotation angles are not aligned in the same direction when viewed at a wide viewing angle, which has a good effect on the human eye and is effective as a countermeasure against color shift, and can further improve color shift and obtain a wide viewing angle.

[0004] The conventional 8-domain VA display structure needs to be controlled by multiple TFTs, which increases manufacturing costs.

[0005] Therefore, the conventional technical solution for the 8-domain VA display structure requires complex structures and manufacturing processes for multiple TFTs, which increases manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0006] The present disclosure provides a pixel structure, an array substrate and a manufacturing method thereof to solve the problem of the conventional 8-domain VA display structure having multiple TFTs that are complicated in structure and manufacturing, leading to increased manufacturing costs. [Means for solving the problem]

[0007] The technical solutions according to the disclosed embodiments are as follows:

[0008] A first aspect is a pixel structure, A gate provided on an upper surface of a base substrate; a gate insulating layer covering the gate and further covering an upper surface of the base substrate other than the gate; A source, an active region located in an upper region corresponding to the gate, a drain, a first doped region having one end connected to the drain and the other end connected to a sub-electrode metal layer, and the sub-electrode metal layer, are sequentially disposed on the upper surface of the gate insulating layer along a direction parallel to the lateral direction of the base substrate. second doped regions at both ends of a top surface of the active region, the second doped region at one end of the top surface of the active region being connected to the source and the second doped region at the other end of the top surface of the active region being connected to the drain, the doping concentration of the first doped region being less than the doping concentration of the second doped region; and a passivation layer covering the source, the portion of the active area exposed from the second doped region, the second doped region, the drain, the first doped region, and the sub-electrode metal layer, on which a main pixel electrode connected to the drain and a sub-pixel electrode connected to the sub-electrode metal layer are provided.

[0009] In one embodiment, the first doped region includes a first highly doped region and a first lightly doped region; The first heavily doped region is arranged at both ends of the first lightly doped region in a direction parallel to the lateral direction of the base substrate, the first heavily doped region arranged at one end of the first lightly doped region is connected to the drain, and the first heavily doped region arranged at the other end of the first lightly doped region is connected to the sub-electrode metal layer.

[0010] In one embodiment, the doping concentration of the first highly doped region is equal to the doping concentration of the second doped region.

[0011] In one embodiment, the doping concentration of the first highly doped region is greater than the doping concentration of the first lightly doped region.

[0012] In one embodiment, the doping type of the first doped region and the doping type of the second doped region are both P-type doped.

[0013] A second aspect is an array substrate, Base substrate and A plurality of scanning lines, a plurality of data lines, and a plurality of pixel units are provided on the base substrate; A plurality of pixel regions are defined by the scan lines and the data lines, the pixel regions including main pixel regions and sub-pixel regions; The pixel unit includes the pixel structure according to the first aspect, wherein the gate is connected to the scan line, the source is connected to the data line, the main pixel electrode is disposed in the main pixel region, and the sub-pixel electrode is disposed in the sub-pixel region.

[0014] A third aspect is a method for manufacturing an array substrate, comprising the steps of: forming a gate on an upper surface of a base substrate; forming a gate insulating layer on the upper surface of the gate and the upper surface of the base substrate other than the gate; forming an active area on an upper surface of the gate insulating layer located above an upper surface region of the gate insulating layer corresponding to the gate; forming second doped regions on both ends of an upper surface of the active region, and forming a first doped region on an upper surface of the gate insulating layer spaced apart from the active region and the second doped regions; forming a source, a drain and a sub-electrode metal layer on the upper surface of the gate insulating layer, wherein the second doped region at one end of the upper surface of the active region is connected to the source, the second doped region at the other end of the upper surface of the active region is connected to a first end of the drain, a second end of the drain is connected to a first end of the first doped region, and a second end of the first doped region is connected to the sub-electrode metal layer; forming a passivation layer over the source, the active region, the second doped region, the drain, the first doped region and the sub-electrode metal layer; disposing a main pixel electrode and a sub-pixel electrode on the passivation layer; connecting the main pixel electrode to the drain; and connecting the sub-pixel electrode to the sub-electrode metal layer.

[0015] In one embodiment, the step of forming second doped regions on both ends of an upper surface of the active region and forming a first doped region on an upper surface of the gate insulating layer spaced apart from the active region and the second doped regions includes: forming a first highly doped region and a first lightly doped region in the first doped region; forming second doped regions on opposite ends of an upper surface of the active region by chemical vapor deposition, and forming a first highly doped region on an upper surface of the gate insulating layer spaced apart from the active region and the second doped region; forming a first lightly doped region between the first heavily doped regions by chemical vapor deposition, the doping concentration of the first heavily doped region being equal to the doping concentration of the second doped region.

[0016] In one embodiment, the gas used in the chemical vapor deposition comprises phosphine and monosilane; a first ratio M of the gas flow rate of the phosphine to the gas flow rate of the monosilane in the first highly doped region and the second doped region satisfies a first predetermined ratio range; The first predetermined ratio range is 1:2.0≦M≦1:1.5.

[0017] In one embodiment, a second ratio N of the gas flow rate of the phosphine to the gas flow rate of the monosilane in the first lightly doped region satisfies a second predetermined ratio range; The second predetermined ratio range is 1:0.5≦N≦1:0.1. Effect of the Invention

[0018] The effect of the pixel structure according to the disclosed embodiment is that the drain of the thin film transistor is directly connected to the main pixel electrode, but also connected to the sub-pixel electrode through the first doped region, and the first doped region of the pixel structure is set as a low doping concentration, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is increased by the low doping concentration of the first doped region, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is larger than the resistance between the drain and the main pixel electrode. Between the drain of the thin film transistor and the sub-pixel electrode, the resistance generated by the first doped region with a low doping concentration has a voltage dividing effect on the data signal voltage, so that the data signal voltage obtained by the sub-pixel electrode is smaller than the data signal voltage obtained by the main pixel electrode, so that the liquid crystal rotation angle of the sub-pixel region is smaller than that of the main pixel region. This allows the use of one thin film transistor to control 8-domain VA display, and reduces the number of TFTs and manufacturing steps in ensuring a large viewing angle range, thereby reducing the structural complexity and manufacturing costs of the pixel structure.

[0019] The effect of the array substrate according to the embodiment of the present disclosure is that the array substrate includes a base substrate, a plurality of scanning lines, a plurality of data lines and a plurality of pixel units provided on the base substrate, the scanning lines and the data lines define a plurality of pixel regions, the pixel regions include a main pixel region and a sub-pixel region, the pixel units include the pixel structure according to any one of the contents of the first embodiment, the gate is connected to the scanning line, the source is connected to the data line, the main pixel electrode is provided in the main pixel region, and the sub-pixel electrode is provided in the sub-pixel region, so that the data signal voltage obtained by the sub-pixel electrode is smaller than the data signal voltage obtained by the main pixel electrode, and therefore the liquid crystal deflection angle in the sub-pixel region is smaller than the liquid crystal deflection angle in the main pixel region, thereby using one thin film transistor to control 8-domain VA display, and reducing the number of TFTs and manufacturing steps in ensuring a large viewing angle range, and reducing the structural complexity and manufacturing cost of the array substrate.

[0020] The effect of the manufacturing method of the array substrate according to the disclosed embodiment is that the drain of the thin film transistor is directly connected to the main pixel electrode, but the drain of the thin film transistor is also connected to the sub-pixel electrode through the first doped region, and the first doped region of the pixel structure is set as a low doping concentration, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is increased by the low doping concentration of the first doped region, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is larger than the resistance between the drain and the main pixel electrode. Between the drain of the thin film transistor and the sub-pixel electrode, the resistance generated by the first doped region with a low doping concentration has a voltage dividing effect on the data signal voltage, so that the data signal voltage acquired by the sub-pixel electrode is smaller than the data signal voltage acquired by the main pixel electrode, so that the liquid crystal rotation angle of the sub-pixel region is smaller than the liquid crystal rotation angle of the main pixel region. Thus, one thin film transistor can be used to control 8-domain VA display, reducing the number of TFTs and manufacturing steps in ensuring a large viewing angle range, and reducing the structural complexity and manufacturing cost of the pixel structure. [Brief description of the drawings]

[0021] In order to more clearly describe the technical solutions provided by the embodiments of the present disclosure, the following briefly introduces drawings required for describing the embodiments or prior art. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without any creative work. [Figure 1] FIG. 2 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present disclosure; [Diagram 2] FIG. 2 is a schematic diagram of an array substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is an equivalent circuit diagram of an array substrate according to an embodiment of the present disclosure. [Figure 4] 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a schematic cross-sectional view corresponding to S10 in the manufacturing method of the array substrate according to the disclosed embodiment. [Figure 6]FIG. 2 is a schematic cross-sectional view corresponding to S20 in the manufacturing method of the array substrate according to the disclosed embodiment. [Figure 7] FIG. 2 is a schematic cross-sectional view corresponding to S30 in the manufacturing method of the array substrate according to the disclosed embodiment; [Figure 8] FIG. 11 is a schematic cross-sectional view corresponding to S40 in the manufacturing method of the array substrate according to the disclosed embodiment. [Figure 9] FIG. 11 is a schematic cross-sectional view corresponding to S50 in the manufacturing method of the array substrate according to the disclosed embodiment. [Figure 10] FIG. 11 is a schematic cross-sectional view corresponding to S60 in the manufacturing method of the array substrate according to the disclosed embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In order to clarify the technical problems, technical solutions and advantages of the present disclosure, the present disclosure will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely used to interpret the present disclosure, and are not intended to limit the present disclosure.

[0023] It should be noted that when an element is described as being "fixed" or "mounted" to another element, it may be directly or indirectly located on the other element. When an element is described as being "connected" to another element, it may be directly or indirectly connected to the other element.

[0024] Any orientations or positions indicated by the terms "up," "down," "left," "right," etc. are based on the orientations or positions shown in the drawings and are for ease of illustration only, and are not to be construed as limitations on the present disclosure as they do not imply or imply that such devices or elements necessarily have a particular orientation or are constructed or operated in a particular orientation.

[0025] The terms "first" and "second" are used for ease of description and should not be understood as implying or denoting relative importance or number of features. "Plurality" means two or more than two, unless otherwise clearly and specifically limited.

[0026] References in the present disclosure to "one embodiment" or "some embodiments" or the like mean that one or more embodiments of the present disclosure include the particular feature, structure, or characteristic described in connection with that embodiment. Thus, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," and the like appearing in different places in this specification do not necessarily refer to the same embodiment, unless otherwise specifically emphasized, but rather mean "one or more, but not all, embodiments." The terms "including," "having," and variations thereof all mean "including, but not limited to," unless otherwise specifically emphasized.

[0027] The conventional 8-domain VA display structure needs to be controlled by multiple TFTs, for example, two TFTs are used to control the main sub-pixel and the sub-sub-pixel respectively, and a third TFT is used to perform partial discharge for the sub-sub-pixel during the voltage holding period of the sub-sub-pixel, or the third TFT is omitted and only two TFTs are used to control the 8-domain VA display structure, so the structure and manufacturing of the multiple TFTs are both complicated.

[0028] (First embodiment) As shown in FIG. 1, a pixel structure 100 according to the present embodiment includes: a gate 611 provided on the upper surface of the base substrate 1; a gate insulating layer 62 covering the gate 611 and further covering the upper surface of the base substrate 1 other than the gate 611; a source 613, an active region 612 provided in an upper region corresponding to the gate 611, a drain 614, a first doped region 63, and a sub-electrode metal layer 65, which are provided in this order on the upper surface of the gate insulating layer 62 along a direction parallel to the lateral direction of the base substrate 1; a second doped region 64 disposed on both ends of the upper surface of the active region 612, the second doped region 64 at one end of the upper surface of the active region 612 being connected to the source 613, and the second doped region 64 at the other end of the upper surface of the active region 612 being connected to the drain, the doping concentration of the first doped region being lower than the doping concentration of the second doped region 64; a passivation layer 66 covering the source 613, the area in the active region 612 not covered by the second doped region 64, the second doped region 64, the drain 614, the first doped region 63, and the sub-electrode metal layer 65, and having a first through hole 67 penetrating to the drain 614 and a second through hole 68 penetrating to the sub-electrode metal layer 65, the drain 614 being connected to the main pixel electrode 41 via the first through hole 67, and the sub-electrode metal layer 65 being connected to the sub-pixel electrode 51 via the second through hole 68.

[0029] In some embodiments, the gate 611, the source 613, and the drain 614 are all metal layers. The source 613 and the drain 614 are all located on the upper surface of the gate insulating layer 62, and are connected by an active region 612 that is also located on the upper surface of the gate insulating layer 62, and the source 613 and the drain 614 are separated by a passivation layer 66 on the upper surface of the active region 612. The gate 611, the source 613, and the drain 614 are separated by the gate insulating layer 62. Here, the gate 611, the source 613, and the drain 614 may all be made of any electrically good conductor material, for example, aluminum (Al), copper (Cu), or the like. Cu ), silver (Ag), molybdenum (Mo), or aluminum (Al), copper ( Cu It is made of an alloy material formed by mixing Cr, silver (Ag), and molybdenum (Mo) in an arbitrary ratio.

[0030] In some embodiments, the gate 611 is also used as a scan line 2. The active area 612 is made of amorphous silicon A-Si or polycrystalline silicon, or made of the metal oxide semiconductor Indium Gallium Zinc Oxide IGZO (Indium Gallium Zinc Oxide).

[0031] In some embodiments, the gate insulating layer 62 and the passivation layer 66 (Passivation, PVX) may be made of any electrically poor conductor material, such as at least one of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer. The gate insulating layer 62 is used to isolate the gate 611, and the passivation layer 66 is used as a protective layer with a certain strength and also has an insulating function.

[0032] In some embodiments, the second doped region 64 is a highly doped region and is likely to form an ohmic contact so as to reduce the contact resistance between the active region 612 formed of a semiconductor material and the source 613 and the drain 614, while the doping concentration of the first doped region 63 is less than that of the second doped region 64, so that the resistance of the first doped region 63 is greater than that of the second doped region 64 and is likely to act as a voltage divider during operation.

[0033] In some embodiments, the first doped region 63 includes a first heavily doped region 631 and a first lightly doped region 632. In a direction parallel to the lateral direction of the base substrate, the first heavily doped region 631 is disposed at both ends of the first lightly doped region 632, the first heavily doped region 631 disposed at one end of the first lightly doped region 632 is connected to the drain 614, and the first heavily doped region 631 disposed at the other end of the first lightly doped region 632 is connected to the sub-electrode metal layer 65. Here, the first heavily doped regions 631 at both ends of the first lightly doped region 632 form ohmic contacts, thereby reducing the contact resistance between the first doped region 63 and the drain 614 and the sub-electrode metal layer 65.

[0034] In some embodiments, the doping concentration of the first heavily doped region 631 is equal to the doping concentration of the second doped region 64, and is greater than the doping concentration of the first lightly doped region 632. The doping concentration of the first heavily doped region 631 being equal to the doping concentration of the second doped region 64 contributes to reducing the complexity of the deposition process and saving the deposition time, and the doping concentration of the first heavily doped region 631 being greater than the doping concentration of the first lightly doped region 632 contributes to forming an ohmic contact, thereby reducing the contact resistance between the first doped region 63 and the drain 614 and the sub-electrode metal layer 65.

[0035] In some embodiments, the doping type of the first doped region 63 and the doping type of the second doped region 64 are both P-type doped, and the P-type doping contributes to the switching control of the thin film transistor 61 .

[0036] (Second embodiment) As shown in FIG. 2, the array substrate 300 according to the present embodiment includes: Base substrate 1 and A plurality of scanning lines 2, a plurality of data lines 3 and a plurality of pixel units 200 are disposed on a base substrate 1; A plurality of pixel regions are defined by the scanning lines 2 and the data lines 3, and the pixel regions include a main pixel region 4 and a sub-pixel region 5; The pixel unit 200 includes the pixel structure 100 according to any one of the first embodiments, in which a gate 611 is connected to a scan line 2, a source 613 is connected to a data line 3, a main pixel electrode 41 is disposed in a main pixel region 4, and a sub-pixel electrode 51 is disposed in a sub-pixel region 5, in which the gate 611, the active region 612, the source 613 and the drain 614 form a thin film transistor 61. Note that Figures 2 and 3 only show one pixel unit 200, one scan line 2 and one data line 3.

[0037] 3, the gate 611 of the thin film transistor 61 receives a scan voltage (SCAN) from the scan line 2, and the gate 611 of the thin film transistor 61 controls the on / off of the thin film transistor 61 according to the scan voltage of the scan line 2. When the thin film transistor 61 is turned on, the data voltage (DATA) from the data line 3 can be applied to the main pixel electrode 41, and the voltage between the main pixel electrode 41 and its opposite upper common electrode (not shown, for providing a voltage VCOM) is applied to the liquid crystal layer (not shown) therebetween, forming a first liquid crystal capacitor 7, and the first liquid crystal capacitor 7 is charged by the data voltage (DATA) from the data line 3, thereby driving the rotation of the corresponding liquid crystal molecules in the main pixel area 4. When the thin film transistor 61 is turned on, a data voltage (DATA) from the data line 3 can be applied to the subpixel electrode 51, and a voltage between the subpixel electrode 51 and its opposite upper common electrode (not shown, for providing a voltage VCOM) is applied to the liquid crystal layer (not shown) therebetween, forming a second liquid crystal capacitor 8, and the second liquid crystal capacitor 8 is charged by the data voltage (DATA) from the data line 3, thereby driving the corresponding liquid crystal molecules in the subpixel region 5 to rotate.

[0038] 3, when the data voltage (DATA) from the data line 3 charges the second liquid crystal capacitor 8, it must pass through the equivalent resistance R formed in the first doped region 63, and the equivalent resistance R has a voltage dividing function and separates a part of the data voltage (DATA) from the data line 3, so that the data voltage in the sub-pixel region 5 is smaller than the data voltage in the main pixel region 4, and further, the rotation degree of the liquid crystal molecules in the sub-pixel region 5 is different from that in the main pixel region 4. In this way, by configuring both the main pixel electrode 41 and the sub-pixel electrode 51 as a 4-domain structure, 8 domains can be realized based on one TFT (thin film transistor 61), and the number of TFTs and manufacturing steps in the pixel structure 100 can be reduced, thereby reducing the structural complexity and manufacturing cost of the pixel structure 100.

[0039] In some embodiments, by satisfying the requirement that the doping concentration of the first doped region 63 is lower than that of the second doped region 64, when the resistance of the first doped region 63 is higher than that of the second doped region 64, the doping concentration of the first doped region 63 can be adjusted based on the viewing angle requirements of the VA display structure to change the magnitude of the partial pressure of the first doped region 63, thereby adjusting the degree of rotation of the liquid crystal molecules in the subpixel region 5, and achieving a better large-angle display viewing angle.

[0040] In some embodiments, second doped region 64 is a metal layer, which reduces deposition time and reduces manufacturing costs.

[0041] This embodiment has the following advantages over the prior art. In the pixel structure and array substrate according to the present embodiment, the drain of the thin film transistor is directly connected to the main pixel electrode, but the drain of the thin film transistor is also connected to the sub-pixel electrode through the first doped region, and the first doped region of the pixel structure is set as a low doping concentration, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is increased by the low doping concentration of the first doped region, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is larger than the resistance between the drain and the main pixel electrode. Between the drain of the thin film transistor and the sub-pixel electrode, the resistance generated by the first doped region with a low doping concentration has a voltage dividing effect on the data signal voltage, so that the data signal voltage acquired by the sub-pixel electrode is smaller than the data signal voltage acquired by the main pixel electrode, so that the liquid crystal rotation angle of the sub-pixel region is smaller than that of the main pixel region. As a result, the number of TFTs and manufacturing steps can be reduced in order to ensure a large viewing angle range using one thin film transistor, and the structural complexity and manufacturing costs of the pixel structure can be reduced.

[0042] The display panel having the pixel structure and array substrate according to the disclosed embodiment can realize 8-domain VA display with only one TFT, reducing the number of TFTs and manufacturing steps while ensuring a wide viewing angle range, and has low structural complexity and manufacturing cost. The display panel further reduces the number of TFTs, thereby increasing the effective display area of ​​a single pixel unit and improving the brightness of the display panel.

[0043] (Third Example) As shown in FIG. 4, the method for manufacturing the array substrate 300 according to this embodiment includes the following steps. S10: As shown in FIG. 5, a gate 611 is formed at one end of the upper surface of the base substrate 1.

[0044] In some embodiments, a first metal layer is formed on the base substrate 1 by physical vapor deposition, and the material of the first metal layer includes at least one of aluminum and molybdenum. Then, a gate 611 is formed by masking and photolithography, and the gate 611 is further used as the scan line 2.

[0045] S20: As shown in FIG. 6, a gate insulating layer 62 is formed on the upper surface of the gate 611 and the upper surface of the base substrate 1 other than the gate 611.

[0046] In some embodiments, further, a gate insulating layer 62 is formed on the upper surface of the gate 611 and the base substrate 1 other than the gate 611 by masking and photolithography through chemical vapor deposition, and the material of the gate insulating layer 62 includes at least one of silicon nitride and silicon oxide.

[0047] S30: As shown in FIG. 7, an active region 612 is formed on the upper surface of the gate insulating layer 62.

[0048] In some embodiments, an amorphous silicon layer or a polycrystalline silicon layer is formed on the upper surface of the gate insulating layer 62 by chemical vapor deposition, and then the active area 612 is formed by a mask photolithography process. Or, a polycrystalline silicon layer or a metal oxide semiconductor layer is formed on the upper surface of the gate insulating layer 62 by physical vapor deposition, and then the active area 612 is formed by a mask photolithography process. Here, the metal oxide comprises IGZO (indium gallium zinc oxide), and the active area 612 is located in the upper surface area of ​​the gate insulating layer 62 corresponding to the gate 611.

[0049] In step S40, as shown in FIG. 8, second doped regions 64 are formed on both ends of the upper surface of the active region 612, and a first doped region 63 is formed in a region other than the upper surface region of the gate insulating layer 62 corresponding to the gate 611.

[0050] In some embodiments, both ends of the upper surface of the active region 612 are ion-doped and deposited by chemical vapor deposition, and the second doped region 64 is formed by masking and photolithography. The second doped region 64 is an ohmic contact layer, and is used to reduce the contact resistance between the active region 612 and the source 613 and the drain 614. Furthermore, the region other than the upper surface region of the upper gate insulating layer 62 corresponding to the gate 611 is ion-doped and deposited, and the first doped region 63 is formed by masking and photolithography.

[0051] In one embodiment, the step of forming the second doped regions 64 on both ends of the upper surface of the active region 612 and forming the first doped regions 63 on the upper surface of the gate insulating layer 62 other than the upper surface of the gate insulating layer 62 corresponding to the gate 611 includes: The first doped region 63 includes a first highly doped region 631 and a first lightly doped region 632. forming second doped regions 64 on both ends of the upper surface of the active region 612 by chemical vapor deposition, and forming first highly doped regions 631 having the same shape as the second doped regions 64 in a region other than the upper surface region of the upper gate insulating layer 62 corresponding to the gate 611; forming a first lightly doped region 632 between the first heavily doped regions 631 by chemical vapor deposition.

[0052] The step of forming the first heavily doped region 631 in the first doped region 63 is used to reduce the contact resistance when both ends of the first lightly doped region 632 are connected to the source 613 and the sub-electrode metal layer 65, respectively, using the first heavily doped region 631 as an ohmic contact layer. Here, the doping concentration of the first heavily doped region 631 is equal to the doping concentration of the second doped region 64, which contributes to simplifying the chemical vapor deposition process and reducing the deposition time.

[0053] In some embodiments, the gases employed in the chemical vapor deposition include phosphine (PH3) and monosilane (SiH4), and a first ratio M of the gas flow rate of phosphine to the gas flow rate of monosilane in the first heavily doped region 631 and the second doped region 64 satisfies a first predetermined ratio range, and a second ratio N of the gas flow rate of phosphine to the gas flow rate of monosilane in the first lightly doped region 632 satisfies a second predetermined ratio range.

[0054] In some embodiments, the first predetermined ratio range is set as 1:2.0≦M≦1:1.5, and the second predetermined ratio range is set as 1:0.5≦N≦1:0.1. The ratio of the gas flow rate of phosphine to the gas flow rate of monosilane in the first predetermined ratio range and the second predetermined ratio range can better control the chemical vapor deposition process and obtain a doped region that meets the doping concentration requirement.

[0055] S50 As shown in FIG. 9 , a source 613 is formed on the upper surface of the gate insulating layer 62, a drain 614 is formed on the upper surface of the gate insulating layer 62 between the active region 612 and the first doped region 63, and a sub-electrode metal layer 65 is formed on the upper surface of the gate insulating layer 62 adjacent to the first doped region 63, with the sub-electrode metal layer 65 and the drain 614 adjacent to both sides of the first doped region 63, respectively.

[0056] In some embodiments, a second metal layer is formed on the upper surface of the gate insulating layer 62 by physical vapor deposition, the material of the second metal layer includes at least one of aluminum and molybdenum, and then a source 613 is formed on the upper surface of the gate insulating layer 62 between the active region 612 and the first doped region 63 by masking and photolithography, a drain 614 is formed on the upper surface of the gate insulating layer 62 between the active region 612 and the first doped region 63, and a sub-electrode metal layer 65 is formed on the upper surface of the gate insulating layer 62. Here, the second doped region 64 at one end of the upper surface of the active region 612 is connected to the source 613, the second doped region 64 at the other end of the upper surface of the active region 612 is connected to a first end of the drain 614, a second end of the drain 614 is connected to a first end of the first doped region 63, and a second end of the first doped region 63 is connected to the sub-electrode metal layer 65.

[0057] S60: As shown in FIG. 10, a passivation layer 66 is formed over the source 613, the top surface region of the active region 612 other than that covered by the second doped region 64, the top surface region of the second doped region 64 other than that covered by the source 613 and the drain 614, the drain 614, the first doped region 63, and the sub-electrode metal layer 65.

[0058] In some embodiments, an insulating material layer is formed over the source 613, the upper surface region of the active region 612 other than that covered by the second doped region 64, the upper surface region of the second doped region 64 other than that covered by the source 613 and the drain 614, the drain 614, the first doped region 63, and the sub-electrode metal layer 65 by chemical vapor deposition or the like, and then a passivation layer 66 is formed by masking and photolithography, the material of the passivation layer 66 including at least one of silicon nitride and silicon oxide. Here, the passivation layer 66 is provided with a first through hole 67 penetrating to the drain 614 and a second through hole 68 penetrating to the sub-electrode metal layer 65, and the drain 614 is connected to the main pixel electrode 41 through the first through hole 67, and the sub-electrode metal layer 65 is connected to the sub-pixel electrode 51 through the second through hole 68.

[0059] Here, connecting the drain 614 to the main pixel electrode 41 via the first through hole 67 and connecting the sub-electrode metal layer 65 to the sub-pixel electrode 51 via the second through hole 68 is, forming a transparent metal layer in the first through-hole 67 and the second through-hole 68 by physical vapor deposition, where the material of the transparent metal layer can be indium tin oxide, indium zinc oxide, aluminum zinc oxide, etc.; Then, the step includes forming a main pixel electrode 41 and a sub-pixel electrode 51 located in the opening region by masking and photolithography, where the main pixel electrode 41 is connected to the drain 614 via the first through hole 67, and the sub-pixel electrode 51 is connected to the sub-electrode metal layer 65 via the second through hole 68.

[0060] The disclosed embodiment has the following advantages over the prior art. In the method for manufacturing an array substrate according to the disclosed embodiment, the drain of the thin film transistor is directly connected to the main pixel electrode, but the drain of the thin film transistor is also connected to the sub-pixel electrode through the first doped region, and the first doped region of the pixel structure is set as a low doped region, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is increased by the low doped region, so that the resistance between the drain of the thin film transistor and the sub-pixel electrode is larger than the resistance between the drain and the main pixel electrode. Between the drain of the thin film transistor and the sub-pixel electrode, the resistance generated by the low doped region has a voltage dividing effect on the data signal voltage, so that the data signal voltage acquired by the sub-pixel electrode is smaller than the data signal voltage acquired by the main pixel electrode, so that the liquid crystal rotation angle of the sub-pixel region is smaller than that of the main pixel region. This allows one thin film transistor to control 8-domain VA display, reducing the number of TFTs and manufacturing steps in ensuring a large viewing angle range, and reducing the structural complexity and manufacturing costs of the pixel structure.

[0061] A display panel having a pixel structure and array substrate according to the disclosed embodiments can realize an 8-domain VA display with only one TFT, reducing the number of TFTs and manufacturing steps while ensuring a wide viewing angle range, and having low structural complexity and manufacturing costs.

[0062] Needless to say, the size of the numbers of each step in the above embodiments does not indicate the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the disclosed embodiments.

[0063] In the above embodiments, the description of each embodiment is given with emphasis, and for the details or parts not described in an embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] The above embodiments are merely for illustrating the technical solutions of the present disclosure, and are not limiting. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can be modified or some features can be replaced with equivalents. These modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and all should be included in the protection scope of the present disclosure. [Explanation of symbols]

[0065] 100 pixel structure 200 pixel units 300 Array Board 1 Base Board 2 Scan Lines 3 Data Line 4. Main pixel area 41 Main pixel electrode 5 Subpixel Area 51 Sub-pixel electrode 61 Thin-film transistor Gate 611 612 Active Area 613 Source 614 Drain 62 Gate insulating layer 63 First doped region 631 First Highly Doped Region 632 First lightly doped region 64 Second doped region 65 Sub-electrode metal layer 66 Passivation Layer 67 First through hole 68 Second through hole 7 First Liquid Crystal Capacitor 8 Second LCD Capacitor 9. First memory capacitor 10 Second memory capacitor

Claims

1. A gate provided on an upper surface of a base substrate; a gate insulating layer covering the gate and further covering an upper surface of the base substrate other than the gate; A source, an active region located in an upper region corresponding to the gate, a drain, a first doped region having one end connected to the drain and the other end connected to a sub-electrode metal layer, and the sub-electrode metal layer are sequentially disposed on the upper surface of the gate insulating layer along a direction parallel to the lateral direction of the base substrate. second doped regions at both ends of a top surface of the active region, the second doped region at one end of the top surface of the active region being connected to the source and the second doped region at the other end of the top surface of the active region being connected to the drain, the doping concentration of the first doped region being less than the doping concentration of the second doped region; a passivation layer covering the source, the portion of the active area exposed from the second doped region, the second doped region, the drain, the first doped region, and the sub-electrode metal layer, on which a main pixel electrode connected to the drain and a sub-pixel electrode connected to the sub-electrode metal layer are provided; Pixel structure.

2. the first doped region includes a first highly doped region and a first lightly doped region; the first heavily doped region is disposed on both ends of the first lightly doped region in a direction parallel to a lateral direction of the base substrate, the first heavily doped region disposed at one end of the first lightly doped region is connected to the drain, and the first heavily doped region disposed at the other end of the first lightly doped region is connected to the sub-electrode metal layer; The pixel structure of claim 1 .

3. the doping concentration of the first highly doped region is equal to the doping concentration of the second highly doped region; The pixel structure according to claim 2 .

4. the doping concentration of the first heavily doped region is greater than the doping concentration of the first lightly doped region; The pixel structure according to claim 2 .

5. The doping type of the first doped region and the doping type of the second doped region are both P-type doped; 3. A pixel structure according to claim 1 or 2.

6. The gate, the source and the drain are each made of at least one material selected from the group consisting of aluminum (Al), copper (Cu), silver (Ag) and molybdenum (Mo), or made of an alloy material formed in any combination ratio of aluminum (Al), copper (Cu), silver (Ag) and molybdenum (Mo).

3. A pixel structure according to claim 1 or 2.

7. The active region is composed of amorphous silicon, polycrystalline silicon, or indium gallium zinc oxide.

3. A pixel structure according to claim 1 or 2.

8. The gate insulating layer is composed of at least one material selected from the group consisting of a silicon nitride layer and a silicon oxide layer.

3. A pixel structure according to claim 1 or 2.

9. Base substrate and A plurality of scanning lines, a plurality of data lines, and a plurality of pixel units are provided on the base substrate; A plurality of pixel regions are defined by the plurality of scan lines and the plurality of data lines, the plurality of pixel regions including main pixel regions and sub-pixel regions; The plurality of pixel units include the pixel structure according to claim 1 or 2, wherein the gate is connected to the plurality of scan lines, the source is connected to the plurality of data lines, the main pixel electrode is disposed in the main pixel region, and the sub-pixel electrode is disposed in the sub-pixel region. Array board.

10. forming a gate on an upper surface of a base substrate; forming a gate insulating layer on the upper surface of the gate and the upper surface of the base substrate other than the gate; forming an active area on an upper surface of the gate insulating layer located above an upper surface region of the gate insulating layer corresponding to the gate; forming second doped regions on both ends of an upper surface of the active region, and forming a first doped region on an upper surface of the gate insulating layer spaced apart from the active region and the second doped region; forming a source, a drain and a sub-electrode metal layer on the upper surface of the gate insulating layer, wherein the second doped region at one end of the upper surface of the active region is connected to the source, the second doped region at the other end of the upper surface of the active region is connected to a first end of the drain, a second end of the drain is connected to a first end of the first doped region, and a second end of the first doped region is connected to the sub-electrode metal layer; forming a passivation layer over the source, the active region, the second doped region, the drain, the first doped region and the sub-electrode metal layer; disposing a main pixel electrode and a sub-pixel electrode on the passivation layer; connecting the main pixel electrode and the drain, and connecting the sub-pixel electrode and the sub-electrode metal layer; A method for manufacturing an array substrate.

11. forming the second doped regions on both ends of the upper surface of the active region, and forming the first doped region on the upper surface of the gate insulating layer at a distance from the active region and the second doped region, forming a first highly doped region and a first lightly doped region in the first doped region; forming the second doped regions on both ends of an upper surface of the active region by chemical vapor deposition, and forming the first highly doped region on an upper surface of the gate insulating layer spaced apart from the active region and the second doped region; forming the first lightly doped regions between the first heavily doped regions by chemical vapor deposition; The method for manufacturing an array substrate according to claim 10 .

12. the doping concentration of the first highly doped region is equal to the doping concentration of the second highly doped region; The method for manufacturing an array substrate according to claim 11 .

13. The gases used in the chemical vapor deposition include phosphine and monosilane; The method for manufacturing an array substrate according to claim 11 .

14. a first ratio M of the gas flow rate of the phosphine to the gas flow rate of the monosilane in the first heavily doped region and the second doped region satisfies a first predetermined ratio range; The first predetermined ratio range is 1:2.0≦M≦1:1.5; The method for manufacturing an array substrate according to claim 13 .

15. a second ratio N of the gas flow rate of the phosphine to the gas flow rate of the monosilane in the first lightly doped region satisfies a second predetermined ratio range; The second predetermined ratio range is 1:0.5≦N≦1:0.1; The method for manufacturing an array substrate according to claim 13 .

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