Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

Abstract

Disclosed is postponing cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative. At least one cache state update in the cache memory resulting from the data request is postponed until the data request becomes non-speculative. Thus, the cache state in the cache memory is not updated for requests resulting from a misprediction. Postponing the cache state update in the cache memory may include postponing storage of speculatively requested data received as a result of a cache miss in a main data array of the cache memory until the data request becomes non-speculative. The received speculatively requested data may be first stored in a speculative buffer memory associated with the cache memory and then stored in the main data array when the data request becomes non-speculative.

Description

[Technical field]

[0001] The technology of this disclosure relates to processor-based systems that employ a central processing unit (CPU), also known as a "processor," and more particularly to cache memory within a processor-based system that is used to store or "cache" a copy of information in main memory for faster access by the processor. [Background technology]

[0002] A central processing unit (CPU), also known as a "processor," performs computational tasks for a wide range of applications. A conventional processor includes one or more processor cores, also known as a "CPU core." The processor executes computer program instructions ("instructions"), also known as "software instructions," that are fetched from an instruction memory. The processor executes the instructions fetched from the memory to perform operations and generate results based on the instruction type and data operands. The results can be provided as input to be consumed by another instruction and / or stored as data in a data memory. The instruction and data memory can be provided in a main memory as part of a processor-based system that includes the processor. The instruction and data memory can also be provided in the form of a cache memory. For example, a data cache memory contains or "caches" a smaller copy of data stored in the main memory to provide the processor with faster access to the data. A cache memory system includes one or more cache memories organized in a hierarchy between the processor and the main memory. Data moves between the main memory and different levels of the cache memory based on cache hits and misses. If a processor requests data that is not stored in any of the levels of cache memory (i.e., a cache miss), the data is retrieved from main memory and stored in the level of cache memory. If a later request for the same data is made resulting in a cache hit (i.e., the data is requested before it has been evicted from the level of cache memory), the data is provided to the processor from the cache memory as opposed to having to re-fetch the data from main memory.

[0003] As a result of a cache miss in a lower level cache memory, data retrieved from a higher level cache memory or main memory is temporarily stored in a dedicated structure known as a fill buffer in the lower level cache memory. The fill buffer is also known as a miss status holding register (MSHR). The fill buffer of a cache memory serves as a staging area for storing incoming data in the cache memory until a cache entry in the cache memory is available to store the incoming data. The cache memory evicts existing cache entries in the data array of the cache memory based on an eviction policy, such as least recently used, to make room for new incoming data as a result of a cache miss. A cache miss to a lower level cache memory may result in a data request (i.e., a read request) to the next higher level cache memory, which has the requested data stored in its data array or still stored in the fill buffer before being stored in the cache data array. In either case, the requested data contained in either the fill buffer or the data array of the higher level cache memory may be provided to the lower level cache memory in response to a request for data from the lower level cache memory. A cache memory can hold incoming data in its fill buffer and not store the data in its data array until the fill buffer is full, because incoming requests for data can be satisfied from the fill buffer as well as the data array.

[0004] Processors may utilize instruction pipelining as a processing technique, whereby the throughput of executed computer instructions may be increased by dividing the processing of each instruction into a series of steps. These steps are executed in an execution pipeline consisting of multiple stages. However, structural hazards may arise in an instruction pipeline that is unable to execute the next instruction without leading to an incorrect computation result. For example, a control hazard may arise as a result of the execution of a control flow instruction that causes a precise interrupt in the processor. One example of a control flow instruction that may cause a control hazard is a conditional branch instruction. A conditional branch instruction may redirect the flow path of instruction execution based on a condition evaluated when the condition of the control branch instruction is executed. One approach to maximizing processor performance includes utilizing a prediction circuit to speculatively predict the outcome of the condition of the conditional branch instruction prior to its execution. In this way, younger instructions that follow the predicted flow path of the conditional branch instruction may be fetched and further processed in the instruction pipeline instead of stalling until the branch condition is resolved when the conditional branch instruction is executed. When the conditional branch instruction finally reaches the execution stage of the instruction pipeline and is executed, the resulting target address of the conditional branch instruction is verified by comparing it with the target address previously predicted when the conditional branch instruction was fetched. If the predicted target address and the actual target address match, it means that a correct prediction was made and no delay is incurred in the instruction execution, because the later instruction at the target address will have been correctly fetched and will already be present in the instruction pipeline when the conditional branch instruction reaches the execution stage of the instruction pipeline. However, if the predicted target address and the actual target address do not match, a mispredicted branch hazard occurs in the instruction pipeline that causes a precise interrupt.As a result, a misprediction recovery process is performed whereby instructions younger than the conditional branch instruction in the instruction pipeline are flushed and the instruction pipeline fetch unit is redirected to fetch new instructions starting from the target address, resulting in delays and performance degradation.

[0005] Even if misprediction recovery involves flushing instructions younger than the conditional branch instruction in the incorrectly predicted flow path and then fetching and processing instructions in the correct flow path, the processing of the younger instruction in the incorrect flow path may still result in data reaching the cache memory as a result of a cache miss. This may cause a security problem in the form of a leak. For example, a malicious attacker process executing in a processor may include code that loads a large amount of data from memory and causes this data to fill and prime the shared cache memory. The attacker process may also prime the branch prediction circuitry to force an incorrect speculative prediction of a conditional branch instruction in a victim process that is executed later to occur later. Load instructions in the incorrectly speculated flow path that follow a conditional branch instruction in a victim process may cause the processor to load data into the cache memory, even though these load instructions are later flushed when the conditional branch instruction is executed and its condition is resolved. This causes some of the data in the cache memory prepared by the attacker process to be evicted from the cache memory by a load instruction in the incorrect flow path of the victim process. When the attacker process runs again after the victim process is switched out, the attacker process can determine which of its prepared data has been evicted from the cache memory. This information may provide information about the data addresses accessed by the victim process.

[0006] The aforementioned security problem can be addressed by providing a non-shared speculative buffer outside the shared cache memory to store data loaded from processing a speculatively processed load instruction. The speculatively loaded data into the speculative buffer from processing a speculatively processed load instruction can still be provided to a consumer instruction depending on the speculatively processed load instruction. Once the load instruction that caused the data to be speculatively loaded into the speculative buffer is executed and becomes non-speculative, if the speculative prediction was correct, the speculative request can be reissued non-speculatively. If the speculative prediction was incorrect, the speculative request for the data is not reissued, thus preventing the speculatively loaded data from being installed in the cache memory. In this way, the data is not loaded into the cache memory as a result of processing an incorrectly speculated load instruction. However, up to twice as many (2X) data requests would be issued to load the data into the processor, which is inefficient. Summary of the Invention

[0007] Aspects disclosed herein include deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative. The processor-based system includes a processor, which may include one or more processor cores, executing computer software instructions to perform operations based on loaded data stored in a main memory. The processor-based system further includes a cache memory system including one or more private and / or shared cache memories organized in a hierarchy between the processor and the main memory. Each cache memory has a cache replacement policy that governs which data in its cache entries is evicted to a higher level cache memory or to the main memory to make room for storing new data requests (i.e., load / read requests). Load-based instructions ("load instructions") that are speculatively processed by the processor as a result of speculatively predicting the condition of a conditional flow control instruction (e.g., a conditional branch instruction) cause a data request to be made to the cache memory system. However, if the condition of the conditional flow control instruction is determined to be mispredicted in execution, the speculatively processed load-based instruction may be flushed. However, a previous data request to the cache memory system resulting from the processing of the speculative load-based instruction that is no longer valid was made to the cache memory system. If such a data request was allowed to evict other cached data in the cache memory system, this may cause cache pollution. This may also cause security issues. For example, a malicious attacker process may learn information about data accessed by a victim process based on the inaccurate speculative data loaded into the cache memory system.A malicious attacker process may prepare the cache memory system with its own data and prepare the control prediction circuitry to mispredict conditional flow control instructions in the victim process, causing incorrect speculative data to be loaded into the cache memory system. The attacker application may learn information about the victim process based on which of the prepared victim data in the cache memory system is replaced with the incorrect speculative data that is loaded into the cache memory system.

[0008] In this regard, in an exemplary aspect disclosed herein, at least one cache state in the cache memory is postponed from being updated in the cache memory in response to a received data request until the data request is non-speculative. This is because the cache memory is not updated based on a data request resulting from a misprediction that should not have been issued in the event of a misprediction, and thus the cache memory is a non-speculative cache memory. In this manner, cache pollution can be reduced. As another example, an attacker process cannot obtain information about a data access by a victim process executing in a processor by preparing a misprediction in a control prediction circuit that causes the victim process to issue a data request that results in a speculatively modified cache state in the cache memory. If a data request that is not resolved as non-speculative can modify a cache state in the cache memory, an attacker application may gain understanding about a data access by a victim process by understanding the modified cache state in the cache memory.

[0009] In one exemplary aspect, deferral of cache state updates in a cache memory is provided by not first storing received speculatively requested data received from a higher level memory as a result of a cache miss to the cache memory in a cache entry in the main data array of the cache memory. Instead, the received speculatively requested data is first stored in a speculative buffer memory that is not in the main data array of the cache memory. For example, the speculative buffer memory may be a fill buffer circuit in the cache memory that serves as a staging area for storing requested data until a cache entry in the main data array of the cache memory is available to store the incoming data. The speculatively requested data stored in the speculative buffer memory is stored in an available cache entry in the main data array of the cache memory when the load instruction that caused the result requested by the data request becomes non-speculative. In response to the data request becoming non-speculative, no new data request needs to be issued by the processor to the cache memory system to store the speculatively requested data stored in the speculative buffer memory in a cache entry in the cache memory.

[0010] In another exemplary aspect, a cache hit results when a data request issued from a processor to a cache memory in a cache memory system is included in a cache entry in the main data array of the cache memory. Because the speculatively requested data is already included in a cache entry in the main data array of the cache memory, the speculatively requested data in the hit cache entry in the main data array of the cache memory is returned to the requestor in the processor. However, updating of the replacement cache state of the cache entry in the main data array that includes the speculatively requested data can be delayed until the load instruction that initiated the data request for the data becomes non-speculative. This is because, for example, when the data request is flushed as a result of a misprediction, the replacement policy of the main data array of the cache memory is not executed based on the replacement cache state that is modified for the cache entry in the main data array that includes the speculatively requested data as a result of the data request.

[0011] In another exemplary aspect, if a data request issued from a processor to a cache memory is not included in the main data array, but is included in a speculative buffer memory associated with the cache memory, the speculatively requested data in the speculative buffer memory is also returned to the requestor in the processor as a cache hit. Updating the cache state for the speculatively requested data is deferred by not writing the speculatively requested data to a cache entry in the main data array of the cache memory until the data request becomes non-speculative. Also, as an example, as discussed above, updating the replacement cache state for the speculatively requested data is automatically deferred until a new data request for the same data results in a cache hit in the main data array of the cache memory.

[0012] In this regard, in one exemplary aspect, a non-speculative cache memory in a processor-based system is provided. The non-speculative cache memory includes a main data array including a plurality of cache entries each configured to store cache data of data associated with a memory address in a memory system of the processor-based system. The non-speculative cache memory further includes a speculative buffer memory including a plurality of buffer entries each including a data entry configured to store cached data associated with a memory address in the memory system. The non-speculative cache memory further includes a cache controller configured to receive a data request from a requester including a target address and an instruction identification (ID) identifying a load instruction including the target address to be processed by a processor in the processor-based system. The cache controller is further configured to search for a cache entry in the main data array associated with the target address of the data request. The cache controller is further configured to search the speculative buffer memory for a buffer entry associated with the target address of the data request. The cache controller is further configured to transmit a data response to the data request to the requester based on the cache data in the main data array being associated with the target address and the cache data in the buffer entry in the speculative buffer memory being associated with the target address. The cache controller is further configured to receive a commit indicator including an instruction ID of the instruction that is non-speculative, and in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative, the cache controller is further configured to update a cache state of a cache entry in the main data array associated with a target address of the data request.

[0013] In another exemplary aspect, a method for updating a cache state in a non-speculative cache memory in a processor-based system is provided. The method includes receiving a data request from a requestor including a target address and an instruction ID identifying a load instruction including the target address to be processed by a processor in the processor-based system. The method further includes searching a main data array for a cache entry associated with the target address of the data request among a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system. The method further includes searching a speculative buffer memory for a buffer entry associated with the target address of the data request among a plurality of buffer entries each configured to store cache data associated with a memory address in the memory system. The method further includes transmitting a data response to the data request to the requestor based on the cache entry in the main data array being associated with the target address and the cache data in the buffer entry in the speculative buffer memory being associated with the target address. The method further includes receiving a commit indicator including an instruction ID of an instruction that is non-speculative. The method further includes updating a cache state of a cache entry in the main data array associated with a target address of the data request in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative.

[0014] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. [Brief description of the drawings]

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1] FIG. 1 is a diagram of an exemplary processor-based system including a processor configured to issue memory requests (i.e., data read requests and data write requests) to a memory system including a cache memory system and a main memory, where at least one cache memory in the cache memory system is configured to postpone updating its cache state in response to receiving a data request from the processor until the data request is non-speculative. [Diagram 2] FIG. 2 is a diagram of an exemplary instruction processing circuit that may be included in the processor of FIG. 1 and includes one or more instruction pipelines for processing computer instructions for execution, the instruction processing circuit including a control flow prediction circuit configured to speculatively predict the state of conditional flow control instructions fetched and processed by the instruction processing circuit. [Diagram 3] 2 is a diagram of an exemplary non-speculative cache memory in the cache memory system of FIG. 1. [Figure 4] 5 is a flowchart illustrating an exemplary process by which a cache controller in the cache memory of FIG. 3 defers updating a cache state of data for a received data request that is speculative, and updates the deferred cache state in the main data array for the data associated with the data request in response to the data request becoming non-speculative. [Figure 5A] FIG. 1 illustrates the processor issuing a data request to a cache memory system resulting in a cache hit in the main data array of the cache memory, and the cache controller of the cache memory allocating an entry in a speculative access record (SAR) circuit associated with a load instruction processed by the processor that generated the data request to record a cache state update deferral for the cache entry in the main data array that stores the speculatively requested data. [Figure 5B]The cache memory of FIG. 3 receives a non-speculative indicator from the processor indicating that a load instruction processed by the processor has become non-speculative, and a cache controller of the cache memory accesses a recorded cache state update deferral associated with the load instruction that has become non-speculative, thereby indicating that the cache state of a cache entry in the main data array that stores the speculatively requested data is to be updated. [Figure 6A] The processor of FIG. 1 issues a data request to a cache memory system resulting in a cache miss in a main data array of the cache memory, and an allocated entry in a speculative access record (SAR) circuit stores an index associated with an instruction associated with the data request in a buffer entry in a speculative buffer memory allocated for storing cache data for the data request to record a cache state update deferral for the data request. [Figure 6B] The cache memory of FIG. 3 receives a non-speculative indicator from the processor indicating that a load instruction processed by the processor has become non-speculative, and in response, a cache controller in the cache memory accesses a recorded cache state update deferral associated with the load instruction in a speculative buffer memory indexed by an entry in the SAR circuit associated with the instruction associated with the data request to update the cache state of a cache entry in the main data array that stores the requested data. [Figure 7A]7A-7D show an example of the processor of FIG. 1 issuing a data request to a cache memory system resulting in a cache hit and a cache miss in the main data array of the cache memory, and an exemplary process of postponing cache state updates for cache data in the main data array associated with the data request through the use of a SAR circuit configured to index a virtual fill buffer circuit, the virtual fill buffer circuit configured to index a speculative buffer memory to record the deferred cache state updates to be used in updating the cache state associated with the data request once the data request becomes non-speculative. [Figure 7B] 7A-7D show an example of the processor of FIG. 1 issuing a data request to a cache memory system resulting in a cache hit and a cache miss in the main data array of the cache memory, and an exemplary process of postponing cache state updates for cache data in the main data array associated with the data request through the use of a SAR circuit configured to index a virtual fill buffer circuit, the virtual fill buffer circuit configured to index a speculative buffer memory to record the deferred cache state updates to be used in updating the cache state associated with the data request once the data request becomes non-speculative. [Figure 7C]7A-7D show an example of the processor of FIG. 1 issuing a data request to a cache memory system resulting in a cache hit and a cache miss in the main data array of the cache memory, and an exemplary process of postponing cache state updates for cache data in the main data array associated with the data request through the use of a SAR circuit configured to index a virtual fill buffer circuit, the virtual fill buffer circuit configured to index a speculative buffer memory to record the deferred cache state updates to be used in updating the cache state associated with the data request once the data request becomes non-speculative. [Figure 7D] 7A-7D show an example of the processor of FIG. 1 issuing a data request to a cache memory system resulting in a cache hit and a cache miss in the main data array of the cache memory, and an exemplary process of postponing cache state updates for cache data in the main data array associated with the data request through the use of a SAR circuit configured to index a virtual fill buffer circuit, the virtual fill buffer circuit configured to index a speculative buffer memory to record the deferred cache state updates to be used in updating the cache state associated with the data request once the data request becomes non-speculative. [Figure 8] A block diagram of an exemplary processor-based system including a processor configured to issue memory requests to a memory system including a cache memory system and a main memory, the cache memory system including at least one cache memory, including but not limited to the cache memories of Figures 1, 3, 5A-5B, 6A-6B, and 7A-7D configured to postpone updating a cache state in response to receiving a data request from a processor until the data request is non-speculative. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Aspects disclosed herein include deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative. The processor-based system includes a processor, which may include one or more processor cores, executing computer software instructions to perform operations based on loaded data stored in a main memory. The processor-based system further includes a cache memory system including one or more private and / or shared cache memories organized in a hierarchy between the processor and the main memory. Each cache memory has a cache replacement policy that governs which data in its cache entries is evicted to a higher level cache memory or to the main memory to make room for storing new data requests (i.e., load / read requests). A load-based instruction ("load instruction") that is speculatively processed by the processor as a result of speculatively predicting the condition of a conditional flow control instruction (e.g., a conditional branch instruction) causes a data request to be made to the cache memory system. In exemplary aspects disclosed herein, at least one cache state in a cache memory is deferred from being updated in the cache memory in response to a received data request until the data request is non-speculative, since the cache memory is not updated based on a data request resulting from a misprediction that should not have been issued in the event of a misprediction, and thus the cache memory is a non-speculative cache memory.

[0017] In this way, cache pollution can be reduced. As another example, an attacker process cannot obtain information about data accesses by a victim process executing in a processor by preparing a misprediction in a control prediction circuit that causes the victim process to issue a data request that results in a speculatively modified cache state in the cache memory. If a data request that is not resolved as non-speculative can modify the cache state in the cache memory, an attacker application may gain understanding about data accesses by a victim process by understanding the modified cache state in the cache memory.

[0018] FIG. 1 is a diagram of an exemplary processor-based system 100 including a central processing unit (CPU) or processor 102 configured to issue memory requests (i.e., data read requests and data write requests) to a memory system 104 including a cache memory system 106 and a main memory 108. For example, the main memory 108 may be a dynamic random access memory (DRAM) provided in separate DRAM chips. The processor 102 includes one or more respective CPU cores 110(1)-110(N), where "N" is a positive integer representing the number of CPU cores included in the processor 102. The processor 102 may be packaged in an integrated circuit (IC) chip 112. The cache memory system 106 includes one or more cache memories 114(1)-114(X), which may be at different tiers within the processor-based system 100, logically located between the CPU cores 110(1)-110(N) and the main memory 108, where "X" is a positive integer representing the number of CPU cores included in the processor 102. The cache memory stores or caches a subset of the data contained in the main memory 108 to provide the CPU cores 110(1)-110(N) with faster access to the data in the main memory 108 to satisfy data requests. The memory controller 116 controls access to the main memory 108.

[0019] For example, CPU cores 110(1)-110(N) as requesting devices may issue data request 118 to read data in response to processing a load instruction. Data request 118 includes a target address of the data to be read from memory. Data request 118 may further include an instruction identification (ID) that identifies the instruction that caused CPU cores 110(1)-110(N) to issue data request 118. Using CPU core 110(1) as an example, if the requested data is not in private cache memory 114(1), which may be considered a level 1 (L1) cache memory (i.e., a cache miss for cache memory 114(1)), private cache memory 114(1) sends data request 118 through interconnect bus 117 in this example to shared cache memory 114(X), which is shared by all CPU cores 110(1)-110(N), which may be a level (3) cache memory. Other shared cache memories 114(2), 114(3) with processor 102 that are shared with only a subset of CPU cores 110(1)-110(N) may also be considered level two (2) cache memories. The requested data is ultimately obtained either in cache memory 114(1)-114(X) or in main memory 108 if it is not contained in any of cache memories 114(1)-114(X). Data received by cache memory 114(1)-114(X) from a higher level cache memory 114(1)-114(X) or main memory 108 due to a cache miss causes the receiving cache memory 114(1)-114(N) to flush the cached data to the higher level memory to make room for new cached data. Each cache memory 114(1)-114(X) has a cache replacement policy that governs which of its cached data is evicted to a higher level cache memory 114(1)-114(X) or to main memory 108 to make room for storing new cache data for the data request 118 that resulted in a cache miss.

[0020] 2 illustrates an instruction processing circuit 200 provided in a CPU core 110, which may be any of the CPU cores 110(1)-110(N) of the processor 102 of FIG. 1. The instruction processing circuit 200 illustratively includes one or more instruction pipelines I0-I1 for processing fetched computer instructions 202F fetched by an instruction fetch circuit 204 for execution from a set of instructions 202 stored in an instruction cache memory 206 or an instruction memory 208. N 1. Instruction cache memory 206 may be provided as part of cache memories 114(1)-114(X) in cache memory 106 in processor-based system 100 of FIG. 1. Instruction memory 208 may be provided in or as part of main memory 108 in processor-based system 100 of FIG. 1. Instruction fetch circuitry 204 feeds one or more instruction pipelines I0-I1 as instruction stream 210 in instruction processing circuitry 200 such that fetched instructions 202F are pre-processed before they reach execution circuitry 212 for execution. N The instruction pipeline I0 to I N are provided across different processing circuits or stages of the instruction processing circuitry 200 to pre-process and process the fetched instructions 202F in a series of steps that can be executed simultaneously to increase throughput prior to execution of the fetched instructions 202F by the execution circuitry 212.

[0021] 2, instruction processing circuitry 200 includes instruction decode circuitry 214 configured to decode fetched instructions 202F fetched by instruction fetch circuitry 204 into decoded instructions 202D to determine the instruction type and operation required. N, P0, P1, ..., P2, ..., P3, ..., P4, ..., P5, ..., P6, ..., P7, ..., P8, ..., P9, ..., P10, ..., P11, ..., P12, ..., P13, ..., P14, ..., P15, ..., P16, ..., P17, ..., P18, ..., P19, ..., P20, ..., P21, ..., P22, ..., P23, ..., P24, ..., P25, ..., P26, ..., P27, ..., P28, ..., P29, ..., P30, ..., P31, ..., P32, ..., P33, ..., P40, ..., P41, ..., P42, ..., P43, ..., P44, ..., P45, ..., P46, ..., P47, ..., P48, ..., P50, ..., P51, ..., P52, ..., P53, ..., P64, ..., P65, ..., P66, ..., P67, ..., P68, ..., P70, ..., P71, ..., P72, ..., P73, ..., P74, ..., P75, ..., P86, ..., P90, ..., P91, ..., P92, ..., P103, ..., P114, ..., P125, ..., P135, ..., P145, ..., P155, ..., P166, ..., P17, ..., P18, ..., P29, ..., P295, ..., P296, ..., P30, ..., P41, ..., P51, ..., P67, ..., P71, ..., P82, ..., P93, ..., P166, ..., P17, ..., P18, ..., P19, ..., P X ) RMT218 is configured to write to each of the logical registers R0 to R P Physical register file (PRF) 222 includes a plurality of mapping entries each mapped to (i.e., associated with) a physical register 220(1)-220(X) in physical register file (PRF) 222. The mapping entries are configured to store information in the form of address pointers to point to physical registers 220(1)-220(X) in PRF 222. Each physical register 220(1)-220(X) in PRF 222 includes a data entry configured to store data for source and / or destination register operands of decoded instruction 202D.

[0022] The instruction processing circuit 200 reads the logical registers R0-R1 in the RMT 218 of the source register operands of the decoded instruction 202D to retrieve values ​​generated from the executed instruction 202E in the execution circuit 212. P The instruction processing circuit 200 further includes a register access (RACC) circuit 224 configured to access the physical registers 220(1)-220(X) in the PRF 222 based on a mapping entry mapped to the physical registers 220(1)-220(X). The RACC circuit 224 is further configured to provide a generated value retrieved from the executed decoded instruction 202E as a source register operand of the decoded instruction 202D to be executed. Furthermore, in the instruction processing circuit 200, a scheduler circuit 226 schedules the instruction pipelines I0-I Nand configured to store the decoded instruction 202D in a reservation entry until all source register operands for the decoded instruction 202D are available. K 2. The instruction processing circuit 200 issues the decoded instruction 202D, ready for execution in the instruction processing circuit 200, to the execution circuit 212. Additionally, write circuitry 228 is provided in the instruction processing circuit 200 to write back or commit values ​​generated from the executed instruction 202E to memory, such as the PRF 222, the cache memory system 106, or the main memory 108.

[0023] 2, the instruction processing circuit 200 further includes a flow control prediction circuit 230. The flow control prediction circuit 230 is configured to predict the flow of the instruction pipeline I0-I1 for execution. N 2. In addition, the flow control prediction circuit 230 is configured to speculatively predict the outcome of a condition of a fetched conditional flow control instruction 202F, such as a conditional branch instruction, that controls whether a taken or not taken path in an instruction control flow path of the instruction stream 210 is fetched. In this manner, the state of the fetched conditional flow control instruction 202F does not need to be resolved in execution by the execution circuitry 212 before the instruction processing circuitry 200 can continue to process the speculatively fetched instruction 202F. The predictions made by the flow control prediction circuitry 230 may be provided to the instruction fetch circuitry 204 as prediction information 232 for use by the instruction fetch circuitry 204 to determine the next instruction 202 to fetch.

[0024] However, when the conditional flow control instruction 202F is executed by the execution circuitry 212, if it is determined that the condition of the conditional flow control instruction 202F was mispredicted, the speculative fetched instructions 202F that were fetched after the conditional flow control instruction 202F and processed by the instruction processing circuitry 202 are flushed because these instructions should not have been processed. The instruction processing circuitry 202 is returned to the state that existed before the conditional flow control instruction 202F was processed. The speculative fetched instructions 202F that are flushed in response to a misprediction may have included load-based instructions ("load instructions") that issued speculative data requests 118 to the cache memory system 106 in the processor-based system 100 of FIG. 1. If such speculative data requests 118 resulted in a cache miss, data is evicted from the cache memory system 106 to make room for the data responses to any such speculative data requests 118. This may cause cache pollution. This may also cause security issues. For example, a malicious attacker process executing within the processor 102 may learn information about data accessed by a victim process executing within the processor 102 based on the incorrect speculative data loaded into the cache memory system 106. The malicious attacker process may prepare the cache memory system 106 with its own data and prepare the flow control prediction circuitry to mispredict the conditional flow control instruction 202F in the victim process, causing the incorrect speculative data to be loaded into the cache memory system 106. The attacker application may learn information about the victim process based on which of the prepared victim data in the cache memory system 106 is replaced with the incorrect speculative data that is loaded into the cache memory system 106.

[0025] In this regard, one or more of the cache memories 114(1)-114(X) in the cache memory system 106 in the processor-based system 100 of Figure 1 may be configured to be a non-speculative cache memory. A non-speculative cache memory is configured to postpone updating a cache state of a cache entry for a received data request 118 until the data request is non-speculative. For example, Figure 3 illustrates an example of a cache memory 114 in the processor-based system 100 of Figure 1 configured as a non-speculative cache memory 114. As shown in FIG. 3, the non-speculative cache memory 114 includes a cache controller 300, which is circuitry configured to control the operation of the non-speculative cache memory 114, including processing data requests 118 for access to cache data stored in the non-speculative cache memory 114 and providing a data response 302 for the cache data to the requestor, a fill request 304 for obtaining cache data from a higher level memory in response to a cache miss for the received data request 118, and a fill response 306 having cache data received from the higher level memory in response to the fill request 304.

[0026] Non-speculative cache memory 114 further includes a main data array 308 including a plurality of cache entries 310(0)-310(M) each configured to store cache data 314(0)-314(M) stored in memory system 104 of Figure 1 at a memory address associated with a respective tag 312(0)-312(M). Non-speculative cache memory 114 further includes a tag array 311 configured to store a plurality of tags 312(0)-312(M) corresponding to each cache entry 310(0)-310(M). Main data array 308 may further include cache replacement status 315(0)-315(M) in each respective cache entry 310(0)-310(M) to indicate the replacement status of the associated cache entry 310(0)-310(M) used by cache controller 300 to determine which cache entry 310(0)-310(M) should be evicted when new data for non-speculative data request 118 needs to be stored in main data array 308. Main data array 308 may further include valid indicator 316(0)-316(M) in each respective cache entry 310(0)-310(M) to indicate whether cache data 314(0)-314(M) is valid. Non-speculative cache memory 114 in this example further includes a speculative buffer memory 318 including a plurality of buffer entries 320(0)-320(B), each configured to store cache data 324(0)-324(B) stored in memory system 104 at a memory address associated with a respective buffer tag 322(0)-322(B). Non-speculative cache memory 114 further includes a tag array 323 configured to store buffer tags 322(0)-322(B) associated with respective buffer entries 320(0)-320(B).For example, the speculative buffer memory 318 may be a fill buffer for the non-speculative cache memory 114, acting as a staging area for incoming data in a fill response 306 in response to an issued fill request 304 to be stored in the non-speculative cache memory 114 until cache entries 310(0)-310(M) in the main data array 308 are available to store the incoming data.

[0027] 3, the speculative buffer memory 318 further includes an instruction identifier (ID) 326(0)-326(B) in each respective buffer entry 320(0)-320(B) for storing an instruction ID of a load instruction that issued the data request 118 to the non-speculative cache memory 114 to track if and when the data request 118 becomes non-speculative. The cache controller 300 is configured to update a cache state associated with the data request 118 in a cache entry 310(0)-310(M) in the main data array 308 associated with the data request 118 after the instruction that caused the data request 118 to be issued becomes non-speculative in the processor 102. As discussed in more detail below, the cache controller 300 is configured to allocate a buffer entry 320(0)-320(B) in the speculative buffer memory 318 in response to a received data request 118. The cache controller 300 is configured to initially update a respective speculative indicator (NS) 330(0)-330(B) in each buffer entry 320(0)-320(B) in a speculative state for a data request 118 received as speculative. Each buffer entry 320(0)-320(B) in the speculative buffer memory 318 further includes an in-cache indicator 332(0)-332(B) indicating whether data in the associated buffer entry 320(0)-320(B) is stored in a cache entry 310(0)-310(M) in the main data array 308, and a valid indicator 334(0)-334(B) indicating whether the buffer entry 320(0)-320(B) is valid. The non-speculative cache memory 114 is configured to receive a commit indicator 328 issued by the processor 102 that includes an instruction ID of an instruction that is non-speculative. Cache controller 300 may use the received instruction ID in commit indicator 328 to look up instruction IDs 326(0)-326(B) in speculative buffer memory 318 and update the respective non-speculative indicators (NS) 330(0)-330(B) in each buffer entry 320(0)-320(B).Cache controller 300 may then update the cache state for the data associated with data request 118 in cache entries 310(0)-310(M) in main data array 308 in response to non-speculative indicator (NS) 330(0)-330(B) for data request 118 becoming non-speculative.

[0028] For example, if load instruction 202D, which is speculatively processed based on control flow prediction in processor 102 of Figure 2, causes processor 102 to issue data request 118 for data to non-speculative cache memory 114 of Figure 3, cache controller 300 is configured to search tag array 311 for tags 312(0)-312(M) in cache entries 310(0)-310(M) associated with the target address of data request 118 to determine whether data is present for data request 118. Cache controller 300 is further configured to search speculative buffer memory 318 for buffer tags 322(0)-322(B) in tag array 323 that correspond to buffer entries 320(0)-320(B) associated with the target address of data request 118 to determine whether data is present in speculative buffer memory 318. In the event of a cache miss, where data for data request 118 is not present in either main data array 308 or speculative buffer memory 318, cache controller 300 issues a fill request 304 for the data from a higher level memory and receives the requested data as a fill response 306. Cache controller 300 may be configured to postpone updating the cache state for data request 118 by not initially storing the data received in fill response 306 to data request 118 in cache entries 310(0)-310(M) in main data array 308. Instead, data received for data request 118 may be initially stored as cache data 324(0)-324(B) in allocated buffer entries 320(0)-320(B) in speculative buffer memory 318 so as not to pollute main data array 308 with speculative data.When data request 118 becomes non-speculative, as indicated by an instruction ID in commit indicator 328 matching an instruction ID 326(0)-326(B) in buffer entries 320(0)-320(B) in speculative buffer memory 318, cache controller 300 can cause the data for data request 118 to be stored in an assigned cache entry 310(0)-310(M) in main data array 308.

[0029] In another example, a cache hit results when the target address of data request 118 corresponds to a matching tag 312(0)-312(M) in tag array 311 in non-speculative cache memory 114. This means that the data for data request 118 is already contained in cache entries 310(0)-310(M) in main data array 308 that correspond to the matching tag 312(0)-312(M). The cache data 314(0)-314(M) for data request 118 stored in respective cache entries 310(0)-310(M) is returned to the requestor in processor 102 as data response 302. However, updating of cache replacement states 315(0)-315(M) of cache entries 310(0)-310(M) with cache data 314(0)-314(M) for data request 118 may be deferred until data request 118 becomes non-speculative. This is because, for example, the replacement policy of non-speculative cache memory 114 is not executed based on the replacement cache state for cache entries 310(0)-310(M) in main data array 308 that has been modified by a speculative data request 118 that may be flushed within processor 102 due to a misprediction that invalidates the update of the cache state.

[0030] In another example, if a data request 118 issued by processor 102 to non-speculative cache memory 114 is not included in cache entries 310(0)-310(M) in main data array 308, but is included in buffer entries 320(0)-320(B) in speculative buffer memory 318, then corresponding cache data 324(0)-324(B) for data request 118 is returned to the requestor in processor 102 as data response 302. However, cache controller 300 may be configured to postpone updating the cache state for data request 118 by not storing the data in speculative buffer memory 318 for data request 118 in cache entries 310(0)-310(M) in main data array 308 so as not to pollute the main data array 308 with speculative data. Once data request 118 becomes non-speculative, as indicated by an instruction ID in commit indicator 328 matching an instruction ID 326(0)-326(B) in buffer entry 320(0)-320(B) in speculative buffer memory 318, cache controller 300 may store data for data request 118 in an allocated cache entry 310(0)-310(M) in main data array 308. Thus, as another example, if a later cache hit occurs on such an allocated cache entry 310(0)-310(M) for a new subsequent data request 118, updating of cache replacement states 315(0)-315(M) of cache entries 310(0)-310(M) in main data array 308 with cache data 314(0)-314(M) for data request 118 is deferred until data request 118 becomes non-speculative, as discussed above for cache hits to main data array 308.

[0031] FIG. 4 is a flow chart illustrating an exemplary process 400 of the cache controller 300 in the non-speculative cache memory 114 of FIG. 3 for postponing updating a cache state of data for a received data request 118 that is speculative. The process 400 of FIG. 4 further includes updating the postponed cache state in the main data array 308 for the data associated with the data request 118 in response to the data request 118 becoming non-speculative. The process 400 of FIG. 4 will be discussed in conjunction with the non-speculative cache memory 114 of FIG. 3 and the processor 102 of FIGS. 1 and 2. In this regard, the non-speculative cache memory 114 receives the data request 118 from a requestor that includes a target address and an instruction identification (ID) that identifies a load instruction that includes the target address to be processed by the processor 102 (block 402 of FIG. 4). The cache controller 300 searches the tag array 311 for a tag 312(0)-312(M) associated with the target address of the data request 118 (block 404 of FIG. 4). Cache controller 300 further searches speculative buffer memory 318 for buffer tags 322(0)-322(B) associated with the target address of data request 118 (block 406 of FIG. 4). Cache controller 300 transmits data response 302 for data request 118 to the requester in processor 102 based on tags 312(0)-312(M) in cache entries 310(0)-310(M) in main data array 308 being associated with the target address and buffer tags 322(0)-322(B) in tag array 323 in speculative buffer memory 318 being associated with the target address of data request 118 (block 408 of FIG. 4). Cache controller 300 receives commit indicator 328 including instruction IDs of instructions that are non-speculative (block 410 of FIG. 4).In response to the received instruction ID in commit indicator 328 indicating that the load instruction of data request 118 is non-speculative, cache controller 300 updates the cache state of cache entries 310(0)-310(M) in main data array 308 associated with the target address of data request 118 (block 412 of FIG. 4).

[0032] As discussed in more detail below, non-speculative cache memory 114 may further include a speculative access record (SAR) circuit 336 to track whether data associated with a data request 118 that is not yet known to be non-speculative is contained in main data array 308 or speculative buffer memory 318. As discussed above, data for a received data request 118 may already be contained in main data array 308, potentially resulting in a cache hit, already contained in speculative buffer memory 318, potentially also resulting in a cache hit, or neither, potentially resulting in a cache miss. In the event of a cache miss, buffer entries 320(0)-320(B) for storing the data for data request 118 are allocated in speculative buffer memory 318. Thus, data for data request 118 may be stored in either main data array 308 or speculative buffer memory 318. In response to receiving a commit indicator 328 indicating the instruction ID of an instruction committed by processor 102, cache controller 300 needs a way to determine whether data associated with a data request 118 issued as a result of an instruction matching the instruction ID is stored in main data array 308 or speculative buffer memory 318 so that the cache controller can update the cache state accordingly. If the data associated with the committed instruction identified by the instruction ID in commit indicator 328 is stored in main data array 308, cache controller 300 needs to update the cache state of cache entries 310(0)-310(M) in main data array 308 that store data for the committed data request 118. If the data associated with the committed instruction identified by the instruction ID in commit indicator 328 is stored in speculative buffer memory 318, cache controller 300 needs to update the non-speculative indicators (NS) 330(0)-330(B) of buffer entries 320(0)-320(B) in speculative buffer memory 318.Cache controller 300 updates the non-speculative indicators (NS) 330(0)-330(B) of buffer entries 320(0)-320(B) associated with the instruction ID as non-speculative, such that the data associated with the committed data request 118 is written to main data array 308 as non-speculative data.

[0033] 3, non-speculative cache memory 114 includes a SAR circuit 336 configured to store SAR entries 338(0)-338(S) associated with respective instruction IDs 340(0)-340(S). When a data request 118 is received, cache controller 300 allocates an allocated SAR entry 338(0)-338(S) within SAR circuit 336 that is associated with the instruction ID of the instruction that issued data request 118. If the data associated with the command identified by the command ID of the received data request 118 is already stored in a cache entry 310(0)-310(M) in the main data array 308, then the main data array (MDA) index 342(0)-342(S) for the assigned SAR entry 338(0)-338(S) is updated with an index to the cache entry 310(0)-310(M) in the main data array 308 that contains the data for the data request 118. If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in cache entries 310(0)-310(M) in main data array 308, but is stored in buffer entries 320(0)-320(B) in speculative buffer memory 318, then speculative buffer (SB) index 344(0)-344(S) for the assigned SAR entry 338(0)-338(S) is updated with an index to buffer entry 320(0)-320(B) in speculative buffer memory 318 that contains the data for data request 118.If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in cache entry 310(0)-310(M) in main data array 308 or buffer entry 320(0)-320(B) in speculative buffer memory 318, resulting in a cache miss, then speculative buffer (SB) index 344(0)-344(S) for the assigned SAR entry 338(0)-338(S) is updated with an index to buffer entry 320(0)-320(B) in speculative buffer memory 318 that contains the data for the data request 118 received from the fill response 306 from a higher level memory in response to the fill request 304. As discussed above, by allocating SAR entries 338(0)-338(S) for data requests 118 in SAR circuit 336, cache controller 300 can determine whether to update the cache state of data associated with data requests 118 that have become non-speculative in main data array 308 or speculative buffer memory 318.

[0034] 5A and 5B are provided to illustrate an example of the use of the SAR circuit 336 by the non-speculative cache memory 114 to track recorded speculative data requests and enable deferring updating the cache state in the non-speculative cache memory 114 until the data request becomes non-speculative. FIG. 5A illustrates the processor 102 of FIG. 1 issuing a data request 118 including an instruction ID and a target address that is received by the non-speculative cache memory 114, resulting in a cache hit in the main data array 308 of the speculative cache memory 114. In this example, the instruction ID of the data request 118 that identifies the processing instruction that caused the data request 118 to be issued is instruction ID1. The cache controller 300 in the non-speculative cache memory 114 is configured to search the main data array 308 and the speculative buffer memory 318 for data corresponding to the target address of the data request 118. In this example, the data corresponding to the target address of the data request 118 is included in the main data array 308 and a cache hit results. Data for data request 118 in main data array 308 is returned to the requestor in processor 102 as data response 302. However, the instruction identified by instruction ID1 that caused data request 118 to be issued is considered speculative until commit indicator 328 is received by non-speculative cache memory 114 indicating otherwise, as previously discussed. Cache controller 300 in non-speculative cache memory 114 is configured, as depicted in FIG. 5A , to allocate SAR entry 338(1) in SAR circuit 336 associated with instruction ID1 to record the deferral of a cache state update in main data array 308 for data request 118. As shown in FIG. 5A , instruction ID1 is stored in instruction ID 340(1) of SAR entry 338(1).Because data request 118 resulted in a cache hit against main data array 308 in non-speculative cache memory 114, the cache set / way of "12 / 4" of cache entries 310(0)-310(M) in main data array 308 that contains data for data request 118 is stored in MDA index 342(1). In this regard, cache controller 300 can later locate and update the cache state of cache entries 310(0)-310(M) in main data array 308 based on MDA index 342(1) when instruction ID1 is indicated as committed according to received commit indicator 328. Note that a null is stored in SB index 344(1) of SAR entry 338(1) because the data for data request 118 is in main data array 308 and not in speculative buffer memory 318. Note that in this example, SAR entry 338(0) records in SB index 344(0) the location of the data for previous data request 118, which corresponds to entry 1 in speculative buffer memory 318. Note further that allocated SAR entries 338(0)-338(S) may be optionally augmented by cache controller 300 with information related to delayed cache replacement policy updates. For example, SAR entries 338(0)-338(S) may be marked as the most recently used (MRU) entries in a least recently used (LRU) cache replacement policy.

[0035] FIG 5B illustrates an example in which processor 102 of FIG 5A receives commit indicator 328 identifying instruction ID1 as being committed. In response, cache controller 300 is configured to search SAR circuit 336 to determine whether SAR entry 338 includes instruction ID1 in instruction IDs 340(0)-340(S) indicating that updating of the cache state for data request 118 associated with instruction ID1 has been deferred. In this example, instruction ID1 is included in SAR entry 338(1) in response to the received data request 118 being caused by processing instruction ID1, as shown in FIG 5A and described above. In response to determining that instruction ID1 is included in SAR entry 338(1), cache controller 300 is configured to update cache replacement states 315(0)-315(M) in cache entries 310(0)-310(M) in main data array 308 indexed by MDA index 342(1). This is because cache entries 310(0)-310(M) in main data array 308 indexed by MDA index 342(1) for the instruction ID are no longer speculative according to the received commit indicator 328. In response to receiving commit indicator 328 indicating that instruction ID1 is committed, cache controller 300 can deallocate SAR entry 338(1) to make room for recording the delayed cache update status of a future received data request 118.

[0036] 6A and 6B are provided to illustrate an example of the use of the SAR circuit 336 and the speculative buffer memory 318 in the non-speculative cache memory 114 to track recorded speculative data requests and enable deferring updating the cache state in the non-speculative cache memory 114 until the data request becomes non-speculative. FIG. 6A illustrates the processor 102 of FIG. 1 issuing a data request 118 including an instruction ID and a target address that is received by the non-speculative cache memory 114, resulting in a cache miss to the main data array 308 and the speculative buffer memory 318. In this example, the instruction ID in the data request 118 that identifies the processing instruction that caused the data request 118 to be issued is instruction ID 7. The cache controller 300 in the non-speculative cache memory 114 is configured to search the main data array 308 and the speculative buffer memory 318 for data corresponding to the target address of the data request 118. In this example, the data corresponding to the target address of data request 118 is not contained in either main data array 308 or speculative buffer memory 318 of non-speculative cache memory 114. The instruction identified by instruction ID1 that caused data request 118 to be issued is considered speculative until a commit indicator 328, as previously discussed, is received by non-speculative cache memory 114 indicating otherwise.

[0037] 6A, cache controller 300 in non-speculative cache memory 114 is configured to allocate an available buffer entry 320(7) in speculative buffer memory 318, which in this example is index 7, so that data for data request 118 associated with instruction ID1 and stored in speculative buffer memory 318 in a speculative state in response to fill response 306 received from a higher level memory can be retrieved by cache controller 300 and installed in main data array 308 when data request 118 becomes non-speculative. In-cache indicator 332(7) in buffer entry 320(7) is set to "0", which in this example means that data associated with received data request 118 is not included in main data array 308. Non-speculative indicator 330(7) for buffer entry 320(7) is set to "0", which in this example indicates a speculative state. Valid indicator 334(7) is set to “1,” which in this example indicates that buffer entry 320(7) is valid. If buffer entries 320(0)-320(B) are not available in speculative buffer memory 318, cache controller 300 may be configured to send a retry indicator to the requestor in processor 102 as data response 302 to instruct the requestor to retry data request 118 at a later time. This provides further time for data requests 118 with recorded deferred cache state updates stored in speculative buffer memory 318 to become non-speculative, which then allows their respective buffer entries 320(0)-320(B) to be used and / or reallocated, as discussed in more detail below with respect to FIG.

[0038] 6A , cache controller 300 in non-speculative cache memory 114 is further configured to allocate SAR entry 338(0) in SAR circuit 336 associated with instruction ID1 to record a deferral of a cache state update in main data array 308 for data request 118. As shown in FIG. 6A , instruction ID1 is stored in instruction ID 340(0) of SAR entry 338(0). Because data request 118 resulted in a cache miss, MDA index 342(0) contains a null because no data for data request 118 is stored in main data array 308. In this example, an SB index of “7” is stored in SB index 344(0), pointing to allocated buffer entry 320(7) in speculative buffer memory 318 that records the speculative state of data request 118 associated with instruction ID1. In this regard, cache controller 300 may then search within SAR circuitry 336 for instruction ID1 when its associated data request 118 becomes non-speculative and determine buffer entries 320(0)-320(B) and update their respective speculative indicators 330(7) to a non-speculative state. Note that a null is stored in MDA index 342(0) of SAR entry 338(1) because no data for data request 118 is included in main data array 308. Cache controller 300 is configured to write data for data request 118 associated with the instruction ID included in buffer entries 320(0)-320(B) in speculative buffer memory 318 having speculative indicator 330(7) as a non-speculative state. FIG. 6B illustrates an example in which processor 102 of FIG. 6A receives a commit indicator 328 that identifies instruction ID1 as committed. In response, cache controller 300 is configured to search SAR circuit 336 to determine whether SAR entry 338 includes instruction ID 1 within instruction IDs 340(0)-340(S) indicating that the cache state update for data request 118 associated with instruction ID 1 has been deferred.In this example, instruction ID1 is included in SAR entry 338(0) in response to received data request 118 being caused by processing instruction ID1, as shown in FIG. 6A and described above. In response to determining that instruction ID1 is included in SAR entry 338(0), cache controller 300 is configured to reference SB index 344(0) to determine buffer entries 320(0)-320(B) associated with instruction ID1. In this example, SB index 344(0) stores an index of “7” and points to buffer entry 320(7) in speculative buffer memory 318. Non-speculative indicator 330(7) is set to a non-speculative state, which in this example is “1”. In this manner, cache controller 300 may write data associated with data request 118 of instruction ID1 recorded in buffer entry 320(7) into main data array 308. Cache controller 300 may wait to write data associated with data request 118 of instruction ID1 recorded in buffer entry 320(7) in main data array 308 while a new buffer entry 320(0)-320(B) needs to be allocated in speculative buffer memory 318 and there are no free buffer entries 320(0)-320(B). The data associated with data request 118 of instruction ID1 may remain in buffer entry 320(7) because a subsequent data request 118 for the same data, based on its target address, may be satisfied as a cache hit from speculative buffer memory 318, as previously described. When cache controller 300 writes the data associated with data request 118 of instruction ID1 recorded in buffer entry 320(7) in main data array 308, in-cache indicator 332(7) is set to indicate that the data is stored in main data array 308 with a “1” indicator.Thus, when cache controller 300 needs to allocate a new buffer entry 320(0)-320(B) in speculative buffer memory 318 for a new data request 118, cache controller 300 may search, in this example, for buffer entries 320(0)-320(B) that have their in-cache indicator set to "1." This means that the data in buffer entries 320(0)-320(B) is written to main data array 308 as non-speculative data, and thus the associated buffer entries 320(0)-320(B) can be deallocated and / or reallocated.

[0039] With respect to the SAR circuit 336 and speculative buffer memory 318 of FIG. 3 and the update of the speculative state of the tracked data requests 118 in the example of FIG. 6B to a non-speculative state, the instruction ID that becomes non-speculative eventually triggers the cache controller 300 to write the data for the data request 118 associated with the instruction ID to the main data array 308. As discussed above, the buffer entry 320(0)-320(B) in the speculative buffer memory 318 for the instruction ID that became non-speculative and its associated mapped SAR entry 338(0)-338(S) are deallocated in the speculative buffer memory 318 to make it available for another data request 118. However, other instruction IDs may be assigned to the SAR entries 338(0)-338(S) in the SAR circuit 336 that are mapped to the same buffer entries 320(0)-320(M) in the speculative buffer memory 318. For example, multiple data requests 118 may have the same target address. If a buffer entry 320(0)-320(M) in the speculative buffer memory 318 that is mapped to multiple SAR entries 338(0)-338(S) is deallocated, the remaining SAR entries 338(0)-338(S) that are mapped to the same buffer entry 320(0)-320(M) in the speculative buffer memory 318 do not know that they point to the deallocated buffer entry 320(0)-320(M). Thus, an instruction ID associated with such a SAR entry 338(0)-338(S) that subsequently becomes non-speculative loses its mapping to the speculative buffer memory 318 and is unable to update its associated cache state. As discussed below, one way to address this issue is to provide another level of indirection of the mapping between the SAR circuit 336 and the speculative buffer memory 318.

[0040] The SAR circuit 336 discussed above for tracking the speculative state of data requests 118 received by non-speculative cache memory 114 may also be used in combination with a virtual fill buffer (VFB) circuit. As discussed below, the virtual fill buffer (VFB) circuit may be used to map SAR entries 338(0)-338(S) to buffer entries 320(0)-320(B) in speculative buffer memory 318. The VFB circuit may be used to track whether data associated with buffer entries 320(0)-320(B) in speculative buffer memory 318 has become non-speculative and been written to main data array 308, thereby allowing other instruction IDs to remain mapped to the VFB circuit. The VFB circuitry can track whether buffer entries 320(0)-320(B) in speculative buffer memory 318 associated with instruction IDs that remain mapped from SAR circuit 336 to the VFB circuitry have been written to main data array 308, so that cache state updates for such other mapped instruction IDs can be updated directly to main data array 308 because the associated buffer entries 320(0)-320(B) in speculative buffer memory 318 have been deallocated.

[0041] With reference to non-speculative cache memory 114 of Figure 3, and with regard to Figures 6A and 6B, it is noted that when a cache entry 310(0)-310(M) is evicted from main data array 308 by cache controller 300, cache controller 300 may also update buffer entries 320(0)-320(B) in speculative buffer memory 318. For example, if a particular cache entry 310(0)-310(M) (e.g., by its set / way) in main data array 308 is identified as a victim entry to be evicted by cache controller 300, cache controller 300 may be configured to search buffer entries 320(0)-320(B) to determine whether there are any buffer entries 320(0)-320(B) in speculative buffer memory 318 that correspond to the cache entry 310(0)-310(M) being evicted. If so, such corresponding buffer entries 320(0)-320(B) may be invalidated by setting their respective valid indicators 334(0)-334(B) to an invalid state (e.g., a "0" state). In this manner, when a new data request 118 having a target address corresponding to an evicted cache entry 310(0)-310(M) is received at non-speculative cache memory 114 that would result in a cache miss to main data array 308, a cache hit will not erroneously occur in speculative buffer memory 318. In this regard, FIGS. 7A-7D illustrate an example in which processor 102 of FIG. 1 issues a data request 118 that is received by non-speculative cache memory 114 in cache memory system 106. In this example, the non-speculative cache memory includes an alternative SAR circuit 700 that can be mapped to entries in a virtual fill buffer (VFB) circuit 708 that is mapped to the speculative buffer memory 318 to track speculative data requests 118 and update the cache state of such requests in the main data array 308 as they become non-speculative.In this example, as shown in FIG. 7A, three data requests 118 are made to non-speculative cache memory 114, identified by three instruction IDs as instruction IDs 1, 4, and 8. Cache controller 300 in non-speculative cache memory 114 is configured to search main data array 308 and speculative buffer memory 318 for data corresponding to the target addresses of these three data requests 118. In this example, data corresponding to the target address of data request 118 with instruction ID 1 is not contained in either main data array 308 or speculative buffer memory 318 of non-speculative cache memory 114, resulting in a cache miss. Cache controller 300 allocates SAR entry 702(0) of SAR circuit 700 shown in FIG. 7A, similar to SAR circuit 336 of FIG. 3. Instruction ID 1 is stored in instruction ID 704(0) of SAR entry 702(0). Cache controller 300 further allocates VFB entry 710(7) in VFB circuit 708 shown in FIG. 7A. An index “7” corresponding to the allocated VFB entry 710(7) is stored in VFB index 706(0) in SAR circuit 700, mapping SAR entry 702(0) for instruction ID1 to VFB entry 710(7) in VFB circuit 708. In-cache indicator 714(7) in SAR entry 702(7) is set to the data associated with data request 118 initiated from instruction ID1 as not being in main data array 308 because data request 118 for instruction ID1 resulted in a cache miss. Thus, MDA index 716(7) in VFB entry 710(7) is set to “0” or null to not point to a location in main data array 308. However, speculative buffer (SB) index 718(7) in VFB circuit 708 is set to index “4,” mapping VFB entry 710(7) to buffer entry 320(4) in speculative buffer memory 318 that contains the data received from fill response 306 into the allocated buffer entry 320(4) in speculative buffer memory 318.

[0042] Cache controller 300 in non-speculative cache memory 114 is further configured to search main data array 308 and speculative buffer memory 318 for data corresponding to the target addresses of data requests 118 of instructions IDs 4 and 8. In this example, both of these searches result in a cache hit against speculative buffer memory 318 because these instructions are for the same target address as for data request 118 of instruction ID 1, and cache controller 300 filled this data from fill response 306 into buffer entry 320(4) in speculative buffer memory 318. Thus, SAR entries 702(0) and 702(2) having instruction IDs 1 and 7 in instruction IDs 704(0) and 704(2) are also both mapped to VFB index "7" in their respective VFB indexes 706(0), 706(2). Thus, by providing VFB circuitry 708, multiple SAR entries, in this example SAR entries 702(1)-702(2), can be mapped to the same VFB index, which can then be mapped to buffer entries 320(0)-320(B) in speculative buffer memory 318 to provide another level of mapping indirection.

[0043] Additionally, it is noted that, optionally, when a current SAR entry 702(0)-702(S) in the SAR circuit 700 is allocated in response to a new data request 118, if there is an older SAR entry 702(0)-702(S) that points to the same VFB entry 710 in the VFB circuit 708, the current SAR entry 702(0)-702(S) may be collapsed into the older SAR entry 702(0)-702(S). The current SAR entry 702(0)-702(S) may replace the older SAR entry 702(0)-702(S), or may be ignored such that a new SAR entry 702(0)-702(S) is not allocated. For example, in SAR circuit 700 of FIG. 7B, if SAR entries 702(0) and 702(1) are both associated with instruction ID1, then both SAR entries 702(0), 702(1) may be provided as one SAR entry 702 because they both point to the same VFB entry 710(7). As shown in FIG. 7B, non-speculative cache memory 114 in this example receives commit indicator 328 for instruction ID1 to indicate that instruction ID1 has been committed within processor 102, and thus, the data associated with data request 118 for instruction ID1 in buffer entry 320(4) in speculative buffer memory 318 is now non-speculative. In this regard, cache controller 300 changes NS indicator 330(4) for buffer entry 320(4) to “1” to indicate that this entry is non-speculative. As further shown in FIG. 7C , cache controller 300 also changes in-cache indicator 332(4) in buffer entry 320(4) to “1” to indicate that the data associated with data request 118 for instruction ID1 is included in main data array 308 in response to the data being received from higher level memory in data response 302.When buffer entry 320(4) is retired, cache controller 300 can write data associated with data request 118 for instruction ID 1 recorded in buffer entry 320(4) into main data array 308 based on its NS indicator 330(4), which indicates a non-speculative state, as shown in FIGURE 7C. As shown in FIGURE 7D, instruction IDs 4 and 8 in SAR entries 702(0), 702(1), which are mapped to VFB entry 710(7), can use in-cache indicator 714(7) and MDA index 716(7) to know the location of cache entries 310(0)-310(M) to update when instructions IDs 4 and 8 become non-speculative. Thus, if buffer entry 320(4) is deallocated by cache controller 300 before instructions IDs 4 and 8 become non-speculative, VFB circuit 708 maintains the necessary information for the cache state for the data of data request 118 associated with instruction IDs 4 and 8 to be updated in main data array 308 using in-cache indicator 714(7) and MDA index 716(7).

[0044] For any of the above described examples, note that the NS indicators 330(0)-330(B) in the speculative buffer memory 318 in the non-speculative cache memory 114 can further be used by the cache controller 300 to affect the order in which the buffer entries 320(0)-320(B) are evicted from the speculative buffer memory 318. Recall that upon evicting the buffer entries 320(0)-320(B), if the NS indicators 330(0)-330(B) are set to a non-speculative state for the buffer entries 320(0)-320(B), the corresponding data in the buffer entries 320(0)-320(B) is written to the main memory 108, otherwise the buffer entries 320(0)-320(B) are discarded. Assuming a base fill buffer replacement policy (e.g., FIFO, LRU, PLRU, MRU, random, SRRIP, DRRIP, etc.), any enhanced replacement policy can be utilized. If the NS indicators 330(0)-330(B) for all buffer entries 320(0)-320(B) are marked non-speculative, then a base replacement policy may be utilized by cache controller 300 to replace buffer entries 320(0)-320(B). If the NS indicators 330(0)-330(B) for one buffer entry 320(0)-320(B) are marked non-speculative, then such buffer entry 320(0)-320(B) may be replaced first. If the NS indicators 330(0)-330(B) for multiple buffer entries 320(0)-320(B) are marked non-speculative, then a base replacement policy may be applied to all buffer entries 320(0)-320(B) having NS indicators 330(0)-330(B) marked non-speculative.If all buffer entries 320(0)-320(B) have NS indicators 330(0)-330(B) marked as speculative, then, by way of example, any of the following replacement policies may be utilized: base replacement policy, select most recently used (MRU) buffer entry 320(0)-320(B), select least recently used (LRU) buffer entry 320(0)-320(B), select most recently inserted buffer entry 320(0)-320(B), select first inserted buffer entry 320(0)-320(B), and select random buffer entry 320(0)-320(B). A combination of the above replacement policies may be selected based on additional meta-information about the cache line requestor (e.g., MRU if likely to be flushed or LRU if streamed).

[0045] Additionally, if the non-speculative cache memory 114 can receive data requests 118 from multiple CPU cores 110(1)-110(N), the SAR circuit 336, 700 can be implemented to maintain a record of all data accesses for the data requests 118 and an identification of the CPU core 110(0)-110(N) as the requestor. The VFB circuit 708 can be shared among the multiple CPU cores 110(1)-110(N). In response to the data requests 118, the non-speculative cache memory 114 can be configured to send back a commit identification to enable a target commit message by the CPU core 110(1)-110(N) to be sent to the non-speculative cache memory 114(1)-114(X). This can reduce traffic on the interconnect bus 117 between the CPU cores 110(0)-110(N) and the cache memories 114(1)-114(X) of FIG. 1. Additionally, instead of sending one commit message for each non-speculative data request 118, processor 102 may also send a bundle message of instruction commit information to reduce traffic on interconnect bus 117. The bundling of instruction commit information may be explicit, where each instruction ID of a data request 118 is specified in the bundle message, or may be implicit, where the instruction ID indicates that all instruction IDs less than the non-speculative instruction ID are also non-speculative.

[0046] 8 is a block diagram of an exemplary processor-based system 800 including a processor 802 (e.g., a microprocessor) including an instruction processing circuit 804. The processor-based system 800 can be, by way of example, the processor-based system 100 of FIG. 1. The instruction processing circuit 804 can be, by way of example, the instruction processing circuit 200 of FIG. 2. The processor-based system 800 can be one or more circuits included in a printed circuit board (PCB), an electronic board card such as a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. The processor 802 represents one or more general-purpose processing circuits such as a microprocessor, a central processing unit, or the like. More specifically, the processor 802 can be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for communicating generated values ​​resulting from the execution of producer instructions. Processor 802 is configured to execute instruction processing logic to perform the operations and steps discussed herein. In this example, processor 802 includes an instruction cache 808 for temporary, fast access memory storage of instructions accessible by instruction processing circuitry 804. Instructions fetched or prefetched from memory, for example from main memory 810 over system bus 812, are stored in instruction cache 808. Instruction processing circuitry 804 is configured to process instructions fetched into instruction cache 808 and process the instructions for execution.

[0047] The processor 802 may include a local cache memory 814 and store cached data in the main memory 810. A cache memory 816 external to the processor 802 between the local cache memory 814 and the main memory 810 may also be provided to provide a cache memory system 818. The cache memories 814, 816 in the cache memory system 818 may include any of the cache memories 114(1)-114(X) of FIGS. 1, 3, 5A-5B, 6A-6B, and 7A-7D and may be configured to defer updating a cache state in response to receiving a data request from the processor 802 until the data request is non-speculative.

[0048] The processor 802 and the main memory 810 are coupled to a system bus 812, which may interconnect peripheral devices included in the processor-based system 800. As is well known, the processor 800 communicates with these other devices by exchanging address, control, and data information through the system bus 812. For example, the processor 802 may communicate bus transaction requests to a memory controller 819 in the main memory 810, as an example of a slave device. Although not shown in FIG. 8, multiple system buses 812 may be provided, with each system bus constituting a different fabric. In this example, the memory controller 819 is configured to provide memory access requests to a memory array 820 in the main memory 810. The memory array 820 includes an array of storage bit cells for storing data. The main memory 810 may be, by way of non-limiting example, a read only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as a synchronous DRAM (SDRAM), and the like, and a static memory (e.g., a flash memory, a static random access memory (SRAM), and the like).

[0049] Other devices may be connected to the system bus 812. As shown in FIG. 8, these devices may include, by way of example, a main memory 810, one or more input devices 822, one or more output devices 824, a modem 826, and one or more display controllers 828. The input devices 822 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output devices 824 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The modem 826 may be any device configured to enable the exchange of data to and from a network 830. The network 830 may include, but is not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH® network, or the like. TM The communication protocol may be any type of network, including a network, a network, or the Internet. The modem 826 may be configured to support any type of communication protocol desired. Additionally, the processor 802 may be configured to access a display controller 828 through the system bus 812 to control information sent to one or more displays 832. The display 832 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0050] 8 may include a set of instructions 834 that are executed by the processor 802 for any application desired in accordance with the instructions. The instructions 834 may be stored in the main memory 810, the processor 802, and / or the instruction cache 808 as examples of non-transitory computer-readable media 836. The instructions 834 may further reside, completely or at least partially, within the main memory 810 and / or within the processor 802 during execution thereof. The instructions 834 may further be transmitted or received over the network 830 via the modem 826 such that the network 830 includes the computer-readable media 836.

[0051] While the computer readable medium 836 is shown to be a single medium in one exemplary embodiment, the term "computer readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer readable medium" should further be taken to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer readable medium" should therefore be taken to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0052] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-executable instructions that cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0053] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include a machine-readable storage medium (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), etc.

[0054] Unless specifically indicated otherwise, and as is apparent from the preceding discussion, discussions using terms such as "processing," "calculating," "determining," "displaying," and the like throughout this description are understood to refer to operations and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data that is similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display device.

[0055] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. A variety of systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Further, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0056] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or other computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be utilized in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memories disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, the various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is realized depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0057] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be realized as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0058] The embodiments disclosed herein may be embodied in hardware and in instructions stored in the hardware, such as in a RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as separate components in a remote station, base station, or server.

[0059] Furthermore, it should be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the illustrated sequence. Furthermore, an operation described as a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps discussed in the exemplary embodiments may be combined. Furthermore, those skilled in the art will understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0060] Unless expressly indicated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order to be followed by its steps, or unless it is otherwise specifically indicated in the claim or description that the steps are to be limited to a particular order, no particular order is intended to be inferred.

[0061] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments incorporating the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed to include everything within the scope of the appended claims and their equivalents.

Claims

1. 1. A non-speculative cache memory in a processor-based system, comprising: a main data array including a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system; a speculative buffer memory including a plurality of buffer entries, each buffer entry including a data entry configured to store cache data associated with a memory address in the memory system; A cache controller, receiving a data request from a requestor, the data request including a target address and an instruction identification (ID) identifying a load instruction including the target address to be processed by a processor in the processor-based system; searching for a cache entry in the main data array associated with the target address of the data request; searching the speculative buffer memory for a buffer entry associated with the target address of the data request; sending a data response to the data request to the requestor based on whether cache data in the main data array is associated with the target address or whether cache data in a buffer entry in the speculative buffer memory is associated with the target address, the data response to the data request including data in the cache entry in the main data array associated with the target address of the data request or data in the speculative buffer memory for the buffer entry associated with the target address of the data request; receiving a commit indicator including an instruction ID of an instruction that is non-speculative; in response to a received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative; and updating a cache state of a cache entry in the main data array associated with the target address of the data request, the non-speculative cache memory including a speculative access record (SAR) circuit configured to store a SAR entry including an instruction ID entry and a main data array entry. A cache controller; Including, The cache controller further comprises: in response to a cache entry in the main data array being associated with the target address of the data request, allocating the SAR entry in the SAR circuit, the SAR entry including an instruction ID entry including the instruction ID of the load instruction of the data request, and a main data array entry including an index to a cache entry in the main data array that is associated with the target address of the data request; determining whether the received instruction ID is included in an instruction ID entry in the SAR entry in the SAR circuit in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative; in response to determining that the received instruction ID is included in the SAR entry in the SAR circuit, updating a cache replacement state of the cache entry in the main data array corresponding to the index in the main data array entry associated with the target address of the data request in the SAR entry that includes the received instruction ID. It is configured as follows: Non-speculative cache memory.

2. the cache controller is further configured to determine whether a cache entry in the main data array is associated with the target address of the data request; in response to a cache entry in the main data array being associated with the target address of the data request, the cache controller is configured to transmit to the requestor the data response to the data request, the data response including cache data in the cache entry in the main data array having the target address associated with the target address of the data request; 2. The non-speculative cache memory of claim 1.

3. 3. The non-speculative cache memory of claim 2, wherein the cache controller is configured to update the cache state including a cache replacement state of the cache entry in the main data array associated with the target address of the data request in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative.

4. the cache controller further comprises, in response to a cache entry in the main data array not being associated with the target address of the data request, determining whether a buffer entry in the speculative buffer memory is associated with the target address of the data request; in response to a buffer entry in the speculative buffer memory being associated with the target address of the data request, the cache controller is configured to transmit to the requestor the data response to the data request, the data response including cache data in the buffer entry in the speculative buffer memory having the target address associated with the target address of the data request.

3. The non-speculative cache memory of claim 2, configured to:

5. The cache controller further comprises, in response to a buffer entry in the speculative buffer memory not being associated with the target address of the data request, sending said data request to a next higher level memory within said processor-based system; receiving data for said data request from a higher level memory by said determining whether a buffer entry in the speculative buffer memory is available for storing cache data; in response to determining that a buffer entry in the speculative buffer memory is available for storing cache data, writing the data for the data request received from the next higher level memory to an available buffer entry in the speculative buffer memory and to an available buffer entry associated with the target address of the data request.

5. The non-speculative cache memory of claim 4, configured to:

6. the cache controller, in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative, writing data for the data request in the buffer entry in the speculative buffer memory associated with the target address of the data request to a cache entry in the main data array associated with the target address of the data request, thereby updating the cache state of the cache entry in the main data array associated with the target address of the data request.

6. The non-speculative cache memory of claim 5, configured to:

7. 7. The non-speculative cache memory of claim 6, wherein the cache controller is further configured to select a buffer entry from among the plurality of buffer entries in the speculative buffer memory to evict from the speculative buffer memory based on a speculative state in a non-speculative indicator of the respective buffer entry.

8. each buffer entry in the speculative buffer memory further includes a non-speculative indicator indicating whether the buffer entry is non-speculative; The cache controller further comprises: in response to a buffer entry in the speculative buffer memory being associated with the target address of the data request; setting a non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request to a speculative state; in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative, setting the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state; in response to the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request being set to a non-speculative state, writing data for the data request in the buffer entry in the speculative buffer memory associated with the target address of the data request to a cache entry in the main data array associated with the target address of the data request, thereby updating the cache state of the cache entry in the main data array associated with the target address of the data request.

6. The non-speculative cache memory of claim 5, configured to:

9. A speculative access record (SAR) circuit configured to store the SAR entries including the instruction ID entries and virtual fill buffer (VFB) index entries; a VFB circuit configured to store a VFB entry including an instruction ID entry and a VFB index entry; Further comprising: The cache controller further comprises: in response to a buffer entry in the speculative buffer memory not being associated with the target address of the data request; allocating the VFB entry in the VFB circuit, the VFB entry including an instruction ID entry including the instruction ID of the load instruction of the data request, and the VFB index entry including an index to a buffer entry in the speculative buffer memory associated with the target address of the data request; allocating the SAR entry in the SAR circuit, the SAR entry including the instruction ID entry storing the instruction ID of the load instruction of the data request and the VFB index entry storing an index to a VFB entry in the VFB circuit having an instruction ID entry including the instruction ID; in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative, determining, based on an index in the VFB index entry in a SAR entry in the SAR circuit having an instruction ID entry that includes the received instruction ID, the VFB entry in the associated VFB circuit having an instruction ID entry that includes the indexed instruction ID; determining the buffer entry in the speculative buffer memory associated with the target address of the data request set to a non-speculative state based on an index in the VFB index entry in the determined VFB entry in the VFB circuit; The cache controller configured to set the non-speculative indicator in the determined buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state.

9. The non-speculative cache memory of claim 8, configured to:

10. The cache controller further comprises, in response to allocating the SAR entry in the SAR circuit, determining whether another SAR entry included in the SAR circuit includes the instruction ID in its instruction ID entry and the VFB index entry in its VFB entry; In response to determining that the other SAR entry is included in the SAR circuit, deallocate the SAR entry within the SAR circuit.

10. The non-speculative cache memory of claim 9, configured to:

11. 2. The non-speculative cache memory of claim 1, wherein the cache controller is further configured to evict a buffer entry in the speculative buffer memory in response to a cache entry in the main data array being evicted corresponding to a memory address corresponding to the buffer entry.

12. 1. A method for updating a cache state in a non-speculative cache memory in a processor-based system, comprising: receiving a data request from a requestor, the data request including a target address and an instruction identification (ID) identifying a load instruction including the target address to be processed by a processor in the processor-based system; searching a main data array for a cache entry associated with the target address of the data request among a plurality of cache entries each configured to store cache data associated with a memory address within a memory system of the processor-based system; searching a speculative buffer memory for a buffer entry associated with the target address of the data request among a plurality of buffer entries each configured to store cache data associated with a memory address in the memory system; sending a data response to the data request to the requestor based on whether a cache entry in the main data array is associated with the target address or cache data in a buffer entry in the speculative buffer memory is associated with the target address, the data response to the data request including data in the cache entry in the main data array associated with the target address of the data request or data in the speculative buffer memory for the buffer entry associated with the target address of the data request; receiving a commit indicator including an instruction ID of an instruction that is non-speculative; updating a cache state of a cache entry in the main data array associated with the target address of the data request in response to a received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative; The method includes storing speculative access record (SAR) entries in a speculative access record (SAR) circuit, the SAR entries including an instruction ID entry and a main data array entry, the method comprising: in response to a cache entry in the main data array being associated with the target address of the data request, allocating a SAR entry in the SAR circuit, the SAR entry including an instruction ID entry including the instruction ID of the load instruction of the data request, and a main data array entry including an index to a cache entry in the main data array that is associated with the target address of the data request; in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative, determining whether the received command ID is included in a command ID entry in the SAR entry in the SAR circuit; and and in response to determining that the received instruction ID is included in the SAR entry in the SAR circuit, updating a cache replacement state of the cache entry in the main data array corresponding to the index in the main data array entry associated with the target address of the data request in the SAR entry that includes the received instruction ID. method.

13. determining whether a cache entry in the main data array is associated with the target address of the data request; 13. The method of claim 12, further comprising: in response to a cache entry in the main data array being associated with the target address of the data request, transmitting to the requestor the data response to the data request including cache data in the cache entry in the main data array having the target address associated with the target address of the data request.

14. in response to a cache entry in the main data array not being associated with the target address of the data request, determining whether a buffer entry in the speculative buffer memory is associated with the target address of the data request; transmitting the data response to the data request to the requestor, the data response including cached data in the buffer entry in the speculative buffer memory having the target address associated with the target address of the data request; The method of claim 13, further comprising:

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