Detection device

Abstract

To provide a detection device capable of improving detection accuracy.SOLUTION: A detection device includes a substrate, a plurality of transistors provided on the substrate, a plurality of scanning lines extending in a first direction, a plurality of signal lines extending in a second direction intersecting the first direction, a plurality of photodiodes each of which is provided in each of regions surrounded by a plurality of scanning lines and a plurality of signal lines and includes a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, and a shield wiring which overlaps the scanning lines and extends in the first direction. The shield wiring is electrically connected to a power signal line that supplies power potential to the transistors among the plurality of signal lines.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] Patent Document 1 describes an optical imaging device having a light-shielding layer with an opening between a microlens and a light sensor. A PIN-type photodiode is known as such a light sensor. The PIN-type photodiode has a structure in which a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer are stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0089928 Summary of the Invention [Problem to be solved by the invention]

[0004] In a PIN-type photodiode, the detection sensitivity can be improved by increasing the sensor area to increase the photocurrent. On the other hand, increasing the sensor area reduces the distance between the photodiode and the scanning line, which may increase the parasitic capacitance. This parasitic capacitance may cause variations in the output signal from the photodiode, reducing the detection accuracy.

[0005] An object of the present invention is to provide a detection device capable of improving detection accuracy. [Means for solving the problem]

[0006] A detection device of one embodiment of the present invention includes a substrate, a plurality of transistors provided on the substrate, a plurality of scanning lines extending in a first direction, a plurality of signal lines extending in a second direction intersecting the first direction, a plurality of photodiodes each provided in an area surrounded by the plurality of scanning lines and the plurality of signal lines, the photodiodes including a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, and a shield wiring overlapping the scanning lines and extending in the first direction, the shield wiring being electrically connected to a power supply signal line among the plurality of signal lines that supplies a power supply potential to the transistors.

[0007] A detection device according to one embodiment of the present invention includes a substrate, a plurality of transistors provided on the substrate, a plurality of scanning lines extending in a first direction, a plurality of signal lines extending in a second direction intersecting the first direction, a plurality of photodiodes each provided in an area surrounded by the plurality of scanning lines and the plurality of signal lines, the photodiodes including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer, and a shield wiring extending in the first direction overlapping the scanning lines and receiving a fixed potential. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to a first embodiment. [Figure 1B] FIG. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to Modification 1. As shown in FIG. [Figure 1C] FIG. 1C is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to Modification 2. As shown in FIG. [Figure 1D] FIG. 1D is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to Modification 3. As shown in FIG. [Diagram 2] FIG. 2 is a plan view showing the detection device according to the first embodiment. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a detection element. [Diagram 5] FIG. 5 is a timing waveform diagram showing an example of the operation of the detection element. [Figure 6] FIG. 6 is a plan view showing a plurality of detection elements. [Figure 7] FIG. 7 is a plan view of a photodiode included in one detection element. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. [Figure 9] FIG. 9 is a circuit diagram showing the connection relationship between a plurality of detection elements, a scanning line driving circuit, and a signal line selection circuit in the detection device according to the first embodiment. [Figure 10] FIG. 10 is a timing waveform diagram showing an example of operation during a readout period of the detection element. [Figure 11] FIG. 11 is a plan view showing a plurality of detection elements according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII' of FIG. [Figure 13] FIG. 13 is a circuit diagram showing a detection element according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The form (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present disclosure. In addition, in this disclosure and each figure, elements similar to those described above with respect to the previously mentioned figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this specification and the claims, when expressing an aspect of arranging another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is arranged directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is arranged above a certain structure via yet another structure.

[0011] Fig. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detector with an illumination device having a detector according to an embodiment. Fig. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detector with an illumination device having a detector according to a first modification. Fig. 1C is a cross-sectional view showing a schematic cross-sectional configuration of a detector with an illumination device having a detector according to a second modification. Fig. 1D is a cross-sectional view showing a schematic cross-sectional configuration of a detector with an illumination device having a detector according to a third modification.

[0012] As shown in FIG. 1A, the detection device 120 with an illumination device includes a detection device 1 and an illumination device 121. The detection device 1 includes an array substrate 2, an optical filter 7, an adhesive layer 125, and a cover member 122. That is, the array substrate 2, the optical filter 7, the adhesive layer 125, and the cover member 122 are laminated in this order in a direction perpendicular to the surface of the array substrate 2. The adhesive layer 125 may be any layer that is translucent and bonds the optical filter 7 and the cover member 122. The adhesive layer 125 may not be present in the area corresponding to the detection area AA. When the adhesive layer 125 is not present in the detection area AA, the adhesive layer 125 bonds the cover member 122 and the optical filter 7 in the area corresponding to the peripheral area GA outside the detection area AA, and an air layer is provided in the detection area AA. The adhesive layer 125 provided in the detection area AA may simply be referred to as a protective layer for the optical filter 7.

[0013] 1A, the illumination device 121 is a so-called side light type front light having a light guide plate that also serves as a cover member 122 of the detection device 1, and a plurality of light sources 123 arranged at one end or both ends of the cover member 122 (light guide plate). The cover member 122 has a light irradiation surface 121a that emits light. According to this illumination device 121, light L1 is irradiated from the light irradiation surface 121a of the cover member 122 toward a finger Fg that is a detection target. For example, a light emitting diode (LED) that emits light of a predetermined color is used as the light source.

[0014] Furthermore, as shown in FIG. 1B, the illumination device 121 may have one or more light sources (e.g., LEDs) directly above the detection area AA of the detection device 1, and the illumination device 121 equipped with a light source also functions as a cover member 122.

[0015] Furthermore, the lighting device 121 is not limited to the example of FIG. 1B, and as shown in FIG. 1C, a light source may be provided to the side or above the cover member 122, and light L1 may be irradiated onto the finger Fg from the side or above the finger Fg.

[0016] 1D, the illumination device 121 may be a so-called direct backlight having a light source (e.g., an LED) provided in the detection area of ​​the detection device 1. In this case, the light guide plate of the illumination device 121 is a separate member from the cover member 122 of the detection device 1, and is disposed below the detection device 1.

[0017] The light L1 emitted from the illumination device 121 is reflected as light L2 by the finger Fg, which is the detection target. The detection device 1 detects the light L2 reflected by the finger Fg (the shadow of the light L2 or the intensity of the reflected light) to detect the unevenness (for example, a fingerprint) on the surface of the finger Fg. Furthermore, in addition to detecting the fingerprint, the detection device 1 may detect information about the living body by detecting the light L2 reflected inside the finger Fg. The information about the living body may be, for example, an image of blood vessels such as veins, a pulse, a pulse wave, etc. The color of the light L1 from the illumination device 121 may be different depending on the detection target. In this embodiment, the detection device 1 uses the finger Fg (fingerprint) as the detection target (detection target), but the detection target may be not only the finger Fg but also any part of the living body, such as the palm, wrist, sole, etc.

[0018] The cover member 122 is a member for protecting the array substrate 2 and the optical filter 7, and covers the array substrate 2 and the optical filter 7. As described above, the cover member 122 may also serve as a light guide plate of the illumination device 121. In the structure shown in FIG. 1C and FIG. 1D in which the cover member 122 is separated from the illumination device 121, the cover member 122 is, for example, a glass substrate. Note that the cover member 122 is not limited to a glass substrate, and may be a resin substrate or a resin film, or may be a multi-layered structure in which these substrates or films are laminated. The cover member 122 may not be provided. In this case, a protective layer such as an insulating film is provided on the surfaces of the array substrate 2 and the optical filter 7, and the finger Fg comes into contact with the protective layer of the detection device 1.

[0019] The optical filter 7 is an optical element that transmits a component of the light L2 reflected by a detected object such as a finger Fg, traveling in the third direction Dz toward the photodiode 30 (see FIGS. 6 and 7) of the array substrate 2, and blocks a component traveling in an oblique direction. The optical filter 7 is also called a collimator aperture or a collimator. The optical filter 7 does not necessarily have to be provided.

[0020] As shown in FIG. 1B, the detection device 120 with the illumination device may be provided with a display panel 126 instead of the illumination device 121. The display panel 126 may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display panel (micro LED, mini LED). Alternatively, the display panel 126 may be a liquid crystal display panel (LCD: Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD: Electrophoretic Display) using electrophoretic elements as display elements. In this case, display light (light L1) irradiated from the display panel 126 is reflected by the finger Fg, and the reflected light passes through the display panel 126 and reaches the optical filter 7. In view of this, it is preferable that the display panel 126 has a light-transmitting portion composed of a light-transmitting substrate or laminated film at least in the detection area AA. Then, based on the light L2, information about the fingerprint or biological information of the finger Fg can be detected.

[0021] FIG. 2 is a plan view showing a detection device according to an embodiment. The first direction Dx shown in FIG. 2 and subsequent figures is one direction in a plane parallel to the substrate 21. The second direction Dy is one direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may not be perpendicular to the first direction Dx but may intersect with it. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the substrate 21. The plan view refers to the positional relationship when viewed from the third direction Dz.

[0022] As shown in FIG. 2, the detection device 1 includes an array substrate 2 (substrate 21), a sensor unit 10, a scanning line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0023] The control board 101 is electrically connected to the board 21 via the wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid board. The wiring board 110 is provided with a detection circuit 48. The control board 101 is provided with a control circuit 102 and a power supply circuit 103. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array) or other IC chips. The control circuit 102 supplies control signals to the sensor unit 10, the scanning line driving circuit 15, and the signal line selection circuit 16 to control the operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as a power supply potential VDD and a reference potential VCOM (see FIG. 4) to the sensor unit 10, the scanning line driving circuit 15, and the signal line selection circuit 16. In the present embodiment, the case where the detection circuit 48 is disposed on the wiring board 110 is illustrated, but is not limited to this. The detection circuit 48 may be disposed on the board 21. Also, a configuration in which the control circuit 102 and the power supply circuit 103 are partly or entirely incorporated into the detection circuit 48 can be adopted.

[0024] The substrate 21 has a detection area AA and a peripheral area GA. In the detection area AA, each element (detection element 3) of the sensor unit 10 is provided. The peripheral area GA is an area outside the detection area AA, and is an area where each element (detection element 3) is not provided. In other words, the peripheral area GA is an area between the outer periphery of the detection area AA and the outer edge of the substrate 21. In the peripheral area GA, a scanning line driving circuit 15 and a signal line selection circuit 16 are provided. The scanning line driving circuit 15 is provided in an area extending in the second direction Dy in the peripheral area GA along one of the left and right sides of the detection area AA. It is possible to adopt a configuration in which the scanning line driving circuit 15 is provided on both sides of the detection area AA along the second direction Dy as described later. The signal line selection circuit 16 is provided along the lower side of the detection area AA, and is provided between the sensor unit 10 and the detection circuit 48.

[0025] Each of the detection elements 3 of the sensor unit 10 is an optical sensor having one or more photodiodes 30 as a sensor element. The photodiodes 30 are photoelectric conversion elements, and output an electrical signal according to the light irradiated thereto. More specifically, the photodiodes 30 are PIN (Positive Intrinsic Negative) photodiodes. The photodiodes 30 may also be called OPDs (Organic Photo Diodes). The detection elements 3 are arranged in a matrix in the detection area AA. The photodiodes 30 of each detection element 3 perform detection according to a gate drive signal (e.g., a reset control signal RST, a read control signal RD) supplied from the scanning line drive circuit 15. Each photodiode 30 changes an electrical signal according to the light irradiated thereto, and the change in the electrical signal is output to the signal line selection circuit 16 as a detection signal Vdet in each detection element 3. The detection device 1 detects information about a living body based on the detection signal Vdet from each detection element 3.

[0026] Fig. 3 is a block diagram showing a configuration example of a detection device according to an embodiment. As shown in Fig. 3, the detection device 1 has a detection control circuit 11 and a detection unit 40. A part or all of the functions of the detection control circuit 11 are included in a control circuit 102. In addition, a part or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0027] The detection control circuit 11 is a circuit that supplies control signals to the scanning line driving circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV and a clock signal CK, to the scanning line driving circuit 15. The detection control circuit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16.

[0028] The scanning line driving circuit 15 is a circuit that drives a plurality of scanning lines (read control scanning line GLrd, reset control scanning line GLrst (see FIG. 4)) based on various control signals. The scanning line driving circuit 15 sequentially or simultaneously selects a plurality of scanning lines, and supplies gate driving signals (e.g., reset control signal RST, read control signal RD) to the selected scanning lines. In this way, the scanning line driving circuit 15 selects the detection element 3 connected to the scanning line.

[0029] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL (see FIG. 4). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on a selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photodiode 30 to the detection unit 40.

[0030] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, and a detection timing control circuit 47. Based on a control signal supplied from the detection control circuit 11, the detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 so that they operate in synchronization with each other.

[0031] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 is a circuit that amplifies the detection signal Vdet, and is, for example, an integration circuit. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0032] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on an output signal from the detection circuit 48. When the finger Fg is in contact with or close to the detection surface, the signal processing circuit 44 can detect unevenness (fingerprint, palm pattern) on the surface of the finger Fg or palm based on a signal from the detection circuit 48. The signal processing circuit 44 may also detect information related to a living body based on a signal from the detection circuit 48. The information related to a living body is, for example, a blood vessel image of the finger Fg or palm, a pulse wave, a pulse rate, blood oxygen saturation, etc.

[0033] The memory circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0034] The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information indicating the shape of the projections and recesses on the surface of the finger Fg, etc. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0035] Next, a circuit configuration example of the detection device 1 will be described. FIG. 4 is a circuit diagram showing a detection element. As shown in FIG. 4, the detection element 3 has a photodiode 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are provided corresponding to one photodiode 30. The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are each composed of an n-type TFT (Thin Film Transistor). However, this is not limited thereto, and each transistor may be composed of a p-type TFT. Although one photodiode 30 is shown in FIG. 4, a configuration in which the detection element 3 has a plurality of photodiodes 30 can be adopted as described later. Alternatively, the plurality of photodiodes 30 can be regarded as one photodiode 30 by being connected in parallel (in this case, as described below, each of the plurality of photodiodes 30 is described as a partial photodiode 30S).

[0036] A reference potential VCOM is applied to the anode of the photodiode 30. The cathode of the photodiode 30 is connected to a node N1. The node N1 is connected to a capacitance Cs, one of the source or drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. Furthermore, the node N1 has parasitic capacitances Cp, C1, and input capacitances Crst and Csf. When light is incident on the photodiode 30, a signal (charge) output from the photodiode 30 is accumulated in the capacitance Cs.

[0037] Here, the capacitance Cs is, for example, a capacitance formed between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 (see FIG. 7) of the photodiode 30. The parasitic capacitances Cp and C1 are capacitances added to the capacitance Cs, and are capacitances formed between various wirings and electrodes provided on the array substrate 2. More specifically, the parasitic capacitance C1 is a capacitance formed between the cathode (n-type semiconductor layer 32) of the photodiode 30 and a scanning line (for example, the readout control scanning line GLrd). Moreover, the input capacitances Crst and Csf are capacitances of the reset transistor Mrst and the source follower transistor Msf, respectively, as viewed from the input side, and more specifically, are a combined capacitance of the gate-source capacitance and the gate-drain capacitance.

[0038] The gate of the reset transistor Mrst is connected to a reset control scanning line GLrst. The other of the source or drain of the reset transistor Mrst is supplied with a reset potential Vrst. When the reset transistor Mrst is turned on (conductive state) in response to a reset control signal RST, the potential of the node N1 is reset to the reset potential Vrst. The reference potential VCOM has a potential lower than the reset potential Vrst, and the photodiode 30 is reverse-bias driven.

[0039] The source follower transistor Msf is connected between a terminal to which a power supply potential VDD is supplied and the readout transistor Mrd (node ​​N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (charge) generated in the photodiode 30 is supplied to the gate of the source follower transistor Msf. As a result, the source follower transistor Msf outputs a voltage signal corresponding to the signal (charge) generated in the photodiode 30 to the readout transistor Mrd. Note that, although a fixed potential (DC potential) having a predetermined potential is adopted as the power supply potential VDD in the following, it is also possible to adopt as the power supply potential a potential having an AC waveform that oscillates between predetermined potentials at a predetermined period.

[0040] The read transistor Mrd is connected between the source of the source follower transistor Msf (node ​​N2) and the output signal line SL (node ​​N3). The gate of the read transistor Mrd is connected to the read control scanning line GLrd. When the read transistor Mrd is turned on in response to the read control signal RD, the signal output from the source follower transistor Msf, i.e., a voltage signal corresponding to the signal (charge) generated in the photodiode 30, is output to the output signal line SL as the detection signal Vdet.

[0041] In the example shown in FIG. 4, the reset transistor Mrst and the readout transistor Mrd each have a so-called double-gate structure in which two transistors are connected in series. However, without being limited thereto, the reset transistor Mrst and the readout transistor Mrd may have a single-gate structure or a multi-gate structure in which three or more transistors are connected in series. Furthermore, the circuit of one detection element 3 is not limited to a configuration having three transistors, namely, the reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd. The detection element 3 may have two or four or more transistors.

[0042] 5 is a timing waveform diagram showing an operation example of the detection element. As shown in FIG. 5, the detection element 3 performs detection in the order of the reset period Prst, the exposure period Pch, and the readout period Pdet. The power supply circuit 103 supplies the reference potential VCOM to the anode of the photodiode 30 over the reset period Prst, the exposure period Pch, and the readout period Pdet.

[0043] At time t0, the scanning line driving circuit 15 sets the reset control signal RST supplied to the reset control scanning line GLrst to high (high-level voltage), and the reset period Prst begins. In the reset period Prst, the reset transistor Mrst is turned on (conductive state), and the potential of the node N1 rises to the potential of the reset potential Vrst.

[0044] At time t1, the scanning line driving circuit 15 sets the read control signal RD supplied to the read control scanning line GLrd to high (high-level voltage), thereby turning on the read transistor Mrd (conducting state).

[0045] At time t2, the scanning line driving circuit 15 makes the reset control signal RST low (low-level voltage), and the reset period Prst ends. At time t2, the reset transistor Mrst turns off (non-conductive state). A signal corresponding to the light irradiated to the photodiode 30 is accumulated, and the potential of the node N1 drops to (Vrst-ΔVn1). Here, ΔVn1 is a signal (voltage fluctuation) corresponding to the light irradiated to the photodiode 30.

[0046] At time t3, the potential of the detection signal Vdet output from the output signal line SL becomes (Vrst-Vthsf-Vrdon), where Vthsf is the threshold voltage Vthsf of the source follower transistor Msf, and Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0047] At time t3, the scanning line driving circuit 15 sets the read control signal RD to low (low-level voltage), which causes the read transistor Mrd to be turned off (non-conductive state), the potential of the node N2 to be constant, and the potential of the detection signal Vdet output from the output signal line SL to be low (low-level voltage).

[0048] At time t4, the scanning line driving circuit 15 again sets the read control signal RD to high (high-level voltage). This causes the read transistor Mrd to turn on (conductive state), the exposure period Pch ends, and the read period Pdet starts. The potential of the detection signal Vdet2 output during the read period Pdet drops by the signal ΔVn1 from the potential of the detection signal Vdet1 acquired at time t3, becoming (Vrst-Vthsf-Vrdon-ΔVn1).

[0049] The detection unit 40 can detect the light irradiated to the photodiode 30 based on a signal (ΔVn1) that is the difference between the detection signal Vdet1 at time t3 and the detection signal Vdet2 at time t5. For example, the signal ΔVn1a shown in FIG. 5 is a signal (voltage fluctuation) that occurs when the illuminance is low, and the signal ΔVn1b is a signal (voltage fluctuation) that occurs when the illuminance is high. The detection device 1 can detect the intensity of the light L2 based on the difference between the signal ΔVn1a and the signal ΔVn1b for each detection element 3. By accumulating the detection results of each of the detection elements 3, it is possible to detect, for example, a fingerprint or blood vessel image (vein pattern) of a finger that is in contact with or close to the detection surface.

[0050] 5 shows an example of the operation of one detection element 3, but the scanning line driving circuit 15 sequentially scans the reset control scanning line GLrst and the readout control scanning line GLrd in a time-division manner, thereby enabling detection by the detection elements 3 in the entire detection area AA. Furthermore, the signal line selection circuit 16 sequentially or simultaneously selects a plurality of output signal lines SL and connects the selected output signal line SL to the detection circuit 48, thereby enabling detection by the detection elements 3 in the entire detection area AA. The configuration and an example of the operation of the signal line selection circuit 16 will be described later.

[0051] Here, assuming that the total capacitance added to the photodiode 30 is capacitance Cn1, the capacitance Cn1 is expressed by the following formula (1). Note that the capacitance Cs, the parasitic capacitance Cp, and the input capacitances Crst and Csf are various capacitances equivalently connected to the cathode (node ​​N1) of the photodiode 30 described above in FIG. Cn1=Cs+Crst+Csf+Cp+C1 (1)

[0052] The signal ΔVn1 is expressed by the following equation (2): where ΔQ represents the charge accumulated during the exposure period Pch, Ip represents the photocurrent that flows in response to the light irradiated to the photodiode 30, and T represents the exposure time (the period from time t3 to time t4). ΔVn1=ΔQ / Cn1=(Ip×T) / Cn1 (2)

[0053] As shown in formula (2), the signal ΔVn1 can be increased by reducing the capacitance Cn1. That is, even when the same object to be detected is detected under the same detection conditions, the detection sensitivity of the detection device 1 can be improved by reducing the capacitance Cn1. Alternatively, the variation in the signal ΔVn1 can be reduced by reducing the variation in the capacitance Cn1. That is, it has been shown that the detection variation of the detection device 1 can be reduced by suppressing the parasitic capacitance C1.

[0054] Next, a description will be given of the planar and cross-sectional configurations of the detection element 3. Fig. 6 is a plan view showing a plurality of detection elements. Note that in Fig. 6, in order to make the drawing easier to see, the configurations of the photodiode 30 and each transistor are partially omitted.

[0055] 6, one detection element 3 includes two scanning lines (a readout control scanning line GLrd and a reset control scanning line GLrst) and four signal lines (an output signal line SL, a power supply signal line SLsf, a reset signal line SLrst, and a reference signal line SLcom). The detection element 3 further includes a first shield wiring SLsf-a and a second shield wiring SLrst-a.

[0056] The read control scanning lines GLrd and the reset control scanning lines GLrst extend in the first direction Dx and are arranged side by side in the second direction Dy. The output signal lines SL, the power supply signal lines SLsf, the reset signal lines SLrst, and the reference signal lines SLcom extend in the second direction Dy and are arranged side by side in the first direction Dx.

[0057] A detection element 3 is defined by an area surrounded by two scanning lines (a readout control scanning line GLrd and a reset control scanning line GLrst) and two signal lines (for example, two power supply signal lines SLsf of adjacent detection elements 3).

[0058] 6, the photodiode 30 has a plurality of partial photodiodes 30S-1, 30S-2, ..., 30S-8. The partial photodiodes 30S-1, 30S-2, ..., 30S-8 are arranged in a triangular lattice pattern.

[0059] More specifically, the partial photodiodes 30S-1, 30S-2, and 30S-3 are arranged in the second direction Dy. The partial photodiodes 30S-4 and 30S-5 are arranged in the second direction Dy and are adjacent to an element row composed of the partial photodiodes 30S-1, 30S-2, and 30S-3 in the first direction Dx. The partial photodiodes 30S-6, 30S-7, and 30S-8 are arranged in the second direction Dy and are adjacent to an element row composed of the partial photodiodes 30S-4 and 30S-5 in the first direction Dx. The positions of the partial photodiodes 30S in the second direction Dy are staggered between adjacent element rows.

[0060] Light L2 is incident on each of the partial photodiodes 30S-1, 30S-2, ..., 30S-8 through the optical filter 7. The partial photodiodes 30S-1, 30S-2, ..., 30S-8 are electrically connected and function as one photodiode 30. That is, signals output from each of the partial photodiodes 30S-1, 30S-2, ..., 30S-8 are integrated, and one detection signal Vdet is output from the photodiode 30. In the following description, when it is not necessary to distinguish between the partial photodiodes 30S-1, 30S-2, ..., 30S-8, they will simply be referred to as the partial photodiode 30S.

[0061] As shown in FIG. 6, the power supply signal line SLsf, the output signal line SL, the reset signal line SLrst, the reference signal line SLcom, the power supply signal line SLsf, ... are repeatedly arranged in this order in the first direction Dx. The partial photodiodes 30S-1, 30S-2, and 30S-3 are arranged between the reference signal line SLcom and the power supply signal line SLsf connected to the adjacent detection element 3 in the first direction Dx. The partial photodiodes 30S-4, 30S-5, ..., and 30S-8 are arranged between the output signal line SL and the reset signal line SLrst in the first direction Dx. In addition, each partial photodiode 30S is arranged between the read control scanning line GLrd and the reset control scanning line GLrst in the second direction Dy.

[0062] The first shield wiring SLsf-a and the second shield wiring SLrst-a extend in the first direction Dx, overlapping the readout control scanning line GLrd. The first shield wiring SLsf-a and the second shield wiring SLrst-a are provided in the same layer as the signal lines (power supply signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom), and are each electrically connected to a signal line among the multiple signal lines that supplies a fixed potential (power supply potential VDD or reset potential Vrst) to each transistor. As a result, a predetermined fixed potential is supplied to the first shield wiring SLsf-a and the second shield wiring SLrst-a.

[0063] More specifically, the first shield wiring SLsf-a is connected to the power supply signal line SLsf and extends in a direction (first direction Dx) intersecting with the power supply signal line SLsf. A signal (power supply potential VDD) having the same potential as that of the power supply signal line SLsf is supplied to the first shield wiring SLsf-a. The first shield wiring SLsf-a includes a portion extending from the power supply signal line SLsf in one direction of the first direction Dx (right side in FIG. 6) and a portion extending in the other direction of the first direction Dx (left side in FIG. 6). As a result, the first shield wiring SLsf-a covers the read control scanning line GLrd located between the power supply signal line SLsf and the output signal line SL in one direction of the first direction Dx (right side in FIG. 6), and covers the read control scanning line GLrd located between the power supply signal line SLsf and the reference signal line SLcom in the other direction of the first direction Dx (right side in FIG. 6). The first shield wiring SLsf-a is provided apart from the output signal line SL and the reference signal line SLcom.

[0064] The second shield wiring SLrst-a is connected to the reset signal line SLrst and extends in a first direction Dx, which is a direction intersecting the reset signal line SLrst. A signal (reset potential Vrst) having the same potential as the reset signal line SLrst is supplied to the second shield wiring SLrst-a. The second shield wiring SLrst-a extends in the other direction (left side of FIG. 6) of the first direction Dx and covers the read control scanning line GLrd located between the reset signal line SLrst and the output signal line SL. The second shield wiring SLrst-a is provided apart from the output signal line SL.

[0065] In other words, among the multiple signal lines, the output signal line SL that outputs the detection signal Vdet from the photodiode 30 is disposed between the first shield wiring SLsf-a and the second shield wiring SLrst-a in the first direction Dx, and is provided at a distance from the first shield wiring SLsf-a and the second shield wiring SLrst-a. Also, among the multiple signal lines, the reference signal line SLcom that supplies the reference potential VCOM to the photodiode 30 is disposed between the first shield wiring SLsf-a and the second shield wiring SLrst-a in the first direction Dx, and is provided at a distance from the first shield wiring SLsf-a and the second shield wiring SLrst-a.

[0066] Moreover, the width of each of the first shield wiring SLsf-a and the second shield wiring SLrst-a in the second direction Dy is larger than the width of the readout control scanning line GLrd in the second direction Dy. In the first shield wiring SLsf-a, a recess SLsf-b recessed in the width direction (second direction Dy) is formed in a region adjacent to the partial photodiode 30S-3. In addition, in the second shield wiring SLrst-a, a recess SLrst-b recessed in the width direction (second direction Dy) is formed in a region adjacent to the partial photodiode 30S-8. As a result, the first shield wiring SLsf-a and the second shield wiring SLrst-a are provided so as not to overlap with the partial photodiode 30S, and it is possible to suppress the occurrence of a short circuit with the partial photodiode 30S.

[0067] A branch portion GLrd-a extending in the second direction Dy is connected to the read control scanning line GLrd, and a gate electrode 84 (see FIG. 7) of the read transistor Mrd is connected to the branch portion GLrd-a. The branch portion GLrd-a is provided so as to overlap with the power supply signal line SLsf.

[0068] The power signal line SLsf has a widened portion SLsf-c at a portion overlapping the branch portion GLrd-a, the widened portion SLsf-c having a width greater than that of a portion not overlapping the branch portion GLrd-a, so that the entire branch portion GLrd-a is covered with the widened portion SLsf-c.

[0069] With this configuration, the first shield wiring SLsf-a is provided to cover the read control scanning line GLrd, and a fixed potential is supplied from the power supply signal line SLsf. The second shield wiring SLrst-a is provided to cover the read control scanning line GLrd, and a fixed potential is supplied from the reset signal line SLrst. The first shield wiring SLsf-a and the second shield wiring SLrst-a cover most of the area of ​​the read control scanning line GLrd.

[0070] This makes it possible to suppress the parasitic capacitance C1 (see FIG. 5) formed between the read control scanning line GLrd and the photodiode 30 (particularly, the partial photodiodes 30S-3 and 30S-8). As a result, as shown in the above-mentioned formula (2), the detection sensitivity of the detection device 1 can be improved. Even when the read control signal RD is supplied to the read control scanning line GLrd and the potential of the read control scanning line GLrd changes, the parasitic capacitance C1 is suppressed, so that the change in the potential of the node N1 (the cathode of the photodiode 30) is suppressed. In addition, it is possible to suppress the variation in the parasitic capacitance C1 caused by the variation in the positional relationship (distance) between the read control scanning line GLrd and the multiple partial photodiodes 30S, and as a result, it is possible to suppress the detection variation of the detection device 1.

[0071] Next, the detailed configuration of the photodiode 30 and each transistor will be described. Fig. 7 is a plan view of a photodiode included in one detection element. Fig. 7 shows an enlarged planar configuration of the photodiode 30 and each transistor included in the detection element 3. In Fig. 7, an aperture OP1 provided overlapping each of the partial photodiodes 30S-1, 30S-2, ..., 30S-8 corresponds to the light guide section of the optical filter 7 (see each figure in Fig. 1), and light L2 is irradiated to each area overlapping with the aperture OP1.

[0072] The partial photodiode 30S includes an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are, for example, amorphous silicon (a-Si). The p-type semiconductor layer 33 is, for example, polysilicon (p-Si). Note that the material of the semiconductor layers is not limited to this and may be polysilicon, microcrystalline silicon, or the like.

[0073] The n-type semiconductor layer 32 is an n+ region formed by doping impurities into a-Si. The p-type semiconductor layer 33 is a p+ region formed by doping impurities into p-Si. The i-type semiconductor layer 31 is, for example, a non-doped intrinsic semiconductor, and has lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0074] 7, a first region R1, which is an effective sensor region in which the p-type semiconductor layer 33 and the i-type semiconductor layer 31 (and the n-type semiconductor layer 32) overlap and are directly connected to each other, is indicated by a dotted line. Each of the partial photodiodes 30S is configured to have at least the first region R1. In other words, the multiple (eight in FIG. 7) first regions R1 are arranged in a triangular lattice shape in plan view. An opening OP1 of the optical filter 7 is provided so as to overlap with the first region R1.

[0075] The partial photodiodes 30S are each formed in a circular or semicircular shape in a plan view. However, without being limited thereto, the partial photodiodes 30S may be in a polygonal shape, etc. Furthermore, the partial photodiodes 30S may have shapes different from each other.

[0076] The n-type semiconductor layers 32 of the partial photodiodes 30S-1, 30S-2, and 30S-3 arranged in the second direction Dy are electrically connected by a coupling portion CA1. The p-type semiconductor layers 33 of the partial photodiodes 30S-1, 30S-2, and 30S-3 are electrically connected by a coupling portion CA2.

[0077] Further, the n-type semiconductor layers 32 (i-type semiconductor layers 31) of the partial photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 are electrically connected by a base BA1. The p-type semiconductor layers 33 of the partial photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 are electrically connected by a base BA2. The bases BA1 and BA2 are formed in a substantially pentagonal shape, and the partial photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 are provided at the vertices. The bases BA1 and BA2 are not limited to a pentagonal shape formed continuously, and may be other shapes. The bases BA1 and BA2 may be formed in a ring shape without the n-type semiconductor layer 32 and the p-type semiconductor layer 33 being formed in the center portion.

[0078] The base BA1 and the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the partial photodiodes 30S-1, 30S-2, and 30S-3 are disposed apart from each other in the first direction Dx. Meanwhile, the base BA2 connected to the p-type semiconductor layer 33 of the partial photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 are electrically connected to the p-type semiconductor layer 33 of the partial photodiodes 30S-1, 30S-2, and 30S-3 by a connecting portion CA2a that passes under the reset signal line SLrst and the reference signal line SLcom along the first direction Dx. This electrically connects the multiple partial photodiodes 30S that constitute one photodiode 30.

[0079] The lower conductive layer 35 is provided in a region overlapping with the partial photodiode 30S, the connecting portions CA1, CA2, CA2a, and the base portions BA1, BA2. The portion of the lower conductive layer 35 overlapping with the partial photodiode 30S is formed in a circular shape. However, the lower conductive layer 35 may have a shape different from that of the partial photodiode 30S. Also, it is sufficient that the lower conductive layer 35 is provided at least in a portion overlapping with the first region R1. The same reference potential VCOM as that of the p-type semiconductor layer 33 is supplied to the lower conductive layer 35, thereby suppressing parasitic capacitance between the lower conductive layer 35 and the p-type semiconductor layer 33.

[0080] The upper conductive layer 34 electrically connects the n-type semiconductor layers 32 of the multiple partial photodiodes 30S. Specifically, the upper conductive layer 34 is electrically connected to the n-type semiconductor layers 32 at positions overlapping the partial photodiodes 30S-1 and 30S-3 through contact holes H1 and H2 provided in the insulating film 27 (see FIG. 8). The connection portion 34a of the upper conductive layer 34 is formed in a T-shape overlapping the coupling portions CA1, CA2, CA2a and the partial photodiode 30S-2, and is connected to the connection portion 34b. The connection portion 34b of the upper conductive layer 34 is electrically connected to the n-type semiconductor layer 32 of the base portion BA1 through a contact hole H3 provided in the insulating film 27 (see FIG. 8) at a position overlapping the base portion BA1.

[0081] Furthermore, the upper conductive layer 34 extends from the connection portion 34b to a region not overlapping with the photodiode 30, and is connected to the connection portion 34c. The connection portion 34c of the upper conductive layer 34 is electrically connected to each transistor (the reset transistor Mrst and the source follower transistor Msf (see FIG. 4)) through a contact hole H4. Note that the upper conductive layer 34 may be provided in any manner, and may, for example, cover a part of the partial photodiode 30S, or may be provided to cover the entire partial photodiode 30S.

[0082] The reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd are provided in a region not overlapping with the photodiode 30. The source follower transistor Msf and the readout transistor Mrd are provided, for example, adjacent to the photodiode 30 in the first direction Dx. Moreover, the reset transistor Mrst is arranged adjacent to the partial photodiode 30S-4 in the second direction Dy, and is arranged between the partial photodiode 30S-1 and the partial photodiode 30S-6 in the first direction Dx.

[0083] One end of the semiconductor layer 61 of the reset transistor Mrst is connected to a reset signal line SLrst. The other end of the semiconductor layer 61 is connected to a connection wiring SLcn3 (node ​​N1) via a contact hole. A portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as a source electrode, and a portion of the connection wiring SLcn3 connected to the semiconductor layer 61 functions as a drain electrode 63. The semiconductor layer 61 is formed in a U-shape and intersects with the reset control scanning line GLrst at two points. A channel region is formed in a portion of the semiconductor layer 61 that overlaps with the reset control scanning line GLrst, and a portion of the reset control scanning line GLrst that overlaps with the semiconductor layer 61 functions as a gate electrode.

[0084] The source follower transistor Msf has a semiconductor layer 65, a source electrode 66, a drain electrode 67, and a gate electrode 68. One end of the semiconductor layer 65 is connected to a power supply signal line SLsf via a contact hole. The other end of the semiconductor layer 65 is connected to a connection wiring SLcn1 (node ​​N2) via a contact hole. A portion of the power supply signal line SLsf connected to the semiconductor layer 65 functions as a drain electrode 67, and a portion of the connection wiring SLcn1 connected to the semiconductor layer 65 functions as a source electrode 66.

[0085] One end of the gate electrode 68 extends in the first direction Dx and overlaps with the semiconductor layer 65. The other end of the gate electrode 68 extends in the second direction Dy and is electrically connected to the connection wiring SLcn3. As a result, the reset transistor Mrst is electrically connected to the gate of the source follower transistor Msf via the connection wiring SLcn3.

[0086] The readout transistor Mrd has a semiconductor layer 81, a source electrode 82, a drain electrode 83, and a gate electrode 84. One end of the semiconductor layer 81 is connected to a connection wiring SLcn1 via a contact hole H16 (see FIG. 8). The other end of the semiconductor layer 81 is connected to a connection wiring SLcn2 branched in the first direction Dx from the output signal line SL via a contact hole H15 (see FIG. 8). A portion of the connection wiring SLcn1 connected to the semiconductor layer 81 functions as a drain electrode 83, and a portion of the connection wiring SLcn2 connected to the semiconductor layer 81 functions as a source electrode 82. The two gate electrodes 84 are arranged side by side in the second direction Dy and overlap the semiconductor layer 81. The two gate electrodes 84 are electrically connected to the readout control scanning line GLrd via a branch portion GLrd-a (see FIG. 6) extending in the second direction Dy and overlapping with the power supply signal line SLsf. In this configuration, the source follower transistor Msf and the readout transistor Mrd are connected to an output signal line SL.

[0087] The output signal line SL is disposed between the source follower transistor Msf and the readout transistor Mrd and the partial photodiodes 30S-6, 30S-7, and 30S-8. The output signal line SL is provided in a zigzag line shape along the partial photodiodes 30S-6, 30S-7, and 30S-8.

[0088] The reset signal line SLrst and the reference signal line SLcom are disposed between the partial photodiodes 30S-1, 30S-2, 30S-3 and the partial photodiodes 30S-4, 30S-5. The reset signal line SLrst and the reference signal line SLcom are provided in a zigzag line shape along the partial photodiode 30S and intersect with the connecting portion CA2a. Since the partial photodiodes 30S-1, 30S-2, 30S-3 and the partial photodiodes 30S-4, 30S-5 are connected by the connecting portion CA2a, the parasitic capacitance of the reset signal line SLrst and the reference signal line SLcom can be suppressed compared to a configuration in which the base portions BA1, BA2 are provided so as to overlap with the reset signal line SLrst and the reference signal line SLcom.

[0089] The reference signal line SLcom is electrically connected to the lower conductive layer 35 through a contact hole H11. The reference signal line SLcom is also electrically connected to the coupling portion CA2 through a contact hole H12. As a result, the reference signal line SLcom is electrically connected to the p-type semiconductor layer 33 of each partial photodiode 30S.

[0090] In this embodiment, a partial photodiode 30S is provided for each of the multiple openings OP1 of the optical filter 7. This reduces the area of ​​the photodiode 30 in the area not directly hit by light, i.e., the area of ​​the three-layer structure constituting the photodiode 30, so that the parasitic capacitance of the photodiode 30 can be suppressed. In addition, since the multiple partial photodiodes 30S are dotted within the element, the degree of freedom in arranging the transistors and wiring can be improved, and the transistors and wiring are provided so as not to overlap with the photodiode 30 as much as possible. Therefore, in this embodiment, the parasitic capacitance of the photodiode 30 can be suppressed compared to the case where the photodiode 30 is provided so as to overlap with the transistors and wiring.

[0091] 6 is merely an example and may be modified as appropriate. For example, the number of partial photodiodes 30S included in one photodiode 30 may be seven or less, or nine or more. The arrangement of the partial photodiodes 30S is not limited to a triangular lattice shape, and may be arranged in a matrix shape, for example.

[0092] Fig. 8 is a cross-sectional view taken along line VIII-VIII' in Fig. 6. Fig. 8 shows the cross-sectional configurations of the partial photodiodes 30S-1, 30S-2, and 30S-7 as well as the cross-sectional configuration of the readout transistor Mrd of the detection element 3. The cross-sectional configurations of the source follower transistor Msf and the reset transistor Mrst, which are not shown in Fig. 8, are similar to that of the readout transistor Mrd.

[0093] 8, the substrate 21 is an insulating substrate, and may be, for example, a glass substrate such as quartz or alkali-free glass, or a resin substrate such as polyimide. The gate electrode 84 is provided on the substrate 21. The insulating films 22 and 23 are provided on the substrate 21 to cover the gate electrode 84. The insulating films 22 and 23 and the insulating films 24, 25, and 26 are inorganic insulating films, and may be, for example, silicon oxide (SiO2), silicon nitride (SiN), or the like.

[0094] The semiconductor layer 81 is provided on the insulating film 23. The semiconductor layer 81 is made of, for example, polysilicon. However, the semiconductor layer 81 is not limited to this and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low temperature polycrystalline silicon (LTPS), or the like. The read transistor Mrd has a bottom gate structure in which a gate electrode 84 is provided below the semiconductor layer 81, but may have a top gate structure in which the gate electrode 84 is provided above the semiconductor layer 81, or may have a dual gate structure in which the gate electrode 84 is provided above and below the semiconductor layer 81.

[0095] The insulating films 24 and 25 are provided on the insulating film 23 to cover the semiconductor layer 81. The source electrode 82 and the drain electrode 83 are provided on the insulating film 25. The source electrode 82 is connected to the high concentration impurity region of the semiconductor layer 81 through a contact hole H15. The drain electrode 83 is connected to the high concentration impurity region of the semiconductor layer 81 through a contact hole H16. The source electrode 82 and the drain electrode 83 are made of a laminated film such as TiAlTi or TiAl, which has a laminated structure of titanium and aluminum.

[0096] Next, the cross-sectional configuration of the photodiode 30 will be described. In FIG. 8, the partial photodiodes 30S-1, 30S-2, and 30S-7 will be described, but the description of the partial photodiodes 30S-1, 30S-2, and 30S-7 can be applied to the other partial photodiodes 30S. As shown in FIG. 8, the lower conductive layer 35 is provided on the substrate 21 in the same layer as the gate electrode 84. The insulating film 22 and the insulating film 23 are provided on the lower conductive layer 35. The photodiode 30 is provided on the insulating film 23. In other words, the lower conductive layer 35 is provided between the substrate 21 and the p-type semiconductor layer 33. The lower conductive layer 35 is formed of the same material as the gate electrode 84, and thus functions as a light-shielding layer, and the lower conductive layer 35 can suppress the intrusion of light from the substrate 21 side into the photodiode 30.

[0097] In the third direction Dz, the i-type semiconductor layer 31 is provided between the p-type semiconductor layer 33 and the n-type semiconductor layer 32. In this embodiment, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are stacked in this order on the insulating film 23.

[0098] Specifically, the p-type semiconductor layer 33 is provided on the insulating film 23 in the same layer as the semiconductor layer 81. The insulating films 24, 25, and 26 are provided to cover the p-type semiconductor layer 33. A contact hole H13 is provided in the insulating films 24 and 25 at positions where the insulating films 24 and 25 overlap with the p-type semiconductor layer 33. The insulating film 26 is provided on the insulating film 25, and covers the side surfaces of the insulating films 24 and 25 that constitute the inner walls of the contact hole H13. Furthermore, a contact hole H14 is provided in the insulating film 26 at a position where the insulating film 24 and 25 overlap with the p-type semiconductor layer 33.

[0099] The i-type semiconductor layer 31 is provided on the insulating film 26, and is connected to the p-type semiconductor layer 33 via a contact hole H14 that passes through the insulating film 26 from the insulating film 24. The n-type semiconductor layer 32 is provided on the i-type semiconductor layer 31.

[0100] More specifically, the photodiode 30 has a first region R1, a second region R2, and a third region R3. The multiple first regions R1 are provided corresponding to the respective partial photodiodes 30S. In each of the multiple first regions R1, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are laminated in direct contact with each other. In other words, the first region R1 is a region defined by the bottom surface of the contact hole H14.

[0101] The second region R2 is provided between a plurality of first regions R1. In the second region R2, at least a p-type semiconductor layer 33 and an i-type semiconductor layer 31 are laminated at a distance from each other in a direction (third direction Dz) perpendicular to the substrate 21. More specifically, the second region R2 has insulating films 24, 25, and 26 provided between the p-type semiconductor layer 33 and the i-type semiconductor layer 31. However, without being limited thereto, the second region R2 may have one or two insulating films between the p-type semiconductor layer 33 and the i-type semiconductor layer 31, or may have four or more insulating films.

[0102] In the second region R2, the thickness of the insulating films 24, 25, 26 provided between the p-type semiconductor layer 33 and the i-type semiconductor layer 31 (the total thickness of the thickness ti1 of the insulating films 24, 25 and the thickness ti2 of the insulating film 26) is thicker than the thickness ti3 of the i-type semiconductor layer 31. The thickness ti1 of the insulating films 24, 25 is thicker than the thickness ti2 of the insulating film 26. In addition, the distance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 in the second region R2 is larger than the distance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 in the first region R1. The thickness relationship between the i-type semiconductor layer 31 and the insulating films 24, 25, 26 is not limited to the above, and a configuration in which the total thickness of the three layers of the insulating films 24, 25, 26 is smaller than the thickness of the i-type semiconductor layer 31 can also be adopted. In the second region R2, it is necessary that insulating films 24, 25, 26 of a predetermined thickness are present between the i-type semiconductor layer 31 (and / or the n-type semiconductor layer 32) and the p-type semiconductor layer 33, but the thicknesses of the insulating films 24, 25, 26 can vary.

[0103] The second region R2 is provided around the first region R1 in a plan view, and includes connecting portions CA1 and CA2 and base portions BA1 and BA2. The partial photodiodes 30S-1, 30S-2, and 30S-3 are connected to each other by a connecting portion CA1 made of an i-type semiconductor layer 31 and an n-type semiconductor layer 32 stacked on the insulating film 26, and a connecting portion CA2 made of a p-type semiconductor layer 33 formed on the insulating film 23. Similarly, the partial photodiodes 30S-4 to 30S-8 are connected to each other by a base portion BA1 made of an i-type semiconductor layer 31 and an n-type semiconductor layer 32 stacked on the insulating film 26, and a base portion BA2 made of a p-type semiconductor layer 33 formed on the insulating film 23.

[0104] With this configuration, the capacitance per unit area formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33 in the second region R2 is smaller than the capacitance per unit area formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33 in the first region R1. Therefore, the photodiode 30 of this embodiment can reduce the capacitance Cs (see FIG. 4) of one photodiode 30 compared to a case in which the i-type semiconductor layer 31 and the n-type semiconductor layer 32 in the second region R2 are laminated on the p-type semiconductor layer 33 without the insulating films 25 and 26 interposed therebetween as in the first region R1. As a result, as shown in the above-mentioned formula (2), even under detection conditions in which the same light is irradiated and exposed for the same exposure time T, the signal ΔVn1 can be increased, and the detection sensitivity of the detection device 1 can be improved. Note that, although the above refers to the capacitance formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33, considering that the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are in direct contact with each other and that the p-type semiconductor layer and the n-type semiconductor layer face each other via the i-type semiconductor layer 31, the above reference to the capacitance can of course be replaced with the capacitance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32.

[0105] In the third region R3, a p-type semiconductor layer 33 is provided, and the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided so as not to overlap with the p-type semiconductor layer 33. The third region R3 is a region in which a connecting portion CA2a made of the p-type semiconductor layer 33 described above is provided. That is, in the third region R3, adjacent first regions R1 are connected at least by the p-type semiconductor layer 33. In addition, in the third region R3, insulating films 24 and 25 are provided on the p-type semiconductor layer 33, and the reset signal line SLrst and the reference signal line SLcom are provided on the insulating films 24 and 25 provided on the p-type semiconductor layer 33. In other words, a gap portion SP of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 is provided on the reset signal line SLrst and the reference signal line SLcom. With this configuration, insulation between each signal line and the n-type semiconductor layer 32 can be ensured, compared to a configuration in which the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided so as to overlap the reset signal line SLrst and the reference signal line SLcom.

[0106] The insulating film 27 is provided on the insulating film 26, covering the photodiode 30. The insulating film 27 is provided in direct contact with the photodiode 30 and the insulating film 26. The insulating film 27 is made of an organic material such as photosensitive acrylic. The insulating film 27 is thicker than the insulating film 26. Note that the relationship between these thicknesses may be reversed. The insulating film 27 has better step coverage than inorganic insulating materials, and is provided to cover the side surfaces of the i-type semiconductor layer 31 and the n-type semiconductor layer 32.

[0107] The upper conductive layer 34 is provided on the insulating film 27. The upper conductive layer 34 is a conductive material having light transmission properties, such as ITO (Indium Tin Oxide). The upper conductive layer 34 is provided following the surface of the insulating film 27, and is connected to the n-type semiconductor layer 32 via contact holes H1 and H3 provided in the insulating film 27. As a result, signals (photocurrents Ip) output from the multiple partial photodiodes 30S are integrated by the common upper conductive layer 34 and output as one detection signal Vdet via the source follower transistor Msf and the readout transistor Mrd (see FIG. 4).

[0108] The contact hole H1 is provided at a position overlapping the first region R1, and the n-type semiconductor layer 32 of the partial photodiode 30S-1 and the upper conductive layer 34 are connected at the bottom surface of the contact hole H1. The contact holes H1 and H3 are not formed in the first region R1 of the partial photodiodes 30S-2 and 30S-7. The contact hole H3 is provided at a position overlapping the second region R2. The width of the first region R1 of the partial photodiode 30S-1 is larger than the width of the first region R1 of the partial photodiodes 30S-2 and 30S-7. However, the upper conductive layer 34 may be connected to the n-type semiconductor layer 32 at any point, and the width and shape of the first region R1 of the multiple partial photodiodes 30S may be formed to be the same.

[0109] The insulating film 28 is provided on the insulating film 27 to cover the upper conductive layer 34. The insulating film 28 is an inorganic insulating film. The insulating film 28 is provided as a protective layer that suppresses the intrusion of moisture into the photodiode 30.

[0110] The protective film 29 is provided on the insulating film 28. The protective film 29 is an organic protective film. The protective film 29 is formed so as to flatten the surface of the detection device 1.

[0111] In this embodiment, the p-type semiconductor layer 33 and the lower conductive layer 35 of the photodiode 30 are provided in the same layer as the transistors, so the manufacturing process can be simplified compared to when the photodiode 30 is formed in a different layer from the transistors.

[0112] The cross-sectional structure of the photodiode 30 shown in Fig. 8 is merely an example. The present invention is not limited to this, and for example, the photodiode 30 may be provided in a layer different from that of each transistor. The stacking order of the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 is also not limited to that shown in Fig. 8, and the n-type semiconductor layer 32, the i-type semiconductor layer 31, and the p-type semiconductor layer 33 may be stacked in this order.

[0113] The first shield wiring SLsf-a overlaps with the readout control scanning line GLrd and is provided in the same layer as each signal line (e.g., the output signal line SL). That is, the first shield wiring SLsf-a is provided on the insulating film 25 and in a layer different from the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the adjacent partial photodiode 30S. Although the second shield wiring SLrst-a is not shown in FIG. 8, the second shield wiring SLrst-a is also provided on the insulating film 25 in the same layer as the first shield wiring SLsf-a.

[0114] Next, the configuration and an operation example of the signal line selection circuit 16 will be described. Fig. 9 is a circuit diagram showing the connection relationship between a plurality of detection elements, a scanning line driving circuit, and a signal line selection circuit in the detection device according to the first embodiment. Fig. 10 is a timing waveform diagram showing an operation example during a readout period of the detection elements.

[0115] 9, the multiple detection elements 3 are arranged in the first direction Dx and the second direction Dy. The multiple detection elements 3 arranged in the first direction Dx are represented as detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3). However, when there is no need to distinguish between the detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3), they are simply referred to as detection elements 3. The output signal lines SL, read control scanning lines GLrd, and reset control scanning lines GLrst are also represented in the same manner.

[0116] 9, the detection device 1 has a first scanning line driving circuit 15A and a second scanning line driving circuit 15B. The readout control scanning lines GLrd(n) and GLrd(n+1) are connected to the first scanning line driving circuit 15A. The reset control scanning lines GLrst(n) and GLrst(n+1) are connected to the second scanning line driving circuit 15B.

[0117] Output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3) are provided corresponding to detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3), respectively.

[0118] The signal line selection circuit 16 has a plurality of switch elements SW(m), SW(m+1), SW(m+2), and SW(m+3). The plurality of switch elements SW(m), SW(m+1), SW(m+2), and SW(m+3) are provided corresponding to the plurality of output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3), respectively. Specifically, the plurality of switch elements SW(m), SW(m+1), SW(m+2), and SW(m+3) switch between connection and non-connection between the plurality of output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3) and the detection circuit 48.

[0119] Fig. 10 shows an enlarged view of the read period Pdet shown in Fig. 5. In order to facilitate understanding, Fig. 10 shows an exaggerated schematic view of the potentials Vn1 and Vn1' at the node N1 when the detection elements 3 are irradiated with light L2 of the same intensity.

[0120] As shown in FIG. 10, the signal line selection circuit 16 sequentially turns on (connected state) a plurality of switch elements SW(m), SW(m+1), SW(m+2), and SW(m+3) in a time-division manner based on a selection signal ASW (see FIG. 2) from the control circuit 102.

[0121] In the read period Pdet1, the switch element SW(m) is turned on, and the output signal line SL(m) is connected to the detection circuit 48. At time t41, the switch element SW(m) is turned off (disconnected state), and after a predetermined period has elapsed, in the read period Pdet2, the switch element SW(m+1) is turned on, and the output signal line SL(m+1) is connected to the detection circuit 48. At time t42, the switch element SW(m+1) is turned off, and after a predetermined period has elapsed, in the read period Pdet3, the switch element SW(m+2) is turned on, and the output signal line SL(m+2) is connected to the detection circuit 48. At time t43, the switch element SW(m+2) is turned off, and after a predetermined period has elapsed, in the read period Pdet4, the switch element SW(m+3) is turned on, and the output signal line SL(m+3) is connected to the detection circuit 48. At time t44, the switch element SW(m+3) is turned off, and the readout of the detection signals Vdet from the detection elements 3(m) to 3(m+3) is completed.

[0122] As described above, the detection device 1 of this embodiment is provided with shield wiring (first shield wiring SLsf-a and second shield wiring SLrst-a), and the parasitic capacitance C1 (see FIG. 5) is suppressed. Therefore, the change over time of the potential Vn1' (indicated by a two-dot chain line in FIG. 10) at the node N1 in the case where there is no shield wiring and the parasitic capacitance C1 occurs is suppressed, and the potential Vn1 at the node N1 at times t41, t42, t43, and t44 ideally exhibits a constant value.

[0123] Therefore, in this embodiment, even if a timing lag occurs in the readout of the multiple detection elements 3 due to the operation of the signal line selection circuit 16, it is possible to suppress the potential fluctuation due to the parasitic capacitance C1 and improve the detection accuracy.

[0124] As described above, the detection device 1 of the present embodiment includes the substrate 21 (array substrate 2), a plurality of transistors (e.g., reset transistor Mrst, readout transistor Mrd, and source follower transistor Msf) provided on the substrate 21, a plurality of scanning lines (e.g., readout control scanning line GLrd) extending in a first direction Dx, a plurality of signal lines (e.g., power supply signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom) extending in a second direction Dy intersecting the first direction Dx, a plurality of photodiodes 30 each including a p-type semiconductor layer 33, an i-type semiconductor layer 31, and an n-type semiconductor layer 32 provided in an area surrounded by the plurality of scanning lines and the plurality of signal lines, and shield wiring (first shield wiring SLsf-a and second shield wiring SLrst-a) overlapping the scanning lines and extending in the first direction Dx. The shield wiring is electrically connected to the power supply signal line SLsf among the plurality of signal lines that supplies a power supply potential to the transistor.

[0125] This makes it possible to suppress the parasitic capacitance C1 (see FIG. 5) formed between the readout control scanning line GLrd and the photodiode 30 (partial photodiode 30S). As a result, as shown in the above-mentioned formula (2), the detection sensitivity of the detection device 1 can be improved. Furthermore, the parasitic capacitance C1 formed between the readout control scanning line GLrd and the multiple partial photodiodes 30S located close to each other is effectively suppressed, and as a result, the variation in the parasitic capacitance C1 caused by the relative positions of the multiple partial photodiodes 30S can be suppressed. Therefore, the detection variation of the detection device 1 can be suppressed.

[0126] Second embodiment Fig. 11 is a plan view showing a plurality of detection elements according to the second embodiment. Fig. 12 is a cross-sectional view taken along line XII-XII' in Fig. 11. Fig. 13 is a circuit diagram showing a detection element according to the second embodiment. In the following description, the same components as those described in the above-mentioned embodiment are denoted by the same reference numerals, and duplicated description will be omitted.

[0127] In the first embodiment, the shield wiring (first shield wiring SLsf-a and second shield wiring SLrst-a) are provided in the same layer as the signal lines. However, the shield wiring may be provided in a layer different from the signal lines.

[0128] 11, in the detection device 1A according to the second embodiment, the shield wiring ML is formed of a metal layer provided in a layer different from that of the signal lines (power supply signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom). The shield wiring ML extends in the first direction Dx overlapping with the readout control scanning line GLrd, and is provided so as to intersect with the multiple signal lines (power supply signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom) arranged in the first direction Dx. The shield wiring ML is electrically connected to the power supply signal line SLsf via a contact hole H20.

[0129] The shield wiring ML has a width larger than that of the read control scanning line GLrd in the second direction Dy, and recesses ML-a and ML-b are formed in the region adjacent to the partial photodiode 30S, as in the first embodiment. The shield wiring ML also has a shield wiring branch portion ML-c that overlaps with the branch portion GLrd-a of the read control scanning line GLrd and extends in the second direction Dy.

[0130] The shield wiring ML is provided continuously over the multiple detection elements 3 (photodiodes PD) arranged in the first direction Dx. However, this is not limited thereto, and a slit may be provided so that the shield wiring ML is spaced apart from each other for each detection element 3.

[0131] 12, the shield wiring ML is provided between a layer in which the readout control scanning line GLrd is provided and a layer in which a plurality of signal lines (e.g., power supply signal line SLsf) are provided. More specifically, the shield wiring ML is provided on an insulating film 24, and is provided in a layer closer to the i-type semiconductor layer 31 and the n-type semiconductor layer 32 than the layer in which the p-type semiconductor layer 33 is provided. An insulating film 25 is provided between the shield wiring ML and the power supply signal line SLsf. The shield wiring ML is electrically connected to the power supply signal line SLsf via a contact hole H20 provided in the insulating film 25.

[0132] In the second embodiment, the shield wiring ML is provided in a layer closer to the readout control scanning line GLrd than in the first embodiment, so that the shield wiring ML can effectively shield the fringe component of the electric field and suppress the parasitic capacitance C1.

[0133] As shown in FIG. 13, a parasitic capacitance C1-1 is formed between the shield wiring ML and a node N1 (the cathode (n-type semiconductor layer 32) of the photodiode 30). A parasitic capacitance C1-2 is formed between the shield wiring ML and the read control scanning line GLrd. The node N1 is capacitively coupled to the read control scanning line GLrd via the shield wiring ML. Therefore, even when a read control signal RD is supplied to the read control scanning line GLrd and the potential of the read control scanning line GLrd changes, the shield wiring ML is connected to a fixed potential (power supply potential VDD), so that the change in the potential of the node N1 (the cathode of the photodiode 30) is suppressed. The description of the capacitive coupling between the node N1 and the read control scanning line GLrd shown in FIG. 13 can also be applied to the above-mentioned first embodiment.

[0134] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present invention. Appropriate modifications made within the scope of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-mentioned embodiments and each modified example. [Explanation of symbols]

[0135] 1. Detection device 2 Array Board 3. Detector element 7 Optical Filters 10 Sensor section 15 Scanning line driving circuit 16 Signal line selection circuit 21 Substrate 30 Photodiode 30S, 30S-1, 30S-2, 30S-3, 30S-4, 30S-5, 30S-6, 30S-7, 30S-8 Partial photodiode 31 i-type semiconductor layer 32 n-type semiconductor layer 33 p-type semiconductor layer 34 Upper conductive layer 35 Lower conductive layer BA1, BA2 base CA1, CA2, CA2a connection part Mrst Reset Transistor Mrd Readout transistor Msf Source Follower Transistor ML Shielded Wiring R1 1st area R2 2nd area R3 3rd area SLsf Power signal line SLrst Reset signal line SLcom reference signal line SLsf-a 1st shield wiring SLrst-a Second shield wiring

Claims

1. A substrate; A plurality of transistors provided on the substrate; A plurality of scan lines extending in a first direction; A plurality of signal lines extending in a second direction intersecting the first direction; a plurality of photodiodes each provided in an area surrounded by the plurality of scanning lines and the plurality of signal lines, the photodiodes including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer; a shield wiring extending in the first direction and overlapping the scanning line; The shield wiring is electrically connected to a power supply signal line that supplies a power supply potential to the transistor among the plurality of signal lines. Detection device.

2. The shield wiring is provided in the same layer as the plurality of signal lines. The detection device according to claim 1 .

3. the signal lines include a reset signal line that supplies a reset signal to the photodiode; The shield wiring includes a first shield wiring connected to the power supply signal line and extending in a direction intersecting the power supply signal line, and a second shield wiring connected to the reset signal line and extending in a direction intersecting the reset signal line.

3. The detection device according to claim 1 or 2.

4. the plurality of signal lines include an output signal line that outputs a signal from the photodiode; The output signal line is provided between the first shield wiring and the second shield wiring in the first direction and spaced apart from the first shield wiring and the second shield wiring.

4. The detection device according to claim 3.

5. The shield wiring is formed of a metal layer provided in a layer between a layer in which the plurality of scanning lines are provided and a layer in which the plurality of signal lines are provided. The detection device according to claim 1 .

6. an insulating film provided between the shield wiring and the power supply signal line; The shield wiring is electrically connected to the power supply signal line through a contact hole provided in the insulating film.

6. The detection device according to claim 5.

7. The shield wiring extends in the first direction overlapping the scanning line in a plan view and intersects with the signal lines.

7. The detection device according to claim 5 or 6.

8. the shield wiring has a width greater than that of the scanning line in the second direction, In a plan view, a recess that is recessed in the width direction is formed in a region of the shield wiring adjacent to the photodiode. A detection device according to any one of claims 1 to 7.

9. the plurality of signal lines include an output signal line that outputs a signal from the photodiode; a signal line selection circuit including a plurality of switch elements corresponding to the plurality of output signal lines, and switching between the plurality of output signal lines and a detection circuit by the plurality of switch elements; A detection device according to any one of claims 1 to 8.

10. Each of the plurality of photodiodes includes a plurality of first regions in which the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked in direct contact with each other; a second region in which at least the p-type semiconductor layer and the i-type semiconductor layer are stacked and spaced apart from each other; Adjacent first regions are connected by at least the p-type semiconductor layer.

10. A detection device according to any one of claims 1 to 9.

11. The p-type semiconductor layer is provided in the same layer as the semiconductor layer of the transistor.

11. The detection device of claim 10.

12. The first regions are arranged in a triangular lattice pattern when viewed from a direction perpendicular to the substrate. Detecting device according to claim 10 or 11.

13. A substrate; A plurality of transistors provided on the substrate; A plurality of scan lines extending in a first direction; A plurality of signal lines extending in a second direction intersecting the first direction; a plurality of photodiodes each provided in an area surrounded by the plurality of scanning lines and the plurality of signal lines, the photodiodes including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer; a shield wiring that overlaps the scanning line, extends in the first direction, and is supplied with a fixed potential; Detection device.

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