SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD

Abstract

The present invention provides a solar cell which has reliable electrical connection between a base electrode and a collector. A solar cell 1 according to one embodiment of the present invention is provided with: a semiconductor substrate 10; a band-like first semiconductor layer 21 and a band-like second semiconductor layer 22, which are alternately superposed on the back surface of the semiconductor substrate; base electrodes 41, 42 which are superposed on the back surfaces of the first semiconductor layer and the second semiconductor layer at the center in the width direction; auxiliary insulating layers 51, 52 which are superposed on the back surfaces of the base electrodes, while having inner openings 53, 54 through which the base electrodes are partially exposed; a main insulating layer 60 which is continuously superposed on the back surfaces of the auxiliary insulating layers and the back surfaces of the first semiconductor layer and the second semiconductor layer in regions where the base electrodes are not superposed, while having backside openings 61, 62 which are in communication with the inner openings; and collectors 71, 72 which are continuously superposed on the back surface of the main insulating layer and the back surfaces of the base electrodes, said back surfaces being exposed through the inner openings and the backside openings.

Description

[Technical field]

[0001] The present invention relates to a solar cell and a method for manufacturing a solar cell. [Background technology]

[0002] A back-contact solar cell is known which includes a plurality of strip-shaped first and second semiconductor layers alternately formed on the back surface of a semiconductor substrate, each extending in a first direction, a plurality of strip-shaped first base electrodes and second base electrodes stacked on the first and second semiconductor layers, respectively, a first collector extending in a second direction intersecting the first direction to connect the plurality of first base electrodes, and a second collector extending in the second direction to connect the plurality of second base electrodes.

[0003] In such solar cells, in order to prevent short circuits between the first base electrode and the second current collector, and between the second base electrode and the first current collector, a configuration is also known in which an insulating material is laminated in the area where the first base electrode intersects with the second current collector and in the area where the second base electrode intersects with the first current collector (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-3724 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the above-mentioned back-contact type solar cell, when the arrangement pitch of the first semiconductor layer and the second semiconductor layer is reduced to improve the current collection efficiency, the insulating material covering the first base electrode may contact the second base electrode, and the insulating material covering the second base electrode may contact the first base electrode. In this case, there is a risk that a resin component will seep out from the insulating material onto the connection surface between the first base electrode and the second base electrode before the insulating material is cured. If the resin component is present on the connection surface between the first base electrode and the second base electrode in this way, the electrical connection between the first base electrode and the first current collector and the electrical connection between the second base electrode and the second current collector will be unstable. In view of this situation, the present invention aims to provide a solar cell in which the electrical connection between the base electrode and the current collector is reliable. [Means for solving the problem]

[0006] A solar cell according to one embodiment of the present invention comprises a semiconductor substrate, strip-shaped first and second semiconductor layers alternately stacked on the back side of the semiconductor substrate, a base electrode stacked in the widthwise center of the back side of the first and second semiconductor layers, an auxiliary insulating layer stacked on the back side of the base electrode and having an inner opening that partially exposes the base electrode, a main insulating layer stacked continuously on the back side of the auxiliary insulating layer and on the back sides of the first and second semiconductor layers in an area where the base electrodes are not stacked, and having a back opening communicating with the inner opening, and a current collector stacked continuously on the back side of the main insulating layer and on the back side of the base electrode exposed from the inner opening and the back opening.

[0007] In the solar cell described above, the main insulating layer may have higher alkali resistance than the auxiliary insulating layer.

[0008] The above-mentioned solar cell may further include a transparent electrode interposed between the first semiconductor layer and the base electrode, and a transparent electrode interposed between the second semiconductor layer and the base electrode.

[0009] In the solar cell described above, the width of the transparent electrode may be smaller than the width of the base electrode.

[0010] In the above-mentioned solar cell, the width of the rear opening may be smaller than the width of the inner opening.

[0011] In the solar cell described above, the width of the main insulating layer may be greater than the width of the base electrode.

[0012] a step of stacking a first resist on the back surface of the base electrode formation material so as to expose a boundary region between the first semiconductor layer and the second semiconductor layer in a planar view; a step of removing a region of the base electrode formation material exposed from the first resist by etching using the first resist as a mask; a step of stacking a second resist continuously on the back surface of the first resist and on the back surfaces of the first semiconductor layer and the second semiconductor layer exposed from the first resist so as to partially expose central portions of the width direction of the first semiconductor layer and the second semiconductor layer in a planar view; a step of removing a region of the first resist exposed from the second resist by etching using the second resist as a mask; and a step of stacking a conductive paste continuously on the back surface of the base electrode formation material exposed in the region from which the first resist was removed and on the back surface of the second resist. Effect of the Invention

[0013] According to the present invention, it is possible to provide a solar cell in which the electrical connection between the base electrode and the current collector is reliable. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a back view showing a solar cell according to one embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along line AA. [Diagram 3] 2 is a flowchart showing the steps of a method for manufacturing the solar cell of FIG. [Figure 4A] 4 is a cross-sectional view showing a first step of the solar cell manufacturing method of FIG. 3. [Figure 4B] 4 is a cross-sectional view showing a second step of the solar cell manufacturing method of FIG. 3. [Figure 4C] 4 is a cross-sectional view showing a third step of the solar cell manufacturing method of FIG. 3. [Figure 4D] 4 is a cross-sectional view showing a fourth step of the solar cell manufacturing method of FIG. 3. [Figure 4E] 4 is a cross-sectional view showing a fifth step of the solar cell manufacturing method of FIG. 3. [Figure 4F] 4 is a cross-sectional view showing a sixth step of the solar cell manufacturing method of FIG. 3. [Figure 4G] 4 is a cross-sectional view showing a seventh step of the solar cell manufacturing method of FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. For convenience, hatching and component symbols may be omitted. In such cases, other drawings should be referenced. Also, the dimensions of various components in the drawings have been adjusted for ease of viewing.

[0016] Fig. 1 is a back view of a solar cell 1 according to one embodiment of the present invention, Fig. 2 is a cross-sectional view of the solar cell 1 taken along line AA.

[0017] The solar cell 1 is a so-called heterojunction back contact type solar cell. The solar cell 1 comprises a semiconductor substrate 10, a plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 22 each formed in a strip shape extending in a first direction on the back side (opposite the light incident surface) of the semiconductor substrate 10 and alternately arranged in a second direction intersecting the first direction, a plurality of first transparent electrodes 31 and a plurality of second transparent electrodes 32 each laminated in a strip shape extending in the first direction at the center in the width direction (second direction) on the back side of the first semiconductor layers 21 and the second semiconductor layers 22, a plurality of first base electrodes 41 and a plurality of second base electrodes 42 laminated over substantially the entire surface on the back side of the first transparent electrodes 31 and the second transparent electrodes 32, the first semiconductor layer 21 having a region where the first base electrode 41 is not laminated and the second semiconductor layer 22 having a region where the second base electrode 42 is not laminated; a first auxiliary insulating layer 51 and a second auxiliary insulating layer 52, which are laminated on the first semiconductor layer 21 and partially expose the first base electrode 41 and the second base electrode 42, respectively; a main insulating layer 60, which is laminated continuously on the back side of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52 and on the back side of the region where the first base electrode 41 of the first semiconductor layer 21 is not laminated and the region where the second base electrode 42 of the second semiconductor layer 22 is not laminated; a first current collector 71, which is laminated continuously on the back side of the main insulating layer 60 and the back side of the region where the first base electrode 41 is exposed, and a second current collector 72, which is laminated continuously on the back side of the main insulating layer 60 and the back side of the region where the second base electrode 42 is exposed.

[0018] The semiconductor substrate 10 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 10 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. An example of the n-type dopant is phosphorus (P). The semiconductor substrate 10 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes). By using crystalline silicon as the material of the semiconductor substrate 10, a relatively small dark current can be obtained, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

[0019] The first semiconductor layer 21 and the second semiconductor layer 22 have different conductivity types. For example, the first semiconductor layer 21 is formed of a p-type semiconductor, and the second semiconductor layer 22 is formed of an n-type semiconductor. The first semiconductor layer 21 and the second semiconductor layer 22 can be formed of, for example, an amorphous silicon material containing a dopant that imparts a desired conductivity type. An example of the p-type dopant is boron (B), and an example of the n-type dopant is phosphorus (P) as described above.

[0020] The first semiconductor layer 21 and the second semiconductor layer 22 are each formed in a strip shape extending in a first direction. In the solar cell 1, a plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 22 are alternately provided in a second direction intersecting the first direction. The first semiconductor layer 21 and the second semiconductor layer 22 are preferably disposed so as to cover substantially the entire surface of the semiconductor substrate 10. The first semiconductor layer 21 and the second semiconductor layer 22 attract carriers generated in the semiconductor substrate 10 to collect charges.

[0021] The first transparent electrode 31 is interposed between the first semiconductor layer 21 and the first base electrode 41, and has substantially the same planar shape as the first base electrode 41. The second transparent electrode 32 is interposed between the second semiconductor layer and the second base electrode 42, and has substantially the same planar shape as the second base electrode 42. Strictly speaking, the width of the first transparent electrode 31 and the second transparent electrode 32 may be smaller than the width of the first base electrode 41 or the second base electrode 42 that is laminated thereon. This allows the main insulating layer 60 to enter the gap between the first semiconductor layer 21 and the first base electrode 41 and the gap between the second semiconductor layer 22 and the second base electrode 42, making it difficult for the main insulating layer 60 to peel off.

[0022] The first transparent electrode 31 and the second transparent electrode 32 are thin layers that collect electricity from the first semiconductor layer 21 and the second semiconductor layer 22 and supply the electric charge to the first base electrode 41 and the second base electrode 42. The first transparent electrode 31 and the second transparent electrode 32 also function as intermediate layers that prevent a decrease in adhesion and an increase in electrical resistance at the interface caused by differences in materials between the first semiconductor layer 21 and the second semiconductor layer 22 and the first base electrode 41 and the second base electrode 42, etc.

[0023] The first transparent electrode 31 and the second transparent electrode 32 are stacked in the first direction over approximately the entire length of the first semiconductor layer 21 and the second semiconductor layer 22, with a width smaller than that of the first semiconductor layer 21 and the second semiconductor layer 22 in the second direction so as not to contact each other.

[0024] The first transparent electrode 31 and the second transparent electrode 32 can be formed from the same material. Examples of materials for forming the first transparent electrode 31 and the second transparent electrode 32 include ITO (Indium Tin Oxide) and zinc oxide (ZnO).

[0025] The first base electrode 41 is laminated on each of the first transparent electrodes 31 so as to extend in the first direction, and the second base electrode 42 is laminated on each of the second transparent electrodes 32 so as to extend in the first direction. The first base electrode 41 and the second base electrode 42 extract charges from the first semiconductor layer 21 and the second semiconductor layer 22 via the first transparent electrode 31 and the second transparent electrode 32.

[0026] The first base electrode 41 and the second base electrode 42 can be formed from a metal such as copper or nickel.

[0027] The first auxiliary insulating layer 51 has a first inner opening 53 that partially exposes the first base electrode 41. The second auxiliary insulating layer 52 has a second inner opening 54 that partially exposes the second base electrode 42. Both side edges in the second direction of the first auxiliary insulating layer 51 substantially overlap with the side edges of the first transparent electrode 31 and the first base electrode 41 in a planar view. Similarly, both side edges in the second direction of the second auxiliary insulating layer 52 substantially overlap with the side edges of the second transparent electrode 32 and the second base electrode 42 in a planar view.

[0028] The width of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52 may be greater than the width of the first base electrode 41 or the second base electrode 42 on which they are laminated. This allows the main insulating layer 60 to penetrate into the front sides of both side portions of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52, making the main insulating layer 60 less likely to peel off. Furthermore, the first inner opening 53 and the second inner opening 54 may be closed openings as shown in the figure, but may also open to the sides of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52.

[0029] The first auxiliary insulating layer 51 and the second auxiliary insulating layer 52 can be formed from a resin composition that will not be corroded by a chemical solution that corrodes the first transparent electrode 31, the second transparent electrode 32, the first base electrode 41, and the second base electrode 42, but will not corrode the first semiconductor layer 21 and the second semiconductor layer 22, and are preferably formed from a material that can be selectively laminated by printing.

[0030] The main insulating layer 60 covers the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52, and has a plurality of first back side openings 61 each communicating with the first inner opening 53, and a plurality of second back side openings 62 each communicating with the second inner opening 54. In other words, the main insulating layer 60 does not substantially cover the area of ​​the first base electrode 41 exposed from the first inner opening 53 and the area of ​​the second base electrode 42 exposed from the second inner opening 54. The main insulating layer 60 prevents contact of the first current collector 71 with the second semiconductor layer 22, the second transparent electrode 32, or the second base electrode 42, and prevents contact of the second current collector 72 with the first semiconductor layer 21, the first transparent electrode 31, or the first base electrode 41.

[0031] The widths of the first back side opening 61 and the second back side opening 62 (the size in the same direction as the widths of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52) may be smaller than the widths of the communicating first inner opening 53 or the second inner opening 54. This makes the widths of the tips of the first current collector 71 and the second current collector 72 larger than the widths of the first back side opening 61 and the second back side opening 62, so that it is possible to prevent the first current collector 71 and the second current collector 72 from detaching from the first inner opening 53 and the second inner opening 54, that is, to prevent the first current collector 71 and the second current collector 72 from peeling off.

[0032] The main insulating layer 60 can be formed from a resin composition that is not corroded by a chemical solution that corrodes the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52 but does not corrode the first base electrode 41 and the second base electrode 42. Typically, the main insulating layer 60 has higher alkali resistance than the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52. In addition, the main insulating layer 60 is preferably formed from a material that can be selectively laminated by printing.

[0033] The first current collector 71 is connected to the areas of the multiple first base electrodes 41 exposed from the first inner opening 53 and the first back side opening 61. Therefore, the first current collector 71 is continuously stacked on the back side of the main insulating layer 60 and the back side of the first base electrode 41 exposed from the first inner opening 53 and the first back side opening 61. The second current collector 72 is connected to the areas of the multiple second base electrodes 42 exposed from the second inner opening 54 and the second back side opening 62. Therefore, the second current collector 72 is continuously stacked on the back side of the main insulating layer 60 and the back side of the second base electrode 42 exposed from the second inner opening 54 and the second back side opening 62.

[0034] The first current collector 71 and the second current collector 72 connect the plurality of first base electrodes 41 and the plurality of second base electrodes 42, respectively. The first current collector 71 and the second current collector 72 can also be used as terminals for extracting power from the solar cell 1. The first current collector 71 and the second current collector 72 can be formed by, for example, solder, a conductive adhesive, or the like.

[0035] Fig. 3 shows the steps of a method for manufacturing the solar cell 1. The solar cell manufacturing method of Fig. 3 is one embodiment of the solar cell manufacturing method according to the present invention.

[0036] The solar cell manufacturing method of this embodiment includes a semiconductor layer forming step (step S1), a transparent electrode forming material lamination step (step S2), a base electrode forming material lamination step (step S3), a first resist lamination step (step S4), a first etching step (step S5), a second resist lamination step (step S6), a second etching step (step S7), and a conductive paste lamination step (step S8).

[0037] 4A, in the semiconductor layer formation process of step S1, strip-shaped first semiconductor layers 21 and second semiconductor layers 22 are alternately formed on the back surface of the semiconductor substrate 10. Specifically, the first semiconductor layer 21 and the second semiconductor layer 22 can be formed in order by forming a mask on the back surface of the semiconductor substrate 10 and stacking semiconductor materials by a film formation technique such as CVD.

[0038] 4B, in the transparent electrode forming material lamination process of step S2, a transparent electrode forming material 30 for forming a first transparent electrode 31 and a second transparent electrode 32 is laminated on the back surface side of the semiconductor substrate 10 so as to cover the first semiconductor layer 21 and the second semiconductor layer 22. The transparent electrode forming material 30 can be laminated by a film formation technique such as CVD or sputtering.

[0039] In the base electrode forming material lamination process of step S3, as shown in Fig. 4C, a base electrode forming material 40 for forming a first base electrode 41 and a second base electrode 42 is laminated so as to cover the transparent electrode forming material 30 on the back surface side of the semiconductor substrate 10. The base electrode forming material 40 can be laminated by, for example, sputtering, plating, or the like.

[0040] 4D, in the first resist lamination process of step S4, a first resist 50 is laminated on the back surface side of the base electrode forming material 40 so as to expose the boundary region between the first semiconductor layer 21 and the second semiconductor layer 22 in a plan view. More specifically, the first resist 50 is laminated so as to have the same planar shape as the first base electrode 41 and the second base electrode 42 to be formed.

[0041] The first resist 50 can be selectively laminated using a printing technique such as screen printing. In the first resist lamination step, a required process such as heat curing (polymerization of resin) can be performed depending on the material of the first resist 50.

[0042] 4E, in the first etching process of step S5, the transparent electrode forming material 30 and the base electrode forming material 40 are removed from the areas exposed from the first resist 50 by a first etching process using the first resist 50 as a mask. As an etching solution used in the first etching process, for example, when the transparent electrode forming material 30 is ITO and the base electrode forming material 40 is copper, a mixture of an aqueous ferric chloride solution and hydrochloric acid, or a mixture of an aqueous ammonium peroxodisulfate solution and hydrochloric acid can be used.

[0043] Depending on the etching conditions in the first etching step, a side etch effect may cause the widths of the first transparent electrode 31 and the second transparent electrode 32 to be smaller than the widths of the first base electrode 41 and the second base electrode 42, or the widths of the first base electrode 41 and the second base electrode 42 to be smaller than the widths of the first auxiliary insulating layer 51 and the second auxiliary insulating layer 52. Depending on the design conditions, such a side etch effect may be intentionally generated to ensure the separation of the first transparent electrode 31 and the second transparent electrode 32 and the separation of the first base electrode 41 and the second base electrode 42.

[0044] In the second resist lamination process of step S6, as shown in FIG. 4F, a second resist (used as a main insulating layer in the solar cell 1) 60 is laminated continuous with the back surface side of the first resist 50 and the back surfaces of the first semiconductor layer 21 and the second semiconductor layer 22 exposed from the first resist 50, so that the central portions in the width direction (second direction) of the first semiconductor layer 21 and the second semiconductor layer 22 are partially exposed in the longitudinal direction (first direction) when viewed in a plan view.

[0045] The second resist 60 can be selectively laminated using a printing technique such as screen printing. In the second resist lamination step, a required process such as heat curing can be performed depending on the material of the second resist 60.

[0046] 4G, in the second etching process of step S7, a region of the first resist 50 exposed from the second resist 60 is removed by a second etching process using the second resist 60 as a mask. As an etching solution used in the second etching process, for example, an alkaline aqueous solution having a pH level that does not dissolve the second resist 60 can be used.

[0047] In this embodiment, the second resist 60 covers the first semiconductor layer 21 and the second semiconductor layer 22 near the boundary region between the first semiconductor layer 21 and the second semiconductor layer 22, and therefore it is possible to prevent the etching solution for removing the first resist 50 from contacting the first semiconductor layer 21 and the second semiconductor layer 22. This makes it possible to prevent a decrease in performance of the solar cell 1 due to dissolution of the first semiconductor layer 21 and the second semiconductor layer 22 in the second etching step.

[0048] Depending on the etching conditions in the second etching step, a side etch effect may cause the widths of the first inner opening 53 and the second inner opening 54 to be larger than the widths of the first back side opening 61 and the second back side opening 62. Depending on the design conditions, such a side etch effect may be intentionally generated in order to improve the connectivity between the first base electrode 41 and the first current collector 71 and the connectivity between the second base electrode 42 and the second current collector 72, or the first resist 50 may be prevented from remaining on both sides of the first inner opening 53 and the second inner opening 54 in the width direction.

[0049] In the conductive paste lamination step of step S8, a conductive paste is continuously laminated on the back surface side of first base electrode 41 exposed in the region from which first resist 50 has been removed and on the back surface side of second resist 60 to form first current collector 71, and a conductive paste is continuously laminated on the back surface side of second base electrode 42 exposed in the region from which first resist 50 has been removed and on the back surface side of second resist 60, spaced apart from first current collector 71, to form second current collector 72. In this way, solar cell 1 shown in FIG. 2 is obtained.

[0050] As the conductive paste for forming the first current collector 71 and the second current collector 72, a solder paste containing solder particles and flux is particularly preferably used, since it can form the first current collector 71 and the second current collector 72 having excellent connectivity and conductivity with the first base electrode 41 and the second base electrode 42. The conductive paste can be laminated using a printing technique such as screen printing. In the conductive paste lamination step, a process required for hardening the conductive paste to form the first current collector 71 and the second current collector 72, such as reflow of the solder particles in the solder paste, may be performed.

[0051] In a conventional manufacturing method in which a solder resist (insulating layer) is baked to prevent unintended short circuit with the base electrode immediately before connecting a current collector to the base electrode, there is a risk that the resin component of the solder resist will seep out and adhere to the surface of the base electrode, but in the solar cell manufacturing method of this embodiment, in the second etching step, the resin component can be removed from the region of the first base electrode 41 where the first current collector 71 is laminated and the region exposed from the second inner opening 54 and the second back opening 62. Therefore, the electrical connection between the first current collector 71 and the first base electrode 41, and the electrical connection between the second current collector 72 and the second base electrode 42, which are formed in the conductive paste lamination step, are reliable, so that the solar cell 1 manufactured by the solar cell manufacturing method of this embodiment has low electrical resistance and high reliability.

[0052] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and variations are possible. For example, the solar cell according to the present invention may not have a transparent electrode. Furthermore, the solar cell according to the present invention may include further components such as an intrinsic semiconductor layer, a passivation layer, an anti-reflection film, and a protective film in addition to the above-described components. [Explanation of symbols]

[0053] 1. Solar Cell 10. Semiconductor Substrate 21 First semiconductor layer 22 Second semiconductor layer 30 Transparent electrode forming material 31 1st transparent electrode 32 Second transparent electrode 40 Base electrode forming material 41 First base electrode 42 Second base electrode 50 1st Resist 51 First auxiliary insulating layer 52 Second auxiliary insulating layer 53 First inner opening 54 Second inner opening 60 Main insulating layer (second resist) 61 First back opening 62 Second back opening 71 First current collector 72 Second current collector

Claims

1. A semiconductor substrate; strip-shaped first semiconductor layers and second semiconductor layers alternately stacked on a rear surface side of the semiconductor substrate; a base electrode laminated at a center portion in a width direction on a rear surface side of the first semiconductor layer and the second semiconductor layer; an auxiliary insulating layer laminated on a rear surface side of the base electrode and having an inner opening that partially exposes the base electrode; a main insulating layer that is laminated continuously on a rear surface side of the auxiliary insulating layer and on rear surfaces of the first semiconductor layer and the second semiconductor layer in an area where the base electrodes are not laminated, and has a rear opening that communicates with the inner opening; a current collector laminated continuously on a rear surface side of the main insulating layer and on a rear surface side of the base electrode exposed through the inner opening and the rear opening; A solar cell comprising:

2. The solar cell according to claim 1 , wherein the main insulating layer has higher alkali resistance than the auxiliary insulating layer.

3. The solar cell according to claim 1 , further comprising a transparent electrode interposed between the first semiconductor layer and the base electrode, and a transparent electrode interposed between the second semiconductor layer and the base electrode.

4. The solar cell according to claim 3 , wherein the width of the transparent electrode is smaller than the width of the base electrode.

5. The solar cell according to claim 1 , wherein the width of the rear opening is smaller than the width of the inner opening.

6. The solar cell according to claim 1 , wherein the width of the main insulating layer is greater than the width of the base electrode.

7. forming strip-shaped first and second semiconductor layers alternately on a rear surface of a semiconductor substrate; laminating a base electrode forming material on a back surface of the semiconductor substrate; laminating a first resist on a back surface side of the base electrode forming material so as to expose a boundary region between the first semiconductor layer and the second semiconductor layer in a plan view; removing a region of the base electrode forming material exposed from the first resist by etching using the first resist as a mask; laminating a second resist continuously to a back surface side of the first resist and to back surfaces of the first semiconductor layer and the second semiconductor layer exposed from the first resist so as to partially expose central portions in a width direction of the first semiconductor layer and the second semiconductor layer in a plan view; removing a region of the first resist that is exposed from the second resist by etching using the second resist as a mask; laminating a conductive paste continuously on a back surface side of the base electrode forming material exposed in an area where the first resist has been removed and on a back surface side of the second resist; A solar cell manufacturing method comprising:

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