Semiconductor Device

Abstract

To provide a display with improved reliability, alternatively, to reduce the frame width of a display.SOLUTION: A display such as a liquid crystal display has: a first substrate; a second substrate that is superimposed on the first substrate; a liquid crystal layer that is provided between the first substrate and the second substrate; a first sealant that surrounds the liquid crystal layer between the first substrate and the second substrate; and a second sealant that surrounds the first sealant, and extends to at least the side faces of the second substrate while closing the gap between the first substrate and the second substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a display device and an electronic device. [Background technology]

[0002] In recent years, technological developments have been progressing to improve the performance of display devices, such as by reducing power consumption and increasing resolution. There are.

[0003] Examples of the display device include a liquid crystal display device and an electroluminescence display device (EL display device). Examples include a liquid crystal display (also called a display device).

[0004] A transistor for driving a display element (such as a liquid crystal element or an EL element) of the display device. Examples of transistors include transistors that use silicon semiconductors in the channel formation region and transistors that use metal oxide semiconductors. For example, a display device shown in Patent Document 1 includes: A metal oxide semiconductor is used in the channel formation region of a transistor that drives a display element. 1 is an example of a display device having a transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-44699 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional display devices have a problem of insufficient reliability. For example, in a conventional display device, a display element is provided between two substrates, and the display element is surrounded by a A sealant is provided between the two substrates, and the two substrates are bonded together to form a display. However, water and other substances may enter the sealed area from the outside through the sealant. When such substances enter the display element, the characteristics of the display element and the transistors that drive the display element deteriorate. This can lead to malfunctions.

[0007] In the display device, in the region where the two substrates overlap, the region where the sealing material overlaps It is preferable that the area other than the display area (also called the frame), including the display area, is narrow. For example, the area occupied by the display unit becomes smaller.

[0008] An object of one embodiment of the present invention is to improve the reliability of a display device. In one embodiment of the present invention, an object is to suppress the expansion of a frame of a display device. It is sufficient to solve at least one of the above problems. [Means for solving the problem]

[0009] In one aspect of the present invention, a gap between a first substrate and a second substrate is sealed using a plurality of sealing materials. This prevents impurities from entering the display device from the outside, which can cause malfunctions. We aim to curb such incidents.

[0010] In one embodiment of the present invention, at least one of the plurality of sealing materials is attached to at least the second substrate. By providing it so as to extend to the side surface of the frame, a narrower frame can be achieved.

[0011] One embodiment of the present invention is a semiconductor device including a first substrate, a second substrate overlapping the first substrate, and a semiconductor device including a first substrate and a second substrate overlapping the first substrate. A liquid crystal layer is provided between the first and second substrates, and a first substrate is provided between the first and second substrates and surrounds the liquid crystal layer. The sealing material surrounds the first sealing material and closes the gap between the first substrate and the second substrate, and a second sealant extending to at least a side surface of the second substrate.

[0012] One embodiment of the present invention is an electronic device that includes a panel equipped with a display device. Effect of the Invention

[0013] According to one embodiment of the present invention, the reliability of a display device can be improved. can be suppressed. [Brief description of the drawings]

[0014] [Figure 1] 1A to 1C are diagrams illustrating examples of a structure of a display device. [Diagram 2] 1A to 1C are diagrams illustrating examples of a structure of a display device. [Diagram 3] 1A to 1C are diagrams illustrating examples of a structure of a display device. [Figure 4] 1A to 1C are diagrams illustrating examples of a structure of a display device. [Diagram 5] 1A to 1C are diagrams illustrating examples of a structure of a display device. [Figure 6] 1A to 1C are diagrams illustrating an example of a manufacturing method of a display device. [Figure 7] 1A to 1C are diagrams illustrating an example of a manufacturing method of a display device. [Figure 8] 1A to 1C are diagrams illustrating an example of a manufacturing method of a display device. [Figure 9] 1A to 1C are diagrams illustrating an example of a manufacturing method of a display device. [Figure 10] 1A to 1C are diagrams illustrating an example of a manufacturing method of a display device. [Figure 11] 1A to 1C are diagrams illustrating examples of a structure of a liquid crystal display device. [Figure 12] 1A to 1C are diagrams illustrating examples of a structure of a liquid crystal display device. [Figure 13] 1A to 1C are diagrams illustrating examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] An embodiment of the present invention will be described. It is easy for a person skilled in the art to modify the content of the embodiment without modifying it. For example, the present invention is not limited to the description of the following embodiment.

[0016] The contents of each embodiment can be appropriately combined with each other. The contents of these can be substituted for each other as appropriate.

[0017] In addition, ordinal numbers such as 1st and 2nd are used to avoid confusion of the components. Prime numbers are not limited to ordinal numbers.

[0018] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0019] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0020] (Embodiment 1) In this embodiment, an example of a display device which is one embodiment of the present invention will be described.

[0021] An example of a configuration of a display device according to this embodiment will be described with reference to FIG.

[0022] FIG. 1A is a schematic top view of the display device, and FIG. 1B is a schematic top view of the display device along the line A- For convenience, FIG. 1(A) shows only a part of the configuration of the display device. The element is omitted.

[0023] The display device shown in FIG. 1A and FIG. 1B includes a substrate 101, a substrate 104, and a display element. The liquid crystal layer 105, the seal material 106, the seal material 107, and the seal material 108 are Yes.

[0024] The substrate 101 has a layer on which elements such as transistors for controlling the electric field of the liquid crystal layer 105 are formed. The layer 113 is provided with functions such as a protection layer and a planarization layer on the transistor. Also included is an insulating layer having a thermal conductivity function.

[0025] The substrate 104 is overlapped with the substrate 101. The substrate 104 may include a colored layer, a light-shielding layer, and a flat layer. A layer 114 is provided on which an insulating layer or the like having a function as a photosensitive layer is formed. In A), for convenience, the substrate 104 is shown by a dotted line.

[0026] The substrate 101 and the substrate 104 may be, for example, a glass substrate.

[0027] A liquid crystal layer 105 is provided between the substrate 101 and the substrate 104 .

[0028] The sealant 106 is provided between the substrate 101 and the substrate 104 so as to surround the liquid crystal layer 105. .

[0029] The sealant 106 prevents impurities (such as water) from entering the display element or transistor. The sealing material 106 has at least a function of preventing or suppressing the intrusion of the liquid from the outside. For example, the function of strengthening the structure, the function of strengthening adhesion, the function of resistance, The sealant 106 may have a function of strengthening impact resistance.

[0030] In addition, the sealant 106 has a property of being adhered to the liquid crystal layer 105 even when it is in contact with the liquid crystal layer 105 before being cured. It is preferable to use a material that does not melt. For example, epoxy resin is used as the sealing material 106. The resin material may be either a thermosetting type or a photosetting type. Alternatively, the sealant 106 may be a mixture of acrylic resin and epoxy resin. In this case, a UV initiator, a heat curing agent, a coupling agent, etc. may be mixed. It may also contain a filler.

[0031] The sealant 107 is provided to surround the sealant 106 and is disposed between the substrate 101 and the substrate 104. The gap is closed and the gap is extended to at least the side surface of the substrate 104. Therefore, the frame can be narrowed compared to the case where the sealant 107 is provided between the substrate 101 and the substrate 104. In addition, the gate driver 103a and the gate driver 103b are disposed between the substrate 101 and the substrate 104. By providing a sealant 107 on the peripheral circuit portion such as the capacitor 103b, the frame can be narrowed. In addition, by providing a seal material 107 so as to extend to the side surface of the substrate 104, for example, The mechanical strength of the substrate 104 can be increased. The mechanical strength of the substrate 101 can also be increased by providing a sealant 107 that extends to the side surfaces. The gap between the substrate 101 and the substrate 104 is sealed by the sealant 106. In this case, the seal is formed so as to contact the seal material 106 and extend to at least the side surface of the substrate 104. A sealing material 107 may be provided.

[0032] The sealant 107 prevents impurities (such as water) from entering the display element or transistor. The sealing material 107 has at least a function of preventing or suppressing the intrusion of the air or the like from the outside. For example, the function of strengthening the structure, the function of strengthening adhesion, the function of resistance, The sealant 107 may have a function of strengthening impact resistance.

[0033] It is preferable that the sealant 107 has a lower moisture permeability than the sealant 106. As the material, for example, a material including a resin material and frit glass can be used. The resin material is preferably of the thermosetting type.

[0034] Here, moisture permeability is the moisture permeability per unit area (1 m 2 ) Water that permeates materials such as films Mass (unit: g / m 2 By lowering the moisture permeability, It is possible to prevent or suppress the intrusion of impurities such as water and moisture from the inside.

[0035] The above moisture permeability can be calculated using moisture permeability tests called the MOCON method and the cup method. The MOCON method uses an infrared sensor to measure water vapor passing through the material to be measured. The cup method is a method of measuring the water vapor that has permeated the material to be measured. This method involves absorbing water into the absorbent in the bottle, and measuring the moisture permeability from the change in weight of the absorbent after absorbing water. It is.

[0036] Regarding moisture permeability, for example, a sealing material commercially available for light-emitting device applications has a film thickness of 100 μm. When set to 16 g / m 2 ·day. In the case of frit glass, it is 0.01 g / m 2 Therefore, by using the sealing structure according to the present invention, The moisture permeability of the device can be set to the above-mentioned moisture permeability or less.

[0037] The sealant 108 is provided to surround the sealant 107 .

[0038] The seal material 108 may be, for example, a metal material or a thermoplastic resin (e.g., plastic). The metal material may be, for example, a material containing aluminum, copper, lead, nickel, etc. Alternatively, solder may be used as the sealing material 108. In this case, the melting point of the solder is It is preferable that the melting point of the solder is lower than the melting point of the sealing material 107. Pb-Sn-Sb series, Sn-Sb series, Sn-Pb-Bi series, Sn-Cu series, Sn-Pb- Cu-based, Sn-In-based, Sn-Ag-based, Sn-Pb-Ag-based, Pb-Ag-based, etc. However, since Pb is harmful to humans and the environment, lead-free solder is recommended. It is preferable to use the seal material 108 having a lower moisture permeability than the seal material 106. In addition, it is preferable that the seal material 108 has a lower moisture permeability than the seal material 107. Furthermore, a stainless steel plate (for example, a SUS plate) may be provided as the seal material 108.

[0039] The sealant 107 may be made of a material that is applicable to the sealant 108. In this case, the sealant 108 does not necessarily have to be provided.

[0040] The width of the seal material 107 and the seal material 108 is 1 mm or less, preferably 0.5 mm or less. It is preferable that the temperature is lower than the above range.

[0041] The transistor included in the layer 113 may be a transistor using an oxide semiconductor in a channel formation region, for example. The transistors used in the present invention can be used.

[0042] Examples of oxide semiconductors include In-based metal oxides, Zn-based metal oxides, and In-Zn-based metal oxides. In-Ga-Zn oxide, In-Ga-Zn metal oxide, etc. can be used. Metal oxides that contain other metal elements in place of part or all of the Ga contained in the metal oxides Note that the oxide semiconductor may have a crystal structure.

[0043] The structure of an oxide semiconductor film that can be used for a channel formation region of a transistor is described below. explain.

[0044] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to films such as oxide semiconductor films.

[0045] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0046] The microcrystalline oxide semiconductor film is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher molecular weight than the amorphous oxide semiconductor film. Also, the defect level density is low.

[0047] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0048] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a quartz microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0049] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0050] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0051] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0052] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0053] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0054] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0055] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0056] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0057] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0058] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0059] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0060] When a compound containing hydrogen such as water is contained in the oxide semiconductor film, a part of the compound becomes an n-type conductive film. This impurity acts as a negative ion source, increasing the off-state current of the transistor or decreasing the threshold voltage. However, this may cause electrical characteristics problems such as fluctuations in the direction of the The display device shown in the form of A sealant 106 having a function of suppressing or preventing the intrusion of A sealant 107 is disposed on the outside so as to surround the sealant 106 and has a lower moisture permeability than the sealant 106. Since the display device has a configuration including the above, it is possible to suppress or prevent water from entering the display device. Therefore, deterioration and change in electrical characteristics of a transistor included in a display device can be suppressed. The reliability of the display device can be improved.

[0061] However, the transistors included in the layer 113 are not limited to transistors using an oxide semiconductor. For example, transistors containing semiconductors with elements of group 14 (such as silicon) are used. In this case, the semiconductor having a group 14 element may be single crystal, polycrystalline, or amorphous. stomach.

[0062] Furthermore, the display device shown in FIG. 1(A) and FIG. 1(B) includes a display device having a plurality of pixel circuits. A display unit 102, a gate driver 103a, and a gate driver 103b are provided. For example, the gate driver 103a and the gate driver 103b are connected to a layer 113 of the substrate 101. In addition, either the gate driver 103a or the gate driver 103b Only one of them may be provided on the display device. In this case, the frame should be 1 mm or less, or even 0.5 mm. It is preferable that the length is equal to or less than m.

[0063] The pixel circuits are arranged in a row and column direction in the display unit 102. The liquid crystal element includes a pair of electrodes, and a liquid crystal layer 105 in which the orientation of the liquid crystal is controlled by a voltage applied by the transistor. The transistor is a transistor that controls the electric field of the liquid crystal layer 105 and is connected between a pair of electrodes of the liquid crystal element. The capacitor element has a function of holding a voltage applied to the liquid crystal element. do.

[0064] Furthermore, the display device shown in FIG. 1(A) and FIG. 1(B) includes a flexible printed circuit board (F A source driver 112 is electrically connected via a PC 110. The printed circuit board 110 is connected to a terminal electrode provided on the layer 113 via an anisotropic conductive layer 115. The source driver 112 may be provided in the layer 113.

[0065] The configuration of the display device according to the present embodiment is not limited to that shown in FIG.

[0066] For example, the display device shown in FIG. 2(A) and FIG. 2(B) may be the same as the display device shown in FIG. In addition to the display device, a sealant 116 is provided. FIG. 2(B) is a schematic cross-sectional view taken along line B-B' in FIG. 2(A). The same parts as those in the display device shown in FIG. 1(A) and FIG. 1(B) are shown in FIG. The explanation of the display device shown in B) will be cited as appropriate.

[0067] The sealant 116 is provided to surround the sealant 106 and is disposed between the substrate 101 and the substrate 104. The seal material 107 is provided so as to close the gap. It is set up as follows.

[0068] As the sealant 116, for example, a material containing frit glass can be used.

[0069] By providing the sealant 116, impurities (such as water) that may cause malfunction of the display device are prevented. This can further enhance the effect of suppressing the intrusion of bacteria from the outside.

[0070] The display device shown in FIG. 3(A) and FIG. 3(B) is the same as the display device shown in FIG. 2(A) and FIG. 2(B). In this structure, the substrate 104 is overlapped on the inner side of the substrate 101. 3(B) is a schematic cross-sectional view taken along line CC' in FIG. 1A and 1B, the same parts as those in the display device shown in FIG. 1A and FIG. The explanation of the display device shown in (B) will be cited as appropriate.

[0071] At this time, the sealant 107 is provided so as to surround the sealant 116, and the substrate 101 and the substrate 104 while closing the gap between the upper surface of the substrate 101 and the side surface of the substrate 104. At this time, the sealant 108 is provided so as to surround the sealant 107. The above configuration may be implemented, for example, as shown in FIG. 3(A) and FIG. 3(B). This is applicable to cases where multiple flexible printed circuit boards are provided by providing 117a and 117b. circle.

[0072] Furthermore, as shown in FIG. 4A, the sealing material of the display device shown in FIG. A configuration without 108 is also possible.

[0073] As shown in FIG. 4B, the sealant 1 of the display device shown in FIG. 08 is not provided, and the seal material 107 is applied to a part of the upper surface and the side surface (flexible It may extend to the sides of the substrate 104 (except for the side that overlaps the printed circuit board 110 ). Alternatively, as shown in FIG. 4B, the sealant 107 may be in contact with the side surface of the sealant 106. stomach.

[0074] In the display device shown in FIG. 1(A) and FIG. 1(B), the upper surfaces of the substrate 101 and the substrate 104 The case where the ends of the seal material 108 and the seal material 107 are substantially aligned with each other is shown as an example. For example, as shown in FIG. 5A, the end of the seal material 107 may be Alternatively, the sealing material may have a region that is in contact with a part of the upper surface of the substrate 104. When the end of 107 has an area in contact with a part of the upper surface of the substrate 101 and / or the substrate 104 Alternatively, the end of the sealant 108 may be provided so as to overlap this region. This makes it possible to increase the mechanical strength of the substrate 101 and the substrate 104.

[0075] Alternatively, as shown in FIG. 5B, the end of the sealant 107 may contact the substrate 101 and / or the substrate 102. 104, an end of the sealant 108 overlaps with the area, and It may have a configuration having an area in contact with a part of the upper surface of the substrate 101 and / or the substrate 104. This increases the mechanical strength of the substrate 101 and the substrate 104 while preventing malfunctions of the display device. This can enhance the effect of suppressing the intrusion of impurities that cause problems.

[0076] The configuration of the display device shown in FIG. 2(A) and FIG. 2(B) and the configuration of the display device shown in FIG. 3(A) and FIG. The configurations of the display devices shown in FIGS. 4(A) and 4(B), 5(A) and 5(B) are appropriately combined. You can also match them.

[0077] Next, as an example of a method for manufacturing a display device according to this embodiment, a method for manufacturing a display device shown in FIG. An example of a method for manufacturing a display device will be described with reference to FIGS. A method for manufacturing a display device using a One Drop Filling (ODF) method An example will be described. However, the present invention is not limited to this example, and a liquid crystal injection method may be used instead of the ODF method. Good too.

[0078] First, a substrate 101 is prepared, and elements such as transistors are formed on the substrate 101. A layer 113 is formed, and a sealant 106 is formed on the layer 113 (FIGS. 6(A-1) and 6(A-2)). (See (A-2)).

[0079] In forming the layer 113, for example, a transistor that is disposed in the display unit 102 and that constitutes a pixel circuit is formed. and transistors constituting the gate driver 103a and the gate driver 103b. Furthermore, at this time, an insulating layer is formed on the transistor, and a liquid crystal is formed on the insulating layer. An electrode constituting the element may be formed. Also, if an alignment film or the like is required, the alignment film may be formed. Then, a rubbing treatment may be performed.

[0080] Furthermore, the sealant 106 may be formed by, for example, a screen printing method, an inkjet device, or the like. A seal pattern is formed in a closed loop on layer 113 using a dispensing device or the like. The seal pattern may be rectangular, circular, elliptical, or polygonal. The seal pattern does not necessarily have to be formed on the substrate 101. For example, the seal pattern may be formed on the layer 1 in advance. A substrate 104 having a layer 114 is prepared, and a seal pattern is formed on the layer 114. It may also be a molding material 106.

[0081] Next, liquid crystal 120 is dropped onto the area surrounded by the sealant 106 in a plan view (FIG. 6(B) -1) and Figure 6 (B-2)).

[0082] For example, the liquid crystal 120 is dropped using a dispenser or an inkjet device. It is also possible to dispense a plurality of droplets of the liquid crystal 120.

[0083] Next, the substrate 104 on which the layer 114 including the colored layer and the light-shielding layer has been formed in advance is bonded to the substrate 101. The layers 113 and 114 are then laminated together so that they face each other. Then, the layers are heat-treated to form a seal. After the material 106 is hardened, the substrate 101 and the substrate 104 are cut (FIG. 7(A-1) and FIG. At this time, the liquid crystal 120 in the area surrounded by the sealant 106 becomes the liquid crystal layer 1 05. If an alignment film or the like is required for the layer 114, the alignment film is formed in advance. A rubbing treatment may be carried out.

[0084] In bonding the substrate 101 and the substrate 104, the substrate 101 and the substrate 104 are bonded together in a reduced pressure atmosphere, for example. By bonding the sealing material 106 and the liquid crystal 120 together, the liquid crystal 120 can be easily filled into the area surrounded by the sealing material 106. In addition, in order to control the alignment of the liquid crystal after bonding the substrate 101 and the substrate 104, The heat treatment may be carried out.

[0085] When a liquid crystal exhibiting a blue phase is used as the liquid crystal layer 105, the sealant 106 is cured. Before the liquid crystal layer 105 is heated, a phase transition process from an isotropic phase to a blue phase and a polymer stabilization process are performed. For example, the liquid crystal layer 105 is preferably heated to a temperature at which the liquid crystal layer 105 transitions from the blue phase to the isotropic phase. Heat treatment is performed at a temperature within +10°C, preferably within +5°C, and then the temperature is gradually lowered. The phase transition temperature between the blue phase and the isotropic phase is determined by increasing the temperature. The temperature at which the blue phase transitions to the isotropic phase or the temperature at which the isotropic phase transitions to the blue phase during cooling In addition, for example, when the blue phase is expressed, liquid crystal, chiral agent, ultraviolet curing resin, and the wavelength at which the UV-curable resin and the photopolymerization initiator react to the liquid crystal material containing the photopolymerization initiator. By irradiating with light, a polymer stabilization treatment can be carried out.

[0086] In addition, when dividing the substrate 101 and the substrate 104, a scriber device, a roll cutter, etc. Using the cutting device, the substrate 101 and the substrate 104 are each cut.

[0087] Next, a sealant 107 is formed to close the gap between the substrate 101 and the substrate 104 (see FIG. 7(B-1) and 7(B-2)).

[0088] As shown in FIG. 7(B-1) and FIG. 7(B-2), the substrate 101 and the substrate 104 are bonded together. Then, a sealant 107 is formed on the substrate 101 or the substrate 104. The frame is narrower than when the substrate 101 and the substrate 104 are bonded together after the material 107 is formed. It can be done.

[0089] In forming the sealant 107, for example, a dispenser or the like is used to apply a suitable amount of the sealant 107. A paste containing a material that can be used is dropped along the side of the substrate 104. A case where the sealant 107 is formed using frit glass will be described below.

[0090] When forming the sealant 107 using frit glass, first, a dispenser or the like is used. A frit paste made of a mixture of glass powder and an organic resin having adhesive properties is applied to the substrate 104. The gap between the substrate 101 and the substrate 104 is closed by dropping the adhesive along the side of the substrate 101 and the substrate 104. The frit paste is melted and solidified by removing organic matter from the frit paste. By this, the seal material 107 is formed. In addition, the present invention is not limited to this, and may be, for example, a glass ribbon. Then, a heat treatment is performed to bond the substrate 101 and the substrate 104 together. The gap may be blocked to form a sealant 107 .

[0091] The heat treatment may be performed by irradiating the liquid crystal layer 1 with laser light. It is preferable to adjust the output so that the laser beam does not deteriorate. Alternatively, the laser light may be extracted from the laser oscillator via an optical fiber or the like. It is preferable that the sealant 106 and the sealant 107 are separated from each other, but this is not limiting. , may be in contact.

[0092] The laser light used in this case may be, for example, a gas laser such as an excimer laser, or a YAG laser. A solid-state laser, such as a laser, can be used as the light source. The wavelength range is preferably from 780 nm to 2000 nm. It is preferable to use a laser beam having a wavelength of 810 nm to 940 nm. There is no particular limitation on the shape, and it can be, for example, rectangular, linear, or circular.

[0093] The glass powder used for the frit glass is, for example, magnesium oxide, Calcium oxide, barium oxide, lithium oxide, sodium oxide, potassium oxide, boron oxide , vanadium oxide, zinc oxide, tellurium oxide, aluminum oxide, silicon dioxide, lead oxide , tin oxide, phosphorus oxide, ruthenium oxide, rhodium oxide, iron oxide, copper oxide, titanium oxide, Tungsten oxide, bismuth oxide, antimony oxide, lead borate glass, tin phosphate glass The material may include one or more of vanadate glass, borosilicate glass, and / or vanadate glass. In addition, by adding a pigment or the like to the frit paste, the laser light absorption rate can be increased. This can increase the thickness of the layer and reduce the output of the laser beam. You can make the image smaller.

[0094] The sealant 116 shown in FIGS. 2(A) and 2(B) is formed using frit glass. In this case, the same materials and methods as those described above can be used to form the substrate 104. The frit paste is melted by irradiating it with a laser beam from above, and the glass powder is bonded. The sealant 116 can be formed by applying the adhesive and then solidifying it.

[0095] In addition, the sealant 116 shown in FIG. 2(A) and FIG. 2(B) is formed using frit glass. In this case, the sealing material 107 is formed under reduced pressure to secure the sealing between the substrate 101 and the substrate 104. The adhesion can be improved.

[0096] Next, a sealant 108 is formed so as to surround the sealant 107 (FIG. 8(A-1) and FIG. 8 (See (A-2)).

[0097] When a metal material is used as the sealant 108, for example, a sputtering method is used. By forming a film of a metal material applicable to the sealant 108 on the side surface of the sealant 107, , a sealant 108 can be formed.

[0098] In addition, when solder is used as the sealing material 108, for example, ultrasonic waves are applied from a heated tip of a soldering iron. The solder is fused to the sealing material 107 by the soldering iron while oscillating the electric current. In this manner, the ultrasonic wave causes a cavitation phenomenon. For example, the sealant 108 can be formed while removing the coating formed on the sealant 107. Therefore, the adhesion between the sealant 107 and the sealant 108 can be improved.

[0099] However, the present invention is not limited to this. For example, as shown in FIG. 10(A-1) and FIG. 10(A-2), A mold 130 having a hollow structure, which is made of a material applicable to the sealant 108, is placed on the mold 130 from above. The sealing material 10 is fitted into the structure formed by the substrate 101 and the substrate 104. However, the present invention is not limited to this. For example, the seal material 107 may be formed in advance on the mold 130. The mold 130 on which the seal material 107 is formed is fitted into the structure. The sealant 107 and the sealant 108 may be formed by the above method.

[0100] Next, the side surface of the sealing material 108 is irradiated with laser light 121 (FIG. 8(B-1) and FIG. 8( At this time, the laser beam 121 is, for example, a laser beam for forming the sealing material 107. The same laser light as that used in the heat treatment in the above step may be applied.

[0101] For example, while rotating the substrate 101 in the horizontal direction, a laser beam 1 is irradiated from the horizontal direction to the substrate 101. At this time, the laser light 121 is irradiated to the sealing material 21 via the sealing material 108, for example. It is preferable that the output is such that a part of the laser beam 121 can be melted. This can improve the adhesion between the seal material 107 and the seal material 108. The laser beam 121 does not necessarily have to be irradiated from the side of the sealant 108. The laser light may be irradiated from an angle of 10 degrees to 45 degrees with the surface 101 as a reference plane.

[0102] In addition, when frit glass is used for the sealant 107, the sealant 108 is formed before the sealant 108 is formed. The material 107 may be irradiated with laser light and temporarily baked. Then, a seal material 108 is formed. The sealing material 107 is melted by irradiating the side of the sealing material 108 with a laser beam 121, and the glass The powders may be allowed to bind and solidify.

[0103] Next, the flexible printed circuit board 110 to which the source driver 112 is connected is The conductive layer 115 is used to attach the conductive layer 115 to the terminal portion (see FIG. 9(A-1) and FIG. 9(A-2)).

[0104] The above is a description of the example of the method for manufacturing the display device shown in FIGS.

[0105] As described with reference to FIGS. 1 to 10, in one example of the display device according to the present embodiment, A first sealant having a function of sealing a liquid crystal layer is provided between the two substrates, and the first substrate The second shield extends to at least a side surface of the second substrate while closing the gap between the first shield and the second substrate. By providing a second sealing material, the display device is prevented from malfunctioning. The intrusion of impurities (such as water) can be suppressed, thereby improving reliability. By providing a third seal material so as to surround the second seal material, the intrusion of the above impurities is prevented. The inhibitory effect can be enhanced.

[0106] In addition, in one example of the display device according to the present embodiment, a first substrate and a second substrate are bonded together. Then, the gap between the first substrate and the second substrate is closed, and the second substrate is then extended to at least the side surface of the second substrate. The second sealing material is provided so as to extend over the first substrate. This allows the frame to be narrower than when a second substrate is attached after the insulating material is formed.

[0107] The method and configuration of the present embodiment described above may be appropriately combined with the methods and configurations of other embodiments. It is possible to do so.

[0108] (Embodiment 2) In this embodiment, as an example of a display device, a metal oxide semiconductor is used for a channel formation region. An example of a liquid crystal display device including such a transistor will be described.

[0109] The display method of the liquid crystal display device according to the present embodiment is Twisted Nema (TN). tic) mode, IPS (In Plane Switching) mode, STN (S upper Twisted Nematic) mode, VA(Vertical Ali) mode gnment) mode, ASM (Axially Symmetric Aligned Micro-cell mode, OCB (Optically Compensated) d Birefringence mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC(AntiFerroelectric) mode Liquid Crystal mode, MVA (Multi-Domain Vert ical Alignment) mode, PVA(Patterned Vertica) l Alignment) mode, FFS (Fringe Field Switchi) ng) mode or TBA (Transverse Bend Alignment) mode A code or the like may also be used.

[0110] In addition, a liquid crystal element may be formed using a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Liquid crystals that exhibit a blue phase have a short response time of 1 msec or less and are optically isotropic. Therefore, no alignment treatment is required and viewing angle dependency is small.

[0111] Liquid crystals that exhibit a blue phase have a short response time and are optically isotropic, so no alignment treatment is required. Therefore, by using liquid crystals that exhibit a blue phase, The operation of the device can be made faster.

[0112] An example of the structure of a liquid crystal display device according to this embodiment will be described with reference to FIG.

[0113] FIG. 11A is a schematic top view of a liquid crystal display device, and FIG. 11B is a diagram showing the line segment of FIG. 11A is a schematic cross-sectional view of a liquid crystal display device MN. Some elements have been omitted.

[0114] The liquid crystal display device shown in FIG. 11(A) and FIG. 11(B) includes a display section 70 in which pixel circuits are provided. 2, a gate driver 703a, a gate driver 703b, and a source driver 712. do.

[0115] Furthermore, the conductive layer 753a and the conductive layer 753b are formed on a flat surface of the substrate 701 with the insulating layer 751 interposed therebetween. It is provided on the surface.

[0116] The conductive layer 753a is provided on the gate driver 703b. The gate serves as the gate of the transistor of the driver 703b.

[0117] The conductive layer 753b is provided in the display portion 702. The transistor of the pixel circuit functions as a gate of the liquid crystal layer 705. It has the function of controlling the electric field.

[0118] The insulating layer 754 is provided over the conductive layer 753a and the conductive layer 753b. , the gate insulating layer of the transistor of the gate driver 703b, and the transistor of the pixel circuit It functions as a gate insulating layer.

[0119] The semiconductor layer 755a overlaps with the conductive layer 753a with the insulating layer 754 interposed therebetween. a is a layer in which the channel of the transistor of the gate driver 703b is formed (channel formation It functions as a membrane (also called a membrane layer).

[0120] The semiconductor layer 755b overlaps with the conductive layer 753b with the insulating layer 754 interposed therebetween. The semiconductor layer b functions as a channel formation layer of the transistor of the pixel circuit. The semiconductor layer 755a and the semiconductor layer 755b are formed from the same semiconductor layer.

[0121] The conductive layer 756a is electrically connected to the semiconductor layer 755a. It functions as one of the source and drain of the transistor of the driver 703b.

[0122] The conductive layer 756b is electrically connected to the semiconductor layer 755a. It functions as the other of the source and drain of the transistor of the driver 703b.

[0123] The conductive layer 756c is electrically connected to the semiconductor layer 755b. The gate serves as one of the source and drain of the transistor in the path.

[0124] The conductive layer 756d is electrically connected to the semiconductor layer 755b. The gate has a function as the other of the source and drain of the transistor in the path.

[0125] The conductive layer 756e is provided on the insulating layer 754. The conductive layer 756e may be, for example, a gate The conductive layer 756e functions as a terminal electrode. Note that the conductive layers 756a to 756e are formed using the same conductive layer.

[0126] An insulating layer 757 is disposed on the semiconductor layers 755a and 755b and on the conductive layers 756a to The insulating layer 757 is provided on the conductive layer 756d. It functions as a protective insulating layer.

[0127] An insulating layer 758 is provided on the insulating layer 757. The insulating layer 758 functions as a planarizing layer. In addition, by providing the insulating layer 758, the conductive layer under the insulating layer 758 and the conductive layers above the insulating layer 758, the occurrence of parasitic capacitance can be suppressed.

[0128] A conductive layer 759 a is provided on the insulating layer 758 .

[0129] The conductive layer 759a overlaps with the semiconductor layer 755a with the insulating layer 757 and the insulating layer 758 interposed therebetween. The conductive layer 759a functions as a gate of a transistor of the gate driver 703b. For example, the conductive layer 759a is connected to the back gate of the transistor of the gate driver 703b. For example, in the case of an N-channel transistor, the back gate The voltage between the source and the gate may be set to a negative voltage. This reduces the threshold voltage of the transistor. The conductive layer 759a may be fixed to a constant potential. .

[0130] The conductive layer 759b is provided on the insulating layer 758. The conductive layer 759b is a capacitance of the pixel circuit. The conductive layer 759a and the conductive layer 759b function as one of a pair of electrodes of the element. 759b is formed from the same conductive layer.

[0131] The insulating layer 760 is provided on the insulating layer 758 with the conductive layer 759b interposed therebetween. 760, the upper side of the transistors of the gate driver 703a and the gate driver 703b By removing the portion formed in the insulating layer 758, hydrogen and water in the insulating layer 758 can be released to the outside. Therefore, it is possible to prevent the insulating layer 758 from peeling off from the insulating layer 757. The insulating layer 760 functions as a protective insulating layer. It functions as a conductive layer.

[0132] The conductive layer 761 is provided on the insulating layer 760, and the insulating layers 757, 758, and An opening through layer 760 electrically connects to conductive layer 756d. The conductive layer 761 overlaps with the conductive layer 759b with the insulating layer 760 interposed therebetween. One of a pair of electrodes of a liquid crystal element of a pixel circuit and the other of a pair of electrodes of a capacitor element It functions as a

[0133] The insulating layer 762 is provided on the insulating layer 758 or on the insulating layer 760 with the conductive layer 761 interposed therebetween. The insulating layer 762 functions as an alignment film.

[0134] The color layer 771 is provided on a part of one surface of the substrate 704. It functions as a filter.

[0135] The insulating layer 772 is provided on one surface of the substrate 704 with the colored layer 771 sandwiched therebetween. has a function as a planarizing layer.

[0136] The conductive layer 773 is provided on one surface of the insulating layer 772. The electrode functions as the other of the pair of electrodes of the element.

[0137] The insulating layer 774 is provided over the conductive layer 773. The insulating layer 774 functions as an alignment film. has.

[0138] The sealant 706 is provided between the substrate 701 and the substrate 704 so as to surround the liquid crystal layer 705. The sealant 706 corresponds to the sealant 106 shown in FIG. 1(A) and FIG. 1(B), for example. do.

[0139] The sealant 707 surrounds the sealant 706 and closes the gap between the substrate 701 and the substrate 704. The sealing material 7 extends to the side surface of the substrate 704 and the upper surface or side surface of the substrate 701. 07 corresponds to, for example, the sealant 107 shown in FIGS.

[0140] The sealant 708 is provided so as to surround the sealant 707. The sealant 708 is, for example, This corresponds to the sealant 108 shown in FIGS.

[0141] The flexible printed circuit board 710 is electrically conductive via a conductive layer 780 and an anisotropic conductive layer 781. The flexible printed circuit board 710 is electrically connected to the gate electrode 756e. A driver 703a, a gate driver 703b, a source driver 712, and a display unit 702 It is electrically connected to the pixel circuit.

[0142] FIG. 12 is a schematic cross-sectional view of a display device of the in-plane switching type. In comparison with the display device shown in (B), the insulating layer 758, the insulating layer 760, the insulating layer 762, and the conductive layer The conductive layer 773 and the insulating layer 774 are not present, and the conductive layer 753c, the conductive layer 793, and the conductive layer 756f are separate. 7, a conductive layer 791a is provided instead of the conductive layer 761, and a conductive layer 759a is provided instead of the conductive layer 759a. The difference is that the liquid crystal layer 791b is included, and the liquid crystal layer 792 is included instead of the liquid crystal layer 705. The same parts as those of the display device shown in FIG. 11(A) and FIG. 11(B) are shown in FIG. The explanation of the display device shown in B) will be cited as appropriate.

[0143] The conductive layer 753c is provided on the insulating layer 751. The conductive layer 753c serves as a capacitance line. The conductive layer 753c has the same function as the conductive layers 753a and 753b. is formed.

[0144] The conductive layer 793 is provided over the insulating layer 754. It functions as one of a pair of electrodes.

[0145] The conductive layer 756f is provided on the insulating layer 754 and has an opening formed therethrough. The conductive layer 756f is electrically connected to the conductive layer 753c through the opening. 93. The conductive layer 756f functions as a wiring. The conductive layer 6f is formed using the same conductive layer as the conductive layers 756a to 756e.

[0146] The conductive layer 791a is provided on the insulating layer 757 and has an opening penetrating the insulating layer 757. The conductive layer 791a is electrically connected to the conductive layer 756d through the opening. Each of the comb teeth of the comb-tooth portion overlaps with the conductive layer 793 with the insulating layer 757 interposed therebetween. 1a functions as one of a pair of electrodes of a liquid crystal element of a pixel circuit. The conductive layer 791a functions as the other of the pair of electrodes of the capacitor in the pixel circuit. At this time, the conductive layer 793 functions as the other of a pair of electrodes of the liquid crystal element in the pixel circuit. Possesses the ability.

[0147] The conductive layer 791b is provided on the insulating layer 757, and is disposed between the semiconductor layer 755 and the insulating layer 757. The conductive layer 791b is used as a gate of a transistor of the gate driver 703b. For example, the conductive layer 791b is For example, in the case of an N-channel transistor, The voltage between the back gate and the source may be a negative voltage. The threshold voltage can be shifted in the positive direction. It may be determined.

[0148] The liquid crystal layer 792 is surrounded by a sealant 706 and is provided over the conductive layers 791a and 793. can be.

[0149] Note that a protective layer is provided on the insulating layer 757 between the conductive layer 791a and the conductive layer 791b. An insulating layer having a function as a protective layer may be provided over the insulating layer 772. In addition, the protective layer may have a function as an alignment film.

[0150] In addition, in FIG. 11(A), FIG. 11(B), and FIG. 12, the transistor is shown as a channel edge. However, the present invention is not limited to this and may be applied to, for example, a channel protection transistor. Alternatively, a top-gate type transistor may be used.

[0151] Furthermore, regarding each component of the display device shown in FIG. 11(A), FIG. 11(B), and FIG. Each layer may have a laminated structure.

[0152] For example, a glass substrate can be used as the substrate 701 and the substrate 704. Examples of the glass include barium borosilicate glass, aluminoborosilicate glass, and aluminoborosilicate glass. It is preferable to use a non-alkali glass substrate such as silicate glass.

[0153] The insulating layer 751 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide In this case, a layer containing a material such as aluminum or hafnium oxide can be applied. It is preferable that the intrusion of impurities from the substrate 701 is suppressed by the barrier 51. The insulating layer 751 does not necessarily have to be provided.

[0154] The conductive layers 753a to 753c can be formed using, for example, molybdenum, titanium, chromium, or titanium. Aluminum, magnesium, silver, tungsten, aluminum, copper, neodymium, or scandium A layer including a metallic material such as tungsten can be applied.

[0155] The insulating layer 754 and the insulating layer 757 may be, for example, silicon oxide, silicon nitride, or oxynitride. Silicon, silicon oxide nitride, aluminum oxide, aluminum nitride, gallium oxide, oxide Gallium oxide, yttrium oxide, yttrium oxynitride, aluminum oxynitride, nitride Layers containing materials such as aluminum oxide or hafnium oxide can also be applied. An oxide layer may be used as the layer 754. The oxide layer may be, for example, In:Ga: For example, a layer of oxide with an atomic ratio of Zn=1:3:2 can be used.

[0156] In order to make the oxide semiconductor layer supersaturated with oxygen, (The insulating layer 754 and the insulating layer 757) preferably include a layer containing excess oxygen.

[0157] For the insulating layer containing excess oxygen, the deposition conditions in the plasma CVD method or sputtering method are appropriately adjusted. A silicon oxide film or a silicon oxynitride film that contains a large amount of oxygen is used. In addition, oxygen may be added by ion implantation, ion doping, or plasma treatment.

[0158] Furthermore, the barrier layer against oxygen, hydrogen, or water is arranged outside the insulating layer containing excess oxygen. The locking layer is preferably provided as insulating layer 754 and insulating layer 757. Diffusion of oxygen contained in the oxide semiconductor layer to the outside and hydrogen from the outside to the oxide semiconductor layer. It can prevent the intrusion of water, etc. The blocking layer can be made of, for example, silicon nitride or aluminum oxide. Nitride, Aluminum Nitride, Gallium Oxide, Gallium Oxide Nitride, Yttrium Oxide, Yttrium nitride, aluminum oxide nitride, aluminum oxide nitride, or hafnium oxide A layer including a material such as the above can be applied.

[0159] The oxide semiconductor layer is surrounded by an insulating layer or a blocking layer containing excess oxygen. A state in which the conductor layer is in a state where the composition is almost the same as the stoichiometric composition, or where the composition is less than the stoichiometric composition. It is possible to make the mixture in a supersaturated state with a large amount of oxygen.

[0160] For example, a stack of a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer. The insulating layer 754 may be formed by the first silicon nitride layer. The second silicon nitride layer preferably has fewer defects than the first silicon nitride layer. It is preferable that the amount of hydrogen desorbed and the amount of ammonia desorbed are smaller than those of the silicon nitride layer.

[0161] Also, for example, the first silicon oxynitride layer, the second silicon oxynitride layer, and the silicon nitride The insulating layer 757 may be formed by stacking layers. In this case, the second silicon oxynitride layer is The silicon oxynitride layer preferably contains more oxygen than the first silicon oxynitride layer. The silicon layer is more resistant to oxygen, hydrogen or the like than the first silicon oxynitride layer and the second silicon oxynitride layer. It is preferable that the blocking property against water is high.

[0162] The semiconductor layers 755a and 755b can be, for example, oxide semiconductor layers. can.

[0163] Examples of the oxide semiconductor include In-based metal oxides, Zn-based metal oxides, and In-Zn-based Metal oxides, In-Ga-Zn-based metal oxides, etc. can be used. a-Zn-based metal oxides that contain other metal elements in place of all or part of the Ga contained in the oxides Metal oxides may also be used.

[0164] The oxide semiconductor may have a crystal structure. For example, the oxide semiconductor may have a polycrystalline structure. Alternatively, the oxide semiconductor may be a single crystal.

[0165] The other metal element is, for example, a metal element capable of bonding with more oxygen atoms than gallium. For example, titanium, zirconium, hafnium, germanium, and tin can be used. One or more of these elements may be used. In addition, the other metal element may be lanthanum. Cr, Cerium, Praseodymium, Neodymium, Samarium, Europium, Gadolinium, Thermo Rubium, Dysprosium, Holmium, Erbium, Thulium, Ytterbium, and One or more of the metal elements may be used. The amount of these metal elements added is determined based on the amount of metal oxide that is semiconductor. It can form more bonds with oxygen atoms than gallium. By using a metal element and supplying oxygen to the metal oxide, the acid in the metal oxide can be It is possible to reduce elementary defects.

[0166] Further, a first oxide semiconductor layer having an atomic ratio of In:Ga:Zn=1:1:1, for example, A second oxide semiconductor layer having an atomic ratio of n:Ga:Zn=3:1:2, and an In:Ga:Z The third oxide semiconductor layer having an atomic ratio of n=1:1:1 is stacked to form the semiconductor layer 755a and The semiconductor layer 755a and the semiconductor layer 755b may be formed by the above-mentioned lamination. By configuring 55b, for example, the transistor can be made a buried channel. , the field effect mobility can be increased.

[0167] The transistor including the oxide semiconductor has a wide band gap and therefore has low leakage current due to thermal excitation. The current is small. In addition, the effective mass of the hole is large, more than 10, and the tunnel barrier height is 2.8 eV or more. This reduces the tunnel current. Furthermore, the carriers in the semiconductor layer Therefore, the off-current can be reduced. For example, the off-current at room temperature (25°C) is 1×10 per μm of channel width -19 A (100zA) or less. More preferably, 1 ×10 -22 A (100yA) or less. The lower the off-state current of a transistor, the better. However, the lower limit of the off-state current of a transistor is about 1×10 -30 Estimated to be A / μm Note that the present invention is not limited to the above-described oxide semiconductor layer, and the semiconductor layer 755a and the semiconductor layer 75 A semiconductor layer having an element of group 14 (such as silicon) may be used as 5b. For example, The semiconductor layer containing silicon may be a single crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. A layer of corn or the like can be used.

[0168] For example, impurities such as hydrogen or water are removed as much as possible, and oxygen is supplied to fill the oxygen vacancies as much as possible. By reducing the amount of the oxide semiconductor as much as possible, a transistor including the oxide semiconductor can be manufactured. In the channel formation region, the amount of hydrogen, known as donor impurities, is measured using secondary ion mass spectrometry. (also known as SIMS) measurement is 1×10 19 / cm 3 Less than or equal to 1×10 18 / cm 3 It is preferable to reduce it to the following:

[0169] For example, a layer containing oxygen is used as a layer in contact with an oxide semiconductor layer, and heat treatment is performed. This makes it possible to highly purify the oxide semiconductor layer.

[0170] In addition, the oxide semiconductor layer immediately after its formation is in a supersaturated state with more oxygen than in the stoichiometric composition. For example, in the case where the oxide semiconductor layer is formed by a sputtering method, It is preferable to form the film under conditions where the proportion of oxygen in the film gas is high, and particularly in an oxygen atmosphere (e.g. For example, it is preferable to form the film using 100% oxygen gas.

[0171] In addition, it is preferable that the amount of residual moisture in the film formation chamber of the sputtering apparatus is small. Therefore, it is preferable to use an adsorption type vacuum pump in the sputtering device. A light trap may also be used.

[0172] In addition, in the formation of the oxide semiconductor layer, heat treatment is preferably performed. The temperature is 150°C or higher and lower than the distortion point of the substrate, and further, 300°C or higher and 450°C or lower. It is preferable that the heat treatment is performed several times.

[0173] The heat treatment device used for the heat treatment is GRTA (Gas Rapid Th Thermal Annealing (LRTA) equipment or Lamp Rapid Thermo RTA (Rapid Thermal Annealing) equipment However, the present invention is not limited to this, and other heating treatment devices such as an electric furnace may be used. A processing device may also be used.

[0174] After the above heat treatment, the heating temperature is maintained or cooled from the heating temperature. In the process of the heating process, high-purity oxygen gas, high-purity N2O gas, or It is recommended to introduce ultra-dry air (with a dew point of -40°C or less, preferably -60°C or less). In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, or the like. The purity of the oxygen gas or N2O gas introduced into the heat treatment device is 6N or more, preferably It is preferable that the impurity concentration in oxygen gas or N2O gas is 1 ppm or more. It is preferable that the concentration of the oxide semiconductor is 0.1 ppm or less. As a result, oxygen is supplied to the oxide semiconductor layer, and defects due to oxygen deficiency in the oxide semiconductor layer can be reduced. The introduction of the high purity oxygen gas, high purity NO gas, or ultra-dry air is performed during the heating process. You may go at any time.

[0175] By using a highly purified oxide semiconductor layer in a field effect transistor, The carrier density of the layer is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than , and more preferably 1×10 11 / cm 3 In this way, the carrier density can be reduced to less than By eliminating the MOSFET, the off-state current of the field-effect transistor per 1 μm of channel width can be reduced by 1× 10 -19 A (100zA) or less, preferably 1×10 -22 A (100yA) or less The lower the off-state current of a field-effect transistor, the better. The lower limit of the off-state current of an effect transistor is approximately 1×10 -30 It is estimated to be A / μm. do.

[0176] Note that the oxide semiconductor may be a CAAC-OS.

[0177] For example, an oxide semiconductor layer which is a CAAC-OS can be formed by a sputtering method. At this time, sputtering is performed using a polycrystalline oxide semiconductor sputtering target. When the ions collide with the sputtering target, The crystal region in the target is cleaved from the ab plane, forming a flat plate with a plane parallel to the ab plane. Or, it may peel off as pellet-shaped sputtered particles. The sputtering particles reach the substrate while maintaining the above-mentioned state. The crystalline state of the target is transferred to the substrate, forming a CAAC-OS.

[0178] In addition, in order to form the CAAC-OS, it is preferable to apply the following conditions:

[0179] For example, by forming a CAAC-OS with a reduced impurity concentration, the acid For example, the destruction of the crystal state of the compound semiconductor can be suppressed by the deposition chamber of the sputtering device. It is preferable to reduce the amount of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present. It is preferable to reduce impurities in the deposition gas. It is preferable to use a deposition gas having a temperature of not higher than 100° C., preferably not higher than −100° C.

[0180] It is also preferable to increase the substrate temperature during film formation. When the plate-shaped sputtered particles reach the substrate, the migration of the sputtered particles occurs. The sputtering particles can be attached to the substrate by facing the flat surface. For example, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or higher and 500° C. or lower. An oxide semiconductor film is formed at a temperature of 0.degree. C. or lower to form an oxide semiconductor layer.

[0181] In addition, the oxygen ratio in the deposition gas is increased and the power is optimized to suppress plasma damage during deposition. For example, the oxygen ratio in the deposition gas is preferably 30% by volume or more. It is preferable that the volume percentage is 100%.

[0182] The conductive layers 756a to 756f and the conductive layer 780 can be formed using, for example, molybdenum or titanium. , Chromium, Tantalum, Magnesium, Silver, Tungsten, Aluminum, Copper, Neodymium, A layer containing a metallic material such as scandium or ruthenium can be applied. For example, tungsten The conductive layers 756a to 756f are formed by stacking a titanium layer, an aluminum layer, and a titanium layer. may be configured as follows.

[0183] The insulating layer 758 may be, for example, a layer of an organic insulating material or an inorganic insulating material. For example, the insulating layer 758 may be made of acrylic resin.

[0184] The conductive layer 759a and the conductive layer 759b have a function as, for example, a conductor and transmit light. For example, a layer of a metal oxide such as indium oxide, zinc oxide or indium Tin oxide and the like can be used.

[0185] The insulating layer 760, the insulating layer 762, and the insulating layer 774 may be, for example, the insulating layer 754. For example, the insulating layer 762 can be made of a silicon nitride layer.

[0186] The conductive layer 761 and the conductive layer 773 are, for example, a layer of a metal oxide that transmits light. For example, indium oxide, zinc oxide, indium tin oxide, or the like can be used.

[0187] The colored layer 771 transmits light having one of the colors red (R), green (G), and blue (B), for example. The colored layer 771 can be a layer containing a dye or a pigment.

[0188] The insulating layer 772 may be, for example, a layer of an organic insulating material or an inorganic insulating material.

[0189] The liquid crystal layer 705 may be, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, or an ECB type. Use of a layer containing liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, or the like can be done.

[0190] The liquid crystal layer 792 may be, for example, a layer containing liquid crystal exhibiting a blue phase. If the alignment can be controlled by the method, a layer containing other liquid crystal that can be applied to the liquid crystal layer 705 can be used. It may be used.

[0191] The layer containing the liquid crystal exhibiting a blue phase may be, for example, a liquid crystal exhibiting a blue phase, a chiral agent, a liquid crystal monomer, or the like. The liquid crystal composition includes a liquid crystal layer, a non-liquid crystal monomer, and a polymerization initiator. The liquid crystal shown in Fig. 1 has a short response time and is optically isotropic, so no alignment treatment is required and the viewing angle is large. Therefore, by using a liquid crystal that exhibits a blue phase, the operation of a liquid crystal display device can be improved. can be done faster.

[0192] The conductive layer 793 can be made of a conductive material that transmits light. For example, A layer of a metal oxide can be applied, for example indium oxide, zinc oxide or indium stannate. The semiconductor layers 755a and 755b may be formed using the same layer. The conductive layer 793 may be formed by making the formed semiconductor layer N-type. For example, Oxygen deficiency in a semiconductor layer formed using the same layer as the semiconductor layers 755a and 755b By adding an element that increases the conductivity of the material and imparts N-type conductivity, it can be made N-type. .

[0193] The sealant 706 may be made of the same material as the sealant 106 shown in the embodiment mode 1. In addition, the sealant 706 can be formed in the same manner as the sealant 106 shown in the embodiment 1. .

[0194] The sealant 707 may be made of the same material as the sealant 107 shown in the embodiment 1. In addition, the sealant 707 can be formed in the same manner as the sealant 107 shown in the embodiment 1. .

[0195] As the sealant 708, the same material as the sealant 108 shown in the embodiment mode 1 can be used. In addition, the sealant 708 can be formed in the same manner as the sealant 108 shown in the embodiment 1. .

[0196] The above is an explanation of the structural example of the liquid crystal display device shown in FIGS.

[0197] As described with reference to FIGS. 11 and 12, in an example of the liquid crystal display device according to the present embodiment, The pixel circuit is a liquid crystal element, a transistor, a capacitor, Furthermore, a transistor having a channel formation region formed of an oxide semiconductor In addition, a third transistor having a function of sealing the liquid crystal layer between the two substrates is used. A first sealant is provided, and the gap between the first substrate and the second substrate is closed while at least A second sealant is provided that also extends to the side surface of the second substrate.

[0198] As described with reference to FIGS. 11 and 12, in an example of the liquid crystal display device according to the present embodiment, In the present invention, a transistor having a channel formation region formed in an oxide semiconductor is used as a transistor. Furthermore, a first sealant having a function of sealing the liquid crystal layer is provided between the two substrates, and The gap between the first substrate and the second substrate is closed while the second substrate is extended to at least the side surface of the second substrate. A second seal material is provided.

[0199] In a transistor in which the channel is formed in an oxide semiconductor, when water or other substances enter the semiconductor layer, Some of them become donors, which causes degradation of electrical characteristics such as an increase in off-state current. Or, it may cause fluctuations in electrical characteristics, such as a negative shift in threshold voltage. However, by providing the second sealant, it is possible to prevent impurities such as water from entering from the outside. Therefore, the deterioration and fluctuation of the electrical characteristics of the transistor can be suppressed. The reliability of the liquid crystal display device can be improved. By providing the sealing material 3, the effect of suppressing the intrusion of the above-mentioned impurities can be further enhanced. can.

[0200] In addition, in one example of the display device according to the present embodiment, a first substrate and a second substrate are bonded together. Then, the gap between the first substrate and the second substrate is closed, and the second substrate is then extended to at least the side surface of the second substrate. The second sealing material is provided so as to extend over the first substrate. This allows the frame to be narrower than when a second substrate is attached after the insulating material is formed.

[0201] In addition, in one example of the liquid crystal display device according to the present embodiment, a gate driver is provided on the same substrate as the pixel circuit. This reduces the wiring required to connect the pixel circuits and the driver circuits. The number can be reduced.

[0202] (Embodiment 3) In this embodiment, an example of an electronic device including a panel using a display device will be described with reference to FIG. This will be explained in light of the above.

[0203] The electronic device shown in FIG. 13A is an example of a portable information terminal.

[0204] The electronic device shown in FIG. 13A includes a housing 1011 and a panel 10 provided in the housing 1011. 12, a button 1013, and a speaker 1014.

[0205] The housing 1011 is provided with a connection terminal for connecting to an external device and an operation button. It's fine.

[0206] Furthermore, even if the panel 1012 is configured using the display device according to the first or second embodiment, good.

[0207] Furthermore, the panel 1012 may be configured using a touch panel. The touch panel can detect touches on the touch panel 12. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0208] The button 1013 is provided on the housing 1011. For example, the button 1013 is a power button. If present, pressing the button 1013 can control the on state of the electronic device.

[0209] The speaker 1014 is provided in the housing 1011. The speaker 1014 outputs sound. do.

[0210] A microphone may be provided in the housing 1011. By doing so, for example, the electronic device shown in FIG. 13(A) can function as a telephone. do.

[0211] The electronic device shown in FIG. 13(A) is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more of the gaming machines.

[0212] The electronic device shown in FIG. 13B is an example of a foldable information terminal.

[0213] The electronic device shown in FIG. 13B includes a housing 1021a, a housing 1021b, and a housing 1021a. A panel 1022a provided on the housing 1021b, a panel 1022b provided on the housing 1021b, and a shaft A portion 1023, a button 1024, a connection terminal 1025, a recording medium insertion portion 1026, and a switch It is equipped with a speaker 1027.

[0214] The housing 1021 a and the housing 1021 b are connected by a shaft portion 1023 .

[0215] Furthermore, the display device according to the first or second embodiment is used to display the panel 1022a and the panel 1022b may be configured.

[0216] Furthermore, the panels 1022a and 1022b may be configured using touch panels. This allows touch detection to be performed on the panel 1022a and the panel 1022b. Examples of touch panels include optical touch panels, capacitive touch panels, A resistive touch panel, etc. can be applied.

[0217] The electronic device shown in FIG. 13B has a shaft portion 1023, so that the panel 1022a and the panel 1022b can be folded in opposition to each other.

[0218] The button 1024 is provided on the housing 1021b. For example, if the button 1024 is a power button, pressing the button 1024 By doing so, the on state of the electronic device can be controlled.

[0219] The connection terminal 1025 is provided on the housing 1021a. In addition, the connection terminal 1025 may be provided between the housing 1021a and the housing 1021b. A plurality of connection terminals 1025 may be provided on one or both of the terminals 21b. This is a terminal for connecting the electronic device shown in FIG. 1 to other devices.

[0220] The recording medium insertion section 1026 is provided in the housing 1021a. The recording medium insertion section 1026 may be provided in the housing 1021a. For example, a plurality of recording medium inserts may be provided on one or both of the housings 1021a and 1021b. By inserting a card-type recording medium into the card slot, data on the card-type recording medium can be read by electronic equipment. It is possible to read data from the electronic device or write data in the card-type recording medium.

[0221] The speaker 1027 is provided in the housing 1021b. The speaker 1027 outputs sound. Note that a speaker 1027 may be provided on the housing 1021a.

[0222] A microphone may be provided in the housing 1021a or the housing 1021b. By providing a microphone in the housing 1021b, the electronic device shown in FIG. It can function as a telephone.

[0223] The electronic device shown in FIG. 13B is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more of the gaming machines.

[0224] The electronic device shown in FIG. 13C is an example of a stationary information terminal. The electronic device includes a housing 1031, a panel 1032 provided on the housing 1031, and a button 10 33 and a speaker 1034.

[0225] Furthermore, even if the panel 1032 is configured using the display device of the first or second embodiment, good.

[0226] Furthermore, the panel 1032 may be configured using a touch panel. 032, touch detection can be performed. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0227] In addition, a panel similar to the panel 1032 may be provided on the deck portion 1035 of the housing 1031.

[0228] Furthermore, the housing 1031 is provided with a ticket output section for outputting tickets, a coin input section, a bill input section, etc. It may be provided.

[0229] The button 1033 is provided on the housing 1031. For example, the button 1033 is a power button. If present, pressing the button 1033 can control the on state of the electronic device.

[0230] The speaker 1034 is provided in the housing 1031. The speaker 1034 outputs sound. do.

[0231] The electronic device shown in FIG. 13C is, for example, an automatic teller machine, a machine for ordering tickets, etc. Functions as an information and communication terminal (also called a multimedia station) for playing games or as a gaming machine has.

[0232] FIG. 13(D) is an example of a stationary information terminal. The electronic device shown in FIG. 13(D) is A body 1041, a panel 1042 provided on the housing 1041, and a support for supporting the housing 1041. The device includes a holder 1043, a button 1044, a connection terminal 1045, and a speaker 1046. can.

[0233] The housing 1041 may be provided with a connection terminal for connecting to an external device.

[0234] Furthermore, even if the panel 1042 is configured using the display device according to the first or second embodiment, good.

[0235] Furthermore, the panel 1042 may be configured using a touch panel. 042, touch detection can be performed. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0236] The button 1044 is provided on the housing 1041. For example, the button 1044 is a power button. If present, pressing button 1044 can control the on state of the electronic device.

[0237] The connection terminal 1045 is provided on the housing 1041. The connection terminal 1045 is shown in FIG. For example, the connection terminal 1045 is a terminal for connecting the electronic device shown in FIG. When the electronic device shown in FIG. 13(D) is connected to a personal computer, An image corresponding to a data signal input from a computer can be displayed on the panel 1042. For example, the panel 1042 of the electronic device shown in FIG. 13D may be connected to the panel of another electronic device. If the screen size is larger than the other electronic device, the image displayed on the other electronic device can be enlarged and multiple people can use the same screen at the same time. Sometimes it's easier to see.

[0238] The speaker 1046 is provided in the housing 1041. The speaker 1046 outputs sound. do.

[0239] The electronic device shown in FIG. 13(D) is, for example, an output monitor, a personal computer, and a television. It has one or more functions as a vision device.

[0240] The above is a description of the example of the electronic device shown in FIG.

[0241] As described with reference to FIG. 13, the electronic device according to the present embodiment is By providing a panel using the display device described in Embodiment 2, electronic devices with high reliability can be provided. can be provided. [Explanation of symbols]

[0242] 101 Substrate 102 Display section 103a Gate Driver 103b Gate Driver 104 Substrate 105 Liquid crystal layer 106 Sealing material 107 Sealing material 108 Sealing material 110 Flexible printed circuit board 112 Source Driver 113 layers 114 layers 115 Anisotropic conductive layer 116 Sealing material 117a Flexible Printed Circuit Board 117b Flexible Printed Circuit Board 120 LCD 121 Laser Light 130 type 701 Substrate 702 Display section 703a Gate Driver 703b Gate Driver 704 Substrate 705 Liquid crystal layer 706 Sealing material 707 Sealing material 708 Sealing material 710 Flexible Printed Circuit Board 712 Source Driver 751 Insulation Layer 753a conductive layer 753b Conductive layer 753c conductive layer 754 Insulation layer 755a Semiconductor layer 755b Semiconductor layer 756a conductive layer 756b Conductive layer 756c conductive layer 756d conductive layer 756e conductive layer 756f conductive layer 757 Insulation Layer 758 Insulation Layer 759a conductive layer 759b Conductive layer 760 Insulating layer 761 Conductive Layer 762 Insulating layer 771 Colored layer 772 Insulation Layer 773 Conductive Layer 774 Insulation Layer 780 Conductive Layer 781 Anisotropic Conductive Layer 791a Conductive layer 791b Conductive layer 792 Liquid crystal layer 793 Conductive Layer 1011 Case 1012 Panel 1013 Button 1014 Speaker 1021a Housing 1021b Case 1022a Panel 1022b Panel 1023 Shaft 1024 Button 1025 Connection terminal 1026 Recording medium insertion section 1027 Speaker 1031 Case Panel 1032 1033 Button 1034 Speaker 1035 Deck section 1041 Case Panel 1042 1043 Support stand 1044 Button 1045 Connection terminal 1046 Speaker

Claims

1. a gate electrode and a first conductive film disposed on an insulating surface; a first insulating film on the gate electrode and the first conductive film; a first metal oxide film having a region in contact with an upper surface of the first insulating film and having a channel formation region of a transistor; a second metal oxide film having a region in contact with an upper surface of the first insulating film and functioning as one electrode of a display element; a second conductive film disposed on the first metal oxide film and functioning as a source electrode or a drain electrode of the transistor; a third conductive film disposed on the second metal oxide film and electrically connected to the second metal oxide film; a second insulating film disposed so as to be in contact with an upper surface of the second conductive film and an upper surface of the third conductive film; a fourth conductive film that functions as the other electrode of the display element and overlaps with the second metal oxide film via the second insulating film; having the first metal oxide film and the second metal oxide film contain In, Ga, and Zn; the second metal oxide film has a region overlapping with the fourth conductive film and a region not overlapping with the fourth conductive film, the first conductive film is electrically connected to the second metal oxide film via the third conductive film; the third conductive film overlaps with the fourth conductive film; the third conductive film has a region that does not overlap with the first conductive film, A semiconductor device, wherein, in a plan view, the first conductive film has a region disposed between the first metal oxide film and the second metal oxide film.

2. a first conductive film disposed on the insulating surface; a first insulating film on the first conductive film; a first metal oxide film having a region in contact with an upper surface of the first insulating film and having a channel formation region of a transistor; a second metal oxide film having a region in contact with an upper surface of the first insulating film and functioning as one electrode of a display element; a second conductive film disposed on the first metal oxide film and functioning as a source electrode or a drain electrode of the transistor; a third conductive film disposed on the second metal oxide film and electrically connected to the second metal oxide film; a second insulating film disposed so as to be in contact with an upper surface of the second conductive film and an upper surface of the third conductive film; a fourth conductive film that functions as the other electrode of the display element and overlaps with the second metal oxide film via the second insulating film; having the first metal oxide film and the second metal oxide film contain In, Ga, and Zn; the second metal oxide film has a region overlapping with the fourth conductive film and a region not overlapping with the fourth conductive film, the first conductive film is electrically connected to the second metal oxide film via the third conductive film; the third conductive film overlaps with the fourth conductive film; the third conductive film has a region that does not overlap with the first conductive film, A semiconductor device, wherein, in a plan view, the first conductive film has a region disposed between the first metal oxide film and the second metal oxide film.

3. a first conductive film disposed on the insulating surface; a first insulating film on the first conductive film; a first metal oxide film having a region in contact with an upper surface of the first insulating film and having a channel formation region of a transistor; a second metal oxide film having a region in contact with an upper surface of the first insulating film and functioning as one electrode of a display element; a second conductive film disposed on the first metal oxide film and functioning as a source electrode or a drain electrode of the transistor; a third conductive film disposed on the second metal oxide film and electrically connected to the second metal oxide film; a second insulating film disposed so as to be in contact with an upper surface of the second conductive film and an upper surface of the third conductive film; a fourth conductive film that functions as the other electrode of the display element and overlaps with the second metal oxide film via the second insulating film; having the first metal oxide film and the second metal oxide film contain In, Ga, and Zn; the second metal oxide film has a region overlapping with the fourth conductive film and a region not overlapping with the fourth conductive film, the first conductive film is electrically connected to the second metal oxide film via the third conductive film; the third conductive film overlaps with the fourth conductive film; the third conductive film has a region that does not overlap with the first conductive film, the first conductive film has a region disposed between the first metal oxide film and the second metal oxide film in a plan view; A semiconductor device, wherein, in a plan view, the third conductive film has a region disposed between the first metal oxide film and the second metal oxide film.

Images