Memory device

Abstract

To provide a semiconductor device having high on-current, a semiconductor device with high operation speed, a semiconductor device capable of retaining data for a long period, and a semiconductor device with reduced power consumption.SOLUTION: In a memory device having a plurality of memory cells arranged in a matrix, each memory cell has a transistor and a capacitor element. The transistor has first and second gates that overlap each other with a semiconductor layer in between. The memory device operates in "write mode", "read mode", "refresh mode", and "NV mode". In the refresh mode, after reading data held in the memory cell, the data is rewritten to the memory cell over a first period. In the NV mode, after reading the data stored in the memory cell, the data is rewritten to the memory cell over a second period, and after that, by supplying a potential that turns off the transistor to the second gate, the data can be stored for a long period if the power supply to the memory cell is stopped.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] One aspect of the present invention relates to a storage device.

[0002] Another aspect of the present invention relates to an article, a method, or a manufacturing method. The method may be a process, machine, manufacture, or composition of matter. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general term for memory devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices. In addition, the present invention may be applied to a storage device, a display device, an electro-optical device, a power storage device, etc. The devices, semiconductor circuits, and electronic devices can also be referred to as semiconductor devices. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, other materials include oxide semiconductors (OS). ) is attracting attention. Examples of oxide semiconductors include indium oxide and zinc oxide. Not only oxides of single-component metals, but also oxides of multi-component metals are known. Oxidation of multi-component metals Among these, research on In-Ga-Zn oxide (hereinafter referred to as IGZO) is particularly focused. is being actively carried out.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous, AC (c-axis aligned crystalline) structure and nc (na A noncrystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with lower crystallinity than those in the conventional semiconductors have fine crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-unique See patent literature 6.) LSIs and displays that utilize these properties have been reported (non- See Patent Document 7 and Non-Patent Document 8.

[0007] In addition, a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) Various semiconductor devices using a semiconductor laser (also called a "transistor") have been proposed.

[0008] In Patent Document 1, an OS transistor is used as a DRAM (Dynamic Random Access Memory) The OS transistor is used in an off-state Since the leakage current (off-state current) is very small, the refresh period is long and power consumption is low. This makes it possible to create a DRAM that does not require

[0009] Moreover, Patent Document 2 discloses a nonvolatile memory using an OS transistor. Unlike flash memory, these non-volatile memories have no limit to the number of times they can be rewritten, and This allows for fast operation and consumes little power.

[0010] In the memory using these OS transistors, the threshold voltage of the OS transistors is increased. This makes it possible to reduce the off-current and improve the data retention characteristics of the memory. In Patent Document 2, a second gate is provided in the OS transistor, An example is disclosed in which the threshold voltage of a transistor is controlled to reduce the off-current.

[0011] In order for the memory to retain data for a long period of time, It is necessary to keep applying a constant negative potential to the OS transistor. An example of a circuit configuration for driving the second gate of the transistor is disclosed. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2013-168631 A [Patent Document 2] JP 2012-069932 A [Patent Document 3] JP 2012-146965 A [Non-patent literature]

[0013] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0014] An object of one embodiment of the present invention is to provide a semiconductor device having high on-state current. An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. Another embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. It shall be one of the following.

[0015] In addition, the description of a plurality of problems does not preclude the existence of each problem. The embodiment does not necessarily solve all of these problems. Also, problems other than those listed may be solved by the specification. These issues will become clear from the description, drawings, claims, etc. This may be an aspect of the invention. [Means for solving the problem]

[0016] One aspect of the present invention is a method for manufacturing a semiconductor memory device having a plurality of memory cells arranged in a matrix. Each of the first and second gates includes a transistor and a capacitance element. The first gate and the second gate overlap each other via a semiconductor layer including a metal oxide. A memory device having an area, the memory device storing data in at least one of a plurality of memory cells. and a function of reading data from at least one of the plurality of memory cells. For at least one of the plurality of memory cells, the first data held in the memory cell is and writing first data to the memory cell for a first time after reading the first data from the memory cell. Reading first data held in at least one of the memory cells After the first data is written to the memory cell for a second time, the second data is written to the memory cell for a second time. supplying a first potential to the port and then stopping the power supply to the plurality of memory cells; The first data is multi-valued data, and the second time is longer than the first time. It is located.

[0017] The semiconductor layer of the transistor preferably contains at least one or both of In and Zn. It is preferable that the second time is 1.5 times or more the first time. The first potential is , which is the potential that turns off the transistor. Also, the threshold voltage of the transistor is Vt When the first potential is set to h, it is preferable that the first potential is equal to or lower than −VthM. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having a high operating speed can be provided. According to one embodiment, a semiconductor device capable of retaining data for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0020] [Figure 1] 1A to 1C illustrate a configuration example of a semiconductor device. [Diagram 2] 1A to 1C are diagrams showing electrical characteristics of a transistor. [Diagram 3] FIG. 2 is a diagram illustrating a configuration example of a voltage generating circuit. [Figure 4]FIG. 2 is a diagram illustrating a configuration example of a voltage holding circuit. [Diagram 5] FIG. 4 is a diagram for explaining an example of the configuration of a temperature detection circuit. [Figure 6] FIG. 4 is a graph for explaining an example of change in voltage VBias with respect to temperature change. [Figure 7] 4 is a timing chart illustrating an example of the operation of a semiconductor device. [Figure 8] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 9] FIG. 2 is a diagram for explaining an example of the configuration of a memory cell array. [Figure 10] FIG. 2 is a circuit diagram illustrating a configuration example of a memory cell. [Figure 11] FIG. 2 is a diagram for explaining a configuration example of a memory cell array and a bit line driver circuit. [Figure 12] FIG. 2 is a diagram illustrating an example of a circuit configuration. [Figure 13] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 14] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 15] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 16] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 17] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 18] FIG. 2 is a diagram for explaining a configuration example of a memory cell array and a bit line driver circuit. [Figure 19] FIG. 2 is a diagram for explaining a configuration example of a memory cell array and a bit line driver circuit. [Figure 20] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 21] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 22] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 23] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 24] FIG. 2 is a diagram for explaining a configuration example of a memory cell array and a bit line driver circuit. [Diagram 25] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 26] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 27] 4 is a timing chart illustrating an example of the operation of the storage device. [Figure 28] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 29] FIG. 2 illustrates an example of the configuration of a storage device. [Diagram 30] 1A to 1C illustrate examples of the structure of a transistor. [Diagram 31] 1A to 1C illustrate examples of the structure of a transistor. [Diagram 32] 1A to 1C illustrate examples of the structure of a transistor. [Diagram 33] 1A to 1C illustrate examples of the structure of a transistor. [Diagram 34] 1A to 1C illustrate examples of the structure of a transistor. [Diagram 35] FIG. 1 is a diagram illustrating an example of an electronic component. [Diagram 36] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 37] 1A to 1C are diagrams illustrating application examples of a storage device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above embodiment, and the form and details of the embodiment are not limited to the above embodiment without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made. The present invention should not be construed as being limited to the contents of the embodiments and examples.

[0022] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be used.

[0023] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0024] In this specification, the high power supply voltage is referred to as the H level (also called "VDD" or "H potential"). ), and low power supply voltage is sometimes called the L level (also called "GND" or "L potential"). be.

[0025] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. For this reason, in this specification and the like, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0026] In addition, the present specification can be appropriately combined with the following embodiments and examples. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be appropriately combined. It is possible to combine them.

[0027] In this specification, the term "metal oxide" refers to a metal oxide in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). For example, metal oxide is used for the semiconductor layer of a transistor. In this case, the metal oxide is sometimes called an oxide semiconductor. In the above description, a transistor having a metal oxide or an oxide semiconductor is used instead. In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Sometimes referred to collectively.

[0028] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistor is a normally-off n-channel field effect transistor. The threshold voltage (also referred to as "Vth") is greater than 0V.

[0029] (Embodiment 1) <Semiconductor device 100> FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. 00 includes a voltage generating circuit 110, a voltage holding circuit 120, a temperature detecting circuit 130, and a voltage control circuit The node between the voltage holding circuit 120 and the voltage control circuit 140 is called a node ND. The voltage holding circuit 120 and the voltage control circuit 140 are connected to the semiconductor device 10 via a node ND. 0 is electrically connected to the output terminal OUT.

[0030] The semiconductor device 100 also has a second gate connected to the second gate of the plurality of transistors M11 via an output terminal OUT. The first gate ("front gate") of transistor M11 is electrically connected to the It has a first gate (also called a "gate") and a second gate (also called a "back gate"). The first gate and the second gate are in an area where they overlap with each other via a semiconductor layer. The second gate has a function of controlling the threshold voltage of the transistor M11, for example. do.

[0031] The transistor M11 is used in various circuits included in memory devices, display devices, arithmetic devices, etc. For example, the transistors in NOR and NAND type memory devices In addition, for example, a liquid crystal display device or an EL display device The transistors included in each display device are also shown. GPU (Graphics Processing Unit), GPU (Graphics Processing Unit) ing Unit), or FPGA (Field Programmable Gat The transistors in the MOSFET's MOSFETs are called MOSFET's.

[0032] Although three transistors M11 are shown in FIG. 1, one embodiment of the present invention is not limited thereto. In addition, the semiconductor device 100 may be connected to more transistors M11.

[0033] Here, we explain the temperature dependence of the Id-Vg characteristic, which is one of the electrical characteristics of a transistor. Figures 2(A) and 2(B) show the Id- An example of the Id-Vg characteristic is shown below. The Id-Vg characteristic is the drain Id vs. the gate voltage (Vg). The horizontal axis of Figure 2(A) and Figure 2(B) shows the change in current (Id). The vertical axis in Figure 2(A) and Figure 2(B) shows Id in log scale. is doing.

[0034] FIG. 2A shows the Id-Vg characteristics of an OS transistor. FIG. 2B shows the channel A transistor that uses silicon for the semiconductor layer on which the transistor is formed (also called a "Si transistor"). The Id-Vg characteristics of the MOSFETs are shown in Fig. 2(A) and 2(B). This is the Id-Vg characteristics of an n-channel transistor.

[0035] As shown in Figure 2(A), the off-state current of the OS transistor increases even when operated at high temperatures. In addition, the Vth of the OS transistor shifts in the negative direction as the operating temperature rises. On the other hand, as shown in Fig. 2(B), the Si transistor As the temperature rises, the off-state current increases. th shifts in the positive direction and the on-current decreases.

[0036] Therefore, by using an OS transistor as the transistor M11, Even if the transistor M11 is not used, the power consumption of the entire semiconductor device including the transistor M11 can be reduced.

[0037] In addition, the semiconductor device 100 has an output terminal OUT connected to the second gate of the transistor M11. It has the function of writing the voltage VBG and then holding it. For example, When a negative potential is applied, the transistor M11 is turned on while the second gate is held at a negative potential. This allows Vth to be shifted in the positive direction. For example, if the transistor M11 is used as a select transistor for a memory cell, In this case, the charge of the capacitive element functioning as storage can be held for a long period of time.

[0038] [Voltage Generation Circuit 110] Examples of the circuit configuration of the voltage generating circuit 110 are shown in FIGS. GND is input to the input terminal IN, and the output of the voltage generating circuit 110 The voltage VBG0 is output from the terminal OUT. Here, as an example, a charge pump circuit The number of stages in the basic circuit is four, but it is not limited to this and any number of stages can be used for the charge pump circuit. A path may be formed.

[0039] The voltage generating circuit 110a shown in FIG. 3A includes transistors M21 to M24. , and capacitance elements C21 to C24.

[0040] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT. and the gate and first electrode of each are connected to function as a diode. The gates of the transistors M21 to M24 are connected to the capacitance elements Capacitor C21 to capacitative element C24 are connected.

[0041] CLK is input to the first electrodes of the odd-numbered capacitor elements C21 and C23, and CLKB is input to the first electrodes of the capacitance elements C22 and C24. This is an inverted clock signal with its phase inverted.

[0042] The voltage generating circuit 110a reduces the GND input to the input terminal IN to generate a voltage VBG0. The voltage generating circuit 110a generates a negative potential by only supplying CLK and CLKB. can be generated.

[0043] The above-described transistors M21 to M24 may be formed of OS transistors. By using OS transistors, the diode-connected transistors M21 to This is preferable because it can reduce the reverse current of the transistor M24.

[0044] The voltage generating circuit 110b shown in FIG. 3B is a p-channel transistor. The other components are configured as voltage The description of the generating circuit 110a will be used.

[0045] The voltage generating circuit 110 may be a step-down charge pump or a step-up charge pump. The voltage generating circuit 110 may have both step-down and step-up charge pumps. It is okay to do so.

[0046] [Voltage holding circuit 120] The voltage holding circuit 120 includes a transistor M12 (see FIG. 1A). A first terminal (either the source or the drain) of M12 is electrically connected to the voltage generating circuit 110. The second terminal (the other of the source and drain) of the transistor M12 is connected to the node ND. are electrically connected.

[0047] The voltage holding circuit 120 turns on the transistor M12 to hold the voltage generated by the voltage generating circuit 110. The threshold voltage VBG0 of the transistor M12 is supplied to the node ND. If the value voltage is Vth1, when transistor M12 is turned on, It is preferable to apply a voltage of VBG0+Vth1 or more to the gate of M12. The voltage holding circuit 120 turns off the transistor M12 to hold the voltage of the node ND. It has the function of

[0048] When a negative potential is supplied as the voltage VBG0, the first gate and the second gate of the transistor M12 are connected to the first gate and the second gate of the transistor M12. A transistor having a gate is used to electrically connect the first gate and the second gate to the second terminal. (See FIG. 4(A)). In this case, the transistor M12 acts as a diode. In addition, if the voltage output from the transistor M12 is VBG1, The relationship VBG1=VBG0+Vth1 holds. The first terminal of the transistor M12 is connected to GN By setting it to D, the negative potential written to the node ND can be maintained.

[0049] In the transistor M12 shown in FIG. 4A, a negative potential is supplied to the node ND, and then the first terminal When Vg is set to GND, Vg becomes 0V. Therefore, Id ("cutoff current") when Vg is 0V is It is preferable that the cutoff current is small. The negative potential written to the ND can be maintained for a long period of time.

[0050] The channel length of transistor M12 is longer than the channel length of transistor M11. For example, when the channel length of the transistor M11 is set to less than 1 μm, The channel length of the stadia M12 is preferably 1 μm or more, more preferably 3 μm or more, and even more preferably The channel length of the transistor M12 is preferably 5 μm or more, and more preferably 10 μm or more. By making it longer, the transistor M12 is not affected by the short channel effect and the cutoff current In addition, the transistor M12 has a high withstand voltage between the source and drain. If the withstand voltage between the source and drain of the transistor M12 is high, This makes it possible to easily connect the voltage generating circuit 110 that generates the voltage Vcc to the transistor M11. This is preferable.

[0051] The transistor M12 is an OS transistor and has a wide band gap in the channel formation region. It is preferable to use transistors using semiconductors. OS transistors and wideband Transistors using gap semiconductors have a small cutoff current and In this specification, the term "wide band gap semiconductor" refers to a semiconductor having a large band gap. Semiconductors with a peak energy of 2.2 eV or more. Examples include silicon carbide, gallium nitride, and diamond. etc.

[0052] The transistor M12 is required to have a smaller cutoff current than the transistor M11. On the other hand, the transistor M11 is required to have a larger on-current than the transistor M12. When transistors with different required properties are to be fabricated on the same substrate, different semiconductors are used. The transistor M12 is a transistor It is preferable to use a semiconductor having a larger band gap than M11 for the channel formation region. In addition, the transistor M11 uses a semiconductor with higher electron mobility than the transistor M12. It is preferably used in the channel formation region.

[0053] The voltage holding circuit 120 is composed of a plurality of transistors M12 connected in series. (See Figs. 4(B) and (C)).

[0054] [Temperature detection circuit 130] The temperature detection circuit 130 includes a temperature sensor 131 and an analog-to-digital conversion circuit ("ADC"). ) 132 (see FIG. 5).

[0055] The temperature sensor 131 senses the temperature of the semiconductor device 100 and outputs an analog signal according to the temperature. The temperature sensor 131 has a function of outputting a signal VA. Temperature sensors made of copper or other materials, thermistors, thermocouples, IC temperature sensors, etc. can be used. do.

[0056] The analog-to-digital conversion circuit 132 converts the analog signal VA into an n-bit digital signal (n is an integer equal to or greater than 1). The digital signal VD is input to the temperature detection circuit 130. and supplied to the voltage control circuit 140.

[0057] The temperature information of the analog signal detected by the temperature detection circuit 130 is converted into a digital signal and output. This reduces the signal attenuation caused by wiring resistance and parasitic capacitance, as well as the effects of noise. Therefore, the temperature detection circuit 130 is provided at a position away from the voltage control circuit 140. Even if the temperature is high, the temperature information can be transmitted to the voltage control circuit 140 accurately.

[0058] [Voltage control circuit 140] As explained with reference to FIG. 2A, the Vth of an OS transistor decreases with decreasing temperature. This shifts the on-state current to the off-state side, resulting in a decrease in the operating speed of the circuit. As the temperature increases, Vth shifts to the negative side and the cutoff current increases. This narrows the temperature range in which the device can operate. By applying a correction voltage according to the operating temperature to the node ND, the output terminal O The voltage output from UT is corrected to ensure the operation of the circuit electrically connected to the output terminal OUT. This can expand the usable temperature range.

[0059] The voltage control circuit 140 includes a logic circuit 145 and a voltage generating circuit 146 (FIG. 1 The logic circuit 145 receives the digital signal from the temperature detection circuit 130. The temperature detection circuit 145 has a function of supplying a signal (temperature information) to the voltage generation circuit 146. 30 is converted into a parallel signal and supplied to a voltage generating circuit 146. In addition, the n-bit digital signal supplied from the temperature detection circuit 130 is converted into m-bit (m is an integer equal to or greater than 1) and supplies the converted digital signal to the voltage generating circuit 146. .

[0060] The voltage generating circuit 146 converts the m-bit digital signal supplied from the logic circuit 145 into m It has the function of converting the voltage into a step voltage and outputting it. In FIG. 1(B), the case where m is 4 is shown as an example. In FIG. 1B, the voltage generating circuit 146 includes a buffer BF1, a buffer BF2, , buffer BF3, buffer BF4, capacitance element C1, capacitance element C2, capacitance element C4, and and a capacitance element C8.

[0061] The 4-bit digital signal output by the logic circuit 145 is input to buffers BF1 to BF5. The first digit of the 4-bit digital signal is supplied to the BF4 input terminal. The first digit is entered into buffer BF1, the second digit is entered into buffer BF2, and the third digit is entered into buffer BF3. The first digit is entered into buffer BF3, and the fourth digit is entered into buffer BF4.

[0062] One electrode of the capacitance element C1 is electrically connected to the output terminal of the buffer BF1, and the other electrode One electrode of the capacitance element C2 is electrically connected to the output terminal OUT. The first electrode is electrically connected to the output terminal, and the other electrode is electrically connected to the output terminal OUT. One electrode of the element C4 is electrically connected to the output terminal of the buffer BF3, and the other electrode is One electrode of the capacitance element C8 is electrically connected to the output terminal OUT of the buffer BF4. and the other electrode is electrically connected to the output terminal OUT.

[0063] The voltage output from the output terminal OUT of the voltage control circuit 140 is called "voltage VBias." The output terminal OUT of the voltage control circuit 140 is electrically connected to a node ND of the semiconductor device 100. will be done.

[0064] The voltage applied to the node ND from the voltage control circuit 140 is a voltage applied to the capacitance element C1, the capacitance element C2, the capacitance It is determined by the ratio of the combined capacitance of the capacitance element C4 and the capacitance element C8 to the parasitic capacitance generated at the node ND. It is preferable that the capacitance value of the capacitive element C1 is sufficiently larger than the capacitance value of the parasitic capacitance. Specifically, the capacitance of the capacitance element C1 is preferably 5 times or more the capacitance of the parasitic capacitance. More than twice as much is more preferable.

[0065] The capacitance values ​​of the capacitance elements C1, C2, C4, and C8 are all Although the capacitances may be the same for all the elements, it is preferable that at least some or all of the elements have different capacitances. In this embodiment, the capacitance value of the capacitive element C2 is set to twice the capacitance value of the capacitive element C1. The capacitance value of the capacitance element C4 is set to four times that of the capacitance element C1, and the capacitance value of the capacitance element C8 is set to The capacitance value of the capacitance element C1 is set to 8 times the capacitance value of the capacitance element C2. It can supply 16 levels of voltage to the ND.

[0066] 6A to 6C show an example of the voltage change of the voltage VBias with respect to the temperature change. The horizontal axis in Fig. 6(A) to (C) indicates temperature on a linear scale. The vertical axis from (C) to (C) indicates the voltage VBias on a linear scale. is an OS transistor, the magnitude of the voltage VBias depends on the operation of transistor M11. It is preferable that the change becomes smaller as the temperature increases (see FIG. 6(A)). Also, depending on the purpose and application, the value may be changed to be larger as the operating temperature increases. (See Figure 6(B).) The magnitude of the voltage VBias does not change linearly with temperature. (See Figure 6(C).) Change in voltage VBias with temperature change can be set by the logic circuit 145.

[0067] <Operation Example of Semiconductor Device 100> FIG. 7 is a timing chart for explaining an example of the operation of the semiconductor device 100. The transistor M11 is an OS transistor and the operating temperature range is 100°C to -50°C. Example of operation in which the voltage VBias changes linearly in the range of 0V to 7.5V when the input voltage VBias changes in the range of 0V to 7.5V. In addition, assume that the voltage VBG is -3V when the operating temperature is 20°C. .

[0068] Also, it is assumed that a 4-bit digital signal VD is output from the temperature detection circuit 130. In this embodiment, when the operating temperature is 100° C., the digital signal VD is “0000”. When the operating temperature is -50°C, "1111" is output.

[0069] In addition, the output of the buffer BF1 connected to one electrode of the capacitance element C1 changes from the L potential to the H potential. When the potential of the other electrode of the capacitance element C1 changes, the potential of the other electrode of the capacitance element C1 increases by 0.5 V. The output of the buffer BF2 connected to one electrode of the capacitance element C2 changes from L potential to H potential. When the potential of the other electrode of the capacitance element C2 is increased by 1.0 V, When the output of the buffer BF3 connected to one of the electrodes of 4 changes from an L potential to an H potential, The potential of the other electrode of the element C4 is increased by 2.0 V. When the output of the buffer BF4 connected to the electrode of the The potential of the other electrode is assumed to increase by 4.0 V.

[0070] [Period T0] The period T0 is a reset period. During the period T0, the buffers BF1 to BF4 The voltage VBG0 is set to -7V, and the L potential (0V) is output from each output terminal. The transistor M12 is turned on. Therefore, the voltage VBG becomes −7 V. During the period T0 In this case, the temperature detection circuit 130 may stop outputting the digital signal VD. The operation of the path 130 may be stopped.

[0071] [Period T1] In the period T1, the transistor M12 is turned off. The voltage of the node ND becomes −7 V. Therefore, the voltage VBG also remains at -7V.

[0072] [Period T2] During a period T2, the temperature detection circuit 130 outputs a digital signal VD(temperature For example, the digital signal VD representing 20°C is “1000”. The pressure is supplied to the pressure control circuit 140.

[0073] The logic circuit 145 outputs the digital signal VD to the buffers BF1 to BF4. Specifically, when the digital signal VD is "1000", The outputs of buffers BF1 to BF3 are at L potential, and the output of buffer BF4 is at H potential. , and controls buffers BF1 to BF4.

[0074] Then, the potential of the output terminal OUT of the voltage control circuit 140 increases by 4 V. Then, the potential of the node N The voltage at D changes from -7V to -3V, and the voltage VBG becomes -3V.

[0075] [Period T3] During a period T3, the temperature detection circuit 130 outputs a digital signal VD(temperature For example, if “0101” is supplied as the digital signal VD indicating 50°C, The pressure is supplied to the pressure control circuit 140.

[0076] As in the period T2, the logic circuit 145 outputs digital When the digital signal VD is "0101", the buffer The output of buffer BF1 is H potential, the output of buffer BF2 is L potential, and the output of buffer BF3 is H potential. At this time, the output of the buffer BF4 becomes the L potential, and the voltage VBG becomes −4.5V.

[0077] [Period T4] During a period T4, the temperature detection circuit 130 outputs a digital signal VD(temperature For example, "1100" is supplied as the digital signal VD indicating -20°C. The voltage is supplied to the voltage control circuit 140.

[0078] As in the periods T2 and T3, the logic circuit 145 controls the buffers BF1 to BF4 to A potential corresponding to the digital signal VD is input to BF4. The digital signal VD is "1100". When the output of buffer BF1 is at L potential, the output of buffer BF2 is at L potential, and buffer BF The output of buffer BF3 goes to H potential, and the output of buffer BF4 goes to H potential. Then, the voltage VBG goes to -1. It becomes 0V.

[0079] In this way, the voltage VBG can be changed according to the temperature change. If temperature changes in the electrical characteristics of the transistor M11 are not taken into consideration, a voltage larger than necessary will be applied to the transistor. A voltage larger than necessary is applied to the second gate of transistor M11. If a voltage is applied to the second gate of M11 for a long period of time, the electrical characteristics of the transistor M11 will deteriorate and the signal According to one aspect of the present invention, the transistor M1 is turned on and off in response to temperature changes. The voltage applied to the second gate of 1 can be changed. Therefore, the minimum required voltage The second gate of the transistor M11 may be applied to the second gate of the transistor M12. This can improve the reliability of a semiconductor device including the transistor M11.

[0080] In addition, a reset period (period T0) is provided at regular intervals to refresh the voltage of node ND. You may do so.

[0081] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0082] (Embodiment 2) In this embodiment, a memory device using the semiconductor device 100 described in the first embodiment will be described. Reveal.

[0083] <Storage device> 8 is a block diagram showing a configuration example of a storage device. , a cell array 401, and a semiconductor device 100. The circuit 311 includes a row decoder 321, a word line driver circuit 322, and a column decoder 33. 1, a bit line driver circuit 330, an output circuit 340, and a control logic circuit 360 Yes.

[0084] The word line driver circuit 322 has a function of supplying a potential to the wiring WL. The driver circuit 330 includes a precharge circuit 332, an amplifier circuit 333, and an input / output circuit 334. The precharge circuit 332 includes a wiring SL (not shown), a wiring BIL, or a wiring R The amplifier circuit 333 has a function of precharging the wiring BIL or the wiring R The line WL, the line SL, The wiring BIL and the wiring RBL are connected to the memory cells (Memory This is the wiring connected to the Amplified Data Cell 411, which will be described in detail later. The signal is output to the storage device 30 via the output circuit 340 as a digital data signal RDATA. 0 is output to the outside.

[0085] The storage device 300 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, A high power supply voltage (VDD) for the cell array 401 and a high power supply voltage (VIL) for the cell array 401 are supplied.

[0086] The memory device 300 also includes control signals (CE, WE, RE), an address signal ADDR, The data signal WDATA is input from the outside. The address signal ADDR is input to the row decoder 32. 1 and a column decoder 331, and the data signal WDATA is input to an input / output circuit 334. is entered.

[0087] The control logic circuit 360 processes external input signals (CE, WE, RE). CE generates control signals for the row decoder 321 and the column decoder 331. WE is the write enable signal, RE is the read enable signal, The signals processed by the control logic circuit 360 are not limited to these. However, other control signals may be input as necessary.

[0088] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0089] The transistors constituting the cell array 401 can be OS transistors. In addition, OS transistors can be used as transistors constituting the peripheral circuit 311. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, The cell array 401 and the peripheral circuit 311 can be manufactured in the same manufacturing process. This allows the manufacturing costs to be kept low.

[0090] [Example of cell array configuration] 9 shows the details of the cell array 401. The cell array 401 has m (m is 1 or more) cells arranged in a row. ) in each row (n is an integer greater than or equal to 1), for a total of m × n memory cells. The memory cells 411 are arranged in a matrix. The address of 11 is also shown. For example, [1,1] is the address of the first row and first column. The memory cell 411 in which the memory cell is located is indicated by [i, j] (i is an integer between 1 and m, and j is an integer between 1 and m). is an integer between 1 and n.) is the address of the memory cell 4 located at the address of the i-th row and the j-th column. 11. The cell array 401 and the word line driver circuit 322 are connected. The number of wirings depends on the configuration of the memory cells 411, the number of memory cells 411 included in one row, etc. Also, the wiring connecting the cell array 401 and the bit line driver circuit 330 is The number of lines depends on the configuration of the memory cells 411, the number of memory cells 411 included in one row, etc. It is decided.

[0091] [Example of memory cell configuration] FIG. 10 shows memory cells 411A to 411B that can be applied to the above-described memory cell 411. An example of the configuration of 1E is shown below.

[0092] [DOSRAM] FIG. 10A shows an example of a circuit configuration of a DRAM type memory cell 411A. DRAM using OS transistors is called DOSRAM (Dynamic Oxid It is called eSemiconductor Random Access Memory (ESRAM). The memory cell 411A includes a transistor M11 and a capacitor Cs.

[0093] A first terminal of the transistor M11 is connected to a first terminal of the capacitance element Cs. The second terminal of the transistor M11 is connected to the wiring BIL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the transistor Cs is connected to the wiring GNDL. The wiring GNDL is a low-level potential ( This is sometimes called the reference potential.

[0094] The wiring BIL functions as a bit line, and the wiring WL functions as a word line. L functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By applying an arbitrary potential to GL, the threshold voltage of transistor M11 can be increased or decreased. It is possible.

[0095] Data is written and read by applying a high-level potential to the wiring WL and 11 is brought into a conductive state, and the wiring BIL and the first terminal of the capacitance element Cs are electrically connected to each other. This is what happens.

[0096] In addition, the memory cells included in the memory device 300 described above are not limited to the memory cells 411A. , the circuit configuration can be changed.

[0097] When the transistor M11 is used in a memory cell, an OS transistor is used as the transistor M11. In addition, it is preferable to use a semiconductor layer of the OS transistor containing indium, an element M, or the like. (Element M is aluminum, gallium, yttrium, or tin), or zinc In particular, an oxide semiconductor containing indium, gallium, or zinc is preferably used. It is preferable to use an oxide semiconductor.

[0098] OS transistors using oxide semiconductors containing indium, gallium, and zinc have The transistor M11 has the characteristic of having an extremely small current. By using the above, the leakage current of the transistor M11 can be made very low. In other words, the written data can be retained for a long time by the transistor M11. Therefore, the frequency of refreshing the memory cells can be reduced. This eliminates the need for refresh operations. Also, the leakage current is very low, so the memory The recell 411A can hold multi-value data or analog data.

[0099] DOSRAM is constructed by applying an OS transistor as transistor M11. It is possible.

[0100] [NOSRAM] FIG. 10B shows a gain cell type ("2Tr 1C type). The memory cell 411B has a circuit configuration example. , a transistor M11, a transistor M3, and a capacitance element Cs.

[0101] A first terminal of the transistor M11 is connected to a first terminal of the capacitance element Cs. The second terminal of the transistor M11 is connected to the wiring WBL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is connected to the wiring BGL. A second terminal of the transistor Cs is connected to the line RL. A first terminal of the transistor M3 is connected to the line RL. A second terminal of the transistor M3 is connected to the line SL. A second terminal of the transistor M4 is connected to the line SL. The gate of M3 is connected to the first terminal of the capacitive element Cs.

[0102] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL is connected to the second terminal of the capacitance element Cs. It functions as a wiring for applying a specific potential. In particular, it is preferable to apply a reference potential to the wiring RL.

[0103] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0104] To write data, a high-level potential is applied to the line WL to turn on the transistor M11. This is achieved by electrically connecting the wiring WBL and the first terminal of the capacitance element Cs. Specifically, when the transistor M11 is in a conductive state, A potential is applied to the first terminal of the capacitance element Cs and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WL to turn off the transistor M11. By setting the capacitor Cs in the ON state, the potential of the first terminal of the capacitor Cs and the gate The potential of the input is maintained.

[0105] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor M3 and the first The potential of the terminal is the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. The potential of the wiring RBL connected to the first terminal of the transistor M3 is By reading out the potential, the first terminal of the capacitance element Cs (or the gate of the transistor M3) In other words, the potential held in the first terminal (or The potential held on the gate of transistor M1 or the gate of transistor M2 is used to determine the potential to be written to this memory cell. The information stored in this memory cell can be read out. You can find out whether it is available or not.

[0106] In addition, the memory cells included in the memory device 300 described above are not limited to the memory cells 411B. The circuit configuration can be changed as appropriate.

[0107] For example, the wiring WBL and the wiring RBL may be combined into one wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. The wiring WBL and the wiring RBL of the transistor M11 are connected to one wiring BIL. The second terminal and the first terminal of the transistor M3 are connected to the wiring BIL. That is, in the memory cell 411C, one wiring BIL is connected to the write bit line and The bit lines 11 and 12 function as read bit lines.

[0108] In the memory cells 411B and 411C, the transistor M11 It is preferable to use an OS transistor as the transistor M11. In addition, 2Tr1C type memory cells such as memory cell 411B and memory cell 411C The memory device using this is called NOSRAM (Non-volatile Oxide Semiconductor RAM). It is called Inductor Random Access Memory.

[0109] It is preferable that the channel formation region of the transistor M3 contains silicon. The silicon may be amorphous silicon, polycrystalline silicon, low temperature polysilicon (LTPS), Low Temperature Poly-Silicon (hereafter A transistor that uses silicon is called a Si transistor. The read transistor can have a higher field-effect mobility than the OS transistor. It is preferable to use a Si transistor as the transistor.

[0110] In addition, when an OS transistor is used as the transistor M3, the memory cell is a unipolar circuit. It can be composed of:

[0111] Also, in Figure 10(D), a gain cell type with 3 transistors and 1 capacitor (called a "3Tr1C type") is shown. 4 shows an example of a circuit configuration of a memory cell 411D of the above-mentioned embodiment. The memory cell 411D is a transistor. A transistor M11, a transistor M5, a transistor M6, and a capacitance element Cs. .

[0112] A first terminal of the transistor M11 is connected to a first terminal of the capacitance element Cs. The second terminal of the transistor M11 is connected to the wiring BIL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is electrically connected to the wiring BGL. The second terminal of the capacitance element Cs is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6. The gate of the transistor M5 is connected to the first terminal of the capacitance element Cs. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring R It is connected to L.

[0113] The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and The line RL functions as a read word line.

[0114] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0115] To write data, a high-level potential is applied to the line WL to turn on the transistor M11. The wiring BIL is connected to the first terminal of the capacitance element Cs. is a potential corresponding to information to be recorded in the wiring BIL when the transistor M11 is in a conductive state. The potential is written to the first terminal of the capacitance element Cs and the gate of the transistor M5. After that, a low-level potential is applied to the line WL to turn off the transistor M11. As a result, the potential of the first terminal of the capacitance element Cs and the potential of the gate of the transistor M5 Hold.

[0116] To read data, a predetermined potential is precharged to the line BIL, and then the line BIL is This is done by putting the wiring RL in an electrically floating state and applying a high-level potential to the wiring RL. Since the line RL is at a high level potential, the transistor M6 is in a conductive state, and the line BIL and The second terminal of the transistor M5 is electrically connected. The potential of the wiring BIL is applied to the second terminal, but the potential of the first terminal ( or the gate of transistor M5), The potential of the second terminal and the potential of the wiring BIL change. By outputting the current, the first terminal of the capacitance element Cs (or the gate of the transistor M5) In other words, the potential stored in the first terminal (or the transistor) of the capacitance element Cs can be read out. The potential held at the gate of transistor M5 indicates that the data written to this memory cell You can read out the information or check whether the information is written in this memory cell. You can find out.

[0117] In addition, the circuit configuration of the memory cell included in the above-described memory device 300 can be changed as appropriate. can.

[0118] In addition, in the memory cell 411D, an OS transistor is used as the transistor M11. It is preferable that the transistor M11 is a 3Tr1C type transistor using an OS transistor. Memory cell 411D is one embodiment of the NOSRAM previously described.

[0119] In addition, the channel forming regions of the transistors M5 and M6 described in this embodiment are It is preferable that the silicon has a silicon content of 10 ... , low-temperature polysilicon. Si transistors are more cost-effective than OS transistors. A Si transistor is used as the readout transistor because it may have a high field effect mobility. It is preferable to apply the stan.

[0120] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell It can be constructed with a unipolar circuit.

[0121] [oxSRAM] FIG. 10(E) shows a static random access memory (SRAM) using OS transistors. 4 shows an example of a circuit configuration of a memory cell 411E of the access memory type. In this paper, the SRAM using OS transistors is called oxSRAM. ) is a backup capable SRAM type memory cell.

[0122] The memory cell 411E includes transistors M7 to M10 and a transistor MS 1 to MS4, and a capacitor Cs1 and a capacitor Cs2. The transistors M7 and M8 correspond to the transistor M11. The transistors M7 to M10 are transistors having a back gate. The transistors MS1 and MS2 are p-channel transistors. The transistor MS3 and the transistor MS4 are n-channel transistors. be.

[0123] A first terminal of the transistor M7 is connected to the wiring BIL, and a second terminal of the transistor M7 is , a first terminal of the transistor MS1, a first terminal of the transistor MS3, and a transistor M a gate of transistor S2, a gate of transistor MS4, and a first terminal of transistor M10; The gate of the transistor M7 is connected to the wiring WL. The back gate of the transistor is connected to the wiring BGL1.

[0124] A first terminal of the transistor M8 is connected to the line BILB, and a second terminal of the transistor M8 is connected to the line BILB. a first terminal of the transistor MS2, a first terminal of the transistor MS4, and a second terminal of the transistor a gate of transistor MS1, a gate of transistor MS3, and a first terminal of transistor M9; The gate of the transistor M8 is connected to the wiring WL. The back gate of is connected to the wiring BGL2.

[0125] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS4 is electrically connected to the wiring GNDL. It is connected to the line GNDL.

[0126] The second terminal of the transistor M9 is connected to the first terminal of the capacitance element Cs1. The gate of the transistor M9 is connected to the wiring BGL. 3. The second terminal of the transistor M10 is connected to the first terminal of the capacitance element Cs2. The gate of the transistor M10 is connected to the wiring BRL. The back gate is connected to a wiring BGL4.

[0127] The second terminal of the capacitance element Cs1 is connected to the wiring GNDL, and the second terminal of the capacitance element Cs2 is It is connected to the wiring GNDL.

[0128] The wirings BIL and BILB function as bit lines, and the wiring WL functions as a word line. The wiring BRL controls the conductive state and non-conductive state of the transistor M9 and the transistor M10. This is the wiring that controls the on state.

[0129] The wirings BGL1 to BGL4 are the transistors M7 to M10, respectively. It functions as a wiring for applying a potential to the back gate.

[0130] The wirings BGL1 to BGL4 are electrically connected to the output terminal OUT of the semiconductor device 100. In addition, a plurality of semiconductor devices 100 are provided in the storage device 300, and wirings BGL1 to BGL2 are provided in the storage device 300. The wirings BGL1 to GL4 may be electrically connected to different semiconductor devices 100. By applying an arbitrary potential to the wiring BGL4, the transistors M7 to The threshold voltage of transistor M10 can be increased or decreased.

[0131] The wiring VDL is a wiring that provides a high-level potential, and the wiring GNDL is a wiring that provides a low-level potential. This is the wiring.

[0132] To write data, a high-level potential is applied to the line WL and a high-level potential is applied to the line BRL. Specifically, when transistor M10 is in a conducting state, A potential corresponding to the information to be recorded is applied to the wiring BIL, and the second terminal side of the transistor M10 The potential is written to

[0133] By the way, the memory cell 411E is configured by the transistors MS1 and MS2. Since an inverter loop is formed by these two transistors, the second terminal of the transistor M8 is connected to the The inverted signal of the corresponding data signal is input. Since transistor M8 is in a conductive state, The line BILB is connected to the potential applied to the wiring BIL, i.e., the potential input to the wiring BIL. The inverted signal of the signal is output. Since the transistor M7 is in a conducting state, the potential of the second terminal of the transistor M7 and the potential of the third terminal of the transistor M8 are The potentials of the two terminals are the first terminal of the capacitance element Cs2 and the first terminal of the capacitance element Cs1, respectively. After that, a low level potential is applied to the wiring WL, and a low level potential is applied to the wiring BRL. By applying a potential V 1 to transistors M7 through M10, transistors M7 through M10 are turned off. , the potential of the first terminal of the capacitance element Cs1 and the potential of the first terminal of the capacitance element Cs2 are held.

[0134] To read data, the lines BIL and BILB are precharged to a predetermined potential. After the write operation, a high-level potential is applied to the wiring WL and a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitance element Cs1 becomes the inverter of the memory cell 411E. The first signal of the capacitance element Cs2 is refreshed by the loop and output to the wiring BILB. The potential of the first terminal is refreshed by the inverter loop of the memory cell 411E, and the The signal is output to the line BIL. The signal is precharged on the lines BIL and BILB. The potential at the first terminal of the capacitance element Cs2 and the potential at the first terminal of the capacitance element Cs1 are Since the potential of the wiring BIL or BILB varies, the potential held in the memory cell can be read out.

[0135] Note that OS transistors may be used as the transistors M7 to M10. It is preferable to use OS transistors for the transistors M7 to M10. Therefore, data written in the memory cell 411E can be retained for a long time. This reduces the frequency of refreshing the memory cell 411E. This eliminates the need for a refresh operation in 11E. Also, the leakage current is very low, Therefore, multi-value data or analog data can be stored in the memory cell 411E. Cut.

[0136] Note that silicon is used for the channel formation regions of the transistors MS1 to MS4. In particular, the silicon may be amorphous silicon, polycrystalline silicon, low-temperature polysilicon, etc. Silicon transistors can be made of silicon. Si transistors have a higher field effect than OS transistors. In some cases, the mobility of the Si transistors in the inverters is high. It is preferable to use a transistor.

[0137] In addition, by using OS transistors in memory cells, the power supply to the memory cells can be stopped. Therefore, the information written in the memory cell can be retained for a long time even if the memory cell is When writing is not required, power supply to a part or all of the peripheral circuit 311 is stopped. This can be done.

[0138] One semiconductor device 100 may be electrically connected to all memory cells. A plurality of semiconductor devices 100 are provided in the memory cell array 300, and a plurality of memory cells are arranged in each column or in each plurality of columns. A single semiconductor device 100 may be electrically connected. The memory cells may be electrically connected to one semiconductor device 100. The included memory cells are divided into multiple blocks, and each block or multiple blocks are Alternatively, one semiconductor device 100 may be provided for each block.

[0139] The memory cells described in this embodiment are included in registers and It can be used in memory elements such as caches.

[0140] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0141] (Embodiment 3) In this embodiment, a configuration example of a cell array 401 included in a storage device 300 and an operation example thereof will be described. In this embodiment, the memory cell 411 is a DRAM type memory cell. Use 411A.

[0142] FIG. 11 shows an example of a cell array 401 different from that shown in FIG. 9. FIG. 11 shows a folded bit line type The memory cell array is of the folded bit line type. A can also be used in memory cell arrays with open bit line technology. can.

[0143] The cell array 401 shown in FIG. 11 has m (m is an integer of 1 or more) cells in one column and n (n is an integer of 1 or more) memory cells 411A, totaling m×n memory cells 11, the addresses of the memory cells 411A are also shown. For example, [i, j] indicates the memory cell 411A in the i-th row and j-th column.

[0144] The cell array 401 shown in FIG. 11 is electrically connected to the word line driver circuit 322. The wiring WL[1] is electrically connected to the memory cell 411A in the first row. Similarly, the wiring WL[i] is electrically connected to the memory cell 411A in the i-th row. .

[0145] Also, the cell array 401 shown in FIG. 11 has two wirings BIL (wirings BILa and In FIG. 11, the wiring BILa in the first column is indicated as wiring BILa[1]. , the wiring BILb in the jth column is indicated as wiring BILb[j].

[0146] The memory cell 411A arranged in the odd-numbered row is connected to one of the wiring BILa and the wiring BILb. The memory cells 411A arranged in the even-numbered rows are electrically connected to the wiring BILa or the wiring B It is electrically connected to the other of ILb.

[0147] The wirings BILa and BILb are connected to a precharge circuit 332 provided for each column. , the amplifier circuit 333, and the input / output circuit 334. 34 is electrically connected to the wiring SALa and wiring SALb for each column. The precharge circuit 332 in the jth column is designated as the precharge circuit 332[1]. The amplifier circuit 333 and the input The output circuit 334 is also indicated in the same manner. It has a coder 331 (see FIG. 8).

[0148] <Circuit configuration example> FIG. 12 shows a J-th column memory cell 411A, a precharge circuit 332, an amplifier circuit 333, and 3 shows an example of a circuit configuration of the input / output circuit 334.

[0149] [Precharge circuit 332] The precharge circuit 332[j] includes n-channel transistors Tr21 to The transistors Tr21 to Tr23 are p-channel transistors. Either the source or the drain of the transistor Tr21 is connected to the wiring BIL a[j], and the other of the source and drain is connected to the wiring PRE. Either the source or the drain of the transistor Tr22 is connected to the wiring BILb[j]. The other of the source and drain of the transistor Tr23 is connected to the wiring PRE. One of the sources or drains is connected to the wiring BILa[j], and the other is connected to the wiring BIL b[j]. The gate of transistor Tr21 and the gate of transistor Tr22 are connected to The gate of the transistor Tr23 and the gate of the transistor Tr24 are connected to the line PL. The circuit 332[j] has a function of initializing the potentials of the wiring BILa[j] and the wiring BILb[j]. Possesses the ability.

[0150] [Amplification circuit 333] The amplifier circuit 333[j] includes a p-channel transistor Tr31 and a p-channel transistor Tr3 2, and n-channel transistors Tr33 and Tr34. Either the source or the drain of the transistor Tr31 is connected to the wiring SP. The other is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BI One of the source and drain of the transistor Tr33 is connected to the transistor La[j]. The gate of transistor Tr32, the gate of transistor Tr34, and the wiring BILa[j] The other of the source and the drain is connected to the wiring SN. Either the source or the drain of 2 is connected to the wiring SP, and the other of the source or the drain is connected to the transistor The gate of transistor Tr31, the gate of transistor Tr33, and the wiring BILb[j] One of the source and drain of the transistor Tr34 is connected to the transistor Tr 31, the gate of transistor Tr33, and the wiring BILb[j]. The other of the source and drain is connected to the wiring SN. The amplifier circuit 333[ j] functions as a latch-type sense amplifier.

[0151] [Input / output circuit 334] The input / output circuit 334[j] includes an n-channel transistor Tr41 and a transistor Tr The transistors Tr41 and Tr42 are p-channel Either the source or the drain of the transistor Tr41 may be connected to the wiring BILa[j ], and the other of the source and drain is connected to the wiring SALa[j]. Either the source or the drain of the transistor Tr42 is connected to the wiring BILb[j]. The other of the drains is connected to the wiring SALb[j]. The output of the transistor Tr41 and the gate of the transistor Tr42 are connected to a line CSEL.

[0152] The input / output circuit 334[j] outputs a potential to the line BILa[ j] and wiring SALa[j], and the conduction state of wiring BILb[j] and wiring SALb[j] That is, the input / output circuit 334[j] controls the conduction state of the wiring S It is possible to select whether or not to output a potential to the wiring ALa[j] and wiring SALb[j].

[0153] The wiring SP, the wiring SN, the wiring CSEL, the wiring PRE, and the wiring PL are connected to a precharge circuit 332. , the amplifier circuit 333, and the input / output circuit 334. The wiring SP, the wiring SN, the wiring CSEL, the wiring PRE, and the wiring PL are the components shown in FIG. The control logic circuit 360 is connected to the It has the function of supplying control signals to the lines SP, SN, CSEL, PRE, and PL. do.

[0154] <Example of operation> The memory cell 411A[i,j], the precharge circuit 332[j], and the amplifier circuit shown in FIG. 333[j] and input / output circuit 334[j] to set the operation mode of storage device 300. The storage device 300 is assumed to be operating at 20° C. Assume that −3 V is supplied from the device 100 to the wiring BGL.

[0155] [Read mode] First, when reading data from the memory cell 411A[i,j], An example of the operation will be described with reference to the timing chart shown in FIG.

[0156] [Period T11] In a period T11, the precharge circuit 332[j] is operated to Specifically, the potential of the wiring PL is set to a high level ( VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is applied to the wiring BILa[j] and the wiring BILb[j]. The potential Vpre is, for example, (VH_SP+VL_SN) / 2. This can be done.

[0157] In the period T11, the potential of the wiring CSEL is at a low level (VL_CSEL). In the input / output circuit 334[j], the transistors Tr41 and Tr42 are off. In addition, the potential of the wiring WL[i] is at a low level (VL_WL), and the The transistor M11 in the filter 411A[i,j] is in the off state. Although not shown in the figure, the potential of the wiring WL[i+1] is at a low level (VL_WL), The transistor M11 in the memory cell 411A[i+1,j] is in an off state. The potentials of the wiring SP and the wiring SN are the potential Vpre, and the amplifier circuit 333[j] is in a stopped state. It has become.

[0158] [Period T12] In a period T12, the potential of the wiring PL is set to a low level (VL_PL), and the transistor T The transistors r21 to Tr23 are turned off. In addition, the wiring WL[i] is selected. Specifically, the potential of the wiring WL[i] is set to a high level (VH_WL). The transistor M11 in the resonator 411A[i,j] is turned on. In the memory cell 411A[i,j], the wiring BILa[j] and the capacitance element Cs form a transistor. The capacitor M11 becomes conductive, and the wiring The potential of BILa[j] fluctuates.

[0159] In FIG. 13, data “1” is stored in the memory cell 411A[i,j], and the capacitance element Cs This shows an example in which a large amount of charge is stored. When the amount of charge stored in the capacitor Cs is large, the charge is discharged from the capacitor Cs to the wiring BILa[j]. As a result, the potential of the wiring BILa[j] rises by ΔV1 from the potential Vpre. The data “0” is stored in the memory cell 411A[i,j] and accumulated in the capacitance element Cs. When the amount of charge is small, the charge flows from the wiring BILa[j] to the capacitance element Cs. As a result, the potential of the wiring BILa[j] drops by ΔV2 (not shown).

[0160] In addition, in the period T12, the potential of the wiring CSEL is at a low level (VL_CSEL). In the input / output circuit 334[j], the transistors Tr41 and Tr42 are off. The potentials of the wiring SP and the wiring SN are the potential Vpre, and the amplifier circuit 333 [j] remains stopped.

[0161] [Period T13] In a period T13, the potential of the wiring SP is changed to a high level (VH_SP). The potential of N is changed to a low level (VL_SN). Then, the amplifier circuit 333[j] The amplifier circuit 333[j] is in an active state. The amplifier circuit 333[j] has a function of amplifying the potential difference (ΔV1 in FIG. 13). By entering the operating state, the potential of the wiring BILa[j] changes from Vpre+ΔV1 to the potential of the wiring S The potential of the wiring BILb[j] approaches the potential of the wiring P (VH_SP). Approaching the potential of line SN (VL_SN).

[0162] Note that at the beginning of the period T13, the potential of the wiring BILa[j] is Vpre-ΔV2. In this case, the amplifier circuit 333[j] is put into an operating state, so that the potential of the wiring BILa[j] The potential of the wiring SN approaches the potential (VL_SN) from Vpre-ΔV2. The potential of [j] approaches the potential (VH_SP) of the wiring SP from the potential Vpre.

[0163] In addition, during the period T13, the potential of the wiring PL is at a low level (VL_PL). In the page circuit 332[j], the transistors Tr21 to Tr23 are in the off state. In addition, the potential of the wiring CSEL is at a low level (VL_CSEL), and the input / output circuit In the path 334[j], the transistors Tr41 and Tr42 are in the off state. In addition, the potential of the wiring WL[i] is at a high level (VH_WL), and the memory cell 411A The transistor M11 in the memory cell [i,j] is in the on state. In [i,j], the amount of charge according to the potential (VH_SP) of the wiring BILa[j] is It accumulates in Cs.

[0164] [Period T14] In the period T14, the potential of the wiring CSEL is controlled to Specifically, the potential of the wiring CSEL is set to high level (VH_CSEL). This causes the transistors Tr41 and Tr42 to be turned on. As a result, the potential of the wiring BILa[j] is supplied to the wiring SALa[j], and the potential of the wiring BILb[ The potential of the line SALb[j] is supplied to the line SALb[j].

[0165] In the period T14, the potential of the wiring PL is at a low level (VL_PL). In the charge circuit 332[j], the transistors Tr21 to Tr23 are off. In addition, the potential of the wiring WL[i] is at a high level (VH_WL), and the The transistor M11 of the wiring SP[i,j] is in an on state. The potential of the line SN is at a low level (VL_SN). Therefore, the amplifier circuit 333[j] is in an active state. In this case, a charge corresponding to the potential (VH_SP) of the wiring BILa[j] is stored in the capacitance element Cs. It is being done.

[0166] [Period T15] In the period T15, the potential of the wiring CSEL is controlled to Specifically, the potential of the wiring CSEL is set to the low level (VL_CSEL). This causes the transistors Tr41 and Tr42 to be turned off.

[0167] In addition, in the period T15, the wiring WL[i] is set to a non-selected state. The potential of L[i] is set to a low level (VL_WL). Then, the memory cell 411A[i, j] is turned off. As a result, the potential of the wiring BILa (VH The amount of charge corresponding to the charge amount SP is stored in the capacitance element Cs of the memory cell 411A[i,j]. Therefore, even after the data is read, the data is stored in the memory cell 411A[i,j ] is held in

[0168] In addition, even if the input / output circuit 334[j] is turned off during the period T15, the amplifier circuit 333 If [j] is in operation, the potential of wiring BILa[j] and wiring BILb[j] is the amplifier circuit 333[j]. Therefore, the amplifier circuit 333[j] is held by the memory cell 411A It has the function of temporarily storing the data read from [i,j].

[0169] By the above operation, data can be read from memory cell 411A[i,j]. The read data is sent via wiring SALa[j] and / or wiring SALb[j]. The output circuit 340 (see FIG. 8) is supplied with the memory cell 411A[i+1,j]. Data can be read from memory cell 411A[i,j] in the same manner as for memory cell 411A[i,j].

[0170] [Write mode] Next, the operation of the amplifier circuit 333[j] when writing data to the memory cell 411A[i,j] will be described. An example of this will be described with reference to the timing chart shown in FIG. Writing data to A[i+1,j] can be done using the same principle as above.

[0171] [Period T21] In a period T21, the transistors Tr21 to Tr22 of the precharge circuit 332[j] The transistor Tr23 is turned on, and the wiring BILa[j] and the wiring BILb[j] are turned on. The potential is initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL) and the transistor The transistors Tr21 to Tr23 are turned on. The potential Vpre of the wiring PRE is supplied to the wiring a[j] and the wiring BILb[j]. The potential Vpre can be, for example, (VH_SP+VL_SN) / 2.

[0172] [Period T22] In a period T22, the potential of the wiring PL is then set to a low level (VL_PL). The transistors Tr21 to Tr23 are turned off. The wiring WL[i] connected to the memory cell 411A[i,j] to be processed is selected. , the potential of the wiring WL[i] is set to a high level (VH_WL), and the memory cell 411A[i,j ] is turned on. This causes the transistor M11 in the memory cell 411A[i , j], the wiring BILa[j] and the capacitance element Cs are in a conductive state through the transistor M11. Become a stubborn person.

[0173] At this time, if data “1” is already stored in the memory cell 411A[i,j], When charge is discharged from element Cs to wiring BILa[j], the potential Vpre changes to ΔV The potential of the wiring BILa[j] increases by 1.

[0174] [Period T23] In a period T23, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to is set to a low level (VL_SN), and the amplifier circuit 333[j] is put into an operating state.

[0175] [Period T24] In the period T24, the potential of the wiring CSEL is controlled to ] is turned on. This brings the wiring BILa[j] and the wiring SALa[j] into a conductive state. As a result, the wiring BILb[j] and the wiring SALb[j] are brought into a conductive state.

[0176] The data signal WDATA is input / output via the wiring SALa[j] and wiring SALb[j]. The data is supplied to the wiring SALa[j] and the wiring SALb[j]. By supplying a write potential corresponding to the data signal WDATA, the input / output circuit 334[j A write potential is applied to the wiring BILa[j] and the wiring BILb[j] via . For example, when data “0” is stored in the memory cell 411A[i,j], the wiring SALa[ j], and a high level (VH_S P).

[0177] Then, the transistors Tr31 to Tr34 in the amplifier circuit 333[j] The on / off state of the line SN is inverted, and the potential of the line SN (VL_SN) is supplied to the line BILa[j]. The potential (VH_SP) of the wiring SP is supplied to the wiring BILb[j]. An amount of charge corresponding to the potential (VL_SN) indicating “0” is stored in the capacitance element Cs. By this operation, data can be written to the memory cell 411A[i,j].

[0178] [Period T25] In the period T25, the wiring WL[i] is set to a non-selected state. The charge written to 11A[i,j] is held. Also, the potential of the wiring CSEL is changed to low level. By setting the bell (VL_CSEL), transistor Tr41 and transistor Tr4 2 to the off state.

[0179] After the potential of the wiring SALa[j] is supplied to the wiring BILa[j], Even if the transistor Tr41 and the transistor Tr42 are turned off in 34[j], If the amplifier circuit 333[j] is in an operating state, the wiring BILa[j] and the wiring BILb[j] The potential is maintained by the amplifier circuit 333[j]. The timing to change the resistor Tr42 from the ON state to the OFF state is determined by wiring WL[i]. This may be before or after.

[0180] By the above operation, data can be written to the memory cell 411A[i,j]. Data is written to the memory cell 411A[i+1,j] by the same method as in the memory cell 411A[ This can be done in the same way as for [i,j].

[0181] [Refresh mode] In order to maintain the data written in the memory cell 411A[i,j], the memory cell 411A[i,j] is refreshed at regular intervals. Refresh operation (rewrite operation) is performed. Amplification circuit 333[j] during refresh operation An example of the operation will be described with reference to the timing chart shown in FIG. The push operation can be performed according to the same principle as above.

[0182] [Period T31] In a period T31, the transistors Tr21 to Tr24 of the precharge circuit 332[j] The transistor Tr23 is turned on, and the wiring BILa[j] and the wiring BILb[j] are turned on. The potential is initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL) and the transistor The transistors Tr21 to Tr23 are turned on. The potential Vpre of the wiring PRE is supplied to the wiring a[j] and the wiring BILb[j].

[0183] [Period T32] In a period T32, the potential of the wiring PL is set to a low level (VL_PL), and the transistor T r21 to transistor Tr23 are turned off. Select the wiring WL[i] connected to the rechargeable cell 411A[i,j]. Specifically, select the wiring W The potential of L[i] is set to a high level (VH_WL), and the potential of the memory cell 411A[i,j] is set to a high level (VH_WL). This causes the transistor M11 in the memory cell 411A[i,j] to be turned on. In this case, the wiring BILa[j] and the capacitance element Cs are in a conductive state via the transistor M11. .

[0184] At this time, if data “1” is already stored in the memory cell 411A[i,j], When charge is discharged from element Cs to wiring BILa[j], the potential Vpre changes to ΔV The potential of the wiring BILa[j] increases by 1.

[0185] [Period T33] In a period T33, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to is set to a low level (VL_SN), and the amplifier circuit 333[j] is put into an operating state. When 33[j] becomes active, the potential of the wiring BILa[j] becomes Vpre+ΔV 1, the potential of the wiring SP (VH_SP) approaches. Also, the potential of the wiring BILb[j] approaches V pre approaches the potential of the wiring SN (VL_SN). The time required for T33 is called the "write time."

[0186] [Period T34] In the period T34, the wiring WL[i] is set to a non-selected state. ] to a low level (VL_WL), This causes the potential of the wiring BILa (VH_SP ) is held in the capacitance element Cs of the memory cell 411A[i,j].

[0187] In refresh mode, no data is read or written, so the input / output circuit 334[j] can remain in the off state. Thus, the refresh mode is the same as the read mode. This can be performed in a shorter time than the read and write modes. The refresh mode of memory cell 411A[i,j] is performed in the same manner as memory cell 411A[i,j]. This can be done.

[0188] [NV mode] By using an OS transistor for the transistor M11, it is possible to achieve a period when there is no need to read or write information. During this time, power supply to a part or all of the peripheral circuit 311 and the cell array 401 is stopped. At this time, the storage device 300 is in NV mode (Non-volatile mode). It is preferable to operate the device in non-volatile mode (NV mode). An example of the operation in NV mode is as follows: This will be explained with reference to the timing chart shown in FIG.

[0189] [Period T41] In a period T41, the transistors Tr21 to Tr24 of the precharge circuit 332[j] The transistor Tr23 is turned on, and the wiring BILa[j] and the wiring BILb[j] are turned on. The potential is initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL) and the transistor The transistors Tr21 to Tr23 are turned on. The potential Vpre of the wiring PRE is supplied to the wiring BILa[j] and the wiring BILb[j]. The period T41 corresponds to the period T31 in the refresh mode.

[0190] [Period T42] In a period T42, the potential of the wiring PL is set to a low level (VL_PL), and the transistor T r21 to transistor Tr23 are turned off. Select the wiring WL[i] connected to the rechargeable cell 411A[i,j]. Specifically, select the wiring W The potential of L[i] is set to a high level (VH_WL), and the potential of the memory cell 411A[i,j] is set to a high level (VH_WL). This causes the transistor M11 in the memory cell 411A[i,j] to be turned on. In this case, the wiring BILa[j] and the capacitance element Cs are in a conductive state via the transistor M11. .

[0191] At this time, if data “1” is already stored in the memory cell 411A[i,j], When charge is discharged from element Cs to wiring BILa[j], the potential Vpre changes to ΔV The potential of the wiring BILa[j] rises by 1. Note that the period T42 is a refresh mode. This corresponds to period T32 in the

[0192] [Period T43] In a period T43, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to is set to a low level (VL_SN), and the amplifier circuit 333[j] is put into an operating state. When 33[j] becomes active, the potential of the wiring BILa[j] becomes Vpre+ΔV 1, the potential of the wiring SP (VH_SP) approaches. Also, the potential of the wiring BILb[j] approaches V The potential of the wiring SN approaches the potential (VL_SN) from pre. Therefore, in the NV mode, the time required for the period T43 is The time between these two is the "write time."

[0193] In the NV mode, in order to ensure that the amount of charge corresponding to the data is stored in the capacitance element Cs, In the NV mode, the write time is set longer than that in the refresh mode. The write time should be at least 1.5 times the write time in the refresh mode, and preferably twice as long. More than 5 times is more preferable, and 5 times or more is even more preferable. This can prevent data from running out.

[0194] [Period T44] In a period T44, the potential of the wiring WL[i] is set to a low level (VL_WL), The transistor in the cell 411A[i,j] is turned off. If the threshold voltage of 11 is VthM (VthM>0V), then regardless of the operating temperature, GL is -VthM or less, preferably -2×VthM or less, more preferably -3×VthM For example, if VthM is 2V, the wiring A potential of -2 V or less, preferably -4 V or less, more preferably -6 V or less is supplied to BGL. In this embodiment, −7 V is supplied to the wiring BGL in the period T44.

[0195] After the end of the period T44, the power supply to the peripheral circuit 311 or the entirety and the cell array 401 is stopped. Stop providing.

[0196] The write time is made longer than the write time in the refresh mode, and the wiring BGL is set to -Vt hM or less, preferably -2×VthM or less, more preferably -3×VthM or less. By supplying power to the cell array 401, the written data can be stored even if the power supply to the cell array 401 is stopped. This makes it possible to maintain the capacitor in an 85°C environment for more than 10 years.

[0197] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0198] (Embodiment 4) In this embodiment, a single memory cell can hold multiple bits of data (multi-value data). A configuration example and an operation example of the storage device 300A and the storage device 300B will be described. 00A is a variation of the storage device 300 described above. The differences between the storage device 300A and the storage device 300 will be described. For the missing parts, other embodiments and the common general technical knowledge of those skilled in the art should be taken into consideration. In this embodiment, the memory cell 411 is a DRAM type memory cell 411A.

[0199] <<Storage device 300A>> <Configuration example> FIG. 17 shows a block diagram for explaining a configuration example of the storage device 300A. The storage device 300A includes: A global logic circuit 350 is added to the memory device 300 shown in FIG. The memory device 300A also includes a bit line driver circuit 330A. The bit line driver circuit 330A has a different configuration from the bit line driver circuit 330 of the memory device 300. Yes.

[0200] The global logic circuit 350 holds the data signal WDATA input from the outside. The global logic circuit 350 also has a data signal WDATA. AL to the bit line driver circuit 330A.

[0201] The information stored in the memory cell 411A is read by the bit line driver circuit 330A. The global logic circuit 350 receives the signal and supplies it to the global logic circuit 350. The global logic circuit 350 has a function of storing information. The output circuit 340 outputs the information as a digital data signal R It has the function of outputting data externally.

[0202] The bit line driver circuit 330A of the memory device 300A includes a precharge circuit 332 and , an input / output circuit 334, and a signal conversion circuit 335. The signal conversion circuit 335 is C(Digital to Analog Converter)337 and ADC(A and a Analog to Digital Converter 338.

[0203] FIG. 18 shows the configuration of the cell array 401 and the bit line driver circuit 330A of the memory device 300A. The cell array 401 shown in FIG. 18 has m×n memory cells in a row and m cells in a column. The memory cells 411A are arranged in rows and columns.

[0204] The cell array 401 shown in FIG. 18 is electrically connected to the word line driver circuit 322. The wiring WL[1] is electrically connected to the memory cell 411A in the first row. Similarly, the wiring WL[i] is electrically connected to the memory cell 411A in the i-th row. .

[0205] Also, the cell array 401 shown in FIG. 18 is electrically connected to the bit line driver circuit 330A. The wiring BIL[1] is electrically connected to the memory cell 411A in the first column. Similarly, the wiring BIL[j] is electrically connected to the memory cell 411A in the jth column. To be continued.

[0206] The wiring BIL is connected to a precharge circuit 332 and a signal conversion circuit 335 (DA C337, ADC338, and the input / output circuit 334. Similarly, in FIG. 18, the precharge circuit 332 in the first column is the precharge circuit 332[1]. and the precharge circuit 332 in the jth column is represented as a precharge circuit 332[j]. The signal conversion circuit 335 and the input / output circuit 334 are also indicated in the same manner.

[0207] The input / output circuit 334 of the storage device 300A has a function of determining the operation of the signal conversion circuit 335. The input / output circuit 334 has a function of detecting the value stored in the memory cell 411A according to the operation mode. The read of the data stored in the memory cell 411A and the write of the data stored in the memory cell 411A are switched. The input / output circuit 334 is connected to the global logic circuit 350 via the wiring SAL. and electrically connected to the

[0208] The precharge circuit 332, the signal conversion circuit 335, the input / output circuit 334, etc. The operation can also be controlled by a control logic circuit 360 (see FIG. 17).

[0209] FIG. 19 shows a more detailed configuration example of the cell array 401 and the bit line driver circuit 330A. FIG. 19 shows nine memory cells 411A from row i, column j to row i+2, column j+2, and 13 shows a portion of the bit line driver circuit 330A corresponding to each of columns j+2 through j+2.

[0210] The precharge circuit 332[j] is electrically connected to the wiring BIL[j]. The circuit 332[j] has a function of precharging the wiring BIL[j]. 34[j] controls the operation of DAC337[j] and ADC338[j] depending on the operating mode. Specifically, when operating in write mode, DAC337 Run [j] and stop ADC338[j].

[0211] The input terminal of the DAC337[j] is electrically connected to the input / output circuit 334[j], and the output terminal is electrically connected to the wiring BIL[j]. The input terminal of ADC338[j] is The output terminal is electrically connected to input / output circuit 334[j], and the output terminal is electrically connected to input / output circuit 334[j].

[0212] An amplifier circuit may be provided between the wiring BIL[j] and the ADC338[j].

[0213] DAC337[j] is a k-bit (k is an integer of 2 or more) digital signal supplied from input / output circuit 334. It has the function of converting digital data into multi-value data (analog data). ADC338 [j] is multi-value data (analog data) stored in the memory cell 411A[i,j]. ) into k-bit digital data.

[0214] <Example of operation> Next, the operation mode of the storage device 300A will be described. Therefore, −3 V is supplied from the semiconductor device 100 to the wiring BGL. It is assumed that

[0215] [Read mode] Next, the bit line driver circuit 3 when reading data from the memory cell 411A[i,j] An example of the operation of 30A will be described with reference to the timing chart shown in FIG. The capacitance element Cs of the memory cell 411A[i,j] stores 4-bit (16-value) digital data. It is assumed that the amount of charge held corresponds to the data "1010".

[0216] [Period T51] In a period T51, the precharge circuit 332[j] is operated to charge the wiring BIL[j]. Specifically, a potential Vpre is supplied to the wiring BIL[j]. In the embodiment, the potential Vpre is the maximum potential (V The potential Vpre = (V H_DA+VL_DA) / 2.

[0217] In the period T51, the potential of the wiring WL[i] is at a low level (VL_WL). The register M11 is in the off state. Also, DAC337[j] and ADC338[j] , and input / output circuit 334[j] are in a stopped state. However, the potential of the wirings WL other than the wiring WL[i] is also VL_WL.

[0218] [Period T52] In a period T52, the precharge circuit 332[j] is stopped and the wiring WL[i] is selected. Specifically, the potential of the wiring WL[i] is set to a high level (VH_WL). This causes the transistor M11 in the memory cell 411A[i,j] to be turned on. Therefore, in the memory cell 411A[i,j], the wiring BIL[j] and the capacitance element Cs are The transistor M11 becomes conductive, and the capacitance element Cs is charged according to the amount of charge stored in the capacitor Cs. The potential of the wiring BIL[j] fluctuates.

[0219] In FIG. 20, the capacitance element Cs of the memory cell 411A[i,j] is charged with data “1010”. The charge amount is stored in the capacitance element Cs. The charge is discharged from the capacitance element Cs to the wiring BIL[j]. As a result, the potential of the wiring BIL[j] rises by ΔV1 from the potential Vpre. Depending on the amount of charge held in element Cs, the potential of wiring BIL[j] may drop. When the transistor M11 is turned on, the memory cell 411A[i,j] The potential of the capacitance element Cs and the potential of the wiring BIL[j] become equal. Start the operation of [j].

[0220] [Period T53] In the period T53, the operation of the ADC338[j] is started. Also, in the period T53, the wiring W The potential of L[i] may be set to VL_WL.

[0221] [Period T54] During period T54, ADC338[j] converts the potential of wiring BIL[j] into digital data. Convert the result and output it to wiring SAL[j].

[0222] [Period T55] In a period T55, the wiring WL[i] is set to a non-selected state. ] is set to low level (VL_WL). The operation of path 334[j] is stopped.

[0223] By the above operation, data can be read from memory cell 411A[i,j]. The read data is supplied to the global logic circuit 350 via the line SAL[j]. As described above, the global logic circuit 350 has the function of holding the data and The data is supplied to the output circuit 340. The data signal RDATA is output to the outside.

[0224] By operating in the read mode, the data stored in the memory cell 411A[i,j] is The amount of charge changes. That is, the information stored in the memory cell 411A[i,j] will be destroyed.

[0225] In order to restore the destroyed information, the storage device 300A is operated in the read mode and then Specifically, when operating in read mode, The data of the memory cell 411A[i,j] held in the global logic circuit 350 is Then, the data is written to memory cell 411A[i,j].

[0226] [Write mode] Next, the bit line driver circuit 33 when writing data to the memory cell 411A[i,j] An example of the operation of the 0A will be described with reference to the timing chart shown in FIG. In this embodiment, a 4-bit (16-value) digital value is stored in the capacitance element Cs of the memory cell 411A[i,j]. In this example, the charge amount corresponding to the data "1010" is written.

[0227] [Period T61] In a period T61, the precharge circuit 332[j] is operated to charge the wiring BIL[j]. Specifically, a potential Vpre is supplied to the wiring BIL[j]. By selecting line WL[i], transistor M11 is turned on. Then, memory cell 4 The potential of the capacitance element Cs of 11A[i,j] also becomes the potential Vpre.

[0228] In a period T61, the DAC 337[j], the ADC 338[j], and the input / output circuit 33 4[j] is in a stopped state.

[0229] [Period T62] In period T62, the input / output circuit 334[j] starts operating.

[0230] [Period T63] In period T63, the operation of DAC337[j] begins.

[0231] [Period T64] During the period T64, the data signal WDATA input from the outside is The data signal WDA Assume that data "1010" is supplied to the line SAL[j] as TA.

[0232] The data "1010" supplied to the wiring SAL[j] is converted to data by DAC337[j]. The potential is converted to a potential corresponding to "1010" and supplied to the wiring BIL[j]. Since the transistor M11 is in the ON state, the capacitance element Cs of the memory cell 411A[i,j] is An amount of charge is supplied that results in the same potential as the line BIL[j].

[0233] [Period T65] In a period T65, the wiring WL[i] is deselected, and the transistor M11 is turned off. By setting the memory cell 411A[i,j] to this state, the amount of charge corresponding to the data “1010” is Also, the operation of the ADC 338[j] and the input / output circuit 334[j] is stopped. .

[0234] By the above operation, data can be written to the memory cell 411A[i,j]. In this embodiment, the time required for the period T64 is the "write time".

[0235] [Refresh mode] In order to maintain the data written in the memory cell 411A[i,j], the memory cell 411A[i,j] is refreshed at regular intervals. Specifically, first, the memory device 300A is read and rewritten. The data held in the memory cell 411A[i,j] is globally read by operating the memory cell 411A[i,j] in the read mode. The global logic circuit 350 is then operated in the write mode to The data held in the logic circuit 350 is written again to the memory cell 411A[i,j]. Even in the refresh mode, the time required for the period T64 is the "write time". It is.

[0236] In the refresh mode, the data signal WDATA is input to the global logic circuit 350. There is no output from the global logic circuit 350 to the output circuit 340.

[0237] [NV mode] The NV mode is performed after the read mode is performed. The memory device 300A is operated in a read mode to read the memory cells 411A[i,j]. The data held in the NV mode is stored in the global logic circuit 350. In the read mode, which is performed as a process, the data signal is WDATA input to the global logic circuit 350, and 50 to the output circuit 340 may not be provided.

[0238] An example of the operation of the storage device 300A in the NV mode will be described with reference to the timing chart shown in FIG. The NV mode is an operation mode that is almost the same as the write mode. In FIG. 22, the NV mode is shown from period T71 to period T75. The period T74 corresponds to the periods T61 to T64 in the write mode. Explanation of periods T71 to T74 will be omitted.

[0239] In NV mode, the amount of charge corresponding to the data is reliably stored in the capacitance element Cs. The write time in the refresh mode is set to be longer than the write time in the refresh mode. is the "write time" in NV mode. The write time in NV mode is It is preferable that the write time is 1.5 times or more longer than the write time in the flash mode, and more preferable that the write time is 2 times or more longer. More than twice as long is even better. By extending the write time, you can prevent data from running out. It is possible.

[0240] [Period T75] In a period T75, the potential of the wiring WL[i] is set to a low level (VL_WL). The transistor in the cell 411A[i,j] is turned off. The transistor M11 is turned on. By turning it off, a voltage corresponding to the data “1010” is applied to the memory cell 411A[i,j]. The load is maintained.

[0241] In addition, when the threshold voltage of the transistor M11 is VthM (VthM>0V), the operating temperature Regardless of the degree, the wiring BGL should be -VthM or less, preferably -2×VthM or less, and more preferably For example, if VthM is 2V, the operation Regardless of temperature, the wiring BGL should be kept at -2V or less, preferably -4V or less, and more preferably -6V or less. In this embodiment, a potential of −7 V or less is supplied to the wiring BGL during the period T75. In addition, the operation of the ADC 338[j] and the input / output circuit 334[j] is stopped.

[0242] After the end of the period T75, the power supply to the peripheral circuit 311 or the entirety and the cell array 401 is stopped. Stop providing.

[0243] The write time in NV mode is made longer than the write time in refresh mode, and wiring BGL is -VthM or less, preferably -2×VthM or less, and more preferably -3×Vth By supplying a potential of M or less, even if the power supply to the cell array 401 is stopped, It is possible for the data written to be retained for more than 10 years in an environment of 85°C.

[0244] A precharge circuit 3 is provided for each column of the memory cells 411A included in the cell array 401. 32, a signal conversion circuit 335 (DAC 337, ADC 338), and an input / output circuit 334 By providing this, data can be read and written at high speed.

[0245] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0246] (Embodiment 5) When the number of bits of the data signal WDATA increases, the area occupied by the bit line driver circuit 330 In particular, the area occupied by the signal conversion circuit 335 increases. For each column of memory cells, a precharge circuit 332, a signal conversion circuit 335, and an input / output circuit Providing the path 334 increases the size of the storage device 300 itself.

[0247] In this embodiment, even if the number of bits of the data signal WDATA increases, the bit line driver circuit 3 The following describes a storage device 300B that is configured to reduce the area occupied by the storage device 30. The storage device 300B is a modified example of the storage device 300A. The example is particularly useful when the data signal WDATA is 3 or more bits of digital data. .

[0248] <<Storage device 300B>> <Configuration example> FIG. 23 is a block diagram illustrating a configuration example of the storage device 300B. The storage device 300B includes: The bit line driver circuit 330B is provided instead of the bit line driver circuit 330A. The line driver circuit 330B provides column switching between the cell array 401 and the precharge circuit 332. The input / output circuit 339 is provided.

[0249] FIG. 24 shows a configuration example of a part of the cell array 401 and the bit line driver circuit 330B. 24 shows three columns of memory cells 411A from row i, column j to row i+2, column j+2. In FIG. 24, the column switching circuit 339, the precharge circuit 332, and the signal A configuration including a conversion circuit 335 and an input / output circuit 334 is shown.

[0250] In addition, in FIG. 24, the gth column switching circuit 339 is indicated as column switching circuit 339[g]. (g is an integer equal to or greater than 1). A precharge circuit 332, a signal conversion circuit 335, and an input The output circuit 334 and the like are represented in the same manner. Column switching is performed every f columns (f is an integer of 2 or more). circuit 339, precharge circuit 332, signal conversion circuit 335, and input / output circuit 334. In this case, g can be expressed as n / f. Therefore, it is preferable that n is a multiple of f. It is.

[0251] The column switching circuit 339 has f switches SW. , f wirings SCL are electrically connected. In FIG. 24, f is 3. Therefore, The column switching circuit 339 shown in FIG. 24 includes switches SW[1] to SW[3]. and is electrically connected to the wirings SCL[1] to SCL[3].

[0252] The wire SCL[1] is electrically connected to the switch SW[1], and the switch SW[1] is turned on. The wire SCL[2] is electrically connected to the switch SW[2]. It has the function of controlling the on / off state of the switch SW[2]. SCL[3] is electrically connected to switch SW[3], and switch SW[3] is in the on state. The on / off state can be controlled by the on / off function.

[0253] An amplifier circuit may be provided between the circuit 339[g] and the ADC 338[g]. An amplifier circuit may be provided between the line BIL[j] and the switch SW[1]. An amplifier circuit may be provided between the wiring BIL[j An amplifier circuit may be provided between switch SW[+2] and switch SW[3].

[0254] <Example of operation> Next, the operation mode of the storage device 300B will be described. Therefore, −3 V is supplied from the semiconductor device 100 to the wiring BGL. It is assumed that

[0255] [Read mode] Read data from memory cells 411A[i,j] to 411A[i,j+2]. An example of the operation of the bit line driver circuit 330B when outputting the signal is shown in the timing chart of FIG. The following description will be given using a chart. Also, a 4-bit capacitance element Cs of the memory cell 411A[i,j] is The charge amount equivalent to the data "1010" out of the 16-value digital data is held. In addition, a 4-bit capacitance element Cs of the memory cell 411A[i+1,j] is Of the 16-value digital data, the charge equivalent to the data "0010" is held. In addition, the capacitance element Cs of the memory cell 411A[i+2,j] is set to 4 bits ( Of the 16-value digital data, the charge equivalent to the data "0111" is held. This shall be the case.

[0256] [Period T81] In the period T81, the precharge circuit 332[g] is operated. A high-level potential (VH_SCL) is supplied to the wirings SCL[1] to SCL[3], and the switches SW Switches SW[1] through SW[3] are turned on. Then, wiring BIL[j] through wiring BIL[j] are turned on. The potential of the wiring IL[j+2] (not shown in FIG. 25) is initialized. A potential Vpre is supplied to wirings BIL[j] to BIL[j+2].

[0257] In the period T81, the potential of the wiring WL[i] is at a low level (VL_WL). The resistor M11 is in the off state. Also, DAC337[g] and ADC338[g] , and input / output circuit 334[g] are in a stopped state.

[0258] [Period T82] In period T82, the precharge circuit 332[g] is stopped. ] to the wiring SCL[3], and a low-level (VL_SCL) potential is supplied to the switch SW[ Switches SW[1] through SW[3] are turned off. Also, wiring WL[i] is selected. In other words, the potential of the wiring WL[i] is set to a high level (VH_WL), The transistor M11 in the circuit 411A[i,j] is turned on.

[0259] As a result, in the memory cell 411A[i,j], the wiring BIL[j] and the capacitance element Cs becomes conductive through the transistor M11, and the amount of charge held in the capacitance element Cs The potential of the wiring BIL[j] varies depending on the memory cell 411A[i+1,j] and The memory cell 411A[i+2,j] operates in the same manner, and the wiring BIL[j+1] and the wiring B The potential of IL[j+2] fluctuates.

[0260] Also, the input / output circuit 334[g] starts operating.

[0261] [Period T83] In the period T83, the operation of the ADC 338[g] is started. Also, in the period T83, the wiring W The potential of L[i] may be set to VL_WL.

[0262] [Period T84] In a period T84, the potential of the line SCL[1] is set to a high level (VH_SCL[1]). Then, the wiring BIL[j] and ADC338[g] are electrically connected. ADC338[g] is The potential of the wiring BIL[j] is converted into digital data and output to the wiring SAL[g].

[0263] [Period T85] In a period T85, the potential of the line SCL[1] is set to a low level (VL_SCL[1]). In addition, the potential of the line SCL[2] is set to a high level (VH_SCL[2]), and the potential of the line B Electrically connect IL[j+1] and ADC338[g]. ADC338[g] is wire B The potential of IL[j+1] is converted into digital data and output to the wiring SAL[g].

[0264] [Period T86] In a period T86, the potential of the line SCL[2] is set to a low level (VL_SCL[2]). In addition, the potential of the line SCL[3] is set to a high level (VH_SCL[3]), and the potential of the line B Electrically connect IL[j+2] and ADC338[g]. ADC338[g] is wire B The potential of IL[j+2] is converted into digital data and output to the wiring SAL[g].

[0265] [Period T87] In a period T87, the wiring WL[i] is set to a non-selected state. The potential of the line SCL[3] is set to low level (VL_WL). Also, the ADC 338[g] and the input / output circuit 334[ g] will stop working.

[0266] By the above operation, the memory cells 411A[i,j] to 411A[i+2,j The data stored in the ] can be read out in sequence. The read data is The data is supplied to the global logic circuit 350 via SAL[g]. The signal is outputted to the outside via a line 340 as a data signal RDATA.

[0267] The switch SW of the column switching circuit 339 is a switching element such as a transistor. In the memory device 300B, the memory cells 411A[i,j] to The data stored in the resiliency cell 411A[i+2,j] is read out in sequence. The switching circuit 339 includes switches SW (switches SW[1] to SW[3] In the above-mentioned embodiment, a transistor with extremely low off-state current, such as an OS transistor, is preferably used. It is.

[0268] By operating in the read mode, memory cells 411A[i,j] to 411A[i,j] are The charge stored in 11A[i+2,j] changes. The information stored in memory cells 411A[i,j] to 411A[i+2,j] is destroyed. It will be lost.

[0269] In order to restore the destroyed information, the storage device 300B is later operated in the read mode. Specifically, when operating in read mode, The memory cells 411B[i,j] to 411B[i,j] held in the global logic circuit 350 The data of memory cell 411A[i+2,j] is again stored in memory cells 411A[i,j] to Write to 411A[i+2,j].

[0270] [Write mode] Next, the bit line driver circuit 33 when writing data to the memory cell 411A[i,j] An example of the operation of the 0B will be described with reference to the timing chart shown in FIG. In this embodiment, a 4-bit (16-value) digital value is stored in the capacitance element Cs of the memory cell 411A[i,j]. The charge amount corresponding to the data "1010" is written. 4-bit (16-value) digital data is input to the capacitance element Cs of memory cell 411A[i,j+1]. The charge amount corresponding to the data "0010" is written. Of the 4-bit (16-value) digital data, It is assumed that the amount of charge corresponding to the data "0111" is to be written.

[0271] [Period T91] In a period T91, the precharge circuit 332[g] is operated. A high-level potential (VH_SCL) is supplied to the wirings SCL[1] to SCL[3], and the switches SW Switches SW[1] through SW[3] are turned on. Then, wiring BIL[j] through wiring BIL[j] are turned on. The potential of IL[j+2] (not shown in FIG. 26) is initialized. Then, the memory cell 411A[i,j The potentials of the capacitor elements Cs of the memory cells 411A[i,j+2] to 411A[i,j+2] are also initialized.

[0272] In a period T91, the DAC 337[g], the ADC 338[g], and the input / output circuit 33 4[g] is in a stopped state.

[0273] [Period T92] In period T92, the input / output circuit 334[g] starts operating.

[0274] [Period T93] In period T93, the operation of the DAC337[g] starts.

[0275] [Period T94] In a period T94, the potential of the line SCL[1] is set to a high level (VH_SCL[1]). The wiring BIL[j] and DAC337[g] are electrically connected. The received data signal WDATA is transmitted to the wiring SAL[g] via the global logic circuit 350. In this case, the data "1010" is supplied to the wiring SAL as the data signal WDATA. [j] shall be supplied.

[0276] The data "1010" supplied to the wiring SAL[j] is converted to data by DAC337[g]. The potential is converted to a potential corresponding to "1010" and supplied to the wiring BIL[j]. Since the transistor M11 is in the ON state, the capacitance element Cs of the memory cell 411A[i,j] is An amount of charge is supplied that results in the same potential as the line BIL[j].

[0277] [Period T95] In a period T95, the potential of the line SCL[1] is set to a low level (VL_SCL[1]). In addition, the potential of the line SCL[2] is set to a high level (VH_SCL[2]), and the potential of the line B IL[j+1] and DAC337[g] are electrically connected. The data signal WDATA is supplied to the wiring SAL[g] via the global logic circuit 350. Here, the data signal WDATA, data “0010”, is transmitted to the wiring SAL[g]. shall be supplied to

[0278] The data "0010" supplied to the wiring SAL[g] is converted to data by DAC337[g]. The potential is converted to a potential corresponding to "0010" and supplied to the wiring BIL[j+1]. Since the transistor M11 is in the on state, the capacitance element of the memory cell 411A[i,j+1] An amount of charge that makes Cs have the same potential as the wiring BIL[j+1] is supplied.

[0279] [Period T96] In a period T96, the potential of the line SCL[2] is set to a low level (VL_SCL[2]). In addition, the potential of the line SCL[3] is set to a high level (VH_SCL[3]), and the potential of the line B IL[j+2] and DAC337[g] are electrically connected. The data signal WDATA is supplied to the wiring SAL[g] via the global logic circuit 350. Here, the data signal WDATA, data “0010”, is transmitted to the wiring SAL[g]. shall be supplied to

[0280] The data "0010" supplied to the wiring SAL[g] is converted to data by DAC337[g]. The potential is converted to a potential corresponding to "0010" and supplied to the wiring BIL[j+2]. Since the transistor M11 is in the on state, the capacitance element of the memory cell 411A[i,j+2] An amount of charge that makes Cs have the same potential as the wiring BIL[j+2] is supplied.

[0281] [Period T97] In a period T97, the wiring WL[i] is deselected, and the transistor M11 is turned off. By setting the memory cells 411A[i,j] to 411A[i,j+2] The amount of charge corresponding to each data is held in the SCL[3] line. The level (VL_SCL[3]) is also set as the ADC 338[g] and the input / output circuit 33 4[g] will stop working.

[0282] By the above operation, data can be written to the memory cell 411A[i,j]. In this embodiment, the time required for the periods T94 to T96 is the "write time".

[0283] [Refresh mode] The refresh mode of the storage device 300B may operate in the same manner as the storage device 300A. Therefore, a detailed description will be omitted here.

[0284] [NV mode] The NV mode of the storage device 300B is also the same as the storage device 300A, after the read mode is executed. FIG. 27 is a timing chart showing an example of the operation of the storage device 300B in the NV mode. The NV mode is an operation mode that is almost the same as the write mode. In FIG. The NV mode is shown by the period T101 to the period T107. T106 corresponds to the period T91 to T96 in the write mode. Explanation of period T101 to T106 will be omitted.

[0285] In NV mode, the amount of charge corresponding to the data is reliably stored in the capacitance element Cs. The write time in the refresh mode is set to be longer than the write time in the refresh mode. The time required for 106 is the “write time” in NV mode. The write time should be at least 1.5 times the write time in refresh mode, and preferably at least 2 times More preferably, 5 times or more is more preferable. This can prevent insufficient writing.

[0286] [Period T107] In a period T107, the potential of the wiring WL[i] is set to a low level (VL_WL). The transistors included in the memory cell 411A[i,j] to the memory cell 411A[i,j+2] By turning off the transistor M11, the memory cell 411A[ The amount of charge corresponding to each data is stored in memory cells 411A[i,j] to 411A[i,j+2]. It will be held.

[0287] In addition, when the threshold voltage of the transistor M11 is VthM (VthM>0V), the operating temperature Regardless of the degree, the wiring BGL should be -VthM or less, preferably -2×VthM or less, and more preferably For example, if VthM is 2V, the operation Regardless of temperature, the wiring BGL should be kept at -2V or less, preferably -4V or less, and more preferably -6V or less. In this embodiment, a potential of −7 V or less is supplied to the wiring BGL during the period T75. In addition, the operation of the ADC 338[g] and the input / output circuit 334[g] is stopped.

[0288] After the end of the period T75, the power supply to the peripheral circuit 311 or the entirety and the cell array 401 is stopped. Stop providing.

[0289] The write time in NV mode is made longer than the write time in refresh mode, and wiring BGL is -VthM or less, preferably -2×VthM or less, and more preferably -3×Vth By supplying a potential of M or less, even if the power supply to the cell array 401 is stopped, It is possible for the data written to be retained for more than 10 years in an environment of 85°C.

[0290] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0291] (Embodiment 6) In this embodiment, an example of a cross-sectional configuration of a storage device 300 will be described with reference to the drawings.

[0292] <Example of memory device structure> FIG. 28 shows a cross section of a portion of a memory device 300. The memory device 300 shown in FIG. 28, a single crystal substrate 231 is used as the substrate 231. 1 shows a case where a crystalline semiconductor substrate (for example, a single crystal silicon substrate) is used.

[0293] [Layer 310] In FIG. 28, layer 310 includes transistors 233a, 233b, and 233c on substrate 231. 28, the transistor 233a, the transistor 3b, and the transistor 233c. 1 shows cross sections of a transistor 233b and a transistor 233c in the channel length direction.

[0294] The channels of the transistors 233a, 233b, and 233c is formed on a part of the substrate 231. When high speed operation is required for the integrated circuit, It is preferable to use a single crystal semiconductor substrate as the substrate 1.

[0295] The transistor 233a, the transistor 233b, and the transistor 233c are element components. The element isolation layer is formed by LOCOS (L local oxidation of silicon method and STI (Shallow The Trench Isolation method and the like can be used.

[0296] An insulating layer 234 is provided on the substrate 231, and a transistor 233a and a transistor 2 An insulating layer 235 and an insulating layer 237 are provided on the transistor 33b and the transistor 233c. An electrode 238 is buried in the layer 237. The electrode 238 is connected to the layer 237 through a contact plug 236. The transistor 233a is electrically connected to one of the source and the drain of the transistor 233a.

[0297] In addition, on the electrode 238 and the insulating layer 237, an insulating layer 239, an insulating layer 240, and an insulating A layer 241 is provided, and an electrode 24 is disposed in the insulating layer 239, the insulating layer 240, and the insulating layer 241. 2 is embedded in the electrode 242. The electrode 242 is electrically connected to the electrode 238.

[0298] Moreover, an insulating layer 243 and an insulating layer 244 are provided on the electrode 242 and the insulating layer 241. An electrode 245 is embedded in the insulating layer 243 and the insulating layer 244. 5 is electrically connected to the electrode 242.

[0299] Moreover, an insulating layer 246 and an insulating layer 247 are provided on the electrode 245 and the insulating layer 244. An electrode 249 is embedded in the insulating layer 246 and the insulating layer 247. , and is electrically connected to electrode 245.

[0300] Moreover, an insulating layer 248 and an insulating layer 250 are provided on the electrode 249 and the insulating layer 247. An electrode 251 is embedded in the insulating layer 248 and the insulating layer 250. , and is electrically connected to electrode 249.

[0301] [Layer 320] Layer 320 is disposed on layer 310. Layer 320 includes transistor 368a, transistor In FIG. 28, the transistor 368b has a capacitance element 369a, and the capacitance element 369b has a capacitance element 369b. 13 shows a cross section of the transistor 368a and the transistor 368b in the channel length direction. , transistor 368a, and transistor 368b are transistors having a back gate. It's Jista.

[0302] The transistor 368a and the transistor 368b are the same as those in the above embodiment. Therefore, the transistor 368a and the transistor 368b correspond to the transistor M11. It is preferable to use an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer. , the transistor 368a, and the transistor 368b are OS transistors. is preferred.

[0303] The transistor 368a and the transistor 368b are formed by insulating layers 361 and 36 2. In addition, insulating layer 363 and insulating layer 364 are provided on insulating layer 362. The back gates of the transistors 368a and 368b are insulated. The insulating layer 364 is embedded in the edge layer 363 and the insulating layer 364. An electrode 367 is provided between the insulating layers 361 to 366. Electrode 367 is electrically connected to electrode 251.

[0304] In addition, the transistor 368a, the transistor 368b, the capacitor 369a, and the capacitor An insulating layer 371, an insulating layer 372, and an insulating layer 373 are formed on the electrode 369b. An electrode 375 is formed on the semiconductor substrate 373. The electrode 375 is connected to the semiconductor substrate 373 via a contact plug 374. It is electrically connected to the electrode 367 .

[0305] Also, on the electrode 375, an insulating layer 376, an insulating layer 377, an insulating layer 378, and an insulating layer 379 are formed. 9 is provided. An electrode 380 is embedded in the insulating layers 376 to 379. The electrode 380 is electrically connected to the electrode 375.

[0306] Moreover, an insulating layer 381 and an insulating layer 382 are provided on the electrode 380 and the insulating layer 379. It is being done.

[0307] <Modification> FIG. 29 shows a cross section of a portion of the memory device 300A. In the example shown, the storage device 300A has a layer 310A and a layer 320. In A, an insulating substrate (for example, a glass substrate) is used as the substrate 231.

[0308] Layer 310A includes transistor 268a, transistor 268b, and capacitive element 269a. The transistors included in layer 310A include thin film transistors (e.g., OS transistors). All the transistors included in layer 310A are OS transistors. This allows layer 310A to be a unipolar integrated circuit. By using OS transistors for all the transistors, the memory device 300A is a unipolar memory device. It can be placed in a position.

[0309] <About the constituent materials> 〔substrate〕 There is no particular restriction on the material used for the substrate, but it should be strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, silicon or silicon carbide is used as the substrate. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, and silicon germanium substrates In addition, a compound semiconductor substrate with a strained surface on an SOI substrate or a semiconductor substrate can be used. Use of transistors, FIN type transistors, and other semiconductor elements. Alternatively, a high electron mobility transistor (HEMT) can be used. Gallium arsenide and aluminum arsenide applicable to the 1000 n Mobility Transistor Nitride, Indium Gallium Arsenide, Gallium Nitride, Indium Phosphide, Silicon In other words, the substrate is not limited to a simple support substrate, but may be any other type of substrate. It may also be a substrate on which devices such as transistors are formed.

[0310] In addition, glass such as barium borosilicate glass and aluminoborosilicate glass can be used as a substrate. A substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may also be used. A flexible substrate may be used as the plate. When a flexible substrate is used, A transistor, a capacitor, or the like may be directly manufactured on a flexible substrate, or may be manufactured on another substrate. A transistor, a capacitor, or the like may be fabricated on the substrate, and then the transistor, the capacitor, or the like may be peeled off and transferred to the flexible substrate. In order to peel and transfer the transistors and capacitors from the manufacturing substrate to the flexible substrate, It is advisable to provide a release layer between the substrate and the resin.

[0311] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used, the less the deformation caused by the environment. The flexible substrate used for the substrate has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 If a material with a temperature of 0.1 to 1.5 K or less is used, Examples of resins include polyester, polyolefin, polyamide (nylon, a Aramid, polyimide, polycarbonate, acrylic, etc. In particular, aramid Since the linear expansion coefficient is low, it is suitable as a flexible substrate.

[0312] [Insulating layer] The insulating layer is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride. Minium, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, oxynitride silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate Materials selected from the above are used in a single layer or in a laminated form. In addition, oxide materials, nitride materials, etc. A mixture of a plurality of materials selected from the group consisting of oxynitride materials and nitride oxide materials may also be used.

[0313] In this specification and the like, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of is, for example, measured by Rutherford Backscattering (RBS) spectroscopy. Measurements can be made using techniques such as kScattering Spectrometry. .

[0314] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, In order to prevent an increase in the hydrogen concentration in the insulating layer, it is preferable to reduce the hydrogen concentration in the insulating layer. The hydrogen concentration in the insulating layer was measured using secondary ion mass spectrometry (SIMS). Ion Mass Spectrometry) is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The following In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0315] In order to prevent an increase in the nitrogen concentration in the semiconductor layer, the nitrogen concentration in the insulating layer can be reduced. Specifically, the nitrogen concentration in the insulating layer is preferably 5×10 19 atom s / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1× 10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 Below Below.

[0316] In addition, at least a region of the insulating layer that contacts the semiconductor layer and at least a region of the insulating layer that contacts the semiconductor layer The region to be formed preferably has few defects. Typically, the region is determined by electron spin resonance (ESR) spectroscopy. It is preferable to have less signal observed by electron spin resonance. For example, the signal mentioned above is the E' center observed at a g value of 2.001. The E' center is caused by a dangling bond of silicon. For example, When a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, the E' center The resulting spin density is 3×10 17 spins / cm 3 Less than or equal to 5×10 16 s pins / cm 3A silicon oxide layer or a silicon oxynitride layer as described below may be used.

[0317] In addition, if signals due to nitrogen dioxide (NO2) are observed in addition to the above signals, The signal is split into three signals due to the nuclear spin of N, g value is 2.037 or more and 2.039 or less (first signal), g value is 2.001 or less 2.003 or less (second signal), and g value is 1.964 or more and 1.966 or less. It is observed below (referred to as the third signal).

[0318] For example, the spin density of the signal caused by nitrogen dioxide (NO2) as an insulating layer is 1× 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Using an insulating layer that is less than It is preferable to have

[0319] In addition, nitrogen oxides (NO x ) forms a level in the insulating layer The level is located within the energy gap of the oxide semiconductor layer. Things (NO x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, the level is As a result, the trapped electrons are transported between the insulating layer and the oxide. Since it remains near the interface of the semiconductor layer, it shifts the threshold voltage of the transistor in the positive direction. Therefore, it is recommended to use a film with a low content of nitrogen oxide as the insulating layer. By using the above-mentioned second insulating layer, the shift in the threshold voltage of the transistor can be reduced.

[0320] Nitrogen oxides (NO xAs an insulating layer with a low emission of ., for example, a silicon oxynitride layer is used. The silicon oxynitride layer can be analyzed by thermal desorption spectroscopy (TDS). In real time desorption spectroscopy, nitrogen oxides ( NO x ) is a membrane that releases more ammonia than water. The amount is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is greater when the heat treatment temperature in TDS is between 50°C and 650°C, or between 5 This is the total amount in the range of 0°C to 550°C.

[0321] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating layer with a high monia emission rate, nitrogen oxides (NO x ) is reduced.

[0322] At least one of the insulating layers in contact with the oxide semiconductor layer is a layer that releases oxygen by heating. Specifically, the insulating layer is preferably formed so that the surface temperature of the insulating layer is 100° C. The TDS is performed at a temperature of 100°C to 500°C or lower. The amount of oxygen released, calculated as oxygen atoms, is 1.0 × 10 18 atoms / cm 3 That's it, part 1. 0×10 19 atoms / cm 3 or more, or 1.0×10 20 atoms / cm 3 End It is preferable to use an insulating layer in which the The oxygen that is released is called "excess oxygen."

[0323] The insulating layer containing excess oxygen can also be formed by performing a process of adding oxygen to the insulating layer. The treatment to add oxygen is carried out by heat treatment in an oxidizing atmosphere or plasma treatment. Alternatively, ion implantation, ion doping, plasma immersion Oxygen may be added by using an on-implantation method or the like. teeth, 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas, or ozone gas In this specification, the process of adding oxygen is referred to as "oxygen doping." The oxygen doping process may be performed by heating the substrate.

[0324] The insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, polyamide resin, or the like. Organic materials having heat resistance, such as amides and epoxy resins, can be used. In addition to the above materials, low-k materials, siloxane resins, and PSG (lingala The material can be shaped by using these materials. The insulating layer may be formed by stacking a plurality of insulating layers formed of the insulating material.

[0325] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0326] The method for forming the insulating layer is not particularly limited. Depending on the material used for the insulating layer, a firing process may be used. In this case, the insulating layer firing process can be combined with other heat treatment processes to efficiently This makes it possible to fabricate transistors efficiently.

[0327] 〔electrode〕 Conductive materials for forming electrodes include aluminum, chromium, copper, silver, gold, platinum, Tantalum, Nickel, Titanium, Molybdenum, Tungsten, Hafnium, Vanadium, Ni Selected from obium, manganese, magnesium, zirconium, beryllium, indium, etc. Materials containing one or more metal elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon, nickel silicide, etc. Alternatively, a silicide such as the above may be used.

[0328] In addition, a conductive material containing the above metal element and oxygen may be used. Conductive materials containing silicon and nitrogen may also be used, such as titanium nitride and tantalum nitride. A conductive material containing nitrogen may be used. um Tin Oxide), Indium Oxide with Tungsten Oxide, Tungsten Oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium gallium zinc oxide, silicon Indium tin oxide doped with nitrogen may also be used. Zinc oxide may also be used.

[0329] In addition, a plurality of conductive layers made of the above materials may be laminated. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining the above-mentioned material containing a metal element and a conductive material containing nitrogen is also available. The above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure may be formed by combining the conductive material containing nitrogen. Alternatively, the conductive material may have a laminated structure in which a conductive material containing oxygen is combined with the conductive material containing oxygen.

[0330] In addition, an oxide semiconductor is used for the semiconductor layer, and the above-mentioned material containing a metal element is used for the gate electrode. When a laminated structure combining a conductive material containing oxygen is used, By providing a conductive material containing oxygen on the semiconductor layer side, Therefore, oxygen released from the conductive material is easily supplied to the semiconductor layer.

[0331] The electrodes are made of highly conductive materials with high embedding properties, such as tungsten and polysilicon. In addition, a highly conductive material with high embedding properties and a titanium layer, a titanium nitride layer, A barrier layer (diffusion prevention layer) such as a tantalum nitride layer may be used in combination. is sometimes called a "contact plug."

[0332] In particular, it is preferable to use a conductive material that is difficult for impurities to permeate for the electrode in contact with the gate insulator. An example of a conductive material that is difficult for impurities to permeate is tantalum nitride.

[0333] The insulating layer is made of insulating material that is difficult for impurities to penetrate, and the electrodes are made of conductive material that is difficult for impurities to penetrate. By using such a material, the diffusion of impurities into the transistor can be further suppressed. This can further increase the reliability of the transistor. It can be further increased.

[0334] [Semiconductor Layer] The semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like. The semiconductor materials may be, for example, silicon. Silicon, germanium, etc. can be used. Silicon germanium, silicon carbide, etc. Compound semiconductors such as silicon, gallium arsenide, oxide semiconductors, and nitride semiconductors, as well as organic semiconductors etc. can be used.

[0335] In addition, when using an organic semiconductor as the semiconductor layer, low molecular weight organic materials with aromatic rings or π-electron Conjugated conductive polymers such as rubrene, tetracene, pentaerythritol, etc. can be used. Tetrathane, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene Polyparaphenylenevinylene, polyparaphenylenevinylene, etc. can be used.

[0336] In addition, the semiconductor layers may be stacked. When stacking the semiconductor layers, the layers may have different crystal states. Alternatively, different semiconductor materials may be used.

[0337] In addition, the band gap of oxide semiconductors, a type of metal oxide, is 2 eV or more. By using an oxide semiconductor for the conductor layer, it is possible to realize a transistor with extremely low off-state current. Specifically, the voltage between the source and drain is 3.5 V and the device is at room temperature (typically 25°C). ) and the off-current per 1 μm of channel width is 1×10 -20 Less than A, 1×10 - 22 Less than A or 1×10 -24 A. That is, the on-off ratio In addition, a transistor using an oxide semiconductor for a semiconductor layer can be used. (OS transistor) has high dielectric strength between source and drain. Therefore, it has good reliability. In addition, a transistor having a large output voltage and a high withstand voltage can be provided. In addition, a highly reliable memory device can be provided. It is possible to provide a storage device, etc.

[0338] In the present specification and the like, the semiconductor layer in which the channel is formed is made of crystalline silicon. The transistor used is also called a "crystalline silicon transistor."

[0339] Crystalline silicon transistors tend to have higher mobility than OS transistors. Crystalline silicon transistors have an extremely low off-state current like OS transistors. Therefore, the semiconductor material used in the semiconductor layer should be appropriately selected according to the purpose and application. For example, depending on the purpose and application, it is necessary to select OS transistors and crystalline Si transistors. A transistor or the like may also be used in combination.

[0340] When an oxide semiconductor layer is used as the semiconductor layer, the oxide semiconductor layer is formed by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, This is preferable because the density of the oxide semiconductor layer can be increased. In this case, the sputtering gas is a rare gas (typically argon), oxygen, or a rare gas. A mixed gas of niobium and oxygen can be used. In addition, the sputtering gas must be highly purified. For example, oxygen gas and rare gases used as sputtering gases have a dew point of -60°C or lower. The gas used is preferably purified to a temperature of -100°C or lower. By forming the oxide semiconductor layer using ring gas, moisture and other substances can be taken into the oxide semiconductor layer. It can be prevented as much as possible.

[0341] In addition, in the case where the oxide semiconductor layer is formed by a sputtering method, It is preferable to remove as much moisture as possible from the deposition chamber. For example, using a cryopump or similar device. A suction-type vacuum pump was used to create a high vacuum (5×10 -7 Pa to 1×10 - 4 It is preferable to evacuate the gas to a pressure of about 10 Pa, especially when the sputtering device is in standby mode. The partial pressure of gas molecules equivalent to HO (gas molecules equivalent to m / z = 18) in the deposition chamber is 1×10 -4 Pa or less, preferably 5×10 -5 It is preferable to set the pressure to 0.1 Pa or less.

[0342] [Metal oxides] Oxide semiconductors, which are a type of metal oxide, often contain at least indium or zinc. It is preferable that the alloy contains indium and zinc. It is preferable that the material contains aluminum, gallium, yttrium, or tin. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium The metal may contain one or more elements selected from the group consisting of ruthenium, cadmium, and the like.

[0343] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M are boron, silicon, titanium, iron, nickel, and germanium. , Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum, Tungsten, magnesium, etc. However, the element M can be a combination of multiple of the above elements. There are cases where it is okay to match them.

[0344] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met de). It may also be called tetrahydrofuran (tetrahydrofuran) oxynitride.

[0345] [Metal oxide composition] The following describes a CAC (Cl This paper explains the configuration of the OUd-Aligned Composite (OUD-Aligned Composite)-OS.

[0346] In this specification, CAAC (c-axis aligned crystal ), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Shows an example.

[0347] CAC-OS or CAC-metal oxide is a material that has the function of electrical conductivity. A part of the material has an insulating function, and the whole material has a semiconductor function. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a material, the function of conductivity is to allow electrons (or holes) to flow as carriers, The insulating function is the function of not allowing the electrons that act as carriers to flow. The function and the function work complementary to each other to provide a switching function (On / Off The function of providing a CAC-OS or CAC-metal oxide with a In CAC-OS or CAC-metal oxide, each function can be By separating them, the functions of both can be maximized.

[0348] In addition, CAC-OS or CAC-metal oxide is used in conductive areas and insulating areas. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0349] In addition, in the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be present in the material:

[0350] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxi de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In the case of this configuration, when a carrier flows, In the narrow gap component, carriers mainly flow. The component having a narrow gap acts complementary to the component having a wide gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on-state, i.e., a large on-current. And high field effect mobility can be obtained.

[0351] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a composite matrix.

[0352] [Metal oxide structures] Oxide semiconductors, a type of metal oxide, are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c-axis aligned crystalline oxide semico inductor, polycrystalline oxide semiconductor, nc-OS (nanocrystalline A-like amorphous oxide semiconductor OS:amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0353] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is caused by the area where multiple nanocrystals are connected. In the region, between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement, Indicates the point where the direction is changing.

[0354] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may be non-regular hexagons. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, in the CAAC-OS, clear grain boundaries (grain boundaries) are not observed even in the vicinity of the strain. It is difficult to confirm the presence of the lattice distortion. This is because the CAAC-OS is aligned in the ab-plane direction. In the case of the ferroelectric material, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0355] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as the (M, Zn) layer) are stacked. Indium and element M tend to have a layered structure. If the element M in the (M, Zn) layer is replaced with indium, then (In, M, Zn) Also, when the indium in the In layer is replaced with element M, (In,M ) layer.

[0356] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has no clear crystalline structure. Since it is difficult to confirm grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides decreases due to the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat resistant and highly reliable.

[0357] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the above.

[0358] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density areas. e-OS has a lower crystallinity than nc-OS and CAAC-OS.

[0359] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductors are amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc- The compound may have two or more of the above-mentioned OS and CAAC-OS.

[0360] [Transistors with metal oxide] Next, a case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0361] By using the above metal oxide for the channel formation region of a transistor, a high field effect It is possible to realize a highly reliable transistor. It is possible.

[0362] In addition, it is preferable to use a metal oxide having a low carrier density for the transistor. In order to reduce the carrier density of the oxide film, the impurity concentration in the metal oxide film is reduced. In the present specification and the like, the impurity concentration is low and the defect level density is low. A low density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides are Carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, more Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than that is fine. .

[0363] In addition, high-purity intrinsic or substantially high-purity intrinsic metal oxide films have a low density of defect states. Therefore, the trap level density may also be low.

[0364] In addition, the charges trapped in the trap levels of the metal oxide take a long time to disappear. Therefore, gold, which has a high density of trap states, A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. do.

[0365] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide In order to reduce the impurity concentration in the metal oxide, it is effective to reduce the It is also preferable to reduce the impurity concentration in the adjacent film. These include potassium metal, alkaline earth metals, iron, nickel, silicon, etc.

[0366] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0367] When metal oxides contain silicon or carbon, which are group 14 elements, the metal oxide This leads to the formation of defect levels in the metal oxide. The concentration of silicon and carbon near the interface with the metal oxide was measured using secondary ion mass spectrometry (SIMS) ) is calculated by dividing the concentration by 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0368] In addition, when alkali metals or alkaline earth metals are included in the metal oxide, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using a metal oxide containing fluorine in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide is Specifically, it is preferable to reduce the amount of alkali metal in the metal oxide obtained by SIMS. The concentration of alkali metals or alkaline earth metals is 1×10 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 To the following:

[0369] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carrier density increases. As a result, the metal oxide containing nitrogen is used to form a channel. The transistor used in the region tends to be normally on. In the case of the nitride, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxide is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 a toms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0370] In addition, the hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, hydrogen-containing metal oxides can generate electrons that are The transistors used in the channel forming region tend to be normally-on. It is preferable that the hydrogen content in the metal oxide is reduced as much as possible. The hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, Preferably 1 x 10 19 atoms / cm 3 less than 5×10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0371] By using metal oxide with sufficiently reduced impurities in the channel formation region of a transistor, , and stable electrical characteristics can be imparted.

[0372] <Film formation method> Insulating materials for forming insulating layers, conductive materials for forming electrodes, or semiconducting layers The semiconductor material for forming the semiconductor layer is prepared by sputtering, spin coating, or CVD (Chemical Vapor Deposition). ical vapor deposition) method (thermal CVD method, MOCVD (Meta l Organic Chemical Vapor Deposition) method, PE CVD (Plasma Enhanced CVD) method, High density plasma CVD (Hig h density plasma CVD) method, LPCVD (low pressur e CVD) method, APCVD (atmospheric pressure CVD) method etc.), ALD (Atomic Layer Deposition) method, or MBE (Molecular Beam Epitaxy) method or PLD (Pul sed Laser Deposition method, dip method, spray coating method, droplet ejection Printing methods (such as inkjet printing) and printing methods (such as screen printing and offset printing) are used. It can be formed by:

[0373] The plasma CVD method can produce high-quality films at relatively low temperatures. When a deposition method that does not use plasma, such as a thermal CVD method, is used, the deposition surface is damaged. For example, the wiring, electrodes, and elements (transistors, capacitors, etc.) contained in memory devices Some elements (such as quantum elements) may become charged up by receiving electric charge from the plasma. At this time, the accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the memory device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage may occur. Since no defects occur, the yield of the memory device can be increased. Since no damage occurs, a film with few defects can be obtained.

[0374] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0375] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the storage device may be improved.

[0376] When forming a film by the ALD method, gases that do not contain chlorine should be used as the material gas. is preferred.

[0377] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0378] (Embodiment 7) In this embodiment mode, a transistor that can be used for the semiconductor device shown in the above embodiment mode and the like is An example of the structure of the resistor will now be described.

[0379] <Transistor structure example 1> An example of the structure of the transistor 510A will be described with reference to FIGS. FIG. 30A is a top view of a transistor 510A. FIG. 30B is a top view of the transistor 510A shown in FIG. FIG 30(C) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG 30(A). 30(A) is a cross-sectional view of a portion indicated by line W1-W2. For convenience, some elements are omitted in the figure.

[0380] In FIGS. 30A, 30B, and 30C, a transistor 510A and a semiconductor device that functions as an interlayer film are shown. Insulating layer 511, insulating layer 512, insulating layer 514, insulating layer 516, insulating layer 580, insulating layer 5 82, and insulating layer 584. Also shown are the transistors 510A and 510B electrically connected to the , the conductive layer 546 (conductive layer 546a and conductive layer 546 5B) and a conductive layer 503 functioning as wiring.

[0381] The transistor 510A includes a conductive layer 560 (conductive layer 560) serving as a first gate electrode. a, and conductive layer 560b), and conductive layer 505 (conductive layer 505a, and conductive layer 505b) and an insulating layer 550 which serves as a first gate insulator. and an insulating layer 521, an insulating layer 522, and an insulating layer 523 functioning as a second gate insulator. 4, and an oxide 530 having a region in which a channel is to be formed (oxide 530a, oxide 530 b, and oxide 530c), and a conductive layer 54 acting as either a source or a drain. 2a, a conductive layer 542b serving as the other of the source and drain, and an insulating layer 574. has.

[0382] In addition, in the transistor 510A shown in FIG. The conductive layer 560 is disposed in an opening provided in the insulating layer 580 via the insulating layer 574. In addition, the oxide 530c, the insulating layer 550, and the conductive layer 560 are formed on the conductive layer 542a and the and conductive layer 542b.

[0383] The insulating layers 511 and 512 function as interlayer films.

[0384] The interlayer film may be silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. , hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT ), strontium titanate (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulators such as the following can be used in a single layer or a laminated layer. , aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, acid Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may also be added. Alternatively, these insulators may be nitrided. A laminate of silicon or silicon nitride may also be used.

[0385] For example, the insulating layer 511 prevents impurities such as water or hydrogen from entering the transistor 510 from the substrate side. It is preferable that the insulating layer functions as a barrier layer to prevent the inclusion of the metal oxide in A. 511 has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use an insulating material that is impermeable to the above-mentioned impurities. (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material that is difficult for oxygen to permeate. Aluminum oxide, silicon nitride, or the like may be used as the material 11. Impurities such as water diffuse from the substrate side to the transistor 510A side through the insulating layer 511. can be suppressed.

[0386] For example, it is preferable that the insulating layer 512 has a lower dielectric constant than the insulating layer 511. By using a thin material for the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0387] The conductive layer 503 is formed so as to be embedded in the insulating layer 512. The height of the upper surface of the conductive layer 503 can be made to be approximately the same as the height of the upper surface of the insulating layer 512. However, the present invention is not limited to this. The conductive layer 503 may have a stacked structure of two or more layers. It is preferable to use a highly conductive material containing copper or aluminum as a main component. .

[0388] In the transistor 510A, the conductive layer 560 is a first gate (also called a top gate). The conductive layer 505 may function as a second gate (bottom gate) electrode. In this case, the potential applied to the conductive layer 505 is By changing the potential of the transistor 510A independently of the potential applied to the transistor 560, In particular, the threshold voltage of the FET can be controlled by applying a negative potential to the conductive layer 505. Therefore, the threshold voltage of the transistor 510A can be made higher than 0 V, and the off-state current can be reduced. Therefore, applying a negative potential to the conductive layer 505 is more effective than not applying a negative potential. However, when the potential applied to the conductive layer 560 is 0 V, the drain current can be reduced. .

[0389] In addition, for example, the conductive layer 505 and the conductive layer 560 are provided so as to overlap each other. When a potential is applied to the conductive layer 505, the electric field generated by the conductive layer 560 and the conductive layer 5 5 and the electric field generated by the oxide 530 are connected to each other, and the channel forming region is formed in the oxide 530. It is possible.

[0390] That is, the electric field of the conductive layer 560 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductive layer 505, which functions as an electrode, electrically connects the channel forming region. In this specification, the electric potential of the first gate electrode and the electric potential of the second gate electrode The structure of a transistor in which the channel formation region is electrically surrounded by a field is called a surrou This is called the ned channel (S-channel) structure.

[0391] The insulating layers 514 and 516 are interlayer insulating layers similar to the insulating layers 511 and 512. For example, the insulating layer 514 functions as a barrier against impurities such as water or hydrogen from the substrate side. It preferably functions as a barrier layer to prevent contamination of transistor 510A. With this configuration, impurities such as hydrogen and water can pass through the insulating layer 514 from the substrate side to the transistor 5 In addition, for example, the insulating layer 516 can be formed by It is preferable that the dielectric constant of the interlayer is lower than that of 514. By using a material with a low dielectric constant as the interlayer, The parasitic capacitance occurring between lines can be reduced.

[0392] The conductive layer 505, which functions as a second gate, is disposed in the opening of the insulating layer 514 and the insulating layer 516. A conductive layer 505a is formed in contact with the inner wall, and a conductive layer 505b is further formed on the inside. Here, the height of the upper surfaces of the conductive layers 505a and 505b and the upper surface of the insulating layer 516 are In the transistor 510A, the conductive layer 505a and the conductive layer Although a configuration in which 505b is stacked is shown, the present invention is not limited to this. For example, the conductive layer 505 may be provided as a single layer or a stacked structure of three or more layers. stomach.

[0393] Here, the conductive layer 505a prevents the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has a function of suppressing the impurities from penetrating the impurities. Alternatively, the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material having the above-mentioned function (i.e., being difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or oxygen. The function is to suppress the diffusion of any one or all of the above oxygen.

[0394] For example, the conductive layer 505a has a function of suppressing oxygen diffusion, so that the conductive layer 505b This can prevent the conductivity from decreasing due to oxidation.

[0395] When the conductive layer 505 also functions as a wiring, the conductive layer 505b is made of tungsten, copper, Alternatively, it is preferable to use a highly conductive material containing aluminum as a main component. In that case, the conductive layer 503 is not necessarily provided. Although shown in the figure, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. It may also be a laminate.

[0396] The insulating layer 521, the insulating layer 522, and the insulating layer 524 function as a second gate insulator. has.

[0397] In addition, the insulating layer 522 preferably has a barrier property. This prevents impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A. It functions as a layer that prevents contamination.

[0398] The insulating layer 522 may be, for example, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide. Hafnium-containing oxides (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba Insulators, including so-called high-k materials such as ,Sr)TiO3(BST), are used as single layers or As transistors become smaller and more highly integrated, Thinning of the insulator can cause problems such as leakage current. By using high-k materials as functional insulators, the physical thickness is maintained while This makes it possible to reduce the gate potential during operation of the transistor.

[0399] For example, the insulating layer 521 is preferably thermally stable. Silicon oxide nitride and silicon oxynitride are preferred because they are thermally stable. By combining the insulator with silicon oxide or silicon oxynitride, Moreover, insulating layer 521 having a laminated structure with a high relative dielectric constant can be obtained.

[0400] Although FIG. 30 shows a three-layered structure as the second gate insulator, a single layer or The laminated structure may be two or more layers. In that case, the laminated structure is not limited to the same material. Alternatively, it may have a laminated structure made of different materials.

[0401] The oxide 530 having a region that functions as a channel formation region is made up of an oxide 530a and an oxide The oxide 530b is on the oxide 530a, and the oxide 530c is on the oxide 530b. By having the oxide 530a under the oxide 530b, the The diffusion of impurities from the structure to the oxide 530b can be suppressed. By having oxide 530c on 530b, the structure formed above oxide 530c The diffusion of impurities from the structure to the oxide 530b can be suppressed. For this purpose, an oxide semiconductor, which is one of the metal oxides described in the above embodiment, can be used. .

[0402] The oxide 530c is formed in the opening in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, the insulating layer 580 is preferably provided. The diffusion of impurities into the oxide 530 can be suppressed.

[0403] One of the conductive layers 542 functions as a source electrode and the other functions as a drain electrode.

[0404] The conductive layer 542a and the conductive layer 542b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten. Metals or alloys containing metals as the main component can be used. In particular, tantalum nitride, etc. Metal nitride films have barrier properties against hydrogen and oxygen, and also have high oxidation resistance. preferable.

[0405] Although a single-layer structure is shown in FIG. 30, a laminated structure of two or more layers may be used. For example, nitride It is preferable to stack a tantalum film and a tungsten film. It is also preferable to stack a titanium film and an aluminum film. Also, a two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium film, etc. A two-layer structure in which a copper film is laminated on a sodium-aluminum alloy film, and a copper film is laminated on a titanium film A two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0406] In addition, a titanium film or a titanium nitride film and an aluminum film over the titanium film or the titanium nitride film are A titanium film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed on the aluminum film or a copper film. Three-layer structure, a molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the tantalum film, and a molybdenum film or The molybdenum nitride film is a three-layer structure. A transparent conductive material containing zinc oxide may also be used.

[0407] A barrier layer may be provided over the conductive layer 542. The barrier layer has a resistance to oxygen or hydrogen. It is preferable to use a material having a barrier property as the insulating layer 574. During the deposition, the conductive layer 542 can be prevented from being oxidized.

[0408] The barrier layer can be made of, for example, a metal oxide. In particular, aluminum oxide, oxide Uses insulating films with barrier properties against oxygen and hydrogen, such as hafnium oxide and gallium oxide. It is also preferable to use silicon nitride formed by a CVD method.

[0409] The inclusion of the barrier layer can broaden the range of material options for the conductive layer 542. For example, The conductive layer 542 is made of a material having low oxidation resistance but high conductivity, such as tungsten or aluminum. In addition, for example, a conductive material that is easy to form a film or process can be used. It is possible.

[0410] The insulating layer 550 functions as a first gate insulator. The insulating layer 550 is connected to the insulating layer 580. In the opening, an oxide layer 530c and an insulating layer 574 are provided. preferable.

[0411] As transistors become smaller and more highly integrated, the gate insulator becomes thinner, causing leakage currents to decrease. In this case, the insulating layer 550 may become a second gate insulator. Similarly, a laminated structure may be used. The insulator that functions as the gate insulator may be a high-k material. By using a laminated structure of a material that is thermally stable and a material that is not thermally stable, the thickness of the material is maintained while the It is possible to reduce the gate potential during transistor operation. In addition, it is thermally stable and has a high relative dielectric constant. It may be a laminated structure.

[0412] The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b. The conductive layer 560a is a conductive layer 560b on the conductive layer 505a. The conductive material has the function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms. Alternatively, oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, etc.) It is preferable to use a conductive material that has a function of suppressing the diffusion of the metal.

[0413] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, the material selection of the conductive layer 560b is In other words, the conductive layer 560a can improve the selectivity. Therefore, the oxidation of the electrode is suppressed, and the decrease in electrical conductivity can be prevented.

[0414] Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and tantalum nitride. It is preferable to use ruthenium, ruthenium oxide, or the like. As a, an oxide semiconductor which can be used as the oxide 530 can be used. In this case, the conductive layer 560b is formed by sputtering to reduce the electrical resistance of the oxide semiconductor. This is called OC (Oxide Conductor). or) electrodes.

[0415] The conductive layer 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductive layer 560 functions as a wiring, it is preferable to use a conductive material having high conductivity. It is preferable to use a conductor, for example a material mainly composed of tungsten, copper, or aluminum. The conductive layer 560b may have a layered structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0416] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510A. The present invention provides an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, other materials such as magnesium oxide, gallium oxide, germanium oxide, and oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide Any metal oxide, silicon oxide nitride or silicon nitride may be used.

[0417] By providing the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 are oxidized. The oxide 530b is prevented from diffusing through the insulating layer 550. In addition, the conductive layer 560 can be prevented from being oxidized due to excess oxygen contained in the insulating layer 580. It is possible.

[0418] The insulating layers 580, 582, and 584 function as interlayer films.

[0419] The insulating layer 582, like the insulating layer 514, prevents impurities such as water or hydrogen from entering the transistor from the outside. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of the oxide in the transistor 510A.

[0420] In addition, the insulating layer 580 and the insulating layer 584 are, like the insulating layer 516, thicker than the insulating layer 582. By using a material with a low dielectric constant as the interlayer film, the This can reduce the parasitic capacitance.

[0421] Transistor 510A is embedded in insulating layer 580, insulating layer 582, and insulating layer 584. Electrical connections may be made to other structures through plugs or wiring, such as recessed conductive layer 546. stomach.

[0422] As the material of the conductive layer 546, similar to the conductive layer 505, a metal material, an alloy material, a metal Conductive materials such as nitride materials or metal oxide materials are used in a single layer or in a laminated form. For example, high melting point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. Alternatively, it may be made of a low-resistance conductive material such as aluminum or copper. It is preferable to use a low-resistance conductive material to reduce the wiring resistance.

[0423] For example, the conductive layer 546 may be a conductive material having a barrier property against hydrogen and oxygen. By using a layered structure of tantalum nitride, which is an electric conductor, and tungsten, which has high electrical conductivity, The diffusion of impurities from the outside can be suppressed while maintaining the electrical conductivity of the wiring.

[0424] By using the above structure, a transistor including an oxide semiconductor with large on-state current can be provided. A semiconductor device having an oxide semiconductor with a low off-state current can be provided. It is possible to provide a semiconductor device having a transistor. As a result, it is possible to provide a semiconductor device having stable electrical characteristics and improved reliability. can.

[0425] <Transistor structure example 2> A structural example of the transistor 510B will be described with reference to FIGS. FIG. 31(A) is a top view of a transistor 510B. FIG. 31(B) is a top view of the transistor 510B shown in FIG. FIG 31(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG 31(A). 31(A) is a cross-sectional view of a portion indicated by line W1-W2. For convenience, some elements are omitted in the figure.

[0426] Transistor 510B is a modification of transistor 510A. In order to prevent this, differences from transistor 510A will be mainly described.

[0427] The transistor 510B includes a conductive layer 542 (conductive layer 542a and conductive layer 542b) and The oxide 530c, the insulating layer 550, and the conductive layer 560 overlap each other. By adopting this structure, a transistor with high on-state current can be provided. It is possible to provide a transistor with high

[0428] The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b. The conductive layer 560a is a conductive layer 560b on the conductive layer 505a. The conductive material has the function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms. Alternatively, oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, etc.) It is preferable to use a conductive material that has a function of suppressing the diffusion of the metal.

[0429] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, the material selection of the conductive layer 560b is In other words, the conductive layer 560a can improve the selectivity. Therefore, the oxidation of the electrode is suppressed, and the decrease in electrical conductivity can be prevented.

[0430] In addition, the upper surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide layer 530c It is preferable to provide an insulating layer 574 so as to cover the surface. It is recommended to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples include magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, etc. Metal oxides such as tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide Silicon oxide, silicon nitride, silicon oxide or silicon nitride can be used.

[0431] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. By providing the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 can be prevented from Therefore, diffusion to star 510B can be suppressed.

[0432] In addition, an insulating layer 576 (insulating layer 580) having a barrier property is provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, the insulating layer 576 can be provided. The oxygen in the edge layer 580 reacts with the conductive layer 546, and the conductive layer 546 is prevented from being oxidized. can be done.

[0433] In addition, by providing the insulating layer 576 having a barrier property, the conductor used for the plug or wiring For example, the conductive layer 546 may be provided with a material that absorbs oxygen. On the other hand, a metal material having high electrical conductivity can be used.

[0434] <Transistor structure example 3> An example of the structure of the transistor 510C will be described with reference to FIGS. FIG. 32(A) is a top view of transistor 510C. FIG. 32(B) is a top view of transistor 510C in FIG. FIG 32(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG 32(A). 32(A) is a cross-sectional view of a portion indicated by a line W1-W2. For convenience, some elements are omitted in the figure.

[0435] Transistor 510C is a variation of transistor 510A. In order to prevent this, differences from transistor 510A will be mainly described.

[0436] Transistor 510C shown in FIG. 32 includes a conductive layer 542a between oxide 530b. 47a is disposed, and conductive layer 547b is disposed between conductive layer 542b and oxide 530b. Here, the conductive layer 542a (conductive layer 542b) is a conductive layer 547a (conductive layer 547b). ) and the side surface on the conductive layer 560 side, and contacts the upper surface of the oxide 530b. Here, the conductive layer 547 is formed using a conductor that can be used for the conductive layer 542. Furthermore, the thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 542. It is.

[0437] The transistor 510C shown in FIG. 32 has the above-mentioned configuration. The conductive layer 542 can be closer to the conductive layer 560 than the conductive layer 510A. The conductive layer 560 can overlap the end of the conductive layer 542a and the end of the conductive layer 542b. This shortens the effective channel length of the transistor 510C, and reduces the on-current and the periphery. The wave number characteristics can be improved.

[0438] In addition, the conductive layer 547a (conductive layer 547b) overlaps with the conductive layer 542a (conductive layer 542b). With such a configuration, the conductive layer 546a (conductive layer In the etching for forming the opening for embedding the conductive layer 547a (conductive layer 54 7b) acts as a stopper to prevent oxide 530b from being over-etched. This can be done.

[0439] 32, an insulating layer 545 is provided on and in contact with the insulating layer 544. The insulating layer 544 is formed by insulating impurities such as water or hydrogen and excess oxygen. The insulating layer 580 is used as a barrier insulating film to prevent the inclusion of The insulating layer 545 preferably functions as the insulating layer 544. An insulating material can be used as the insulating layer 544. For example, aluminum nitride can be used. , titanium aluminum nitride, titanium nitride, silicon nitride or silicon oxynitride, Nitride insulators may also be used.

[0440] 32 is different from the transistor 510A shown in FIG. In this case, the conductive layer 505 may be formed in a single layer structure. 5, an insulating film that will become the insulating layer 516 is formed, and the upper part of the insulating film is placed on the upper surface of the conductive layer 505. The conductive layer 505 may be removed by a CMP method or the like until the flat surface of the conductive layer 505 is exposed. It is preferable to improve the flatness. For example, the average surface roughness (Ra) of the upper surface of the conductive layer 505 is 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. This improves the flatness of the insulating layer formed on the conductive layer 505 and the oxide 530b In addition, the crystallinity of the oxide 530c can be improved.

[0441] <Transistor structure example 4> An example of the structure of the transistor 510D will be described with reference to FIGS. FIG. 33A is a top view of a transistor 510D. FIG. 33B is a top view of the transistor 510D shown in FIG. FIG 33(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG 33(A). 33(A) is a cross-sectional view of a portion indicated by line W1-W2. For convenience, some elements are omitted in the figure.

[0442] Transistor 510D is a variation of transistor 510A. In order to prevent this, differences from transistor 510A will be mainly described.

[0443] In FIG. 33(A) to (C), the conductive layer 503 is not provided, and the function of the second gate is not provided. The conductive layer 505 also functions as a wiring. 0, and a metal oxide 552 on the insulating layer 550. The conductive layer 560 has an insulating layer 570 on the conductive layer 560. It has an edge layer 571 .

[0444] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing a metal oxide 552 that suppresses oxygen diffusion between the conductive layer 560 and the conductive layer 560, The diffusion of oxygen into the layer 560 is suppressed. In other words, the amount of oxygen supplied to the oxide 530 is reduced. In addition, oxidation of the conductive layer 560 due to oxygen can be suppressed.

[0445] Note that the metal oxide 552 may function as a part of the first gate. For example, The oxide semiconductor that can be used as the oxide 530 is used as the metal oxide 552. In that case, the conductive layer 560 can be formed by a sputtering method. The electrical resistance of the material 552 can be reduced to make it a conductive layer. Conductor electrodes.

[0446] The metal oxide 552 may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 550, It is preferable that 552 is made of a metal oxide, which is a high-k material having a high dielectric constant. This laminated structure is stable against heat and has a high dielectric constant. Therefore, the gate voltage applied during transistor operation can be reduced while maintaining the physical film thickness. In addition, the equivalent oxide thickness (EO T) can be made thinner.

[0447] In the transistor 510D, the metal oxide 552 is shown as a single layer; however, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a gate insulator A metal oxide that functions as a part of the insulating layer may be laminated thereon.

[0448] When the metal oxide 552 functions as a gate electrode, This improves the on-state current of the transistor 510D without weakening the effect of the electric field. Alternatively, a metal oxide layer 552 may be used as the gate insulator. The physical thickness of the conductive layer 560 and the oxide 530 maintain a distance between them, thereby preventing the conductive layer 560 from being damaged. Therefore, the leakage current between the insulating layer 560 and the oxide 530 can be suppressed. 550 and a metal oxide 552 are stacked to form a conductive layer 560 and an oxide 5 30 and the electric field strength from conductive layer 560 to oxide 530. It can be easily adjusted as needed.

[0449] Specifically, the oxide semiconductor that can be used for the oxide 530 can be made to have a low resistance. Metal oxide 552 can be used. Alternatively, hafnium, aluminum, gallium, Aluminum, Yttrium, Zirconium, Tungsten, Titanium, Tantalum, Nickel, Germanium Metal oxide containing one or more metals selected from nium, magnesium, etc. Compounds such as fluorine-containing fluorine compounds can be used.

[0450] In particular, the insulating layer contains an oxide of one or both of aluminum and hafnium. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (haf It is preferable to use hafnium aluminate. In particular, hafnium aluminate is It has higher heat resistance than hafnium oxide film. Therefore, the crystallization is prevented during the heat treatment in the later process. The metal oxide 552 is not an essential component. It is sufficient to design appropriately according to the transistor characteristics.

[0451] The insulating layer 570 has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material, such as aluminum oxide or hafnium oxide. This prevents the conductive layer 560 from being oxidized by oxygen from above the insulating layer 570. In addition, the insulating layer 570 can be prevented from being decomposed by water, hydrogen, or the like. Any impurities may enter the oxide 230 through the conductive layer 560 and the insulating layer 550. can be suppressed.

[0452] The insulating layer 571 functions as a hard mask. In the processing of 0, the side of the conductive layer 560 is approximately vertical, specifically, the side of the conductive layer 560 and the substrate The angle between the surfaces is between 75 degrees and 100 degrees, preferably between 80 degrees and 95 degrees. can be done.

[0453] Note that the insulating layer 571 has a function of suppressing permeation of impurities such as water or hydrogen and oxygen. By using an insulating material having such a property, the insulating layer may also function as a barrier layer. In addition, the insulating layer 570 is not necessarily provided.

[0454] Using the insulating layer 571 as a hard mask, the insulating layer 570, the conductive layer 560, and the metal oxide layer 5 52, insulating layer 550, and oxide 530c are selectively removed to remove these The sides can be made roughly flush and part of the oxide 530b surface can be exposed.

[0455] Transistor 510D also has regions 531a and 531b on a portion of the exposed oxide 530b surface. One of the regions 531a and 531b functions as a source region. the other functions as the drain region.

[0456] The regions 531a and 531b are formed by, for example, an ion implantation method or an ion doping method. , plasma immersion ion implantation, or plasma treatment to remove the exposed oxide. This can be achieved by introducing impurity elements such as phosphorus or boron into the surface of the object 530b. In this embodiment and the like, the term "impurity elements" refers to elements other than the main component elements.

[0457] In addition, after exposing a part of the surface of the oxide 530b, a metal film is formed and then heat-treated. As a result, the elements contained in the metal film are diffused into the oxide 530b, forming the regions 531a and Region 531b may also be formed.

[0458] The region of the oxide 530b into which the impurity element is introduced has a reduced electrical resistivity. Region 531a and region 531b may be referred to as "impurity regions" or "low resistance regions." .

[0459] By using the insulating layer 571 and / or the conductive layer 560 as a mask, the regions 531a and and region 531b can be formed in a self-aligned manner. The region 531a and / or the region 531b do not overlap with the conductive layer 560, and thus the parasitic capacitance is reduced. In addition, the channel formation region and the source / drain region (region 531a or No offset region is formed between region 531a and region 531b. By forming b in a self-aligned manner, the on-current is increased and the threshold This makes it possible to reduce the voltage required and improve the operating frequency.

[0460] In order to further reduce the off-state current, an off-state A set region may be provided. The offset region is a region having a high electrical resistivity. The offset region is a region where the impurity element is not introduced. This can be achieved by introducing the impurity element described above after forming the insulating layer 57. 5 also functions as a mask in the same manner as the insulating layer 571. Therefore, the insulating layer of the oxide 530b Impurity elements are not introduced into the region overlapping with 575, and the electrical resistivity of the region remains high. This can be done.

[0461] The transistor 510D also includes an insulating layer 570, a conductive layer 560, a metal oxide 552, and an insulating On the side of the layer 550 and the oxide 530c is an insulating layer 575. The insulating layer 575 is a dielectric It is preferable to use an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon Silicon, carbon and nitrogen doped silicon oxide, silicon oxide with vacancies, or resin In particular, silicon oxide, silicon oxynitride, silicon oxynitride, etc. In the case where silicon oxide having voids is used for the insulating layer 575, the insulating layer 575 may be formed in a later process. This is preferable because the excess oxygen region can be easily formed. Con is preferable because it is thermally stable. In addition, the insulating layer 575 has a function of diffusing oxygen. It is preferable to have

[0462] Transistor 510D also includes insulating layer 575 and insulating layer 574 on oxide 530. The insulating layer 574 is preferably formed by a sputtering method. By using this method, it is possible to form an insulator film with few impurities such as water or hydrogen. For example, the insulating layer 574 may be formed using aluminum oxide.

[0463] In addition, the oxide film formed by the sputtering method may extract hydrogen from the structure on which the film is formed. Thus, insulating layer 574 absorbs hydrogen and water from oxide 230 and insulating layer 575. This allows the hydrogen concentration in the oxide 230 and the insulating layer 575 to be reduced.

[0464] <Transistor structure example 5> An example of the structure of the transistor 510E will be described with reference to FIGS. FIG. 34(A) is a top view of a transistor 510E. FIG. 34(B) is a top view of the transistor 510E shown in FIG. FIG 34(C) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG 34(A). 34(A) is a cross-sectional view of a portion indicated by line W1-W2. For convenience, some elements are omitted in the figure.

[0465] Transistor 510E is a modification of transistor 510A. In order to prevent this, differences from transistor 510A will be mainly described.

[0466] In FIG. 34(A) to (C), the conductive layer 542 is not provided, and the exposed oxide 530b surface is A part of the region 531a and a part of the region 531b are included. One acts as a source region and the other acts as a drain region. An insulating layer 573 is provided between the insulating layer 574 and the insulating layer 573 .

[0467] The region 531 (region 531a and region 531b) shown in FIG. The region 531 is a region where the above-mentioned elements are added. For example, a dummy gate is used for the region 531. It can be formed with.

[0468] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to It is preferable to use the oxide 530b and add an element that reduces the resistance of the oxide 530b. However, the element is added to the region that does not overlap with the dummy gate, and a region 531 is formed. The method of adding the element is to add the ionized source gas by mass separation. and ion doping, in which ionized source gas is added without mass separation. , plasma immersion ion implantation, etc. can be used.

[0469] Representative elements for reducing the resistance of the oxide 530 include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. Representative examples of rare gas elements include helium, neon, argon, krypton, and The concentration of these elements is measured using secondary ion mass spectrometry (SIMS) and other methods. It is sufficient to measure it.

[0470] In particular, boron and phosphorus are essential for the production of amorphous silicon or low-temperature polysilicon. This is preferable because existing equipment can be used. Capital investment can be reduced.

[0471] Next, an insulating film that will become an insulating layer 573 is formed on the oxide 530b and the dummy gate. An insulating film to be the insulating layer 574 may be formed. By laminating an insulating film to be 574, the region 531, the oxide 530c, and the insulating film There may be an area of ​​overlap with layer 550 .

[0472] Specifically, an insulating film that will become the insulating layer 580 is provided on the insulating film that will become the insulating layer 574, and then the insulating film is The insulating film that will become layer 580 is subjected to CMP (Chemical Mechanical Polishing). By carrying out the etching process, a part of the insulating film that will become the insulating layer 580 is removed, and a dummy gate When the dummy gate is subsequently removed, the insulating layer 573 in contact with the dummy gate is exposed. Therefore, the insulating layer 580 is formed on the side of the opening. 574 and the insulating layer 573 are exposed, and the bottom surface of the opening is provided with an oxide 530b. A part of the insulating region 531 is exposed. Next, an oxide film that becomes an oxide 530c is formed in the opening. After forming an insulating film that will become the edge layer 550 and a conductive film that will become the conductive layer 560 in this order, the insulating layer 5 The oxide film that becomes the oxide 530c and the insulating layer 550 are formed by CMP processing or the like until the insulating layer 80 is exposed. 34. By removing the insulating film to be the conductive layer 560 and the conductive film to be the conductive layer 560, A transistor can be formed.

[0473] Note that the insulating layer 573 and the insulating layer 574 are not essential components. The design should be appropriate depending on the requirements.

[0474] The transistor shown in FIG. 34 can be made from an existing device, and further includes conductive layer 542. Since no additional components are provided, costs can be reduced.

[0475] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0476] (Embodiment 8) This embodiment mode will be described with reference to an electronic component and an electronic An example of the device is shown.

[0477] <Electronic components> First, an example of an electronic component incorporating the storage device 300 will be described with reference to FIGS. 35(A) and 35(B). Make a statement.

[0478] FIG. 35A shows an electronic component 700 and a substrate on which the electronic component 700 is mounted (a substrate 704 on which the electronic component 700 is mounted). The electronic component 700 shown in FIG. 35(A) is an IC chip, and the leads and The electronic component 700 is mounted on, for example, a printed circuit board 702. A number of such IC chips are combined and each is electrically connected on the printed circuit board 702. This completes the mounting board 704.

[0479] The electronic component 700 includes the memory device 300 shown in the above embodiment as a circuit unit. In FIG. 35A, the package of the electronic component 700 is a QFP (Quad Flat Package). However, the form of the package is not limited to this.

[0480] FIG. 35B shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) MCM (Multi Chip Module) The electronic component 730 is an interposer on a package substrate 732 (printed circuit board). A semiconductor device 735 and a plurality of memory devices are provided on the interposer 731. A station 300 is provided.

[0481] In the electronic component 730, the storage device 300 is a high bandwidth memory (HBM). dth Memory). The semiconductor device 735 is a CP Integrated circuits (semiconductor devices) such as U, GPU, and FPGA can be used.

[0482] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be a silicon interposer, a resin interposer, or the like. An interposer or the like can be used.

[0483] The interposer 731 has a plurality of wirings and electrically connects a plurality of integrated circuits having different terminal pitches. The wiring has a function of effectively connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 73. 2. The interposer is sometimes called a "rewiring substrate" or an "intermediate substrate." A through electrode is provided in the package substrate 732, and the through electrode is used to electrically connect the integrated circuit and the package substrate 732. In addition, in silicon interposers, TSV (Transistor Via) is used as a through electrode. Through Silicon Via can also be used.

[0484] It is preferable to use a silicon interposer as the interposer 731. Silicon Since there is no need to provide active elements in an interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring that is difficult to achieve with resin interposers.

[0485] In HBM, many wires must be connected to achieve a wide memory bandwidth. Therefore, the interposer that mounts HBM requires fine and high-density wiring. Therefore, the interposer for mounting HBM should be a silicon interposer. is preferred.

[0486] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to the difference in the expansion coefficient between the silicon interposer. The silicon interposer has a high surface flatness, so the integrated circuit and silicon interposer can be mounted on the silicon interposer without any problems. In particular, it is difficult to cause connection failure between interposers. In 2.5D packaging (2.5-dimensional assembly), silicon interposers are used to place It is preferable to use:

[0487] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the memory device 300 and the semiconductor device 735 It is preferable to make the heights of the electrodes uniform.

[0488] In order to mount the electronic component 730 on another substrate, electrodes 733 are provided on the bottom of the package substrate 732. 35B shows an example in which the electrode 733 is formed using a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (Ba In addition, the electrodes 733 can be formed with conductive pins. The bottom of the package substrate 732 may be provided with conductive pins arranged in a matrix. This allows for PGA (Pin Grid Array) implementation.

[0489] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ay), LGA (Land Grid Array), QFP, QFJ (Quad Fl at J-leaded package), or QFN (Quad Flat No The mounting method such as n-leaded package can be used.

[0490] <Electronic equipment> Next, an example of an electronic device including the above electronic components will be described with reference to FIG.

[0491] The robot 7100 is equipped with a light sensor, a microphone, a camera, a speaker, a display, Various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may have a function of controlling the peripheral devices. The memory has a function of storing the data.

[0492] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has a function of emitting audio signals such as voice and warning sounds. The 7100 analyzes the audio signal input through the microphone and outputs the necessary audio. The robot 7100 can emit audio signals from a speaker. and a speaker for communication with the user.

[0493] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has a function of moving using a moving mechanism. It is possible to capture images and analyze them to detect the presence or absence of obstacles when moving around.

[0494] The flying object 7120 has a propeller, a camera, a battery, etc., and is an autonomous flying object. The electronic component 730 has a function of controlling these peripheral devices.

[0495] For example, image data captured by a camera is stored in the electronic component 700. It can analyze image data and detect the presence or absence of obstacles when moving. The remaining battery charge is estimated from the change in the storage capacity of the battery by the electronic component 730. can be done.

[0496] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The robot has a brush, a control button, various sensors, etc. The 7300 is equipped with tires, a suction port, etc. The cleaning robot 7300 is self-propelled. It can detect dust and suck it up through a suction port provided on the bottom surface.

[0497] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. It can determine whether there is an obstacle. Also, by analyzing images, it can detect wires and other objects that are entangled in the brush. If such an object is detected, the brush can stop rotating.

[0498] The automobile 7160 has an engine, tires, brakes, a steering system, a camera, etc. For example, the electronic components 730 may include navigation information, speed, engine status, gear selection status, To optimize the driving condition of the car 7160 based on data such as the frequency of brake use, For example, image data captured by a camera is stored in the electronic component 700.

[0499] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (a television receiver device), smartphone 7210, PC 7220 (personal computer), PC 72 30, game machine 7240, game machine 7260, etc.

[0500] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic components 730 can perform functions such as noise reduction, resolution up-conversion, etc. Which image processing is performed?

[0501] The smartphone 7210 is an example of a portable information terminal. The electronic component 730 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by

[0502] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The keyboard 7232 and the monitor device 7233 are connected to the 7230 by wireless or wired connection. The game machine 7240 is an example of a portable game machine. The game machine 7260 is a stationary game machine. The game machine 7260 is an example of a stationary game machine. 262 is connected to the controller 7262. Component 730 may also be included.

[0503] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0504] (Embodiment 9) In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is applicable to, for example, various electronic devices (e.g., terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used in a memory card (e.g., Various removable media such as cards, USB memory, and SSDs (Solid State Drives) FIG. 37 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. and used in various storage devices and removable memory.

[0505] FIG. 37A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, The cap 1102, the USB connector 1103, and the board 1104 are included. For example, the substrate 1104 includes a memory chip 1105. , and a controller chip 1106 are attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 05 or the like.

[0506] FIG. 37(B) is a schematic diagram of the external appearance of an SD card, and FIG. 37(C) shows the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate. The substrate 1113 is housed in a housing 1111. For example, the substrate 111 A memory chip 1114 and a controller chip 1115 are attached to the board 3. By providing a memory chip 1114 on the back side of the board 1113, the capacity of the SD card 1110 In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the memory to be wirelessly transmitted between the host device and the SD card 1110. This allows data to be read from and written to the memory chip 1114 on the substrate 1113. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0507] FIG. 37(D) is a schematic diagram of the external appearance of the SSD, and FIG. 37(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 may include a memory The chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing the memory 4, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0508] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of symbols]

[0509] 100: semiconductor device, 110: voltage generating circuit, 120: voltage holding circuit, 130: temperature detection circuit, 131: temperature sensor, 132: analog-to-digital conversion circuit, 140: voltage control circuit circuit, 145: logic circuit, 146: voltage generating circuit

Claims

1. A memory cell, a peripheral circuit, and a semiconductor device, the memory cell includes a first transistor having a first gate and a second gate; The first gate and the second gate have a region where they overlap with each other via a semiconductor layer containing a metal oxide, writing the first data for a first time after reading the first data; a function of writing the first data for a second period of time after reading the first data held; and a function of supplying a first potential to the second gate of the first transistor to turn off the first transistor, and then stopping the supply of power to the memory cell and the peripheral circuit, The semiconductor device includes a second transistor, one of a source and a drain of the second transistor is electrically connected to the second gate of the first transistor; the first data is multi-valued data, The second time period is greater than the first time period. storage device.

2. In claim 1, The second transistor has a channel length longer than that of the first transistor. storage device.

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