Semiconductor device manufacturing method

Abstract

To provide a manufacturing method of a semiconductor device for forming an IIL (Integrated Injection Logic) circuit section that suppresses a parasitic operation of a parasitic transistor in a simple manner and without causing a significant increase in manufacturing cost.SOLUTION: When the parasitic transistor with a secondary p-type impurity region 6a as an emitter, a first n-type impurity region 5a and an n-type embedding layer 4a as a base, and a separation region 3 as a collector, which is a base of a multi-collector npn transistor in an IIL circuit section, is turned on, the width of the first n-type impurity region 5a is widened and the impurity concentration at a connection portion between the first n-type impurity region 5a and the n-type embedding layer 4a is increased to suppress the parasitic operation of the parasitic transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device provided with an IIL element. [Background technology]

[0002] When an IIL (Integrated Injection Logic) element is included as an element constituting a bipolar semiconductor integrated circuit, a bipolar circuit section in which a bipolar element is formed and an IIL circuit section in which an IIL element is formed are each formed in a semiconductor region separated by an isolation region.

[0003] As shown in Fig. 5, the IIL circuit section is structured such that a multi-collector npn transistor Tr1 having multiple collectors and a pnp transistor Tr2 for supplying a base current to the base of the npn transistor Tr1 are formed. Fig. 6 is a cross-sectional view of a general IIL circuit section and an isolation region that separates the IIL circuit section from an adjacent bipolar circuit section. As shown in Fig. 6, an n-type epitaxial layer 2 is laminated on a p-type substrate 1, and the n-type epitaxial layer 2 is surrounded by an isolation region 3 formed by a p-type buried layer 3a formed between the p-type substrate 1 and the n-type epitaxial layer 2 and a first p-type impurity region 3b formed from the surface of the n-type epitaxial layer 2, thereby partitioning the IIL circuit section.

[0004] In this IIL circuit section, an n-type buried layer 4 is formed between a p-type substrate 1 and an n-type epitaxial layer 2, and a first n-type impurity region 5 is formed so as to reach the n-type buried layer 4 and partition the n-type epitaxial layer 2. A second p-type impurity region 6 is formed on the surface of the n-type epitaxial layer 2 partitioned by this first n-type impurity region 5, and a plurality of second n-type impurity regions 7 are formed on the surface of the p-type impurity region 6. 8 denotes a third p-type impurity region formed on the surface of the n-type epitaxial layer 2.

[0005] In the semiconductor device having such a structure, the multi-collector npn transistor Tr1 has the n-type epitaxial layer 2 as an emitter, the second p-type impurity region 6 as a base, and the second n-type impurity region 7 as a collector. collector , the n-type epitaxial layer 2 is the base, and the third p-type impurity region 8 is Emitter This type of semiconductor device is described in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-220793 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a method for manufacturing a semiconductor device having such a structure, in order to connect the n-type buried layer 4 and the first n-type impurity region 5, impurities are diffused from above the p-type substrate 1 into the n-type buried layer 4, and from the surface of the n-type epitaxial layer 2 into the first n-type impurity region 5. The concentration profile in the depth direction is shown in Fig. 7. As shown in Fig. 7, it can be seen that there is a region with a low impurity concentration at a depth corresponding to the connection portion between the first n-type impurity region 5 and the n-type buried layer 4.

[0008] In this region where the impurity concentration is low, when the impurity concentration is relatively high, the parasitic operation of a parasitic transistor in which the second p-type impurity region 6 serves as the emitter, the first n-type impurity region 5 and the n-type buried layer 4 serve as the base, and the isolation region 3 serves as the collector is suppressed.

[0009] However, in this type of semiconductor device, it is preferable to form the bipolar circuit section and the IIL circuit section simultaneously, and it is difficult to appropriately set the impurity concentration of the IIL circuit section alone. Therefore, there is a problem that manufacturing costs increase if the bipolar circuit section and the IIL circuit section are manufactured separately in order to optimize the impurity concentration. In view of the above situation, the object of the present invention is to provide a manufacturing method for a semiconductor device that can form an IIL circuit section that suppresses the parasitic action of a parasitic transistor in a simple manner without significantly increasing manufacturing costs. [Means for solving the problem]

[0010] In order to achieve the above object, the present invention according to claim 1 comprises an isolation region consisting of a buried layer of one conductivity type and a first impurity region of one conductivity type, which partitions a semiconductor layer of an opposite conductivity type formed on a surface of a semiconductor substrate of one conductivity type as an IIL circuit section, a buried layer of the opposite conductivity type formed between the semiconductor substrate and the semiconductor layer of the IIL circuit section, a first impurity region of the opposite conductivity type formed from the surface of the semiconductor layer and reaching the buried layer of the opposite conductivity type, a second impurity region of one conductivity type and a third impurity region of one conductivity type formed on the surface of the semiconductor layer surrounded by the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type, and In a method for manufacturing a semiconductor device comprising forming a first transistor having at least the semiconductor layer as an emitter, the second impurity region of one conductivity type as a base, and the second impurity region of the opposite conductivity type as a collector, and a second transistor having the third impurity region of one conductivity type as an emitter, the semiconductor layer as a base, and the second impurity region of one conductivity type as a collector, when an impurity concentration at a connection portion between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is low, and a parasitic transistor having the second impurity region of one conductivity type as an emitter, at least the first impurity region of the opposite conductivity type and the buried layer of the opposite conductivity type as a base, and the isolation region as a collector is turned on, before The first impurity region of the opposite conductivity type The formation conditions are not changed when forming the first impurity region of the opposite conductivity type, which is the channel length of the parasitic transistor.In comparison with the case where the parasitic transistor is turned on only by changing the width of the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type, the impurity concentration of the connection portion between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is increased to increase the impurity concentration difference between the emitter and the base of the parasitic transistor, and further, the dimension of overlap between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is increased to suppress the parasitic operation of the parasitic transistor.

[0011] The invention according to claim 2 of the present application comprises an isolation region made of a buried layer of one conductivity type and a first impurity region of one conductivity type, which divides a semiconductor layer of an opposite conductivity type formed on a surface of a semiconductor substrate of one conductivity type into a first semiconductor layer of an opposite conductivity type and a second semiconductor layer of an opposite conductivity type as an IIL circuit section and a bipolar circuit section, respectively; a first buried layer of the opposite conductivity type formed between the semiconductor substrate and the first semiconductor layer in the IIL circuit section; a first impurity region of the opposite conductivity type formed from the surface of the first semiconductor layer and reaching the first buried layer of the opposite conductivity type; a first transistor including at least the first semiconductor layer as an emitter, the second impurity region of one conductivity type as a base, and the second impurity region of the opposite conductivity type as a collector; and a second transistor including at least the first semiconductor layer as an emitter, the second impurity region of one conductivity type as a base, and the second impurity region of the opposite conductivity type as a collector. a second buried layer of the opposite conductivity type is formed between the semiconductor substrate of the bipolar circuit section and the second semiconductor layer of the opposite conductivity type simultaneously with the first buried layer of the opposite conductivity type; a third impurity region of the opposite conductivity type is formed from a surface of the second semiconductor layer and reaches the second buried layer of the opposite conductivity type simultaneously with the first impurity region of the opposite conductivity type; a fourth impurity region of one conductivity type is formed on the surface of the second semiconductor layer simultaneously with the second impurity region of one conductivity type; In a method for manufacturing a semiconductor device for forming a third transistor, which is formed simultaneously with a second impurity region and has at least the second semiconductor layer as a collector, the fourth impurity region of one conductivity type as a base, and the fourth impurity region of the opposite conductivity type as an emitter, when an impurity concentration at a connection portion between the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is low, and a parasitic transistor having the second impurity region of one conductivity type as an emitter, at least the first impurity region of the opposite conductivity type and the first buried layer of the opposite conductivity type as a base, and the isolation region as a collector is turned on, beforeThe first impurity region of the opposite conductivity type The formation conditions are not changed when forming the first impurity region of the opposite conductivity type, which is the channel length of the parasitic transistor. In comparison with the case where the parasitic transistor is turned on by only changing the width of the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type, the impurity concentration of the connection portion between the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is increased to increase the impurity concentration difference between the emitter and the base of the parasitic transistor, and further, the dimension of overlap between the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is increased to suppress the parasitic operation of the parasitic transistor. Effect of the Invention

[0012] According to the manufacturing method of the semiconductor device of the present invention, the size of the impurity region is adjusted to suppress the parasitic operation of the parasitic transistor, and an IIL element with excellent characteristics can be easily formed while maintaining the characteristics required of the bipolar transistor formed in the bipolar circuit section. Moreover, the effect can be obtained by changing the impurity region by about several μm, and there is no significant increase in product cost due to an increase in the area occupied by the IIL circuit section.

[0013] In particular, by lowering the impurity concentration in the epitaxial layer of the bipolar circuit section, it is possible to form a bipolar element with high breakdown voltage and an IIL element with excellent characteristics. [Brief description of the drawings]

[0014] [Figure 1] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] FIG. 1 is a diagram illustrating a typical IIL circuit. [Figure 6] FIG. 1 is a diagram illustrating a semiconductor device including a general IIL circuit. [Figure 7] FIG. 1 is a diagram showing a concentration profile of a portion of a semiconductor device having a typical IIL circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The method for manufacturing a semiconductor device according to the present invention is a suitable method for forming an IIL circuit section in a semiconductor device having a bipolar circuit section in which a bipolar element is formed and an IIL circuit section in which an IIL element is formed. EXAMPLES

[0016] An embodiment of the present invention will be described in detail according to a manufacturing process of a semiconductor device in which a multi-collector npn transistor and a pnp transistor are formed in an IIL circuit section, and an npn transistor is formed in a bipolar circuit section.

[0017] First, an n-type epitaxial layer is formed on a p-type substrate 1. At this time, impurity ions of a desired conductive type are implanted into the surface of the p-type substrate 1 in order to form a p-type buried layer 3a constituting an isolation region separating an IIL circuit section from a bipolar circuit section, a first n-type buried layer 4a in the IIL circuit section, and a second n-type buried layer 4b in the bipolar circuit section. The impurity concentration of the n-type epitaxial layer is set according to the withstand voltage of an npn transistor formed in the bipolar circuit section, and generally, the impurity concentration of the n-type epitaxial layer is set low in order to increase the withstand voltage of the npn transistor. As the n-type epitaxial layer grows, the impurity ions implanted in the p-type substrate 1 diffuse, forming a p-type buried layer 3a, a first n-type buried layer 4a, and a second n-type buried layer 4b. If necessary, it is also possible to form buried layers by repeating the process of implanting desired impurity ions and then performing epitaxial growth.

[0018] Then, a first p-type impurity region 3b is formed from the surface of the n-type epitaxial layer to reach the p-type buried layer 3a, and an isolation region 3 consisting of the p-type buried layer 3a and the first p-type impurity region 3b is formed. A part of the n-type epitaxial layer partitioned by this isolation region 3 (first n-type epitaxial layer 2a) becomes an IIL circuit section, and another part of the n-type epitaxial layer partitioned by the isolation region 3 (second n-type epitaxial layer 2b) becomes a bipolar circuit section (Figure 1).

[0019] Next, a first n-type impurity region 5a is formed from the surface of the first n-type epitaxial layer 2a to reach the first n-type buried layer 4a, thereby partitioning a part of the first n-type epitaxial layer 2a. At the same time, a third n-type impurity region 5b is formed from the surface of the second n-type epitaxial layer 2b to reach the second n-type buried layer 4b (FIG. 2).

[0020] A second p-type impurity region 6a and a third p-type impurity region 8a are formed on the surface of the first n-type epitaxial layer 2a. At the same time, a fourth p-type impurity region 6b is formed on the surface of the second n-type epitaxial layer 2b. Next, a second n-type impurity region 7a is formed on the surface of the second p-type impurity region 6a. At the same time, a fourth n-type impurity region 7b is formed on the surface of the fourth p-type impurity region 6b (FIG. 3). The second p-type impurity region 6a formed in the IIL circuit section serves as the base of the npn transistor, and is preferably disposed in close proximity to or in contact with the base in order to increase the efficiency of injection from the base to the emitter (first n-type impurity region 5a).

[0021] As explained in the conventional example, when the impurity concentration at the depth corresponding to the junction between the first n-type impurity region 5a and the first n-type buried layer 4a decreases, in addition to a normal npn transistor having the second n-type impurity region 7a as the collector, the second p-type impurity region 6a as the base, and the first n-type epitaxial layer 2a as the emitter, a pnp parasitic transistor having the second p-type impurity region 6a as the emitter, the first n-type epitaxial layer 2a, the first n-type impurity region 5a and the first buried layer 4a as the base, and the isolation region 3A as the collector turns on, and parasitic operation cannot be suppressed.

[0022] In this type of semiconductor device, the bipolar circuit section and the IIL circuit section are formed simultaneously to reduce manufacturing costs, and therefore it is desirable to avoid forming the first n-type impurity region 5a of the IIL circuit section and the third n-type impurity region 5b of the bipolar circuit section in separate processes in order to increase the impurity concentration at a depth corresponding to the connection between the first n-type impurity region 5a and the first n-type buried layer 4a.

[0023] Therefore, in this embodiment, when the impurity concentration at the connection portion between the first n-type impurity region 5a and the first n-type buried layer 4a decreases due to conditions such as the impurity concentration and thickness of the n-type epitaxial layer, causing the parasitic transistor to turn on, the width of the first n-type impurity region 5a (corresponding to the channel length of the parasitic transistor) is expanded to increase the impurity concentration near the connection portion.

[0024] FIG. 4 shows the lowest impurity concentration of the connection part when the first n-type impurity region 5a is formed under the same forming conditions and only the mask width dimension is changed. As shown in FIG. 4, the impurity concentration of the connection part can be increased by widening the width of the first n-type impurity region 5a. After the impurity concentration becomes constant, the dimension where the first n-type impurity region 5a and the first n-type buried layer 4a overlap increases. In other words, by widening the mask width, the impurity concentration difference between the emitter and base of the parasitic transistor is increased, and by further increasing the length, the parasitic operation of the parasitic transistor is suppressed. As a result, it is possible to eliminate the contribution of the parasitic transistor and form an IIL element with excellent characteristics.

[0025] In the example shown in FIG. 4, by setting the width of the first n-type impurity region to 5 μm or more, it was confirmed that the leakage current, which is thought to be due to a parasitic transistor in the IIL circuit portion, was stably reduced.

[0026] On the other hand, the npn transistor in the bipolar circuit section can obtain desired characteristics since the impurity concentration of the second n-type epitaxial layer 2b is set so as to obtain a desired breakdown voltage.

[0027] Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above-mentioned embodiments. For example, the example in which an IIL element and an npn transistor as a bipolar element are formed simultaneously has been described, but the present invention is not limited to this. [Explanation of symbols]

[0028] 1: p-type substrate, 2: n-type epitaxial layer, 2a: first n-type epitaxial layer, 2b: second n-type epitaxial layer, 3: separation region, 3a: p-type buried layer, 3b: first p-type impurity region, 4: n-type buried layer, 4a: first n-type buried layer, 4b: second n-type buried layer, 5, 5a: first n-type impurity region, 5b: third n-type impurity region, 6, 6a: second p-type impurity region, 6b: fourth p-type impurity region, 7, 7a: second n-type impurity region, 7b: fourth n-type impurity region, 8, 8a: third p-type impurity region

Claims

1. a buried layer of the opposite conductivity type formed between the semiconductor substrate and the semiconductor layer of the IIL circuit portion; a first impurity region of the opposite conductivity type formed from a surface of the semiconductor layer and reaching the buried layer of the opposite conductivity type; a second impurity region of the one conductivity type and a third impurity region of the one conductivity type formed on the surface of the semiconductor layer surrounded by the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type; and a second impurity region of the opposite conductivity type formed on a surface of the second impurity region of the one conductivity type, the first transistor having at least the semiconductor layer as an emitter, the second impurity region of the one conductivity type as a base, and the second impurity region of the opposite conductivity type as a collector, the method comprising the steps of: forming a first transistor having the third impurity region of the one conductivity type as an emitter, the semiconductor layer as a base, and the second impurity region of the one conductivity type as a collector; When the impurity concentration of a connection portion between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is low, a parasitic transistor having the second impurity region of one conductivity type as an emitter, at least the first impurity region of the opposite conductivity type and the buried layer of the opposite conductivity type as a base, and the isolation region as a collector is turned on, a first impurity region of the opposite conductivity type, which is a channel length of the parasitic transistor, is increased in width, compared to when the parasitic transistor is turned on, by increasing the impurity concentration at the connection between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type, thereby increasing the impurity concentration difference between the emitter and base of the parasitic transistor, and further increasing the dimension of overlap between the buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type, thereby suppressing parasitic operation of the parasitic transistor.

2. a first transistor comprising: an isolation region including a buried layer of one conductivity type and a first impurity region of one conductivity type, which divides a semiconductor layer of an opposite conductivity type formed on a surface of a semiconductor substrate of one conductivity type into a first semiconductor layer of an opposite conductivity type and a second semiconductor layer of an opposite conductivity type as an IIL circuit section and a bipolar circuit section, respectively; a first buried layer of the opposite conductivity type formed between the semiconductor substrate of the IIL circuit section and the first semiconductor layer; a first impurity region of the opposite conductivity type formed from the surface of the first semiconductor layer and reaching the first buried layer of the opposite conductivity type; a second impurity region of one conductivity type and a third impurity region of one conductivity type formed on the surface of the first semiconductor layer surrounded by the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type; and a second impurity region of the opposite conductivity type formed on the surface of the second impurity region of the one conductivity type, a second transistor having the third impurity region of one conductivity type as an emitter, the first semiconductor layer as a base, and the second impurity region of one conductivity type as a collector, a second buried layer of the opposite conductivity type is formed between the semiconductor substrate of the bipolar circuit portion and the second semiconductor layer of the opposite conductivity type simultaneously with the first buried layer of the opposite conductivity type, a third impurity region of the opposite conductivity type formed from a surface of the second semiconductor layer and reaching the second buried layer of the opposite conductivity type simultaneously with the first impurity region of the opposite conductivity type, a fourth impurity region of one conductivity type is formed on the surface of the second semiconductor layer simultaneously with the second impurity region of one conductivity type, and a fourth impurity region of the opposite conductivity type is formed on a surface of the fourth impurity region of one conductivity type simultaneously with the second impurity region of the opposite conductivity type, When the impurity concentration of a connection portion between the first buried layer of the opposite conductivity type and the first impurity region of the opposite conductivity type is low, and a parasitic transistor having the second impurity region of one conductivity type as an emitter, at least the first impurity region of the opposite conductivity type and the first buried layer of the opposite conductivity type as a base, and the isolation region as a collector is turned on, a first buried layer of the opposite conductivity type and a first impurity region of the opposite conductivity type, the first buried layer of the opposite conductivity type being connected to the first impurity region of the opposite conductivity type, and the first impurity region of the opposite conductivity type being connected to the first buried layer of the opposite conductivity type; a first impurity region of the opposite conductivity type being connected to the first buried layer of the opposite conductivity type; a first impurity region of the opposite conductivity type being connected to the first impurity region of the opposite conductivity type;

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