Charge pump circuit and image sensor including same

Abstract

To provide a charge pump circuit and an image sensor including the same.SOLUTION: A charge pump circuit according to the present invention receives a clock signal and generates a negative output voltage. The charge pump circuit includes a first pump unit including a first capacitor and a first transistor and generating a first node voltage using a clock signal, and a second pump unit including a second capacitor, a second transistor, and a third transistor and generating an output voltage using the first node voltage. Each of the clock signal and the first node voltage is toggled between a low level voltage and a high level voltage. The level of the output voltage is higher than the level of the high level voltage of the clock signal, and the body of the second transistor and the body of the third transistor are electrically insulated from each other.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a charge pump circuit and an image sensor including a charge pump circuit. [Background technology]

[0002] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and includes a pixel array having a plurality of pixels, a circuit for driving the pixel array, etc. In recent years, as the demand for performance of image sensors increases, various researches have been conducted to improve the dark current characteristics of image sensors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-75865 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide a charge pump circuit capable of outputting a high negative voltage, and an image sensor including the same. [Means for solving the problem]

[0005] In order to solve the above-mentioned object, one aspect of the present invention provides a charge pump circuit that receives a clock signal and generates a negative output voltage, the charge pump circuit comprising: a first pump unit including a first capacitor and a first transistor, and generating a first node voltage using the clock signal; and a second pump unit including a second capacitor, a second transistor, and a third transistor, and generating the output voltage using the first node voltage, wherein each of the clock signal and the first node voltage toggles between a low level voltage and a high level voltage, the magnitude of the output voltage is greater than the magnitude of the high level voltage of the clock signal, and the body of the second transistor and the body of the third transistor are electrically insulated.

[0006] According to another aspect of the present invention, which has been made to achieve the above object, there is provided a charge pump circuit for receiving a clock signal and generating a negative output voltage, the charge pump circuit comprising: a substrate in which a first well and a second well are formed; a first pump unit including a first capacitor and a first transistor formed in the first well; a second pump unit including a second capacitor and a second transistor formed in the second well; and an isolation layer electrically insulating the first well and the second well, wherein the clock signal toggles between a low level voltage and a high level voltage at a constant period, and the magnitude of the output voltage is greater than the magnitude of the high level voltage.

[0007] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a pixel array including a plurality of pixels defined by a first element isolation film, and a charge pump circuit that receives a clock signal and provides a negative output voltage to the pixel array, the charge pump circuit including a first pump unit including a first capacitor and a first transistor and generating a first node voltage using the clock signal, and a second pump unit including a second capacitor, a second transistor, and a third transistor and generating the output voltage using the first node voltage, and a body of the second transistor and a body of the third transistor are electrically insulated.

[0008] According to an embodiment, there is provided a charge pump circuit for receiving a clock signal and generating a negative output voltage, the charge pump circuit comprising: a substrate in which a first well, a second well, and a third well are formed; a first pump unit including a first capacitor and a p-type transistor formed in the first well; a second pump unit including a second capacitor, a p-type transistor formed in the second well, and an n-type transistor formed in the third well; and an isolation film formed between the first well, the second well, and the third well, respectively, and electrically insulating the first well, the second well, and the third well, respectively; the clock signal toggles between a low level voltage and a high level voltage at a constant period, and a magnitude of the output voltage is greater than a magnitude of the high level voltage. Effect of the Invention

[0009] Since the charge pump circuit of the present invention can generate a high negative voltage by increasing the number of pump units as the pump units are electrically isolated from each other, the image sensor can increase the potential of the gate of the transmission transistor or reset transistor by providing a high negative voltage to the gate of the transmission transistor or reset transistor, thereby increasing the full well capacitance (FWC) of the photoelectric conversion element or floating diffusion region of each of the multiple pixels. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image sensor including a charge pump circuit according to an embodiment of the present invention; [Diagram 2] 1 is a block diagram illustrating an example of a charge pump circuit according to an embodiment of the present invention; [Diagram 3] FIG. 3 is a circuit diagram for explaining the charge pump circuit of FIG. 2. [Figure 4] 4 is a graph for explaining the operation of the charge pump circuit of FIG. [Diagram 5] 4 is a cross-sectional view for explaining a first example of the charge pump circuit of FIG. 3. [Figure 6A] 4 is a cross-sectional view for explaining a second example of the charge pump circuit of FIG. 3. FIG. [Figure 6B] 4 is a cross-sectional view for explaining a third example of the charge pump circuit in FIG. [Figure 6C] 4 is a cross-sectional view for explaining a fourth example of the charge pump circuit in FIG. [Figure 7] 11 is a circuit diagram illustrating another example of a charge pump circuit according to an embodiment of the present invention. [Figure 8] 8 is a graph for explaining the operation of the charge pump circuit of FIG. 7. [Figure 9] FIG. 8 is a cross-sectional view for explaining the charge pump circuit of FIG. [Figure 10] FIG. 13 is a block diagram illustrating an example of a charge pump circuit according to another embodiment of the present invention. [Figure 11] FIG. 11 is a circuit diagram for explaining the charge pump circuit of FIG. [Figure 12A] 12 is a cross-sectional view for explaining a first example of the charge pump circuit of FIG. 11. FIG. [Figure 12B] 12 is a cross-sectional view for explaining a second example of the charge pump circuit of FIG. 11. FIG. [Figure 13] 1 is a plan view illustrating an active pixel sensor array of an image sensor according to an embodiment of the present invention; [Figure 14A] 14 is a cross-sectional view of the first example taken along line XX' in FIG. 13. [Figure 14B] FIG. 14 is a cross-sectional view of the second example taken along line XX′ in FIG. 13. [Figure 14C] FIG. 14 is a cross-sectional view of the third example taken along line XX′ in FIG. 13. [Figure 15A] 1 is a circuit diagram illustrating an active pixel sensor array of an image sensor according to an embodiment of the present invention; [Figure 15B] 15B is a diagram illustrating control signals applied to the active pixel sensor array shown in FIG. 15A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0012] Fig. 1 is a block diagram illustrating an image sensor 1 including a charge pump circuit 10 according to an embodiment of the present invention. Fig. 2 is a block diagram illustrating an example of the charge pump circuit 10 according to an embodiment of the present invention.

[0013] 1 and 2, the image sensor 1 includes a charge pump circuit 10, an active pixel sensor array 20, a row decoder 30, a row driver 40, a column decoder 50, a timing generator 60, a correlated double sampler (CDS) 70, an analog-digital converter (ADC) 80, and an input / output buffer 90.

[0014] The active pixel sensor array 20 includes a plurality of pixels PX (see FIG. 13) arranged, for example, two-dimensionally. The active pixel sensor array 20 converts optical signals into electrical signals. The active pixel sensor array 20 is driven by a plurality of drive signals, such as a pixel select signal, a reset signal, and a charge transfer signal, from a row driver 40. The electrical signals converted by the active pixel sensor array 20 are provided to the CDS 70.

[0015] The row driver 40 provides a plurality of driving signals to the active pixel sensor array 20 for driving a plurality of pixels according to the result of decoding by the row decoder 30. When the pixels included in the active pixel sensor array 20 are arranged in a matrix, a driving signal is provided for each row.

[0016] A timing generator 60 provides timing and control signals to the row decoder 30 and the column decoder 50. According to the present embodiment, the timing generator 60 provides a clock signal CLK to the charge pump circuit 10.

[0017] The CDS 70 receives, maintains, and samples the electrical signals generated by the active pixel sensor array 20. The CDS 70 double samples a specific noise level and a signal level based on the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0018] The ADC 80 converts the analog signal corresponding to the difference level output from the CDS 70 into a digital signal and outputs the digital signal. The input / output buffer 90 latches the digital signal, and outputs the latched signal sequentially according to the decoding result of the column decoder 50.

[0019] The charge pump circuit 10 receives a clock signal CLK to generate an output voltage VOUT, and outputs the output voltage VOUT to the active pixel sensor array 20. The clock signal CLK is a signal in which a low level voltage VL and a high level voltage VH are held for a certain period of time, and the low level voltage VL and the high level voltage VH are alternately displayed periodically. That is, the clock signal CLK toggles between the low level voltage VL and the high level voltage VH at a certain period. For example, the low level voltage VL is a ground voltage, and the high level voltage VH is a power supply voltage.

[0020] The output voltage VOUT is a negative voltage and has a constant magnitude. In one embodiment, the absolute value of the output voltage VOUT is greater than the absolute value of the high-level voltage VH, for example, the output voltage VOUT is greater than or equal to twice the magnitude of the high-level voltage VH. For example, the absolute value of the output voltage VOUT is n times the absolute value of the high-level voltage VH, for example, n times the power supply voltage.

[0021] The charge pump circuit 10 includes first to n-th pump units (100_1 to 100_n). The first to n-th pump units (100_1 to 100_n) are connected to each other in series, and the first to n-th pump units (100_1 to 100_n) generate negative voltages whose absolute values ​​gradually increase in sequence. Here, n is a natural number of 2 or more. In one embodiment, n may be a natural number of 3 or more.

[0022] The first pump unit 100_1 outputs a first node voltage VN1 having the same period as the clock signal CLK and toggling between a low level voltage lower than the low level voltage VL of the clock signal CLK and a high level voltage lower than the high level voltage VH of the clock signal CLK. For example, the first pump unit 100_1 outputs a first node voltage VN1 that periodically changes between a negative voltage having the same magnitude as the power supply voltage and a ground voltage.

[0023] The n-th pump unit 100_n receives the n-1th node voltage VNn-1 and outputs an output voltage VOUT, which is a negative voltage having an absolute value greater than that of the low level voltage of the n-1th node voltage VNn-1. At this time, the n-1th node voltage VNn-1 has the same period as the clock signal CLK and is a voltage that changes between a low level voltage lower than the low level voltage VL of the clock signal CLK and a high level voltage lower than the high level voltage VH of the clock signal CLK. For example, the n-1th node voltage VNn-1 changes periodically between a negative voltage having a magnitude (n-2) times the power supply voltage and a negative voltage having a magnitude (n-1) times the power supply voltage.

[0024] In one embodiment, the first pump unit 100_1 includes a capacitor and a transistor, and the nth pump unit 100_n includes a capacitor and a plurality of transistors. In one embodiment, a well in which the transistor of the first pump unit 100_1 is formed and a well in which the transistor of the nth pump unit 100_n is formed are electrically insulated from each other. In one embodiment, different wells in which the transistors included in the nth pump unit 100_n are formed are electrically insulated from each other.

[0025] In order to reduce the dark current of the image sensor 1, the output voltage VOUT is provided to the isolation layer of the active pixel sensor array 20. The charge pump circuit 10 according to the present invention includes first to n-th pump units 100_1 to 100_n, each of which generates a negative voltage having an absolute value that increases in sequence. Therefore, the image sensor 1 according to the present invention can apply a high voltage to the isolation layer of the active pixel sensor array 20, and dark current characteristics are improved. An embodiment in which the output voltage VOUT is provided to the isolation layer of the active pixel sensor array 20 will be described below with reference to Figures 14A to 14C.

[0026] The output voltage VOUT is provided to the gate of the transfer transistor of each of the pixels of the active pixel sensor array 20. The image sensor 1 according to the present invention can increase the potential of the gate of the transfer transistor by providing a high negative voltage to the gate of the transfer transistor, thereby increasing the full well capacitance (FWC) of the photoelectric conversion element of each of the pixels. Alternatively, the output voltage VOUT is provided to the gate of the reset transistor of each of the pixels of the active pixel sensor array 20. The image sensor 1 according to the present invention can increase the potential of the gate of the reset transistor by providing a high negative voltage to the gate of the reset transistor, thereby increasing the full well capacitance (saturation capacitance) of the floating diffusion region of each of the pixels. In the description of FIG. 15 and the like, an embodiment in which the output voltage VOUT is provided to the pixel PX of the active pixel sensor array 20 will be described later.

[0027] Fig. 3 is a circuit diagram for explaining the charge pump circuit 10 of Fig. 2. Fig. 4 is a graph for explaining the operation of the charge pump circuit 10 of Fig. 3.

[0028] 3, the charge pump circuit 10 includes an inverter INV and first to n-th pump units (100_1 to 100_n), where n is a natural number equal to or greater than 2. Each of the first to n-th pump units (100_1 to 100_n) includes a capacitor that accumulates charge and a transistor.

[0029] The inverter INV inverts the clock signal CLK to output the inverted clock signal CLKb. The ground voltage GND and the power supply voltage VDD are applied to the inverter INV as operating voltages. Although the charge pump circuit 10 includes the inverter INV in FIG. 3, the charge pump circuit 10 according to the present invention does not need to include the inverter INV. The clock signal CLK is a signal that periodically changes between the ground voltage GND and the power supply voltage VDD.

[0030] The first pump unit 100_1 includes a first capacitor C1 and a first P-type transistor PT1, a first terminal of the first capacitor C1 is connected to the inverter INV, and a second terminal of the first capacitor C1 is connected to a first node N1.

[0031] The drain of the first P-type transistor PT1 is connected to a first node N1, and a first source voltage VS1 is applied to the source of the first P-type transistor PT1, which may be, for example, a ground voltage GND.

[0032] A first body voltage VB1 is applied to the body of the first P-type transistor PT1. For example, the first body voltage VB1 is a power supply voltage VDD. A switch signal SW11 is provided to the gate of the first P-type transistor PT1 as a control signal.

[0033] The n-th pump unit 100_n includes an n-th capacitor Cn, an n-th P-type transistor PTn, and an N-type transistor NT. A first end of the n-th capacitor Cn is connected to the N-1-th node Nn-1, and a second end of the n-th capacitor Cn is connected to the n-th node Nn. For example, when n is 2, a first end of the n-th capacitor Cn is connected to the first node N1.

[0034] The drain of the n-th P-type transistor PTn is connected to the n-th node Nn, and the source of the n-th P-type transistor PTn is applied with the n-th source voltage VSn, which is a negative voltage having a magnitude (n-1) times the absolute value of the power supply voltage VDD.

[0035] An n-th body voltage VBn is applied to the body of the n-th P-type transistor PTn. For example, the n-th body voltage VBn is a negative voltage having a magnitude (n-2) times the absolute value of the power supply voltage VDD. A switch signal SWn1 is provided to the gate of the n-th P-type transistor PTn as a control signal.

[0036] The drain of the N-type transistor NT is connected to the n-th node Nn, and the body of the N-type transistor NT is connected to the n-th node Nn. A switch signal SWn2 is provided as a control signal to the gate of the N-type transistor NT. The N-type transistor NT is connected to the output terminal OP and outputs an output voltage VOUT in response to the switch signal SWn2.

[0037] 3 and 4, the clock inversion signal CLKb is a signal that periodically changes between a power supply voltage VDD and a ground voltage GND. For example, the clock inversion signal CLKb maintains the power supply voltage VDD from the reference time t0 to the first time t1, from the second time t2 to the third time t3, and from the fourth time t4 to the fifth time t5. The clock inversion signal CLKb maintains the ground voltage GND from the first time t1 to the second time t2, and from the third time t3 to the fourth time t4.

[0038] Here, the first to fifth times (t1, t2, t3, t4, t5) are times that arrive sequentially after the reference time t0. The difference between adjacent times in the time series is constant, but is not limited to this. For example, the time difference between the reference time t0 at which the clock inversion signal CLKb maintains the power supply voltage VDD and the first time t1 may be greater or smaller than the time difference between the first time t1 at which the clock inversion signal CLKb maintains the ground voltage GND and the second time t2.

[0039] According to the present embodiment, when the clock inversion signal CLKb is the power supply voltage VDD, the switch signal SW11 controlling the first P-type transistor PT1 is the first negative voltage -VDD, which is equal to the magnitude of the power supply voltage VDD. The first P-type transistor PT1 is turned on in response to the switch signal SW11, and the first node voltage VN1 of the first node N1 becomes substantially equal to the ground voltage GND, which is the first source voltage VS1. Thus, the potential difference between the first terminal and the second terminal of the first capacitor C1 is substantially equal to the power supply voltage VDD.

[0040] According to this embodiment, when the clock inversion signal CLKb is the ground voltage GND, the switch signal SW11 controlling the first P-type transistor PT1 is the ground voltage GND. The first P-type transistor PT1 is turned off in response to the switch signal SW11. Since the voltage across the first capacitor C1 changes continuously, the potential difference between the first terminal and the second terminal of the first capacitor C1 maintains the power supply voltage VDD. Thus, the first node voltage VN1 is a first negative voltage -VDD, which is the same as the magnitude of the power supply voltage VDD.

[0041] Therefore, the first pump unit 100_1 receives the clock inversion signal CLKb that periodically changes between the power supply voltage VDD and the ground voltage GND, and outputs the first node voltage VN1 that periodically changes between the ground voltage GND and the first negative voltage -VDD. For example, each of the first to n-th pump units (100_1 to 100_n) outputs a voltage that is reduced by the magnitude of the power supply voltage VDD from the received voltage. The n-1-th node voltage VNn-1 of the n-1-th node Nn-1 is a voltage that periodically changes between the (n-2)-th negative voltage -(n-2)·VDD having a magnitude (n-2) times the power supply voltage VDD and the (n-1)-th negative voltage -(n-1)·VDD having a magnitude (n-1) times the power supply voltage VDD. However, when n is 2, the (n-2)-th negative voltage -(n-2)·VDD is a ground voltage GND that is not a negative voltage, and when n is 3 or more, the (n-2)-th negative voltage -(n-2)·VDD is a negative voltage.

[0042] According to this embodiment, when the clock inversion signal CLKb is the power supply voltage VDD, the switch signal SWn1 controlling the nth P-type transistor PTn is the nth negative voltage -n·VDD having a magnitude n times the power supply voltage VDD. The nth P-type transistor PTn is turned on in response to the switch signal SWn1, and the nth node voltage VNn of the nth node Nn becomes substantially equal to the (n-1)th negative voltage -(n-1)·VDD, which is the nth source voltage VSn. As a result, the potential difference between the first terminal and the second terminal of the nth capacitor Cn is substantially equal to the power supply voltage VDD.

[0043] The switch signal SWn2 controlling the N-type transistor NT is substantially the same as the switch signal SWn1 controlling the nth P-type transistor PTn. Therefore, when the inverted clock signal CLKb is the power supply voltage VDD, the switch signal SWn2 controlling the N-type transistor NT is the nth negative voltage -n·VDD, the N-type transistor NT is turned off, and the nth node Nn is not connected to the output terminal OP.

[0044] According to this embodiment, when the clock inversion signal CLKb is the ground voltage GND, the switch signal SWn1 controlling the nth P-type transistor PTn is the (n-1)th negative voltage -(n-1)·VDD, which has a magnitude (n-1) times the power supply voltage VDD. The nth P-type transistor PTn is turned off in response to the switch signal SWn1. Since the voltage across the nth capacitor Cn changes continuously, the potential difference between the first terminal and the second terminal of the nth capacitor Cn maintains the power supply voltage VDD. As a result, the nth node voltage VNn is the nth negative voltage -n·VDD.

[0045] When the clock inversion signal CLKb is the ground voltage GND, the switch signal SWn2 controlling the N-type transistor NT is the (n-1)th negative voltage -(n-1)·VDD. The N-type transistor NT is turned on, and the n-th node voltage VNn is output as the output voltage VOUT from the output terminal OP of the n-th pump unit 100_n. In one embodiment, a capacitor is further connected to the output terminal OP, so that even if the N-type transistor NT is turned off, the output voltage VOUT becomes the n-th negative voltage -n·VDD.

[0046] The configuration of the charge pump circuit 10 shown in FIG. 3 is merely exemplary, and the charge pump circuit 10 according to the present invention is not limited thereto, and the charge pump circuit 10 that accumulates charges and outputs a high voltage can be embodied in various ways. Also, in FIG. 3, only the circuits in which the first to n-th pump units (100_1 to 100_n) generate the output voltage VOUT using the clock inversion signal CLKb are described, but the charge pump circuit 10 according to the present invention is not limited to the above-mentioned circuit. For example, the charge pump circuit 10 further includes a complementary circuit connected to the output terminal OP, which generates an output voltage VOUT of the n-th negative voltage -n·VDD using a signal obtained by re-inverting the clock inversion signal CLKb when the clock inversion signal CLKb is the power supply voltage VDD. The complementary circuit will be described later with reference to FIG. 7, etc.

[0047] In the charge pump circuit 10 according to the present invention, the first to n-th pump units (100_1 to 100_n) are formed to be electrically insulated from one another, thereby increasing the number of pump units included in the charge pump circuit 10. Therefore, the magnitude of the output voltage VOUT increases in proportion to the number of pump units, and the charge pump circuit 10 can generate a high negative voltage.

[0048] Fig. 5 is a cross-sectional view for explaining a first example of the charge pump circuit 10 of Fig. 3. Fig. 5 is a diagram showing the charge pump circuit 10 shown in Fig. 3 with the inverter INV removed.

[0049] 5, the charge pump circuit 10 includes a substrate SUB, an epilayer P-EPI formed in the substrate SUB, and wells (NW1, NW2, PW) formed in the epilayer P-EPI. The wells (NW, PW) include an N-well doped with N-type impurities and a P-well doped with P-type impurities. For example, the first well NW1 and the second well NW2 are N-wells, and the third well PW is a P-well.

[0050] In one embodiment, the substrate SUB may be, but is not limited to, a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon germanium substrate, etc. In one embodiment, the substrate SUB comprises at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0051] According to one embodiment, the substrate SUB is a doped semiconductor layer. According to one embodiment, the substrate SUB is doped with P-type impurities, but is not limited thereto.

[0052] The substrate SUB includes a first surface 100f and a second surface 100b facing each other. The first surface 100f of the substrate SUB is a front surface of the substrate SUB, and the second surface 100b of the substrate SUB is a back surface of the substrate SUB.

[0053] According to one embodiment, the epilayer P-EPI is a semiconductor material layer formed by selective epitaxial growth. According to one embodiment, the epilayer P-EPI is doped with P-type impurities, such that the epilayer P-EPI is doped at a higher concentration than the substrate SUB, but is not limited thereto. In one embodiment, the epilayer P-EPI is omitted. Thereby, the wells (NW1, NW2, PW) are formed in the substrate SUB, and the substrate SUB is doped with a high concentration of P-type impurities.

[0054] A first P-type transistor PT1 is formed in the first well NW1. The first P-type region 103, the second P-type region 105, and the N-type region 101 formed in the first well NW1, as well as the gate insulating layer 107 and the gate electrode 109 formed on the first well NW1, constitute the first P-type transistor PT1. The gate insulating layer 107 is formed between the first well NW1 and the gate electrode 109.

[0055] The first P-type region 103 and the second P-type region 105 formed in the first well NW1 constitute different electrodes of the first P-type transistor PT1, and are respectively a source and a drain. For example, a first source voltage VS1 is applied to the first P-type region 103, and a first node voltage VN1 is applied to the second P-type region 105 connected to a first node N1. A switch signal SW11 is applied to the gate electrode 109.

[0056] An N-type region 101 formed in the first well NW1 is a contact region for applying a voltage to the body of the first P-type transistor PT1. For example, a first body voltage VB1 is applied to the first well NW1 via the N-type region 101.

[0057] An nP-type transistor PTn is formed in the second well NW2. The first P-type region 103n, the second P-type region 105n, and the N-type region 101n formed in the second well NW2, and the gate insulating layer 107n and the gate electrode 109n formed on the second well NW2 constitute the nP-type transistor PTn. The gate insulating layer 107n is formed between the second well NW2 and the gate electrode 109n.

[0058] The first P-type region 103n and the second P-type region 105n formed in the second well NW2 constitute different electrodes of the n-th P-type transistor PTn, and are respectively a source and a drain. For example, the first P-type region 103n is applied with an n-th source voltage VSn, and the second P-type region 105n is connected to the n-th node Nn and is applied with an n-th node voltage VNn. A switch signal SWn1 is applied to the gate electrode 109n.

[0059] The N-type region 101n formed in the second well NW2 is a contact region for applying a voltage to the body of the n-th P-type transistor PTn. For example, an n-th body voltage VBn is applied to the second well NW2 via the N-type region 101n.

[0060] An N-type transistor NT is formed in the third well PW. The first N-type region 113n, the second N-type region 115n, and the P-type region 111n formed in the third well PW, and the gate insulating layer 117n and the gate electrode 119n formed on the third well PW constitute the N-type transistor NT. The gate insulating layer 117n is formed between the third well PW and the gate electrode 119n.

[0061] The first N-type region 113n and the second N-type region 115n formed in the third well PW constitute different electrodes of the N-type transistor NT, and are respectively the source and drain. The first N-type region 113n is connected to the n-th node Nn, and the n-th node voltage VNn is applied to the first N-type region 113n. The second N-type region 115n is connected to the output terminal OP. A switch signal SWn2 is applied to the gate electrode 119n.

[0062] The P-type region 111n formed in the third well PW is a contact region for applying a voltage to the body of the N-type transistor NT. For example, the third well PW is connected to the n-th node Nn through the P-type region 111n, and the n-th node voltage VNn is applied to the third well PW.

[0063] In one embodiment, the P-type regions (103, 105, 103n, 105n, 111n) are regions heavily doped with P-type impurities and the N-type regions (101, 101n, 113n) are regions heavily doped with N-type impurities.

[0064] According to one embodiment, the first to n-th capacitors (C1 to Cn) are formed at the same level as a wiring layer formed by a BEOL (back end of line) and / or a FEOL (front end of line) process. According to one embodiment, the first to n-th capacitors (C1 to Cn) are formed by a BEOL and / or a FEOL process.

[0065] An isolation layer 120 is formed between the first well NW1, the second well NW2, and the third well PW to which different voltages are applied. The isolation layer 120 is formed to surround the first well NW1, the second well NW2, and the third well PW. In one embodiment, the isolation layer 120 includes an insulating material, for example, but is not limited to, silicon oxide, and the insulating material constituting the isolation layer 120 can be variously modified.

[0066] In one embodiment, the element isolation film 120 extends from the first surface 100f of the substrate SUB to the second surface 100b of the substrate SUB. In this embodiment, the element isolation film 120 has a narrower cross-sectional width as it is farther from the first surface 100f of the substrate SUB and closer to the second surface 100 of the substrate SUB. For example, the element isolation film 120 has a first width FW of a surface in contact with the first surface 100f that is wider than a second width BW of a surface in contact with the second surface 100b. In one embodiment, the element isolation film 120 is formed by vertically etching a portion of the substrate SUB from the first surface 100f of the substrate SUB and then filling it with an insulating material.

[0067] In the charge pump circuit according to the present invention, a plurality of transistors, each having a body to which a different voltage is applied, are formed in a different well, and the different wells are separated by an isolation film 120. The isolation film 120 prevents a junction breakdown caused by a voltage difference applied to the different wells. For example, a junction breakdown between the second well NW2 and the third well PW caused by a difference between an n-th body voltage VBn and an n-th node voltage VNn applied to the second well NW2 and the third well PW, respectively, is prevented. Therefore, the number of pump units connected in series included in the charge pump circuit is increased, and the charge pump circuit can generate a high negative voltage.

[0068] Figures 6A to 6C are cross-sectional views for explaining second to fourth examples of the charge pump circuit 10 of Figure 3. Figures 6A to 6C are drawings showing the charge pump circuit 10 shown in Figure 3 with the inverter INV removed. In the explanation of Figures 6A to 6C, duplicated explanations will be omitted for the same reference numerals as in Figure 5.

[0069] 6A, an isolation layer 120B is formed between the first well NW1, the second well NW2, and the third well PW. The isolation layer 120B is formed to surround the first well NW1, the second well NW2, and the third well PW. In one embodiment, the isolation layer 120B includes an insulating material.

[0070] In this embodiment, the element isolation film 120B has a wider cross-sectional width as it is farther from the first surface 100f of the substrate SUB and closer to the second surface 100b of the substrate SUB. For example, the element isolation film 120B has a first width FWB of a surface in contact with the first surface 100f that is narrower than a second width BWB of a surface in contact with the second surface 100b. In one embodiment, the element isolation film 120B is formed by vertically etching a portion of the substrate SUB from the second surface 100b of the substrate SUB and then filling the substrate with an insulating material.

[0071] 6B, an isolation layer 120R is formed between the first well NW1, the second well NW2, and the third well PW. The isolation layer 120R is formed to surround the first well NW1, the second well NW2, and the third well PW. In one embodiment, the isolation layer 120R includes an insulating material.

[0072] In this embodiment, the element isolation film 120R has a narrower cross-sectional width from the first surface 100f and the second surface 100b of the substrate SUB toward the center. For example, the element isolation film 120R has a first width FWF of a surface in contact with the first surface 100f that is wider than a third width MW of the central cross-section of the element isolation film 120R, and a second width BWF of a surface in contact with the second surface 100b that is wider than the third width MW. In one embodiment, the element isolation film 120R is formed by vertically etching a part of the substrate SUB from the first surface 100f of the substrate SUB, vertically etching a part of the substrate SUB from the second surface 100b again, and then filling with an insulating material. Alternatively, in another embodiment, the element isolation film 120R can be formed by vertically etching a part of the substrate SUB from the second surface 100b of the substrate SUB, vertically etching a part of the substrate SUB from the first surface 100f again, and then filling with an insulating material.

[0073] 6C, the substrate N_SUB is doped with N-type impurities. In one embodiment, the epi layer P-EPI is omitted. Thereby, wells (NW1, NW2, PW) are formed in the substrate N_SUB.

[0074] Fig. 7 is a circuit diagram for explaining another example of the charge pump circuit 10 according to an embodiment of the present invention. Fig. 8 is a graph for explaining the operation of the charge pump circuit 10 of Fig. 7. In the explanation of Fig. 7 and Fig. 8, the same reference numerals as Fig. 3 and Fig. 4 will not be explained repeatedly.

[0075] Referring to FIG. 7, the nth pump unit 100_n' of the charge pump circuit 10 includes an nth capacitor Cn, an nth P-type transistor PTn, and an N-type transistor NT', and further includes a capacitor Cnb, a first transistor PTnb which is a P-type transistor, and second to fourth transistors (NTb, NTnab, NTna) which are N-type transistors.

[0076] The drain of the N-type transistor NT' is connected to the n-th node Nn, and the body of the N-type transistor NT' is connected to the n-th node Nn via the fourth transistor NTna. For example, the body of the N-type transistor NT' is connected to the second body node NB2n, and the first electrode of the fourth transistor NTna is connected to the n-th node Nn, and the second electrode of the fourth transistor NTna is connected to the second body node NB2n. A switch signal SWn2 input to the gate of the N-type transistor NT' is provided as a control signal to the gate of the fourth transistor NTna, and the fourth transistor NTna electrically connects the n-th node Nn and the second body node NB2n in response to the switch signal SWn2.

[0077] The n-th pump unit 100_n' shown in Fig. 7 further includes a complementary circuit compared to the n-th pump unit 100_n shown in Fig. 3. The complementary circuit includes a capacitor Cnb, a first transistor PTnb, a second transistor NTb, and a third transistor NTnab.

[0078] A complementary voltage VNn-1b of the n-1th node voltage VNn-1 is input to one end of the capacitor Cnb of the complementary circuit. The other end of the capacitor Cnb of the complementary circuit is connected to the subnode Nnb. In this embodiment, the gate of the N-type transistor NT' and the gate of the fourth transistor NTna are connected to the subnode Nnb. Therefore, the switch signal SWn2 applied to the gate of the N-type transistor NT' is the subnode voltage VNnb of the subnode Nnb.

[0079] The drain of the first transistor PTnb of the complementary circuit is connected to the subnode Nnb, and the n-th source voltage VSn is applied to the source of the first transistor PTnb, for example, the n-th source voltage VSn is a negative voltage having a magnitude (n-1) times the absolute value of the power supply voltage VDD.

[0080] An n-th body voltage VBn is applied to the body of the first transistor PTnb of the complementary circuit. For example, the n-th body voltage VBn is a negative voltage having a magnitude that is (n-2) times the absolute value of the power supply voltage VDD. That is, the same voltage is applied to the body of the first transistor PTnb of the complementary circuit and the body of the n-th P-type transistor PTn, and in one embodiment, the body of the first transistor PTnb of the complementary circuit and the body of the n-th P-type transistor PTn are connected to a first body node NB1n.

[0081] A switch signal SWn1b is provided to the gate of the first transistor PTnb of the complementary circuit as a control signal. The switch signal SWn1b applied to the gate of the first transistor PTnb of the complementary circuit is complementary to the switch signal SWn1 applied to the gate of the n-th P-type transistor PTn.

[0082] The source of the second transistor NTb of the complementary circuit is connected to the output terminal OP and outputs an output voltage VOUT in response to a switch signal SWn2b. The gate of the second transistor NTb is connected to the n-th node Nn, and the switch signal SWn2b input to the gate of the second transistor NTb is the n-th node voltage VNn.

[0083] The drain of the second transistor NTb is connected to the subnode Nnb, and the body of the second transistor NTb is connected to the subnode Nnb via the third transistor NTnab.

[0084] For example, the body of the third transistor NTnab is connected to the second body node NB2n, the first electrode of the third transistor NTnab is connected to the sub-node Nnb, and the second electrode of the third transistor NTnab is connected to the second body node NB2n. A switch signal SWn2b is provided to the gate of the third transistor NTnab as a control signal, and the sub-node Nnb and the second body node NB2n are electrically connected in response to the switch signal SWn2b.

[0085] 7 and 8, the complementary voltage VNn-1b of the n-1th node voltage VNn-1 is a voltage that periodically changes between the (n-2)th negative voltage -(n-2)·VDD, which has a magnitude (n-2) times the power supply voltage VDD, and the (n-1)th negative voltage -(n-1)·VDD, which has a magnitude (n-1) times the power supply voltage VDD.

[0086] The switch signal SWn1b input to the gate of the first transistor PTnb and the switch signal SWn2b input to the gate of the second transistor NTb of the complementary circuit are equal to the n-th node voltage VNn. The switch signals (SWn1b, SWn2b) are complementary to the switch signal SWn2 that controls the N-type transistor NT′ and the switch signal SWn1 that controls the n-type P-type transistor PTn.

[0087] The subnode voltage VNnb of the subnode Nnb is the same as the switch signal SWn2 that controls the N-type transistor NT' and the switch signal SWn1 that controls the nP-type transistor PTn. The capacitor Cnb of the complementary circuit receives the complementary voltage VNn-1b of the n-1th node voltage VNn-1, and the first transistor PTnb of the complementary circuit is controlled by the switch signal SWn1b complementary to the switch signal SWn1 of the nP-type transistor PTn, so that the subnode voltage VNnb of the subnode Nnb is complementary to the nth node voltage VNn.

[0088] According to this embodiment, when the inverted clock signal CLKb is the power supply voltage VDD, the switch signal SWn2b input to the gate of the second transistor NTb is the (n-1)th negative voltage -(n-1)·VDD, and the second transistor NTb is turned on. The n-th node Nn is connected to the output terminal OP, and the subnode voltage VNnb is output as the output voltage VOUT from the output terminal OP of the n-th pump unit 100_n'.

[0089] On the other hand, when the clock inversion signal CLKb is the ground voltage GND, the switch signal SWn2 controlling the N-type transistor NT' is the (n-1)th negative voltage -(n-1)·VDD. The N-type transistor NT' is turned on, and the n-th node voltage VNn is output from the output terminal OP of the n-th pump unit 100_n' as the output voltage VOUT. Therefore, when the clock inversion signal CLKb is the ground voltage GND or the power supply voltage VDD, the output voltage VOUT output from the output terminal OP is stably maintained at a constant value of n times the power supply voltage.

[0090] Fig. 9 is a cross-sectional view for explaining the charge pump circuit 10 of Fig. 7. Fig. 9 is a diagram showing the n-th pump unit shown in Fig. 7.

[0091] 9, the charge pump circuit includes a substrate SUB, an epilayer P-EPI formed in the substrate SUB, and a well (NW, PW) formed in the epilayer P-EPI. The well (NW, PW) includes an N-well NW doped with an N-type impurity and a P-well PW doped with a P-type impurity.

[0092] In the N-well NW, an nP-type transistor PTn and a first transistor PTnb of a complementary circuit are formed. A first P-type region 103n, a second P-type region 105n, and an N-type region 101n formed in the N-well NW, and a first gate insulating layer 107n and a first gate electrode 109n formed on the N-well NW constitute the nP-type transistor PTn. A third P-type region 103nb, a fourth P-type region 105nb, and an N-type region 101n formed in the N-well NW, and a second gate insulating layer 107nb and a second gate electrode 109nb formed on the N-well NW constitute the first transistor PTnb of the complementary circuit.

[0093] The first P-type region 103n and the second P-type region 105n formed in the N-well NW constitute different electrodes of the nP-type transistor PTn, and are respectively the source / drain. The third P-type region 103nb and the fourth P-type region 105nb formed in the N-well NW constitute different electrodes of the first transistor PTnb of the complementary circuit, and are respectively the source / drain.

[0094] An N-type region 101n formed in the N-well NW is a contact region for applying a voltage to the bodies of the n-th P-type transistor PTn and the first transistor PTnb. For example, an n-th body voltage VBn is applied to the N-well NW via the N-type region 101n.

[0095] In the P well PW, N-type transistors (NT', NTb, NTna, NTnab) are formed. The first N-type region 113n, the second N-type region 115n, and the P-type region 111n formed in the P well PW, and the first gate insulating layer 117n and the first gate electrode 119n formed on the P well PW constitute the N-type transistor NT'. The first N-type region 113n and the second N-type region 115n formed in the P well PW constitute different electrodes of the N-type transistor NT', and are the source / drain, respectively.

[0096] The third N-type region 113nb, the fourth N-type region 115nb, and the P-type region 111n formed in the P-well PW, and the second gate insulating layer 117nb and the second gate electrode 119nb formed on the P-well PW constitute a second transistor NTb of a complementary circuit. The third N-type region 113nb and the fourth N-type region 115b formed in the P-well PW constitute different electrodes of the second transistor NTb, and are the source / drain, respectively.

[0097] The fifth N-type region 123nb, the sixth N-type region 125nb, and the P-type region 111n formed in the P-well PW, and the third gate insulating layer 127nb and the third gate electrode 129nb formed on the P-well PW constitute a third transistor NTnab of a complementary circuit. The fifth N-type region 123nb and the sixth N-type region 125nb formed in the P-well PW constitute different electrodes of the third transistor NTnab, and are the source / drain, respectively.

[0098] The seventh N-type region 123n, the eighth N-type region 125n, and the P-type region 111n formed in the P-well PW, and the fourth gate insulating layer 127n and the fourth gate electrode 129n formed on the P-well PW constitute a fourth transistor NTna. The seventh N-type region 123n and the eighth N-type region 125n formed in the P-well PW constitute different electrodes of the fourth transistor NTna, and are the source / drain, respectively.

[0099] The charge pump circuit according to the present invention includes wells (NW, PW) formed in a substrate SUB in which a plurality of transistors are formed. At this time, an isolation layer 120 is formed to surround each of the wells (NW, PW) to which different voltages are applied. Therefore, the isolation layer 120 prevents junction breakdown caused by a voltage difference applied to the different wells (NW, PW) and allows the number of pump units connected in series to be increased in the charge pump circuit.

[0100] Fig. 10 is a block diagram for explaining an example of a charge pump circuit 10A according to another embodiment of the present invention. Fig. 11 is a circuit diagram for explaining the charge pump circuit 10A of Fig. 10. In the explanation of Fig. 10 and Fig. 11, the same reference numerals as Fig. 2 and Fig. 3 will not be explained repeatedly.

[0101] 10 and 11, the charge pump circuit 10A receives a clock signal CLK to generate first to n-th output voltages (VOUT_1 to VOUT_n), and outputs the first to n-th output voltages (VOUT_1 to VOUT_n) to, for example, the active pixel sensor array 20 (FIG. 1), where n is a natural number equal to or greater than 2, and in one embodiment, n may be a natural number equal to or greater than 3.

[0102] The charge pump circuit 10A includes an inverter INV and first to n-th pump units (100_1A to 100_nA). The first to n-th pump units (100_1A to 100_nA) are connected to each other in series, and the first to n-th pump units (100_1A to 100_nA) output corresponding output voltages, respectively. For example, the first pump unit 100_1A outputs a first output voltage VOUT_1 from a first output terminal OP1, and the n-th pump unit 100_nA outputs an n-th output voltage VOUT_n from an n-th output terminal OPn. The first to n-th pump units (100_1A to 100_nA) respectively generate negative output voltages whose absolute values ​​gradually increase in sequence.

[0103] In one embodiment, the absolute value of the n-th output voltage VOUT_n is greater than the absolute value of the high-level voltage VH. For example, the absolute value of the n-th output voltage VOUT_n is n times the absolute value of the high-level voltage VH.

[0104] Each of the first to n-th pump units (100_1A to 100_nA) includes a capacitor for storing electric charge, a P-type transistor, and an N-type transistor. However, the charge pump circuit 10A according to the present invention is not limited thereto, and at least one of the first to n-th pump units (100_1A to 100_nA) may not include one of an N-type transistor and a P-type transistor.

[0105] The first pump unit 100_1A includes a first capacitor C1, a first P-type transistor PT1, and a first N-type transistor NT1. The drain of the first N-type transistor NT1 is connected to a first node N1, and the body of the first N-type transistor NT1 is connected to the first node N1. A switch signal SW12 is provided as a control signal to the gate of the first N-type transistor NT1. The first N-type transistor NT1 is connected to a first output terminal OP1, and outputs a first output voltage VOUT_1 in response to the switch signal SW12.

[0106] The nth pump unit 100_nA includes an nth capacitor Cn, an nth P-type transistor PTn, and an nth N-type transistor NTn. The drain of the nth N-type transistor NTn is connected to the nth node Nn, and the body of the nth N-type transistor NTn is connected to the nth node Nn. A switch signal SWn2 is provided as a control signal to the gate of the nth N-type transistor NTn. The nth N-type transistor NTn is connected to the nth output terminal OPn, and outputs the nth output voltage VOUTn in response to the switch signal SWn2.

[0107] Figures 12A and 12B are cross-sectional views for explaining a first example and a second example of the charge pump circuit 10A of Figure 11. Figures 12A and 12B are diagrams showing the charge pump circuit 10A shown in Figure 11 without the inverter INV. In the explanation of Figures 12A and 12B, the same reference numerals as in Figure 5 will not be explained repeatedly.

[0108] 12A, the charge pump circuit includes a substrate SUB, an epilayer P-EPI formed in the substrate SUB, and wells (NW1, PW1, NW2, PW2) formed in the epilayer P-EPI. The wells (NW1, PW1, NW2, PW2) include a first well NW1 and a second well NW2 doped with N-type impurities, and a third well PW1 and a fourth well PW2 doped with P-type impurities.

[0109] A first N-type transistor NT1 is formed in the third well PW1. The first N-type region 113, the second N-type region 115, and the P-type region 111 formed in the third well PW1, as well as the gate insulating layer 117 and the gate electrode 119 formed on the third well PW1, constitute the first N-type transistor NT1. The gate insulating layer 117 is formed between the third well PW1 and the gate electrode 119.

[0110] The first N-type region 113 and the second N-type region 115 formed in the third well PW1 constitute different electrodes of the first N-type transistor NT1, and are the source / drain, respectively. The first N-type region 113 is connected to the first node N1, and a first node voltage VN1 is applied to the first N-type region 113. The second N-type region 115 is connected to the first output terminal OP1. A switch signal SWn12 is applied to the gate electrode 119.

[0111] A P-type region 111 formed in the third well PW1 is a contact region for applying a voltage to the body of the first N-type transistor NT1. For example, the third well PW1 is connected to the first node N1 through the P-type region 111, and a first node voltage VN1 is applied to the third well PW1.

[0112] An n-th N-type transistor NTn is formed in the fourth well PW2. The first N-type region 113n, the second N-type region 115n, and the P-type region 111n formed in the fourth well PW2, and the gate insulating layer 117n and the gate electrode 119n formed on the fourth well PW2 constitute the n-th N-type transistor NTn. The gate insulating layer 117n is formed between the fourth well PW2 and the gate electrode 119n.

[0113] The first N-type region 113n and the second N-type region 115n formed in the fourth well PW2 constitute different electrodes of the n-th N-type transistor NTn, and are the source / drain, respectively. The first N-type region 113n is connected to the n-th node Nn, and the n-th node voltage VNn is applied to the first N-type region 113n. The second N-type region 115n is connected to the n-th output terminal OPn. A switch signal SWn2 is applied to the gate electrode 119n.

[0114] The P-type region 111n formed in the fourth well PW2 is a contact region for applying a voltage to the body of the n-th N-type transistor NTn. For example, the fourth well PW2 is connected to the n-th node Nn through the P-type region 111n, and the n-th node voltage VNn is applied to the fourth well PW2.

[0115] An isolation film 120 is formed between each of the first well NW1, the second well NW2, the third well PW1, and the fourth well PW2 to which different voltages are applied. The isolation film 120 is formed to surround each of the first well NW1, the second well NW2, the third well PW1, and the fourth well PW2.

[0116] 12B, a third well PW1' in which a first N-type transistor NT1 included in the first pump unit is formed is formed inside a first well NW1' in which a first P-type transistor PT1 included in the first pump unit is formed. A voltage having a relatively small magnitude is applied to the first pump unit of the charge pump circuit according to the present invention, compared to the n-th pump unit. As a result, the first pump unit is less likely to experience junction breakdown compared to the n-th pump unit. Therefore, by forming the third well PW1' inside the first well NW1' without forming an isolation film 120' between the first well NW1' and the third well PW1', the area occupied by the charge pump circuit can be reduced.

[0117] 12B, the first well NW1' may be formed inside the third well PW1'. Also, when n is 3 or more, the N well in which the second P-type transistor included in the second pump unit is formed and the P well in which the second N-type transistor is formed may not be insulated by the device isolation film 120'. That is, the P well may be formed inside the N well in which the second pump unit is formed.

[0118] 13 is a plan view illustrating an active pixel sensor array 20 of an image sensor according to an embodiment of the present invention, and FIGS. 14A to 14C are cross-sectional views of first to third examples taken along line XX′ in FIG.

[0119] 13 and 14A, the active pixel sensor array 20 includes a plurality of pixels PX. The plurality of pixels PX are arranged in a matrix. A device isolation film DTI is formed to surround each of the plurality of pixels PX and isolate each of the plurality of pixels PX. That is, each of the plurality of pixels PX is defined by the device isolation film DTI.

[0120] In this embodiment, the device isolation layer DTI includes a first device isolation layer 220_1 and a second device isolation layer 220_2. The first device isolation layer 220_1 includes a material having excellent gap filling performance, such as polysilicon. In one embodiment, the first device isolation layer 220_1 is doped with a P-type impurity, such as boron (B), but is not limited thereto. In one embodiment, the first device isolation layer 220_1 has the same length in the vertical direction to separate each of the plurality of pixels PX.

[0121] The second isolation layer 220_2 includes an insulating material, and in one embodiment, the second isolation layer 220_2 includes, but is not limited to, a material having a high dielectric constant.

[0122] In this embodiment, the element isolation film DTI has a narrower cross-sectional width as it is farther from the first surface 200f and closer to the second surface 200b. For example, the element isolation film DTI has a first width at a surface in contact with the first surface 200f that is wider than a second width at a surface in contact with the second surface 200b. In one embodiment, the element isolation film DTI is formed by vertically etching a part of the photodiode region PDR from the first surface 200f, and then filling the material constituting the second element isolation film 220_2 and the material constituting the first element isolation film 220_1.

[0123] According to an embodiment, an output voltage VOUT (FIG. 1) is applied to the first isolation film 220_1 through the contact via 223. The output voltage VOUT applied to the first isolation film 220_1 may be, for example, the output voltage VOUT described in FIGS. 2 to 9, or may be one selected from the first to n-th output voltages (VOUT_1 to VOUT_n) described in FIGS. 10 and 11. Referring to FIG. 14A, the contact via 223 for applying the output voltage VOUT is disposed adjacent to the first surface 200f, but the present invention is not limited thereto. For example, the contact via 223 may be disposed adjacent to the second surface 200b, or may be disposed adjacent to each of the first surface 200f and the second surface 200b.

[0124] A photodiode is formed in the photodiode region PDR. According to an embodiment, a voltage lower than that of the photodiode region PDR is applied to the first device isolation layer 220_1, thereby increasing an energy barrier between the first device isolation layer 220_1 and the photodiode region PDR and reducing dark current, thereby improving reliability of the image sensor.

[0125] The interlayer insulating film 211 and the front wiring 213 are disposed on the first surface 200f. The front wiring 213 is covered by the interlayer insulating film 211 and is protected and insulated by the interlayer insulating film 211.

[0126] The interlayer insulating film 211 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. The front wiring 213 includes, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), etc.

[0127] The front wiring 213 includes a plurality of wires stacked in sequence. In Fig. 14A, the front wiring 213 is shown to include three layers stacked in sequence, but is not limited thereto.

[0128] The insulating film 221 is disposed between the first surface 200f and the interlayer insulating film 211. The insulating film 221 covers and protects the contact vias 223. In one embodiment, the insulating film 221 includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0129] A color filter CF is disposed on the photodiode region PDR, and a microlens ML is disposed on the color filter CF. The microlens ML is made of an organic material such as a photosensitive resin or an inorganic material. The microlens ML focuses incident light onto the pixel PX.

[0130] 14B, the device isolation film DTI' includes a first device isolation film 220_1' and a second device isolation film 220_2'. In this embodiment, the device isolation film DTI' has a wider cross-sectional width as it is farther from the first surface 200f and closer to the second surface 200b. For example, the device isolation film DTI' has a first width at a surface in contact with the first surface 200f narrower than a second width at a surface in contact with the second surface 200b. In one embodiment, the device isolation film DTI' is formed by vertically etching a portion of the photodiode region PDR from the second surface 200b and then filling it with a material.

[0131] 14B, the element isolation film DTI′ does not have to be in contact with the first surface 200f. In this case, the contact via 223 is formed in contact with the second surface 200b to provide the output voltage VOUT to the element isolation film DTI′.

[0132] Referring to FIG. 14C, the element isolation film DTI″ includes a first element isolation film 220_1″ and a second element isolation film 220_2″. In this embodiment, the element isolation film DTI″ has a cross-sectional width that narrows from the first surface 200f and the second surface 200b toward the center. For example, the element isolation film DTI″ has a first width at a surface in contact with the first surface 200f that is wider than a third width of the central cross section of the element isolation film DTI″, and a second width at a surface in contact with the second surface 200b that is wider than the third width. In one embodiment, the element isolation film DTI″ is formed by vertically etching a portion of the photodiode region PDR from the first surface 200f, then vertically etching a portion of the photodiode region PDR from the second surface 200b again, and then filling with material. Alternatively, in one embodiment, the element isolation film DTI″ can be formed by vertically etching a portion of the photodiode region PDR from the second surface 200b, then vertically etching a portion of the photodiode region PDR from the first surface 200f again, and then filling with material.

[0133] Fig. 15A is a circuit diagram illustrating an active pixel sensor array 20 of an image sensor according to an embodiment of the present invention, and Fig. 15B is a diagram illustrating control signals applied to the active pixel sensor array 20 shown in Fig. 15A.

[0134] 15A, the active pixel sensor array 20 includes a plurality of pixels PX, which are arranged in a matrix. According to one embodiment, each of the pixels PX includes a transmission transistor TX and logic transistors (RX, SX, DX), where the logic transistors include a reset transistor RX, a selection transistor SX, and a drive transistor DX.

[0135] The photoelectric conversion element PD generates and accumulates photoelectric charges in proportion to the amount of light incident from the outside. The photoelectric conversion element PD may be any one of a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0136] In response to a charge transfer signal TG, the transfer transistor TX transfers the charge accumulated in the photoelectric conversion element PD to the floating diffusion region FD, and the photocharge generated in the photoelectric conversion element PD is stored in the floating diffusion region FD. The drive transistor DX is controlled by the amount of photocharge accumulated in the floating diffusion region FD.

[0137] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD in response to a reset signal RG. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode is connected to a power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX is transferred to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged and the floating diffusion region FD is reset.

[0138] The drive transistor DX performs a source follower function in combination with a positive current source located outside the pixel PX, amplifies the potential change in the floating diffusion region FD, and outputs it to the output line Lout. The selection transistor SX selects the pixel PX to be read row by row in response to a pixel selection signal SG. When the selection transistor SX is turned on, the power supply voltage VDD is transmitted to the source electrode of the drive transistor DX.

[0139] 15A and 15B, when light is incident on the photoelectric conversion element PD, the photoelectric conversion element PD generates and accumulates photocharges. In one embodiment, for example, an output voltage VOUT (FIG. 1) is applied as a charge transmission signal TG to a transmission transistor TX of at least one pixel among the plurality of pixels PX. The output voltage VOUT may be, for example, the output voltage VOUT described in FIGS. 2 to 9, or may be a selected one of the first to n-th output voltages (VOUT_1 to VOUT_n) described in FIGS. 10 and 11.

[0140] Since a high negative voltage is applied to the transmission transistor TX, the difference between the potential of the gate of the transmission transistor TX and the potential of the photoelectric conversion element PD increases. Therefore, the full well capacitance, which is the capacity at which photocharges are stored in the photoelectric conversion element PD, increases.

[0141] In one embodiment, the output voltage VOUT may be applied as a reset signal RG to at least one reset transistor RX of the pixels PX. Since a high negative voltage is applied to the reset transistor RX, the difference between the potential of the gate of the reset transistor RX and the potential of the floating diffusion region FD increases. Therefore, the full well capacitance, which is the capacity at which photocharges are stored in the floating diffusion region FD, increases.

[0142] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Industrial Applicability]

[0143] The present invention is applicable, for example, to imaging-related technical fields. [Explanation of symbols]

[0144] 1 Image sensor 10, 10A Charge Pump Circuit 20 Active Pixel Sensor Array 30 Line Decoder 40 Line Driver 50 Column Decoder 60 Timing Generator 70 Correlated Double Sampler (CDS) 80 Analog-to-Digital Converter (ADC) 90 Input / Output Buffers 100_1~100_n, 100_1A~100_nA 1st to nth pump units 100_n′ nth pump unit 100b, 200b 2nd side 100f, 200f 1st page 101, 101n N-type region 103, 103n 1st P type region 103nb 3rd P type region 105, 105n 2nd P type region 105nb 4th P type region 107, 107n Gate insulating layer 117n First gate insulating layer 107nb, 117nb Second gate insulating layer 109, 109n, 119n gate electrodes 109nb, 119nb Second gate electrode 111n P-type region 113n 1st N type region 113nb 3rd N type region 115n 2nd N type region 115nb 4th N type region 120, 120', 120B, 120R Element isolation film 123n 7th N type region 123nb 5th N type region 125n 8th N type region 125nb 6th N type region 129n Fourth gate electrode 129nb Third gate electrode 211 Interlayer insulating film 213 Front wiring 220_1, 220_1′, 220_1″ First element isolation film 220_2, 220_2′, 220_2″ Second element isolation film 221 Insulating film 223 Contact Via CLK Clock signal VH High level voltage VL Low level voltage VN1 to VNn-1 1st to n-1th node voltages VOUT Output voltage VOUT_1~VOUT_n 1st to nth output voltage V

Claims

1. 1. A charge pump circuit that receives a clock signal and generates a negative output voltage, comprising: The charge pump circuit comprises: a first pump unit including a first capacitor and a first transistor, the first pump unit generating a first node voltage at a first node using the clock signal; a second pump unit including a second capacitor, a second transistor, and a third transistor, the second pump unit generating the output voltage using the first node voltage; the second capacitor having a first terminal coupled to the first node and a second terminal coupled to the second transistor; each of the clock signal and the first node voltage toggles between a low level voltage and a high level voltage; the magnitude of the output voltage is greater than the magnitude of the high level voltage of the clock signal; a body of said second transistor and a body of said third transistor are electrically insulated from each other;

2. 2. The charge pump circuit according to claim 1, further comprising an isolation film that electrically insulates a body of the second transistor from a body of the third transistor.

3. the second transistor is an n-type transistor, 2. The charge pump circuit of claim 1, wherein the third transistor is a p-type transistor.

4. 4. The charge pump circuit of claim 3, wherein the second pump unit further comprises an n-type transistor formed in a well forming the second transistor.

5. 2. The charge pump circuit of claim 1, wherein the magnitude of the output voltage is greater than or equal to twice the magnitude of the high level voltage of the clock signal.

6. The first pump unit outputs a first output voltage having a constant magnitude; The second pump unit outputs a second output voltage having a constant magnitude; 2. The charge pump circuit of claim 1, wherein the magnitude of the second output voltage is greater than the magnitude of the first output voltage.

7. the first pump unit further includes a fourth transistor; 2. The charge pump circuit according to claim 1, further comprising an isolation film that electrically insulates a body of the first transistor from a body of the fourth transistor.

8. the first pump unit further includes a fourth transistor; 2. The charge pump circuit of claim 1, wherein a well forming the body of the fourth transistor is formed within a well forming the body of the first transistor.

9. 2. The charge pump circuit of claim 1, further comprising an inverter receiving the clock signal and providing a clock inversion signal to the first pump unit.

10. 1. A charge pump circuit that receives a clock signal and generates a negative output voltage, comprising: The charge pump circuit comprises: A substrate; a first well and a second well formed in the substrate; a first pump unit including a first capacitor and a first transistor formed in the first well; a second pump unit including a second capacitor and a second transistor formed in the second well; an isolation film electrically insulating the first well and the second well; The clock signal is applied to a first end of the first capacitor, and a second end of the first capacitor is connected to a first node; A drain of the first transistor is connected to the first node, and a source voltage is applied to a source of the first transistor; a first end of the second capacitor is coupled to the first node and a second end of the second capacitor is coupled to a second node; a drain of the second transistor is connected to the second node, and a source voltage is applied to a source of the second transistor; The clock signal toggles between a low level voltage and a high level voltage at a constant period, 13. A charge pump circuit, comprising: a first input terminal for inputting a first voltage to a first output terminal of said charge pump;

11. the substrate includes a first surface on which a transistor is formed and a second surface opposite to the first surface; The charge pump circuit according to claim 10 , wherein the device isolation film extends from the first surface to the second surface.

12. 12. The charge pump circuit of claim 11, wherein a first width of the cross section of the isolation film in contact with the first surface is narrower than a second width of the cross section of the isolation film in contact with the second surface.

13. the substrate includes a first surface on which a transistor is formed and a second surface opposite to the first surface; a first width of a cross section where the element isolation film contacts the first surface is wider than a third width of a central cross section of the element isolation film between the first surface and the second surface; 12. The charge pump circuit of claim 11, wherein a second width of a cross section of the isolation film where the isolation film contacts the second surface is wider than a third width of a central cross section of the isolation film between the first surface and the second surface.

14. 11. The charge pump circuit of claim 10, wherein the substrate is doped with P-type impurities.

15. a pixel array including a plurality of pixels defined by a first element isolation film; a charge pump circuit that receives a clock signal and provides a negative output voltage to the pixel array; The charge pump circuit comprises: a first pump unit including a first capacitor and a first transistor, the first pump unit generating a first node voltage at a first node using the clock signal; a second pump unit including a second capacitor, a second transistor, and a third transistor, the second pump unit generating the output voltage using the first node voltage; the second capacitor having a first terminal coupled to the first node and a second terminal coupled to the second transistor; the body of the second transistor and the body of the third transistor are electrically insulated from each other.

16. 16. The image sensor of claim 15, wherein the output voltage is provided to the first device isolation layer.

17. Each of the plurality of pixels comprises: a photoelectric conversion element that generates and accumulates photocharges in proportion to the amount of incident light; a transfer transistor for transferring the photocharges accumulated in the photoelectric conversion element to a floating diffusion region; a reset transistor for resetting the charge stored in the floating diffusion region; 16. The image sensor of claim 15, wherein the output voltage is provided to a gate of the transfer transistor.

18. Each of the plurality of pixels comprises: a photoelectric conversion element that generates and accumulates photocharges in proportion to the amount of incident light; a transfer transistor for transferring the photocharges accumulated in the photoelectric conversion element to a floating diffusion region; a reset transistor for resetting the charge stored in the floating diffusion region; 16. The image sensor of claim 15, wherein the output voltage is provided to a gate of the reset transistor.

19. 16. The image sensor of claim 15, wherein the charge pump circuit further comprises a second element isolation film electrically insulating a body of the second transistor from a body of the third transistor.

20. The first pump unit outputs a first output voltage having a constant magnitude; the second pump unit outputs a second output voltage greater than the magnitude of the first output voltage; 16. The image sensor of claim 15, wherein one of the first output voltage and the second output voltage is selectively provided to the pixel array.

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