Imaging device

Abstract

The imaging device according to one embodiment of the present disclosure comprises: a semiconductor substrate; and a plurality of pixels. Each of the plurality of pixels includes a first capacitive element that includes: a first electrode provided above the semiconductor substrate; a second electrode provided above the semiconductor substrate; and a dielectric layer that is positioned between the first electrode and the second electrode. The first electrode and / or the second electrode has a first electrical contact that is electrically connected to a first electrical element, and a second electrical contact that is electrically connected to a second electrical element that is different from the first electrical element. The first capacitive element includes at least one trench part that has a trench shape.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] There has been proposed an imaging device having a structure in which a photoelectric conversion layer is disposed above a semiconductor substrate on which a CCD (Charge Coupled Device) circuit or a CMOS (Complementary Metal Oxide Semiconductor) circuit is formed. An imaging device having a photoelectric conversion layer above a semiconductor substrate is also called a stacked imaging device. For example, Patent Document 1 discloses a solid-state imaging element having such a stacked structure.

[0003] A stacked-type imaging device accumulates charges generated by photoelectric conversion in a charge accumulation region, and reads out the accumulated charges by a readout circuit including a CCD circuit or a CMOS circuit. The photoelectric conversion layer is generally disposed on an insulating layer that covers a semiconductor substrate on which the readout circuit is formed. The photoelectric conversion layer on the insulating layer is electrically connected to the readout circuit via a connection portion provided in the insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-195803 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the field of imaging devices, there is a demand for noise reduction. [Means for solving the problem]

[0006] An imaging device according to an embodiment of the present disclosure includes a semiconductor substrate and a plurality of pixels. Each of the plurality of pixels includes a first capacitance element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has a first electrical contact electrically connected to a first electrical element and a second electrical contact electrically connected to a second electrical element different from the first electrical element. The first capacitance element includes at least one trench portion having a trench shape.

[0007] The generic or specific aspects may be realized as an element, a device, a system, an integrated circuit, or a method. Also, the generic or specific aspects may be realized as any combination of an element, a device, an apparatus, a system, an integrated circuit, and a method. Effect of the Invention

[0008] According to one aspect of the present disclosure, an imaging device capable of further reducing noise is provided. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an exemplary circuit configuration of an imaging device according to the first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a circuit configuration of a pixel included in the imaging device according to the first embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view of a pixel included in the imaging device according to the first embodiment. [Figure 4] FIG. 4 is a schematic plan view showing an example of the layout of elements included in a pixel included in the imaging device according to the first embodiment. [Diagram 5] FIG. 5 is a schematic plan view showing an example of the shape and arrangement of a first capacitance element and a trench portion included in a pixel of the imaging device according to the first embodiment. [Figure 6A]FIG. 6A is a schematic cross-sectional view for explaining a via forming step included in the method for manufacturing the imaging device according to the first embodiment. [Figure 6B] FIG. 6B is a schematic cross-sectional view for illustrating a step of forming an insulating layer, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6C] FIG. 6C is a schematic cross-sectional view for illustrating a trench forming step included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6D] FIG. 6D is a schematic cross-sectional view for illustrating a step of forming a lower electrode, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6E] FIG. 6E is a schematic cross-sectional view for illustrating a dielectric layer forming step included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6F] FIG. 6F is a schematic cross-sectional view for illustrating a step of forming an upper electrode, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6G] FIG. 6G is a schematic cross-sectional view for illustrating a step of forming an insulating layer, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6H] FIG. 6H is a schematic cross-sectional view for explaining a step of forming a via and a wiring layer, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 6I] FIG. 6I is a schematic cross-sectional view for explaining a step of forming an insulating layer, a via, and a wiring layer, which is included in the method for manufacturing the image pickup device according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of a pixel included in an imaging device according to a modification of the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of a pixel included in the imaging device according to the second embodiment. [Figure 9] FIG. 9 is a schematic plan view showing an example of the shape and arrangement of a first capacitance element and a trench portion included in a pixel of an imaging device according to the second embodiment. [Figure 10]FIG. 10 is a schematic plan view showing an example of the shape and arrangement of a first capacitance element and a trench portion included in a pixel of an imaging device according to a modification of the second embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of a circuit configuration of a pixel included in an imaging device according to the third embodiment. In FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a pixel included in the imaging device according to the third embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of a pixel included in the imaging device according to the fourth embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of a pixel included in the imaging device according to the fifth embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view of a pixel included in an imaging device according to a modification of the fifth embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of a pixel included in an imaging device according to another modification of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Summary of the Disclosure) According to certain non-limiting exemplary embodiments of the present disclosure, the following is provided:

[0011] An imaging device according to an embodiment of the present disclosure includes a semiconductor substrate and a plurality of pixels. Each of the plurality of pixels includes a first capacitance element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has a first electrical contact electrically connected to a first electrical element and a second electrical contact electrically connected to a second electrical element different from the first electrical element. The first capacitance element includes at least one trench portion having a trench shape.

[0012] As a result, since the first capacitive element is provided with two or more electrical contacts, the degree of freedom in the layout of the wiring that electrically connects the first capacitive element and the multiple electrical elements can be increased. Therefore, for example, the wiring can be arranged so that parasitic capacitance between the wiring is unlikely to occur even in a narrow pixel region, so that noise can be reduced. In this way, an imaging device that can further reduce noise can be realized. In addition, since the degree of freedom in the layout of the wiring can be increased, the pixel area can be reduced, and thus miniaturization of the imaging device can be achieved.

[0013] Also, for example, at least one of the first electrical contact and the second electrical contact may be provided in the at least one trench portion. Also, for example, at least one of the first electrical contact and the second electrical contact may be provided on a bottom surface of the at least one trench portion. Also, for example, the first electrical contact may be provided in the at least one trench portion, and the second electrical contact may be provided outside the at least one trench portion.

[0014] In this way, the bottom or side surface of the trench can be used to electrically connect to the electric element, which means that electrical contacts can be provided not only on the flat portion of the first capacitive element but also on other portions of the flat portion, thereby increasing the degree of freedom in the layout of the wiring.

[0015] Also, for example, the at least one trench portion may include a plurality of trench portions, and the plurality of trench portions may include a trench portion in which the first electrical contact and the second electrical contact are not provided.

[0016] This makes it possible to increase the capacitance of the first capacitive element while suppressing an increase in the area occupied by the first capacitive element in a plan view, i.e., it is possible to provide a first capacitive element having a large capacitance in a small pixel area.

[0017] Also, for example, the first electrode may be provided closer to the semiconductor substrate than the second electrode, and may have the first electrical contact and the second electrical contact.

[0018] Thereby, for example, when forming a trench, the exposed portion of the via or wiring portion can be exposed to plasma, and the exposed portion can be activated. By connecting the exposed portion and the first electrode of the first capacitance element at a contact point, the contact resistance between the via or wiring portion and the first electrode can be reduced. By reducing the contact resistance, the variation in contact resistance between pixels can be reduced, and therefore the roughness of the image generated by the imaging device can be suppressed. In this way, an imaging device that can further reduce noise can be realized.

[0019] Also, for example, the second electrode may be provided farther from the semiconductor substrate than the first electrode, and may have the first electrical contact and the second electrical contact.

[0020] This allows the electrode on which the electrical contact is provided to be not limited to the first electrode, further increasing the degree of freedom in the layout of the wiring.

[0021] Furthermore, for example, the first electrode and the second electrode may contain TiN or TaN.

[0022] This makes it possible to form the first and second electrodes with small surface roughness, thereby suppressing variation in the distance between the first and second electrodes and thereby suppressing variation in the capacitance value of the first capacitive element.

[0023] Also, for example, an imaging device according to one aspect of the present disclosure may further include a plurality of wiring layers provided above the semiconductor substrate, and among the plurality of wiring layers, the number of wiring layers located above the first capacitive element may be greater than the number of wiring layers located below the first capacitive element.

[0024] In many cases, an impurity region that functions as part of a charge storage section for storing signal charges generated in a photoelectric conversion section is formed in a semiconductor substrate. Since the number of wiring layers close to the semiconductor substrate can be reduced, it is possible to suppress fluctuations in the potential of the charge storage section due to parasitic capacitance components of the wiring layers. Therefore, it is possible to realize an imaging device that can further reduce noise.

[0025] Also, for example, the first electrical contact and the second electrical contact may both be connected to a via.

[0026] As a result, for example, the upper end of the via is activated by being exposed to plasma when forming the trench, which facilitates metallic bonding between the upper end of the via and the electrode of the first capacitance element, thereby reducing the contact resistance between the via and the electrode of the first capacitance element.

[0027] Also, for example, each of the plurality of pixels may further include a photoelectric conversion unit and an impurity region electrically connected to the photoelectric conversion unit and provided in the semiconductor substrate, and in a planar view, the first capacitive element may overlap at least a portion of the impurity region.

[0028] As a result, when the first electrode or the second electrode is formed using a material having a light-shielding property, the first capacitance element can prevent light incident on the imaging device from reaching the impurity region, which can prevent unnecessary charges from being generated in the impurity region, thereby further reducing noise.

[0029] Also, for example, each of the plurality of pixels may further include a photoelectric conversion unit, an impurity region electrically connected to the photoelectric conversion unit and provided in the semiconductor substrate, a transistor electrically connected to the impurity region, and a second capacitance element, the transistor being one of the first electrical contact and the second electrical contact, and the second capacitance element being the other of the first electrical contact and the second electrical contact. Also, for example, the transistor may be a reset transistor that resets charges generated in the photoelectric conversion unit and stored in the impurity region.

[0030] This allows the first or second electrode to have the same potential as one electrode of the second capacitance element and the source or drain region of the transistor. For example, the first or second electrode, one electrode of the second capacitance element, and the source or drain region of the transistor can be used as a reset drain node.

[0031] Also, for example, the second capacitive element may be electrically connected to the impurity region via the first electrode or the second electrode.

[0032] This allows the first electrode or the second electrode of the first capacitance element to be used as part of the wiring, which reduces the amount of dedicated wiring required for electrical connection, thereby increasing the space within the pixel and further increasing the degree of freedom in the layout of other wiring.

[0033] Also, for example, each of the multiple pixels may further include a photoelectric conversion unit and an impurity region electrically connected to the photoelectric conversion unit and provided in the semiconductor substrate, the first electrode may be provided closer to the semiconductor substrate than the second electrode and electrically connected to the impurity region, and the second electrode may be electrically connected to a pad to which a predetermined voltage value is applied.

[0034] This makes it possible to adjust the potential of the first capacitive element by the voltage applied to the pad.

[0035] Also, for example, the imaging device may further include a sensitivity adjustment line electrically connected to the pad and the second electrode for adjusting the sensitivity of the imaging device.

[0036] This makes it possible to adjust the sensitivity according to the amount of light incident on the imaging device, thereby making it possible to increase the dynamic range of the imaging device from dark scenes to bright scenes.

[0037] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings, and the benefits and / or advantages may be provided by the various embodiments or features disclosed in the specification and drawings individually, and not all are required to obtain one or more of them.

[0038] Hereinafter, the embodiment will be specifically described with reference to the drawings.

[0039] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims are described as optional components.

[0040] In addition, each figure is a schematic diagram and is not necessarily illustrated precisely. Therefore, for example, the scales in each figure do not necessarily match. In addition, in each figure, substantially the same configurations are given the same reference numerals, and duplicated explanations are omitted or simplified.

[0041] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

[0042] In this specification, the terms "above", "top" and "upper", as well as "below", "lower" and "lower", do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "above" and "lower" are applied not only to the case where two components are arranged with a gap between them and another component is present between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0043] In this specification, the term "planar view" refers to a view from a direction perpendicular to the main surface of the semiconductor substrate.

[0044] (Embodiment 1) [1. Circuit configuration] Fig. 1 is a diagram showing an exemplary circuit configuration of an imaging device 100 according to the present embodiment. As shown in Fig. 1, the imaging device 100 includes a plurality of pixels 10 and peripheral circuits. The plurality of pixels 10 are arranged, for example, two-dimensionally to form a pixel area RA. For simplicity, Fig. 1 shows four pixels 10 out of the plurality of pixels 10, and the other pixels 10 are not shown.

[0045] For example, if the imaging device 100 complies with the VGA (Video Graphics Array) standard, the imaging device 100 includes approximately 300,000 pixels 10 arranged in a matrix. If the imaging device 100 complies with the 8K standard, the imaging device 100 includes approximately 36 million pixels 10 arranged in a matrix. The above-mentioned peripheral circuits are disposed in a peripheral region outside the pixel region RA.

[0046] Needless to say, the number and arrangement of the pixels 10 are not limited to this example. The arrangement of the pixels 10 may be one-dimensional. In this case, the imaging device 100 can be used as a line sensor.

[0047] Each of the pixels 10 is connected to a power supply line 22. When the imaging device 100 is in operation, a predetermined power supply voltage AVDD is supplied to each of the pixels 10 via the power supply line 22. An accumulation control line 17 is also connected to each of the pixels 10. As will be described in detail later, each of the pixels 10 includes a photoelectric conversion unit that photoelectrically converts incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In a typical embodiment, the accumulation control line 17 applies a predetermined voltage in common to the photoelectric conversion units of each pixel 10.

[0048] In the configuration illustrated in Fig. 1, the peripheral circuits of the imaging device 100 include a vertical scanning circuit 16, a plurality of load circuits 19, a plurality of column signal processing circuits 20, a plurality of inverting amplifiers 24, and a horizontal signal readout circuit 21. The load circuits 19, the column signal processing circuits 20, and the inverting amplifiers 24 are arranged for each column of the pixels 10 arranged two-dimensionally. The vertical scanning circuit is also called a row scanning circuit. The column signal processing circuit is also called a row signal storage circuit. The horizontal signal readout circuit is also called a column scanning circuit.

[0049] An address signal line 30 and a reset signal line 26 are connected to the vertical scanning circuit 16. The vertical scanning circuit 16 selects a plurality of pixels 10 arranged in each row on a row-by-row basis by applying a predetermined voltage to the address signal line 30. By selecting a plurality of pixels 10 on a row-by-row basis, the signal voltage of the selected pixels 10 is read out and the signal charge is reset, which will be described later.

[0050] In the illustrated example, a feedback control line 28 and a sensitivity adjustment line 32 are further connected to the vertical scanning circuit 16. The vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, thereby forming a feedback loop that negatively feeds back the output of the pixel 10. In addition, the vertical scanning circuit 16 can supply a predetermined voltage to the multiple pixels 10 via the sensitivity adjustment line 32.

[0051] The imaging device 100 has vertical signal lines 18 provided for each column of the pixels 10. A load circuit 19 is electrically connected to each vertical signal line 18. Each of the pixels 10 is electrically connected to a column signal processing circuit 20 via the corresponding vertical signal line 18.

[0052] The column signal processing circuits 20 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 21 is electrically connected to the column signal processing circuits 20 provided corresponding to each column of the multiple pixels 10. The horizontal signal readout circuit 21 sequentially reads out signals from the multiple column signal processing circuits 20 to a horizontal common signal line 23.

[0053] As shown in FIG. 1, the power supply wiring 22, the feedback line 25, and the vertical signal line 18 extend in the vertical direction in FIG. 1, that is, in the column direction of the pixels 10. Each of the feedback lines 25 and each of the vertical signal lines 18 provided for each column of the pixels 10 are connected to each of the pixels 10 arranged along the column direction. On the other hand, the accumulation control line 17, the reset signal line 26, the feedback control line 28, the address signal line 30, and the sensitivity adjustment line 32 extend, for example, in the row direction of the pixels 10. These signal lines are connected to each of the pixels 10 arranged along the row direction. The accumulation control line 17 and the sensitivity adjustment line 32 may extend in the column direction of the pixels 10. The accumulation control line 17 and the sensitivity adjustment line 32 may be connected to each of the pixels 10 arranged along the column direction.

[0054] In the configuration illustrated in FIG. 1, an inverting amplifier 24 is provided corresponding to each column of the pixels 10. A negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18, and a predetermined voltage Vref is supplied to a positive input terminal of the inverting amplifier 24. The voltage Vref is, for example, a positive voltage of 1V or close to 1V. An output terminal of the inverting amplifier 24 is connected to a pixel 10 having a connection to the negative input terminal of the inverting amplifier 24 via one of a plurality of feedback lines 25 provided corresponding to the plurality of columns of the pixels 10. The inverting amplifier 24 constitutes a part of a feedback circuit that negatively feeds back the output from the pixel 10. The inverting amplifier 24 may be called a feedback amplifier.

[0055] 2 is a diagram showing an example of a circuit configuration of a pixel 10 included in the imaging device 100 according to the present embodiment. In the present embodiment, the multiple pixels 10 included in the imaging device 100 have the same configuration.

[0056] 2, the pixel 10 includes a photoelectric conversion unit 15 and a signal detection circuit SC. In the configuration illustrated in Fig. 2, the imaging device 100 includes a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC.

[0057] The photoelectric conversion unit 15 has a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c as a pixel electrode. The first electrode 15a of the photoelectric conversion unit 15 is connected to an accumulation control line 17. The second electrode 15c of the photoelectric conversion unit 15 is connected to a charge accumulation node 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, charges of either polarity among positive charges (specifically, holes) and negative charges (specifically, electrons) generated in the photoelectric conversion layer 15b by photoelectric conversion can be collected in the second electrode 15c. When holes are used as signal charges, for example, the potential of the first electrode 15a may be made higher than that of the second electrode 15c. The following illustrates a case in which holes are used as signal charges. For example, a voltage of about 10V is applied to the first electrode 15a via the accumulation control line 17. As a result, the signal charges are accumulated in the charge accumulation node 44. Electrons may be used as signal charges.

[0058] The signal detection circuit SC includes a signal detection transistor 34 that amplifies and outputs a signal generated by the photoelectric conversion unit 15, and a first capacitance element 41. In the illustrated example, the signal detection circuit SC further includes a reset transistor 36, a feedback transistor 38, a second capacitance element 42 having a capacitance value smaller than that of the first capacitance element 41, and an address transistor 40. Thus, in this embodiment, each of the multiple pixels 10 has one or more capacitance elements therein. As will be described in detail later, the first capacitance element 41 has a relatively large capacitance value, which can effectively reduce kTC noise, for example. In the following, an example will be described in which an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a transistor such as the signal detection transistor 34.

[0059] The gate of the signal detection transistor 34 is connected to the charge accumulation node 44. In other words, the gate of the signal detection transistor 34 is connected to the second electrode 15c. The drain of the signal detection transistor 34 is connected to the power supply wiring 22 as a source follower power supply, and the source is connected to the vertical signal line 18 via the address transistor 40. The signal detection transistor 34 and a load circuit 19 (see FIG. 1) not shown in FIG. 2 configure a source follower circuit.

[0060] In the example shown in FIG. 2, the address transistor 40 is connected between the source of the signal detection transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When a signal charge is accumulated in the charge accumulation node 44, a voltage according to the amount of the accumulated signal charge is applied to the gate of the signal detection transistor 34. The signal detection transistor 34 amplifies the voltage applied to the gate. When the address transistor 40 is turned on, the voltage amplified by the signal detection transistor 34 is selectively read out as a signal voltage. The address transistor 40 may be connected between the drain of the signal detection transistor 34 and the power supply wiring 22. That is, the drain of the signal detection transistor 34 may be connected to the power supply wiring 22 via the address transistor 40.

[0061] In the configuration illustrated in FIG. 2, one of a pair of electrodes of the first capacitance element 41 is connected to a sensitivity adjustment line 32. A pad is connected to the sensitivity adjustment line 32, and the potential of the sensitivity adjustment line 32 is adjusted by a voltage applied to the pad. For example, during operation of the imaging device 100, the potential of the sensitivity adjustment line 32 is fixed to a constant potential such as 0V. The sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. The other of the pair of electrodes of the first capacitance element 41 is connected to one of the pair of electrodes of the second capacitance element 42. Hereinafter, a node including a connection point between the first capacitance element 41 and the second capacitance element 42 may be referred to as a reset drain node 46.

[0062] The other of the pair of electrodes of the second capacitance element 42 is connected to the charge storage node 44. That is, of the pair of electrodes of the second capacitance element 42, the electrode that is not connected to the reset drain node 46 is electrically connected to the second electrode 15c of the photoelectric conversion unit 15. In the example shown in FIG. 2, the reset transistor 36 is connected in parallel to the second capacitance element 42. The gate of the reset transistor 36 is connected to the reset signal line 26.

[0063] 2, pixel 10 includes a feedback transistor 38. As shown, one of the source and drain of feedback transistor 38 is connected to a reset drain node 46. The other of the source and drain of feedback transistor 38 is connected to feedback line 25. The gate of feedback transistor 38 is connected to feedback control line 28.

[0064] [2. Pixel device structure] Next, an example of the device structure of the pixel 10 will be described with reference to FIGS.

[0065] Fig. 3 is a schematic cross-sectional view of a pixel 10 included in the imaging device 100 according to the present embodiment. Fig. 4 is a schematic plan view showing an example of the layout of each element included in the pixel 10 included in the imaging device 100 according to the present embodiment. Fig. 3 is a schematic cross-sectional view taken along line III-III in Fig. 4.

[0066] In Fig. 3, the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f included in the interlayer insulating layer 4 are not shaded to show a cross section. The same applies to Figs. 6A to 6I, 7, 8, and 12 to 15 described later.

[0067] As shown in Fig. 4, the imaging device 100 has a semiconductor substrate 2. For example, a silicon substrate can be used as the semiconductor substrate 2. The semiconductor substrate 2 is not limited to a substrate whose entirety is a semiconductor. For example, the semiconductor substrate 2 may be an insulating substrate having a semiconductor layer provided on its surface. Here, a p-type silicon substrate is exemplified as the semiconductor substrate 2.

[0068] Each of the multiple pixels 10 is formed in a semiconductor substrate 2. Each of the multiple pixels 10 is electrically isolated from the other pixels 10 by an element isolation region 2t formed in the semiconductor substrate 2. The element isolation region 2t is formed, for example, by performing ion implantation of an acceptor under predetermined implantation conditions.

[0069] 3, an interlayer insulating layer 4 that covers the semiconductor substrate 2 is disposed between the semiconductor substrate 2 and the photoelectric conversion unit 15. The interlayer insulating layer 4 has a laminated structure of insulating layers 4a, 4b, 4c, 4d, 4e, and 4f. Each of the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f is an insulating layer made of, for example, silicon dioxide. In this example, the photoelectric conversion unit 15 is located on the insulating layer 4f that is located farthest from the semiconductor substrate 2.

[0070] The semiconductor substrate 2 has impurity regions 2a, 2b, and 2c formed therein. The impurity regions 2a, 2b, and 2c are, for example, regions in which an N-type dopant is diffused. A gate insulating layer 36g and a gate electrode 36e of the reset transistor 36 are provided in this order in a region between the impurity region 2a and the impurity region 2b on the main surface of the semiconductor substrate 2. A gate insulating layer 38g and a gate electrode 38e of the feedback transistor 38 are provided in this order in a region between the impurity region 2b and the impurity region 2c on the main surface of the semiconductor substrate 2. The main surface of the semiconductor substrate 2 is the surface on which the interlayer insulating layer 4 and the photoelectric conversion unit 15 are provided, among the multiple surfaces of the semiconductor substrate 2. The main surface of the semiconductor substrate 2 is covered with an insulating layer 4a of the interlayer insulating layer 4.

[0071] The impurity region 2a functions as one of the drain region and the source region of the reset transistor 36. The impurity region 2b functions as the other of the drain region and the source region of the reset transistor 36. In the example shown in FIG. 3, the reset transistor 36 and the feedback transistor 38 are electrically connected to each other by sharing the impurity region 2b. In other words, the impurity region 2b also functions as one of the drain region and the source region of the feedback transistor 38.

[0072] The impurity region 2c functions as the other of the drain region and source region of the feedback transistor 38. The impurity region 2c is connected to a feedback line 25 that spans multiple pixels 10 through plugs, vias, and a wiring layer disposed in the interlayer insulating layer 4. As shown in FIG 1, the feedback line 25 is a signal line that extends to the outside of the pixel region RA.

[0073] 3, the portion of the feedback line 25 located within the pixel 10 of interest is included in a wiring layer 51 located between the second electrode 15c of the photoelectric conversion unit 15 and the semiconductor substrate 2. Also, a wiring layer 52 located in the same layer as the wiring layer 51 includes the portion of the vertical signal line 18 located within the pixel 10 of interest. That is, in this example, the vertical signal line 18 and the feedback line 25 are located in the same layer within the pixel 10. The vertical signal line 18 is also a signal line that extends to the outside of the pixel region RA, similar to the feedback line 25.

[0074] The term "same layer" means that they are located on a common insulating layer. In this case, if the common insulating layer is a planarizing film, the heights from the main surface of the semiconductor substrate 2 are substantially equal to each other.

[0075] Moreover, the signal lines extending to the outside of the pixel region RA include not only the vertical signal lines 18 and the feedback lines 25 but also the reset signal lines 26, the feedback control lines 28, the address signal lines 30, and the sensitivity adjustment lines 32. At least one of the wiring layers 51 and 52 may include a part of the reset signal lines 26, the feedback control lines 28, the address signal lines 30, or the sensitivity adjustment lines 32, which are control lines for driving two or more pixels.

[0076] Further, on the main surface of the semiconductor substrate 2, a gate insulating layer 34g and a gate electrode 34e of the signal detection transistor 34 are provided in this order. As can be seen from FIG. 4, the drain region and the source region of the signal detection transistor 34 are located on the front side and the back side of the paper surface of FIG. 3, respectively. In the example shown in FIG. 3, a set of the reset transistor 36 and the feedback transistor 38 and a set of the signal detection transistor 34 and the address transistor 40 (not shown in FIG. 3) are separated by an element isolation region 2u. The element isolation region 2u can be formed, for example, by ion implanting an acceptor under a predetermined implantation condition, similar to the element isolation region 2t. Each of the element isolation regions 2t and 2u may be an insulating region formed by an STI (Shallow Trench Isolation) process. The element isolation region 2t and the element isolation region 2u are integrally formed in the pixel region.

[0077] 3, each pixel 10 has a connection portion 50 in the interlayer insulating layer 4 that electrically connects the impurity region 2a of the semiconductor substrate 2 to the second electrode 15c of the photoelectric conversion unit 15. The impurity region 2a is an example of an impurity region electrically connected to the photoelectric conversion unit 15. The impurity region 2a functions as at least a part of a charge accumulation region that accumulates signal charges generated by the photoelectric conversion unit 15.

[0078] The connection portion 50 includes a plug P1, a plug P2, and a wiring portion 50a. The plug P1 has a lower end connected to the impurity region 2a of the semiconductor substrate 2, and an upper end connected to the wiring portion 50a. The plug P2 has a lower end connected to the gate electrode 34e of the signal detection transistor 34, and an upper end connected to the wiring portion 50a. The wiring portion 50a connects the plug P1 and the plug P2 to each other. The impurity region 2a and the gate electrode 34e are electrically connected to each other by the plug P1, the plug P2, and the wiring portion 50a. That is, the impurity region 2a functioning as the drain region or source region of the reset transistor 36 and the gate electrode 34e of the signal detection transistor 34 are electrically connected to the second electrode 15c of the photoelectric conversion portion 15 via the connection portion 50.

[0079] The plugs P1 and P2 and the wiring portion 50a are formed using a conductive material. For example, the plugs P1 and P2 and the wiring portion 50a are formed using polysilicon that is doped with impurities to provide conductivity. At least one of the plugs P1 and P2 and the wiring portion 50a may be formed using a metal material such as copper.

[0080] The connection portion 50 further includes wiring layers 50b and 50c, and vias 50d, 50e, and 50f. Between the wiring portion 50a and the second electrode 15c, the via 50d, the wiring layer 50b, the via 50e, the wiring layer 50c, and the via 50f are provided in this order from the semiconductor substrate 2 side. The wiring layers 50b and 50c and the vias 50d, 50e, and 50f are formed using a metal material such as copper. Alternatively, the wiring layers 50b and 50c and the vias 50d, 50e, and 50f may be formed using a conductive material other than a metal material such as polysilicon to which conductivity has been imparted.

[0081] 3, the wiring layer 50b is located in the same layer as the wiring layers 51 and 52. For example, the wiring layer 50b, the wiring layer 51, and the wiring layer 52 can be formed at the same time. In this case, the wiring layer 50b, the wiring layer 51, and the wiring layer 52 have the same thickness and material. Therefore, the wiring layers 51 and 52 may also be formed from a metal such as copper.

[0082] The number of wiring layers disposed in the interlayer insulating layer 4 and the number of insulating layers in the interlayer insulating layer 4 are not limited to the number of layers exemplified in FIG. 3, and can be set arbitrarily.

[0083] The photoelectric conversion unit 15 supported by the semiconductor substrate 2 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c. The photoelectric conversion unit 15 has a structure in which the photoelectric conversion layer 15b is sandwiched between the first electrode 15a and the second electrode 15c.

[0084] The first electrode 15a of the photoelectric conversion unit 15 is provided on the side where light from a subject is incident. The first electrode 15a is formed of a transparent conductive material such as ITO (Indium Tin Oxide). The first electrode 15a may be formed directly on the photoelectric conversion layer 15b, or another layer may be disposed between the first electrode 15a and the photoelectric conversion layer 15b.

[0085] The photoelectric conversion layer 15b generates positive and negative charges, specifically, hole-electron pairs, upon receiving incident light. The photoelectric conversion layer 15b is made of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 15b may include a layer made of an organic material and a layer made of an inorganic material.

[0086] The second electrode 15c is located closer to the semiconductor substrate 2 than the first electrode 15a and the photoelectric conversion layer 15b. The second electrode 15c is provided separately for each pixel 10. Specifically, the second electrode 15c is spatially separated from the second electrodes 15c of the other adjacent pixels 10, and is thus electrically separated from them. The second electrode 15c collects charges generated by photoelectric conversion in the photoelectric conversion layer 15b. The second electrode 15c is formed of, for example, a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide conductivity.

[0087] The first electrode 15a and the photoelectric conversion layer 15b are formed, for example, across a plurality of pixels 10. Alternatively, at least one of the first electrode 15a and the photoelectric conversion layer 15b may be spatially separated from one another among a plurality of pixels 10, similar to the second electrode 15c.

[0088] In this embodiment, the first capacitance element 41 is provided in the interlayer insulating layer 4 between the photoelectric conversion unit 15 and the semiconductor substrate 2. Specifically, the first capacitance element 41 is located between the semiconductor substrate 2 and wiring layers 51 and 52 including at least a part of the signal line connected to two or more pixels 10. In the configuration illustrated in FIG. 3, the first capacitance element 41 is located between the semiconductor substrate 2 and the wiring layer 52 including a part of the vertical signal line 18 and the wiring layer 51 including a part of the feedback line 25. In other words, in this embodiment, the first capacitance element 41 has an arrangement such that it is located closer to the semiconductor substrate 2 than the wiring layer including a part of the signal line connected to two or more pixels 10. That is, in this embodiment, among the multiple wiring layers included in the imaging device 100, the number of wiring layers located above the first capacitance element 41 is greater than the number of wiring layers located below the first capacitance element 41. Note that a wiring layer may not be provided below the first capacitance element 41.

[0089] The first capacitance element 41 has an upper electrode 41a, a lower electrode 41c, and a dielectric layer 41b disposed between the upper electrode 41a and the lower electrode 41c. The upper electrode 41a is an example of a second electrode, and is located between the wiring layer 52 and the semiconductor substrate 2 in the cross-sectional view shown in FIG. 3. The lower electrode 41c is an example of a first electrode, and is located between the upper electrode 41a and the semiconductor substrate 2.

[0090] The lower electrode 41c, the dielectric layer 41b, and the upper electrode 41a are laminated in this order from the semiconductor substrate 2 side. The dielectric layer 41b contacts the lower electrode 41c and covers the entire lower electrode 41c. The lower electrode 41c is not exposed to the outside because it is covered by the dielectric layer 41b. The upper electrode 41a contacts the dielectric layer 41b and covers the dielectric layer 41b. The upper electrode 41a and the lower electrode 41c are not in contact with each other because the dielectric layer 41b is disposed between them.

[0091] The first capacitance element 41 is a trench type capacitor. Specifically, the first capacitance element 41 includes at least one trench portion. In the example shown in Fig. 3, the first capacitance element 41 includes a flat portion 41d and two trench portions 41e and 41f. The two trench portions 41e and 41f are provided so as to sandwich the connection portion 50 therebetween in a cross-sectional view.

[0092] The flat portion 41d is a portion of the first capacitance element 41 located on the upper surface of the insulating layer 4c. The trench portion 41e is a portion of the first capacitance element 41 located in a trench 4t provided in the insulating layer 4c. The trench portion 41f is a portion of the first capacitance element 41 located in a trench 4u provided in the insulating layer 4c. In each of the flat portion 41d and the trench portions 41e and 41f, the lower electrode 41c and the dielectric layer 41b are formed with a substantially uniform thickness. The upper electrode 41a is provided so as to fill the trenches 4t and 4u. Alternatively, the upper electrode 41a may also be formed with a substantially uniform thickness.

[0093] With this configuration, not only the flat portion 41d but also the trench portions 41e and 41f contribute to the capacitance value of the first capacitance element 41. The first capacitance element 41 has a larger capacitance value corresponding to the surface area of ​​the walls of the trenches 4t and 4u compared to a parallel plate capacitor that does not have the trench portions 41e and 41f. In this way, by including the trench portions 41e and 41f in the first capacitance element 41, it is possible to increase the capacitance value while suppressing an increase in the area occupied in a plan view. Note that the first capacitance element 41 may have only one of the trench portions 41e and 41f.

[0094] In this embodiment, at least one of the lower electrode 41c and the upper electrode 41a has two or more electrical contacts. The two or more electrical contacts are electrically connected to different electrical elements. In the example shown in Fig. 3, the lower electrode 41c has two contacts 41g and 41h. The two contacts 41g and 41h are provided in the trench portions 41e and 41f, respectively.

[0095] Specifically, the contact 41g is provided on the bottom surface of the trench portion 41e. The bottom surface is the surface of the trench portion 41e facing the semiconductor substrate 2 (specifically, the lower surface). The contact 41g is a contact with the via v1 at the bottom surface of the trench portion 41e. The via v1 is joined to the impurity region 2b through the plug P3. That is, the contact 41g is electrically connected to the reset transistor 36 and the feedback transistor 38. The reset transistor 36 and the feedback transistor 38 are each an example of an electric element to which the contact 41g is electrically connected. In this way, one contact of the first capacitance element may be connected to multiple electric elements.

[0096] The contact 41h is provided on the bottom surface of the trench portion 41f. The contact 41h is a contact point with the via v2 on the bottom surface of the trench portion 41f. The via v2 is joined to the electrode 42a. The electrode 42a overlaps with the gate electrode 34e via the insulating film 42b. That is, the electrode 42a and the gate electrode 34e form the second capacitance element 42. The second capacitance element 42 is an example of an electric element to which the contact 41h is electrically connected. In this way, the contact 41g and the contact 41h are connected to different electric elements.

[0097] The capacitance value of the second capacitive element 42 can be set to a desired value by adjusting the material or thickness of the insulating film 42b, or the area where the electrode 42a and the gate electrode 34e overlap.

[0098] Although the method of forming the first capacitance element 41 will be described later, by providing the contacts 41g and 41h of the lower electrode 41c on the bottom surfaces of the trench portions 41e and 41f, the contact resistance value between the lower electrode 41c and the vias v1 and v2 can be reduced. This makes it possible to suppress the variation in the contact resistance value of each pixel 10.

[0099] The lower electrode 41c of the first capacitance element 41, the via v1, the plug P3, the via v2, and the electrode 42a constitute a part of the reset drain node 46. As shown in Fig. 2, the charge storage node 44 is electrically coupled to the reset drain node 46 via the second capacitance element 42. Therefore, the potential of the charge storage node 44 may vary in accordance with the potential fluctuation of the reset drain node 46.

[0100] That is, when the contact resistance between the lower electrode 41c and each of the vias v1 and v2 varies among the pixels 10, this leads to a fluctuation in the potential of the reset drain node 46. For example, even if the same amount of light is incident on each pixel 10 and the same amount of charge is generated from the photoelectric conversion unit 15, if the potential of the reset drain node 46 fluctuates, the potential of the charge storage node 44 will not be the same for each pixel 10. For this reason, the obtained image appears to have noise (also called graininess).

[0101] In the present embodiment, by reducing the resistance value of the reset drain node 46, it is possible to make the potential of the reset drain node 46 in all the pixels 10 closer to a constant value.

[0102] The upper electrode 41a of the first capacitance element 41 may be a part of a wiring layer located between the second electrode 15c of the photoelectric conversion unit 15 and the gate electrode 34e of the signal detection transistor 34. The upper electrode 41a is electrically connected to a pad not shown in FIG. 3. The pad is, for example, a portion to which a predetermined voltage is applied. For example, the pad is connected to the upper electrode 41a via a sensitivity adjustment line 32. The upper electrode 41a extends in a plane parallel to the main surface of the semiconductor substrate 2 as shown in FIG. 5. The same is true for the lower electrode 41c and the dielectric layer 41b.

[0103] The upper electrode 41a and the lower electrode 41c are each formed using a conductive material such as a metal or a metal compound. The conductive material may be a metal such as titanium (Ti), aluminum (Al), gold (Au), or platinum (Pt), or an alloy of two or more of these metals. Alternatively, the conductive material may be a conductive metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or hafnium nitride (HfN). The upper electrode 41a and the lower electrode 41c may be formed using the same type of material or different types of materials.

[0104] The dielectric layer 41b is made of a so-called high-k material having a higher dielectric constant than silicon oxide. Specifically, the dielectric layer 41b contains an oxide of hafnium (Hf) or zirconium (Zr) as a main component.

[0105] As described above, the first capacitance element 41 has a "Metal-Insulator-Metal (MIM) structure" in which a dielectric is sandwiched between two electrodes made of a metal or a metal compound. Here, in order to equalize the potential of the reset drain node 46 among the pixels 10, it is desirable to minimize the leakage current flowing between the upper electrode 41a and the lower electrode 41c. This is because if the leakage current is large, the charge of the reset drain node 46 flows into the sensitivity adjustment line 32 connected to the upper electrode 41a.

[0106] Theoretically, there should be no leakage current flowing through the dielectric layer 41b located between the upper electrode 41a and the lower electrode 41c. However, in this embodiment, in order to increase the capacitance value of the first capacitance element 41, a high-k material with a high refractive index is used as the dielectric layer 41b. This narrows the band gap of the dielectric layer 41b. For the same purpose, the thickness of the dielectric layer 41b is made thin, within a range of about 5 nm to about 40 nm. For these reasons, in reality, the leakage current tends to increase.

[0107] In order to suppress this leakage current, the surface roughness of the upper electrode 41a and the lower electrode 41c should be reduced. There is a relationship between the leakage current and the surface roughness of each electrode such that the greater the surface roughness, the greater the leakage current. For example, when the surface roughness of the upper electrode 41a and the lower electrode 41c is large, the thickness of the dielectric layer 41b becomes non-uniform. Since the electric field tends to concentrate in the portion where the dielectric layer 41b is thin, the leakage current tends to increase.

[0108] In contrast, in the present embodiment, for example, TiN or TaN is used as the conductive material for forming the upper electrode 41a and the lower electrode 41c. This allows TiN or TaN to reduce the surface roughness when formed, thereby suppressing the leakage current of the first capacitance element 41. Furthermore, making the surface roughness of the upper electrode 41a and the lower electrode 41c uniform can also contribute to suppressing the variation in the capacitance value of the first capacitance element 41 in each pixel 10. Furthermore, TiN or TaN has a small sheet resistance, so it is possible to reduce the resistance component generated in the reset drain node 46.

[0109] Fig. 5 is a schematic plan view showing an example of the shape and arrangement of the first capacitance element 41 and the trench portions 41e and 41f included in the pixel 10 of the imaging device 100 according to the present embodiment. Specifically, Fig. 5 shows an example of the positional relationship of the upper electrode 41a, the trench portions 41e and 41f, the vias v1 and v2, the impurity regions 2b and 2c, and the second capacitance element 42 when the photoelectric conversion unit 15 is removed from the pixel 10 and viewed from the normal direction of the main surface of the semiconductor substrate 2.

[0110] In the example shown in Fig. 5, vias v1 and v2 are formed at approximately the center of the trench portions 41e and 41f, respectively. The outlines of the trench portions 41e and 41f are indicated by thick solid lines. The via v1 is located directly above the impurity region 2b to which it is connected. The via v2 is located directly above the electrode 42a. The arrangement and shape of the trench portions 41e and 41f are not particularly limited.

[0111] As illustrated in FIG. 5, according to the present embodiment, the first capacitance element 41 of one pixel 10 has two or more trench portions 41e and 41f. As illustrated in FIG. 3, contacts 41g and 41h are provided on the bottom surfaces of the trench portions 41e and 41f. The contacts 41g and 41h are electrically connected to different electric elements, respectively, so that the reset drain node 46 can be designed according to the circuit diagram with the shortest path. In addition, the reset drain node 46 is formed in a layer below the wiring layer 51 including the feedback line 25 and the wiring layer 52 including the vertical signal line 18, which are provided across a plurality of pixels 10. For this reason, the reset drain node 46 has a structure that is less susceptible to noise, and the influence of parasitic capacitance can be reduced.

[0112] 5, the first capacitance element 41 is provided so as to occupy most of the pixel 10 in plan view. The shape of the first capacitance element 41 in plan view is substantially rectangular, and an opening AP is provided in the center. The shape of the first capacitance element 41 in plan view is substantially the same as the shape of the upper electrode 41a in plan view. The opening AP is a through hole for passing the connection portion 50. The position where the opening AP is provided is not particularly limited.

[0113] 3, in the present embodiment, the first capacitance element 41 overlaps at least a part of the impurity region 2a in a plan view. Specifically, at least one of the upper electrode 41a and the lower electrode 41c overlaps the impurity region 2a. For example, both the upper electrode 41a and the lower electrode 41c cover the entire impurity region 2a. That is, in a plan view, the entire impurity region 2a is located inside the upper electrode 41a and the lower electrode 41c.

[0114] The upper electrode 41a and the lower electrode 41c each have a light-shielding property. Therefore, light that is incident on the imaging device 100 and travels through the interlayer insulating layer 4 without being photoelectrically converted by the photoelectric conversion unit 15 is blocked by the upper electrode 41a or the lower electrode 41c. This makes it possible to suppress light that reaches the impurity region 2a. When light is incident on the impurity region 2a, charges are generated, which may cause noise. By suppressing the light that reaches the impurity region 2a, it is possible to reduce noise.

[0115] [3. Manufacturing method] Next, the manufacturing method of the imaging device 100 according to the present embodiment, particularly the process of manufacturing the first capacitance element 41, will be described with reference to Fig. 6A to Fig. 6I. Fig. 6A to Fig. 6I are cross-sectional views for explaining a plurality of steps included in the process of manufacturing the first capacitance element 41. The following description focuses on one trench portion 41e, but the same applies to the trench portion 41f.

[0116] First, as shown in FIG. 6A, vias v1 and v3 are formed in an insulating layer 4b formed above a semiconductor substrate 2 (not shown). At this time, a via v2 is also formed at the same time, although not shown in FIG. 6A. Specifically, a silicon oxide film is first formed as the insulating layer 4b by a plasma CVD (Chemical Vapor Deposition) method or the like. Then, the formed insulating layer 4b is patterned by photolithography and etching to form contact holes h1 and h3. Next, a metal material such as tungsten (W) or copper (Cu) is filled into the contact holes h1 and h3 by a vapor deposition method, a sputtering method, a CVD method, plating, or the like, to form the vias v1 and v3.

[0117] 6A, in addition to the via v1, a via v3 is formed at the same time. The via v3 is a part of the via 50d included in the connection portion 50 connected to the second electrode 15c of the photoelectric conversion portion 15.

[0118] Next, as shown in FIG. 6B, insulating layer 71 and insulating layer 4c are sequentially formed on the entire surface of insulating layer 4b by plasma CVD. Insulating layer 71 is, for example, a silicon carbonitride film (SiCN film). Insulating layer 4c is, for example, a silicon oxide film. The silicon carbonitride film can suppress diffusion of metal contained in vias v1 and v3. Note that illustration of insulating layer 71 is omitted in FIG. 3. Also, the formation of insulating layer 71 is not essential and may be omitted.

[0119] Next, as shown in FIG. 6C, a trench 4t is formed by dry etching, penetrating the insulating layer 71 and the insulating layer 4c. The trench 4t is a through hole for exposing the via v1. When the first capacitive element 41 includes multiple trench portions, the multiple trenches are formed simultaneously. For example, the trench 4t and the trench 4u are formed simultaneously.

[0120] Next, as shown in FIG. 6D, a lower electrode 41c is formed. Specifically, first, a conductive thin film such as a titanium nitride film is formed. The titanium nitride film is formed by, for example, ALD (Atomic Layer Deposition) or plasma CVD. Next, a resist mask is formed on the conductive thin film formed, and then a part of the conductive thin film is removed by, for example, dry etching using chlorine (Cl2) gas, and the resist mask is removed by oxygen ashing. As a result, a lower electrode 41c patterned in a predetermined shape is formed as shown in FIG. 6D.

[0121] In addition, the contact resistance between the lower electrode 41c and the via v1 can be reduced by successively performing the step of forming the trench 4t and the step of forming the conductive thin film that constitutes the lower electrode 41c. In the step of forming the trench 4t, the surface of the via v1 needs to be exposed to plasma, so the state of the surface where the via v1 is exposed is activated. By forming a conductive thin film on top of this, metallic bonds are easily formed between the conductive thin film and the via v1, so the contact resistance can be suppressed.

[0122] Next, as shown in FIG. 6E, a dielectric layer 41b is formed. Specifically, first, a dielectric film is formed on the entire surface of the insulating layer 4c so as to cover the lower electrode 41c. The dielectric film is, for example, a hafnium oxide film. The hafnium oxide film is formed by, for example, the ALD method or the plasma CVD method. Next, a resist mask is formed on the formed dielectric film, and then, for example, a part of the dielectric film is removed by dry etching using chlorine gas, and the resist mask is removed by oxygen ashing. As a result, as shown in FIG. 6E, a dielectric layer 41b patterned in a predetermined shape is formed. At this time, by leaving the dielectric layer 41b larger than the lower electrode 41c, the lower electrode 41c can be completely covered by the dielectric layer 41b so that the end of the lower electrode 41c is not exposed.

[0123] Next, as shown in FIG. 6F, the upper electrode 41a is formed. Specifically, first, a conductive thin film such as a titanium nitride film is formed on the entire surface of the insulating layer 4c so as to cover the dielectric layer 41b. The titanium nitride film is formed by, for example, the ALD method or the plasma CVD method. Next, a resist mask is formed on the conductive thin film formed, and then a part of the conductive thin film is removed by, for example, dry etching using chlorine gas. As a result, as shown in FIG. 6F, the upper electrode 41a patterned in a predetermined shape is formed. At this time, by leaving the upper electrode 41a larger than the dielectric layer 41b, the dielectric layer 41b can be completely covered by the upper electrode 41a so that the end of the dielectric layer 41b is not exposed.

[0124] After forming the lower electrode 41c, the dielectric film and the conductive thin film may be successively formed. After the dielectric film and the conductive thin film are successively formed, the conductive thin film and the dielectric film may be patterned in order to form the upper electrode 41a and the dielectric layer 41b in a predetermined shape. In this case, the end of the upper electrode 41a and the end of the dielectric layer 41b are substantially flush with each other, and the upper electrode 41a and the dielectric layer 41b have substantially the same shape in plan view.

[0125] Through the above steps, the first capacitance element 41 including the flat portion 41d and the trench portion 41e is formed.

[0126] 6G, an insulating layer 4d is formed on the entire surface so as to cover the upper electrode 41a of the first capacitance element 41. The insulating layer 4d is, for example, a silicon oxide film.

[0127] Next, as shown in Fig. 6H, vias v4 and v5 and wiring layers 50b and 53 are formed. The vias v4 and v5 are formed in the same manner as the vias v1 and v3. That is, after forming contact holes by photolithography and etching, the formed contact holes are filled with a metal material to form the vias v4 and v5.

[0128] The via v4 is a part of the via 50d included in the connection portion 50. Although the via v5 and the wiring layer 53 are not shown in Fig. 3, they are parts that electrically connect the upper electrode 41a of the first capacitance element 41 and the sensitivity adjustment line 32. In Fig. 6H, the via v5 is provided so as to penetrate the upper electrode 41a, but the via v5 may be in contact with the upper surface of the upper electrode 41a.

[0129] 6I, an insulating layer 4e is formed, and vias 50e and v6 and wiring layers 50c and 54 are formed. The specific formation method is similar to the formation method of the insulating layer 4d, and the formation method of the vias v4 and v5 and wiring layers 50b and 53.

[0130] By repeating the formation of the insulating layer, the via, and the wiring layer, it is possible to form the interlayer insulating layer 4 consisting of a desired number of laminated layers. This makes it possible to draw out various signal lines including the sensitivity adjustment line 32 to the outside of the pixel region.

[0131] [4. Modifications] Here, a modification of the first embodiment will be described with reference to FIG.

[0132] 7 is a schematic cross-sectional view of a pixel 11 included in an imaging device according to this modification. As shown in FIG. 7, an electrical contact 41i is provided on a side surface of a trench portion 41f of a first capacitance element 41. Specifically, a lower electrode 41c of the first capacitance element 41 has an electrical contact 41i. The electrical contact 41i is a junction portion between the lower electrode 41c and a wiring layer 55.

[0133] In this modification, the trench portion 41f is provided so as to penetrate the insulating layers 4c and 4g. The insulating layer 4g is an insulating layer located between the insulating layer 4b and the insulating layer 4c. Since the trench portion 41f is provided so as to penetrate the insulating layers 4c and 4g, a wiring layer 55 can be provided between the insulating layer 4c and the insulating layer 4g. This allows a contact 41i to be formed on the side surface of the trench portion 41f.

[0134] The number of insulating layers through which the trench portion 41f penetrates is not limited to two, and may be three or more, which allows a plurality of electrical contacts to be provided at different heights on the side surface of the trench portion 41f.

[0135] The wiring layer 55 is electrically connected to the upper end of the via v2. The wiring layer 55 is formed so as to be exposed on the side surface of the trench 4u provided in the insulating layers 4c and 4g. Thus, by forming the lower electrode 41c along the side surface of the trench 4u, the wiring layer 55 and the lower electrode 41c can be electrically connected. The first capacitance element 41 is connected to the electrode 42a of the second capacitance element 42 through the electrical contact 41i of the lower electrode 41c, the wiring layer 55, and the via v2.

[0136] As described above, the electrical contact of the lower electrode 41c of the first capacitance element 41 does not have to be provided at the bottom of the trench portion 41f, and may be provided at the side surface of the trench portion 41f. Also, the electrical contact of the lower electrode 41c may be provided at the flat portion 41d of the first capacitance element 41.

[0137] (Embodiment 2) Next, a second embodiment will be described.

[0138] The imaging device according to embodiment 2 is different from the imaging device according to embodiment 1 in the number of trench portions included in the first capacitive element. The following description will focus on the differences from embodiment 1, and the description of the commonalities will be omitted or simplified.

[0139] Fig. 8 is a schematic cross-sectional view of a pixel 110 included in the imaging device according to the present embodiment. Fig. 9 is a schematic plan view showing an example of the shape and arrangement of a first capacitance element 141 and a trench portion included in the pixel 110 included in the imaging device according to the present embodiment.

[0140] 8, the pixel 110 is different from the pixel 10 according to the first embodiment in that the pixel 110 includes a first capacitive element 141 instead of the first capacitive element 41. The first capacitive element 141 includes three or more trench portions. Specifically, as shown in FIG. 9, the first capacitive element 141 includes six trench portions 41e, 41f, 141a, 141b, 141c, and 141d.

[0141] As shown in FIG. 8, the trench portions 41e and 41f are provided with electrical contacts 41g and 41h in the same manner as in the first embodiment. The trench portions 141a, 141b, 141c, and 141d are not provided with electrical contacts. The bottom and side surfaces of the trench portion 141a are in contact with and covered by the insulating layers 4b and 4c, respectively. As shown in FIG. 9, no via is provided that overlaps the trench portion 141a in a plan view. The same is true for the trench portions 141b, 141c, and 141d.

[0142] In this manner, in the present embodiment, the first capacitance element 141 includes many trench portions, so that the capacitance value can be increased. The specification value of the capacitance value of the first capacitance element 141 often varies depending on the type of image sensor. For example, when capturing an image of a bright scene, the reset transistor 36 is turned on, and not only the charge storage node 44 but also the reset drain node 46 can be used as a charge storage portion. In this case, the larger the capacitance value of the first capacitance element 141 is, the less the gate potential of the signal detection transistor 34 rises even if a large amount of charge is stored. This makes it possible to switch the conversion gain, and to provide an image without whiteout even in a bright scene.

[0143] The number of trench portions without electrical contacts is not limited to four. The number of trench portions without electrical contacts may be only one, or may be two, three, or five or more. The number of trench portions with electrical contacts is not limited to two, but may be only one, or may be three or more.

[0144] 8 and 9, in this embodiment, the wiring layers 51 and 52 are provided above the first capacitive element 141. As described above, the wiring layers 51 and 52 include, for example, the vertical signal line 18 and the feedback line 25.

[0145] At this time, a parasitic capacitance occurs between the upper electrode 41a of the first capacitance element 141 and the wiring layers 51 and 52. In particular, the potentials of the vertical signal line 18 and the feedback line 25 vary over time depending on the brightness of each pixel 10. For this reason, the parasitic capacitance component is detected as a noise component of the vertical signal line 18 and the feedback line 25.

[0146] The parasitic capacitance value is proportional to the dielectric constant of the insulating film between the wiring layers 51 and 52 and the upper electrode 41a, and the differential voltage generated between them. On the other hand, in order to reduce the parasitic capacitance value, the upper electrode 41a of the first capacitance element 141 and the wiring layers 51 and 52 may be arranged so as not to overlap with each other, as shown in Fig. 10. This makes it possible to suppress noise components due to the parasitic capacitance. Note that Fig. 10 is a schematic plan view showing an example of the shape and arrangement of the first capacitance element 141 and the trench portion included in the pixel 111 of the imaging device according to the modified example of the second embodiment.

[0147] 8 and 10, in this modification, the area that the first capacitance element 141 occupies in the pixel is reduced in plan view, and therefore the capacitance value of the flat portion 41d of the first capacitance element 141 is reduced.

[0148] On the other hand, in order to realize a desired capacitance value in the first capacitance element 141, it is necessary to ensure a certain electrode area in the first capacitance element 141 in a plan view. There is a trade-off between ensuring this electrode area and suppressing overlap with the wiring layer. In other words, if the electrode area is increased, it becomes difficult to avoid overlap with the wiring layer.

[0149] In contrast, in the first capacitance element 141 according to this modification, by providing a plurality of trench portions 41e, 41f, 141a, 141b, 141c, and 141d while avoiding overlap with the wiring layer in a plan view, it is possible to increase the electrode area by utilizing the side walls of these trench portions. This makes it possible to increase the capacitance value of the first capacitance element 141 while suppressing noise components caused by parasitic capacitance.

[0150] (Embodiment 3) Next, a third embodiment will be described.

[0151] The imaging device according to the embodiment 3 has a different circuit configuration compared to the imaging devices according to the embodiments 1 and 2. In the following, the differences with the embodiments 1 and 2 will be mainly described, and the description of the commonalities will be omitted or simplified.

[0152] Fig. 11 is a diagram showing an example of a circuit configuration of a pixel 210 included in the imaging device according to the present embodiment. As shown in Fig. 11, the pixel 210 is different from the pixel 10 according to the first embodiment in that the pixel 210 does not include a second capacitive element 42 and a feedback transistor 38. The pixel 210 does not include a reset drain node 46. Furthermore, the pixel 210 includes a reset transistor 36 between one of a pair of electrodes of the first capacitive element 41 and the feedback line 25. That is, the reset transistor 36 is provided at the same position as the feedback transistor 38 according to the first embodiment.

[0153] 11, the charge accumulation node 44 is connected to one of a pair of electrodes of the first capacitance element 41. Therefore, the first capacitance element 41 functions as a charge accumulation section. That is, the signal charge generated in the photoelectric conversion section 15 is also accumulated in the first capacitance element 41. This makes it possible to increase the amount of signal charge accumulated in the pixel 210, thereby making it possible to suppress the occurrence of whiteout even in a bright scene.

[0154] Fig. 12 is a schematic cross-sectional view of a pixel 210 included in an imaging device according to the present embodiment. As shown in Fig. 12, instead of the feedback transistor 38 shown in Fig. 3, a reset transistor 36 is provided at the same position as the feedback transistor 38. That is, the impurity region 2b is one of the source region and the drain region of the reset transistor 36. The impurity region 2c is the other of the source region and the drain region of the reset transistor 36.

[0155] 12, the pixel 210 includes a connection portion 250 instead of the connection portion 50. The connection portion 250 does not include the plug P1 and the wiring portion 50a shown in Fig. 3. The connection portion 250 electrically connects the second electrode 15c of the photoelectric conversion unit 15 and the gate electrode 34e of the signal detection transistor 34.

[0156] The gate electrode 34e is connected to the via v2 through the plug P4 and the wiring portion 250a. The via v2 is connected to the lower electrode 41c of the first capacitance element 41 as in the first embodiment. With this configuration, as shown in FIG. 12, the second electrode 15c of the photoelectric conversion unit 15 is connected to the impurity region 2b through the connection portion 250, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the lower electrode 41c of the first capacitance element 41, the via v1, and the plug P3. That is, the second electrode 15c, the connection portion 250, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the lower electrode 41c of the first capacitance element 41, the via v1, the plug P3, and the impurity region 2b function as the charge storage node 44.

[0157] As described above, in this embodiment, the capacity of the charge storage section that stores the signal charge generated in the photoelectric conversion section 15 can be increased, so that the occurrence of whiteout can be suppressed even in bright scenes.

[0158] (Embodiment 4) Next, a fourth embodiment will be described.

[0159] The imaging device according to embodiment 4 differs from the imaging devices according to embodiments 1 to 3 in that an electrical contact is provided on the upper electrode. The following description will focus on the differences from embodiments 1 to 3, and the description of the commonalities will be omitted or simplified.

[0160] Fig. 13 is a schematic cross-sectional view of a pixel 310 included in the imaging device according to the present embodiment. As shown in Fig. 13, the pixel 310 includes a connection portion 350 instead of the connection portion 50 of the pixel 10 according to the first embodiment.

[0161] The connection portion 350 includes a plug P5, a wiring portion 350a, an electrode 342a, vias v7, 350d, 50e, and 50f, and wiring layers 50b and 50c. The connection portion 350 electrically connects the second electrode 15c of the photoelectric conversion portion 15 and the gate electrode 34e of the signal detection transistor 34. Although not shown in FIG. 13, the gate electrode 34e is electrically connected to the impurity region 2a.

[0162] 13, compared to the pixel 10 according to the first embodiment, the pixel 310 includes a first capacitive element 341 and a second capacitive element 342 instead of the first capacitive element 41 and the second capacitive element 42. The first capacitive element 341 has an upper electrode 341a, a dielectric layer 41b, and a lower electrode 41c.

[0163] The upper electrode 341a of the first capacitance element 341 has an electrode portion 342b. The electrode portion 342b is a portion provided so as to extend from the upper electrode 341a onto the upper surface of the insulating layer 4c. Specifically, the electrode portion 342b overlaps a portion of the electrode 342a included in the connection portion 350 in a plan view. As a result, the electrode portion 342b and the portion of the electrode 342a form the second capacitance element 342.

[0164] The upper electrode 341a of the first capacitance element 341 has contacts 341g and 341h. The contacts 341g and 341h are provided on a portion of the upper electrode 341a that extends onto the insulating layer 4c.

[0165] The contact 341g is provided on the bottom surface of the upper electrode 341a. The contact 341g is connected to the via v8, and is connected to the impurity region 2b through the via v8 and the plug P3. That is, the contact 341g is connected to the reset transistor 36 and the feedback transistor 38. In the present embodiment, similarly to the first embodiment, the reset transistor 36 and the feedback transistor 38 are each an example of an electric element to which the contact 341g is electrically connected.

[0166] The contact point 341h is a connection portion between the upper electrode 341a and the electrode portion 342b. That is, the contact point 341h is connected to the second capacitance element 342. In the present embodiment, the second capacitance element 342 is an example of an electric element to which the contact point 341h is electrically connected.

[0167] In the example shown in Fig. 13, a contact 41g is also provided on the lower electrode 41c. The contact 41g is connected to a via v1. Although not shown in Fig. 13, the contact 41g is connected to the sensitivity adjustment line 32 through the via v1.

[0168] As described above, in the imaging device according to the present embodiment, the two contacts 341g and 341h are provided on the upper electrode 341a of the first capacitive element 341. The contacts 341g and 341h are provided on a portion of the first capacitive element 341 other than the trench portion 41e. The contacts 341g and 341h may be provided on the upper surface of the upper electrode 341a. That is, a via provided on the first capacitive element 341 and the upper electrode 341a may be electrically connected.

[0169] Also, at least one contact may be provided on the upper electrode 341a in the trench portion 41e. For example, in FIG. 13, the upper electrode 341a is provided so as to fill the trench 4t, but the upper electrode 341a may be configured with a uniform film thickness even in the trench 4t, and may have a curved shape along the bottom and side surfaces of the trench 4t, similar to the dielectric layer 41b and the lower electrode 41c. In this case, the contact may be provided on the inner bottom surface of the upper electrode 341a in the trench portion 41e. Alternatively, the contact may be provided on the inner side surface of the upper electrode 341a in the trench portion 41e.

[0170] (Embodiment 5) Next, a fifth embodiment will be described.

[0171] The imaging device according to embodiment 5 differs from the imaging devices according to embodiments 1 to 4 in that a photoelectric conversion unit is provided in a semiconductor substrate. The following description will focus on the differences from embodiments 1 to 4, and description of commonalities will be omitted or simplified.

[0172] FIG. 14 is a schematic cross-sectional view of a pixel 410 included in the imaging device according to the present embodiment.

[0173] 14, the pixel 410 includes a photodiode PD instead of the photoelectric conversion unit 15. The photodiode PD is an example of a photoelectric conversion unit, and is, for example, a photodiode having a PN junction. The photodiode PD is formed by an impurity region formed in the semiconductor substrate 2, etc.

[0174] The imaging device according to this embodiment is a back-illuminated CMOS image sensor. The back surface is one of two main surfaces of the semiconductor substrate 2, and is the surface opposite to the main surface on which the interlayer insulating layer 4 is provided. In the imaging device according to this embodiment, light is incident from the back surface side of the semiconductor substrate 2, that is, from above the paper surface in FIG.

[0175] The imaging device according to the present embodiment has a chip stack structure. Specifically, the imaging device includes a first chip 410a and a second chip 410b. The first chip 410a and the second chip 410b are arranged in a vertically overlapping manner, that is, stacked.

[0176] As shown in FIG. 14, the first chip 410a includes a semiconductor substrate 2 and an interlayer insulating layer 4. The second chip 410b includes a semiconductor substrate 402 and an interlayer insulating layer 404. The first chip 410a and the second chip 410b are manufactured and then stacked to form an imaging device including pixels 410. Specifically, the interlayer insulating layer 4 formed on the main surface of the semiconductor substrate 2 and the interlayer insulating layer 404 formed on the main surface of the semiconductor substrate 402 are bonded together. In FIG. 14, the bonded surfaces are typically shown by dashed lines. In this embodiment, the interlayer insulating layer 4 includes five insulating layers 4a, 4b, 4c, 4d, and 4e. The interlayer insulating layer 404 includes two insulating layers 404a and 404b. The number of layers of each of the interlayer insulating layers 4 and 404 is not limited to these.

[0177] 14, the first chip 410a is provided with a reset transistor 36, a feedback transistor 38, and a first capacitance element 141. The second chip 410b is provided with a signal detection transistor 34 and an address transistor 40. The second capacitance element 42 may be provided in the interlayer insulating layer 4 or in the interlayer insulating layer 404. Each element included in the signal detection circuit SC of the pixel 410 may be provided in either the first chip 410a or the second chip 410b.

[0178] 14, insulating layer 4e, which is the uppermost layer (the lower layer on the paper surface) of interlayer insulating layer 4, is provided with a conductive terminal portion 60. Similarly, insulating layer 404b, which is the uppermost layer of interlayer insulating layer 404, is provided with a conductive terminal portion 460. Terminal portion 60 and terminal portion 460 are in contact with each other and connected to each other, thereby enabling electrical connection between each element provided on semiconductor substrate 2 and each element provided on semiconductor substrate 402.

[0179] In this embodiment, a contact 41g is provided on the bottom surface of the trench portion 41e of the first capacitive element 141. The contact 41g is connected to the reset transistor 36 through a via v1.

[0180] In addition, a contact 41h is provided on the bottom surface of the trench portion 41f of the first capacitive element 141. Although not shown in FIG. 14, the contact 41h is electrically connected to the second capacitive element 42. The second capacitive element 42 is provided, for example, in the first chip 410a. In this manner, two or more electric elements to which two or more electrical contacts of the first capacitive element 141 are connected are provided in the first chip 410a on which the first capacitive element 141 is provided.

[0181] The two or more electric elements to which the two or more electrical contacts of the first capacitance element 141 are connected may not be provided in the first chip 410a. At least one electric element or all electric elements may be connected to the second chip 410b.

[0182] Fig. 15 is a schematic cross-sectional view of a pixel 411 included in an imaging device according to this modification. In the pixel 411 shown in Fig. 15, a reset transistor 36 and a first capacitance element 141 are provided in a first chip 410a. A feedback transistor 38 is provided in a second chip 410b. The signal detection transistor 34, the address transistor 40, and the second capacitance element 42 may be provided in the first chip 410a or in the second chip 410b.

[0183] 15, the pixel 411 includes a first capacitance element 341. An upper electrode 341a of the first capacitance element 341 includes contacts 341g and 341i. The contact 341g is electrically connected to the reset transistor 36. That is, the reset transistor 36 is an example of an electric element. The contact 341i is electrically connected to the feedback transistor 38. That is, the feedback transistor 38 is an example of an electric element.

[0184] In this manner, the two or more electric elements to which the two or more contacts of the first capacitive element 341 are connected may be provided on the first chip 410a and the second chip 410b, respectively. That is, the first chip 410a and the second chip 410b may be stacked, so that the contacts and the electric elements are electrically connected to each other.

[0185] (Other embodiments) Although the imaging device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments are also included within the scope of the present disclosure. Fig. 16 is a schematic cross-sectional view of a pixel 12 included in an imaging device according to another modification of the first embodiment. As shown in Fig. 16, in the pixel 12, the upper electrode 41a of the first capacitance element 41 is electrically connected to the sensitivity adjustment line 32 through a via. The sensitivity adjustment line 32 extends from inside the pixel region to outside the pixel region. Outside the pixel region, the sensitivity adjustment line 32 is electrically connected to the pad 70 through a via. Therefore, the upper electrode 41a is electrically connected to the pad 70 through the sensitivity adjustment line 32.

[0186] For example, in the above-described embodiment, the number of insulating layers and wiring layers included in the interlayer insulating layer of the imaging device is not particularly limited, and the position of the capacitive element in the interlayer insulating layer is not particularly limited.

[0187] Also, for example, the number of trench portions included in the first capacitive element may be only one. None of the trench portions included in the first capacitive element may be provided with electrical contacts. In this case, two or more electrical contacts may be provided on the upper electrode in the flat portion of the first capacitive element, or on the lower electrode in the flat portion. The electrical contacts may be provided on either the upper surface or the lower surface of the upper electrode or the lower electrode.

[0188] Furthermore, for example, the dielectric layer 41b may be an insulating film such as a silicon oxide film or a silicon nitride film, instead of a thin film made of a high-k material.

[0189] Also, for example, each transistor included in the signal detection circuit SC of the imaging device may be a P-channel MOSFET. Also, each transistor does not have to be a FET, and may be a bipolar transistor.

[0190] Furthermore, each of the above embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents. [Industrial Applicability]

[0191] The imaging device according to an embodiment of the present disclosure is useful, for example, in an image sensor, a digital camera, etc. For example, the imaging device according to an embodiment of the present disclosure can be used in a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc. [Explanation of symbols]

[0192] 2, 402 Semiconductor substrate 2a, 2b, 2c impurity region 2t, 2u element isolation area 4, 404 Interlayer insulation layer 4a, 4b, 4c, 4d, 4e, 4f, 4g, 71, 404a, 404b insulation layer 4t, 4u trench 10, 11, 110, 111, 210, 310, 410, 411 pixels 15 Photoelectric conversion unit 15a 1st electrode 15b Photoelectric conversion layer 15c 2nd electrode 16 Vertical scanning circuit 17 Storage control line 18 Vertical signal line 19 Load circuit 20 Column signal processing circuit 21 Horizontal signal readout circuit 22 Power wiring 23 Horizontal common signal line 24 Inverting Amplifier 25 Feedback Line 26 Reset signal line 28 Feedback Control Line 30 Address signal line 32 Sensitivity adjustment line 34 Signal detection transistor 34e, 36e, 38e Gate electrodes 34g, 36g, 38g Gate insulation layer 36 Reset transistor 38 Feedback Transistor 40 Address transistor 41, 141, 341 First capacitance element 41a, 341a Upper electrode 41b Dielectric layer 41c lower electrode 41d flat area 41e, 41f, 141a, 141b, 141c, 141d Trench section 41g, 41h, 41i, 341g, 341h, 341i contacts 42, 342 Second capacitance element 42a, 342a electrode 42b Insulating film 44 Charge Storage Node 46 Reset drain node 50, 250, 350 Connection 50a, 250a, 350a Wiring section 50b, 50c, 51, 52, 53, 54, 55 wiring layer 50d, 50e, 50f, 350d, v1, v2, v3, v4, v5, v6, v7, v8 via 60, 460 terminal section 100 Imaging device 342b Electrode part 410a 1st chip 410b Second Chip h1, h3 contact holes AP aperture FC Feedback Circuit P1, P2, P3, P4, P5 plugs PD Photodiode RA pixel area SC signal detection circuit

Claims

1. A semiconductor substrate; a plurality of pixels; Each of the plurality of pixels includes a first capacitance element provided above the semiconductor substrate, the first capacitance element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; At least one of the first electrode and the second electrode has a first electrical contact connected to a first electrical element and a second electrical contact electrically connected to a second electrical element; the first capacitive element includes a first trench portion and a second trench portion; the first electrical contact is disposed in the first trench portion; the second electrical contact is disposed in the second trench portion. Imaging device.

2. (i) the first electrical contact is provided on a bottom surface of the first trench portion; (ii) the second electrical contact is provided on a bottom surface of the second trench portion; or (iii) the first electrical contact is provided on a bottom surface of the first trench portion, and the second electrical contact is provided on a bottom surface of the second trench portion; The imaging device according to claim 1 .

3. The first capacitive element has a third electrical contact electrically connected to a third electrical element different from the first electrical element and the second electrical element; The third electrical contact is provided outside the first trench portion and the second trench portion. The imaging device according to claim 1 .

4. the first capacitive element includes a third trench portion; The third trench portion is not provided with an electrical contact. The imaging device according to claim 1 .

5. the first electrode is provided closer to the semiconductor substrate than the second electrode, and has the first electrical contact and the second electrical contact; The imaging device according to claim 1 .

6. the second electrode is provided farther from the semiconductor substrate than the first electrode, and has the first electrical contact and the second electrical contact; The imaging device according to claim 1 .

7. The first electrode and the second electrode include TiN or TaN. The imaging device according to claim 1 .

8. Further, the semiconductor device includes a plurality of wiring layers provided above the semiconductor substrate, Among the plurality of wiring layers, the number of wiring layers located above the first capacitance element is greater than the number of wiring layers located below the first capacitance element. The imaging device according to claim 1 .

9. the first electrical contact and the second electrical contact are connected to a via; The imaging device according to claim 1 .

10. Each of the plurality of pixels is A photoelectric conversion unit that converts light into an electric charge; an impurity region formed in the semiconductor substrate, the impurity region storing the charge and electrically connected to the photoelectric conversion unit; In a plan view, the first capacitance element overlaps with the entire impurity region. The imaging device according to claim 1 .

11. Each of the plurality of pixels is A photoelectric conversion unit that converts light into an electric charge; an impurity region formed in the semiconductor substrate, the impurity region storing the charge and electrically connected to the photoelectric conversion unit; a transistor electrically connected to the impurity region; a second capacitive element; the transistor is one of the first electric element and the second electric element, the second capacitive element is the other of the first electric element and the second electric element; The imaging device according to claim 1 .

12. the transistor is a reset transistor that resets charges generated in the photoelectric conversion unit and stored in the impurity region; The imaging device according to claim 11.

13. the second capacitance element is electrically connected to the impurity region; 13. The imaging device according to claim 11 or 12.

14. Each of the plurality of pixels is A photoelectric conversion unit that converts light into an electric charge; an impurity region formed in the semiconductor substrate, the impurity region storing the charge and electrically connected to the photoelectric conversion unit; the first electrode is provided closer to the semiconductor substrate than the second electrode and is electrically connected to the impurity region; The second electrode is electrically connected to a pad portion to which a predetermined voltage value is applied. The imaging device according to claim 1 .

15. the imaging device further includes a sensitivity adjustment line electrically connected to the pad portion and the second electrode for adjusting a sensitivity of the imaging device. The imaging device according to claim 14.

16. the imaging device further includes a signal line extending to the plurality of pixels and transmitting a time-varying signal; Each of the plurality of pixels further includes an impurity region formed in the semiconductor substrate, the impurity region storing charges generated by photoelectric conversion; one of the first trench portion and the second trench portion is located between the impurity region and the signal line and on a line connecting the impurity region and at least a part of the signal line; The imaging device according to claim 1 .

17. the imaging device further includes a signal line extending to the plurality of pixels and transmitting a time-varying signal; Each of the plurality of pixels further comprises: A photoelectric conversion unit that converts light into an electric charge; a first via that connects the semiconductor substrate and the photoelectric conversion unit; a second via connecting the signal line and the semiconductor substrate; One of the first trench portion and the second trench portion is located between the first via and the second via and on a line connecting the first via and the second via. The imaging device according to claim 1 .

18. the imaging device further includes a signal line extending to the plurality of pixels and transmitting a time-varying signal; each of the plurality of pixels includes a second via that connects the signal line and the semiconductor substrate; In a plan view, the first capacitive element does not overlap the second via. The imaging device according to claim 1 .

19. Each of the plurality of pixels further comprises: A photoelectric conversion unit that converts light into an electric charge; a first via that connects the semiconductor substrate and the photoelectric conversion unit; In a cross-sectional view, the first via is located between the first trench portion and the second trench portion. The imaging device according to claim 1 .

20. The second electrical element is different from the first electrical element. The imaging device according to claim 1 .

21. The first trench portion is locally disposed with respect to the first capacitance element at a position overlapping the first electrical contact in a plan view; the second trench portion is locally disposed with respect to the first capacitive element at a position overlapping with the second electrical contact in a plan view; The imaging device according to claim 1 .

22. The first trench portion is not arranged so as to reach from one end to the other end of the first capacitive element, The second trench portion is not disposed so as to reach from one end to the other end of the first capacitive element. The imaging device according to claim 1 .

Images