Semiconductor device and electronic device

Abstract

To provide a novel semiconductor device.SOLUTION: A structure extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The structure includes a third conductor, a first insulator, a first semiconductor, and a second insulator. At a first intersection where the structure and the first conductor intersect, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. At a second intersection where the structure and the second conductor intersect, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically outside the third conductor.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), storage devices, and sensors are used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components are being improved in various aspects, including miniaturization and low power consumption.

[0004] In particular, the amount of data handled by the above-mentioned electronic devices is increasing, and there is a demand for storage devices with large storage capacities. As a means for increasing storage capacity, for example, Patent Document 1 and Patent Document 2 disclose a three-dimensional NAND memory element using a metal oxide as a channel formation region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 3060 Brochure [Patent Document 2] Patent Publication No. 2018-207038 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a highly reliable storage device.An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to provide a novel storage device.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0007] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including a processing unit and a memory device, where the processing unit and the memory device have overlapping regions. The memory device has a plurality of memory cells, each of which includes an oxide semiconductor. The memory device is a NAND type memory device having a function of operating as a RAM.

[0009] One aspect of the present invention is a semiconductor device having a structure extending in a first direction, and a first conductor and a second conductor extending in a second direction, the structure having a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor, and at a first intersection where the structure and the first conductor intersect, a second semiconductor adjacent to the second insulator and a third insulator adjacent to the second semiconductor are provided between the structure and the first conductor, At a second intersection where the first structure and the second conductor intersect, the structure has a fourth conductor adjacent to the second insulator and a fourth insulator adjacent to the fourth conductor, and at the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged outside the third conductor, and at the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor, and the fourth insulator are concentrically arranged outside the third conductor.

[0010] The first direction is perpendicular to the second direction. The first intersection functions as a transistor for writing data, and the second intersection functions as a transistor for reading data and a capacitive element.

[0011] The first intersection can function as a transistor, and the second intersection can function as a transistor and a capacitive element. The semiconductor device can function as, for example, a NAND type memory device.

[0012] At least one of the first semiconductor and the second semiconductor is preferably an oxide semiconductor, and the oxide semiconductor preferably contains at least one of indium and zinc.

[0013] Another embodiment of the present invention is an electronic device including at least one of an operation switch, a battery, and a display portion, and any of the above-described semiconductor devices. Effect of the Invention

[0014] According to one embodiment of the present invention, a highly reliable storage device can be provided. Alternatively, a storage device with a large storage capacity can be provided. Alternatively, a new storage device can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a large storage capacity can be provided. Alternatively, a new semiconductor device can be provided.

[0015] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description of the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0016] [Figure 1] 1A is a perspective view of a memory cell, and FIG 1B is a cross-sectional view of the memory cell. [Diagram 2] 2A and 2B are cross-sectional views of a memory cell. [Diagram 3] 3A and 3B are cross-sectional views of a memory cell. [Figure 4] 4A to 4C are equivalent circuit diagrams of a memory cell. [Diagram 5] 5(A) and (B) are equivalent circuit diagrams of a memory cell. [Figure 6] FIG. 6 is a cross-sectional view of a memory string. [Figure 7] FIG. 7 is an equivalent circuit diagram of a memory string. [Figure 8] FIG. 8 is an equivalent circuit diagram of a memory string. [Figure 9] FIG. 9 is an equivalent circuit diagram of a memory string. [Figure 10] FIG. 10 is an equivalent circuit diagram of a memory string. [Figure 11] 11(A) and (B) are top views of a memory string. [Figure 12] 12(A) and (B) are cross-sectional views of a memory cell. [Figure 13] 13(A) and (B) are cross-sectional views of a memory cell. [Figure 14] FIG. 14 is a cross-sectional view of a memory cell. [Figure 15] FIG. 15 is a cross-sectional view of a memory cell. [Figure 16] 16(A) and (B) are cross-sectional views of a memory cell. [Figure 17] 17(A) and (B) are cross-sectional views of a memory cell. [Figure 18] Figure 18(A) is a perspective view of a memory cell, and Figure 18(B) is a cross-sectional view of the memory cell. [Figure 19] Figure 19(A) is a perspective view of a memory cell, and Figure 19(B) is a cross-sectional view of the memory cell. [Figure 20] 20(A) and (B) are cross-sectional views of a memory cell. [Figure 21] FIG. 21 is a cross-sectional view of a memory cell. [Figure 22] 22(A) and (B) are cross-sectional views of a memory cell. [Figure 23] 23(A) and (B) are cross-sectional views of a memory cell. [Figure 24] 24(A) and (B) are cross-sectional views of a memory cell. [Diagram 25] 25(A) and (B) are cross-sectional views of a memory cell. [Figure 26] FIG. 26 is a top view of a memory string. [Figure 27]Fig. 27(A) is a diagram for explaining classification of crystal structures of oxide semiconductors, Fig. 27(B) is a diagram for explaining an XRD spectrum of a CAAC-IGZO film, and Fig. 27(C) is a diagram for explaining a micro-electron beam diffraction pattern of a CAAC-IGZO film. [Figure 28] 28(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 29] 29(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 30] 30(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 31] 31(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 32] 32(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 33] 33(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 34] Fig. 34(A) is a cross-sectional view illustrating a method for manufacturing a memory cell, and Fig. 34(B) is a perspective view illustrating a method for manufacturing a memory cell. [Diagram 35] 35(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 36] 36(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 37] FIG. 37 is a circuit diagram of the semiconductor device. [Figure 38] 38(A) and (B) are timing charts illustrating an example of the operation of the semiconductor device. [Figure 39] Fig. 39(A) is a perspective view illustrating a configuration example of a semiconductor device, Fig. 39(B) is a top view illustrating a configuration example of a semiconductor device, and Fig. 39(C) is a cross-sectional view illustrating a configuration example of a semiconductor device. [Diagram 40]Fig. 40(A) is a perspective view illustrating a configuration example of a semiconductor device, Fig. 40(B) is a top view illustrating a configuration example of a semiconductor device, and Fig. 40(C) is a cross-sectional view illustrating a configuration example of a semiconductor device. [Diagram 41] 41(A) and (B) are cross-sectional views illustrating a semiconductor device. [Diagram 42] 42(A) and (B) are cross-sectional views illustrating a semiconductor device. [Diagram 43] FIG. 43 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 44] 44A to 44G are diagrams illustrating examples of circuit configurations of memory cells. [Diagram 45] 45(A) and (B) are diagrams illustrating an example of a circuit configuration of a memory cell. [Figure 46] 46A to 46C are perspective views illustrating configuration examples of a semiconductor device. [Figure 47] FIG. 47(A) is a perspective view showing an example of a semiconductor wafer, FIG. 47(B) is a perspective view showing an example of a chip, and FIGS. 47(C) and (D) are perspective views showing an example of an electronic component. [Figure 48] FIG. 48 is a block diagram illustrating the CPU. [Figure 49] 49(A) and (B) are perspective views of a semiconductor device. [Figure 50] 50(A) and (B) are perspective views of a semiconductor device. [Figure 51] 51(A) and (B) are perspective views of a semiconductor device. [Figure 52] 52(A) and (B) are diagrams showing various storage devices by hierarchical level. [Diagram 53] 53A to 53J are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 54] 54(A) to 54(E) are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 55] 55(A) to (C) are diagrams illustrating an example of an electronic device. [Figure 56] FIG. 56 is a diagram for explaining an example of the configuration of a computer system. [Figure 57] Figure 57 is a diagram showing the hierarchical structure of IoT networks and trends in required specifications. [Figure 58] Figure 58 is an image diagram of factory automation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices.

[0018] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in the figure or text. X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0019] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling its on and off state. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0020] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0021] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0022] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0023] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0024] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance", "load", and "region having a resistance value", and conversely, the terms "resistance", "load", and "region having a resistance value" can be replaced with terms such as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0025] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance appearing between wirings, a gate capacitance appearing between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0026] In addition, in this specification, etc., a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, etc., the terms source and drain can be replaced. In addition, in this specification, etc., when explaining the connection relationship of a transistor, the notation "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source or drain" (or the second electrode, or the second terminal) are used. Note that, depending on the structure of the transistor, in addition to the above-mentioned three terminals, a backgate may be provided. In this case, in this specification, etc., one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0027] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0028] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0029] In addition, in this specification and the like, the terms "high level potential (also referred to as "high level potential", "H potential", or "H")" and "low level potential (also referred to as "low level potential", "L potential", or "L")" do not mean any specific potential. For example, when two wirings are both described as "functioning as wirings that supply a high level potential", the high level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low level potential", the low level potentials provided by both wirings do not have to be equal to each other.

[0030] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and the amount of current is described as a positive value. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and the amount of current is described as a negative value. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0031] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0032] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] In addition, the positional relationship of the components changes appropriately depending on the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, etc., and can be appropriately rephrased depending on the situation. For example, in this specification, etc., words and phrases indicating the arrangement, such as "above" and "below," may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Therefore, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing by 180 degrees. Also, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left surface (or right surface) of the conductor" by rotating the orientation of the drawing by 90 degrees.

[0034] Similarly, in this specification and the like, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state where "electrode B is formed on insulating layer A", but does not exclude the state where "electrode B is formed under insulating layer A" or "electrode B is formed on the right (or left) side of insulating layer A", etc.

[0035] In addition, in this specification, the terms "adjacent" and "close to" do not limit the components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0037] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wiring" are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0038] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0039] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, or a transition metal other than the main component, and in particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, oxygen, a Group 1 element other than hydrogen, a Group 2 element, a Group 13 element, or a Group 15 element, and the like.

[0040] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0043] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0044] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. "Approximately parallel" or "generally parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. "Approximately perpendicular" or "generally perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. "Orthogonal" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0045] In this specification and elsewhere, when referring to counting and measurement values, or to objects, methods, and events that can be converted into counting or measurement values, terms such as "same," "equal," and "uniform" are intended to include an error of plus or minus 20% unless expressly stated.

[0046] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0047] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0048] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0049] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0050] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0051] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0052] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will easily understand that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or top views.

[0053] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include signal, voltage, or current variations due to noise, or signal, voltage, or current variations due to timing deviations.

[0054] In this specification and the like, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, “[m,n]”, etc. may be added to the reference symbol. For example, one of two wirings GL may be written as wiring GL[1] and the other as wiring GL[2].

[0055] (Embodiment 1) FIG. 1A shows a perspective view of a memory cell 100 according to one embodiment of the present invention. The memory cell 100 is a storage device having a three-dimensional stacked structure. In FIG. 1A, a part of the memory cell 100 is omitted in order to make the internal structure of the memory cell 100 easier to understand. In the drawings, arrows indicating the X direction, the Y direction, and the Z direction may be added. The X direction, the Y direction, and the Z direction are directions perpendicular to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction may be called the "first direction" or the "first direction". The other one may be called the "second direction" or the "second direction". The remaining one may be called the "third direction" or the "third direction". In FIG. 1 and the like, the direction parallel to the central axis 108 is the Z direction.

[0056] <Memory cell configuration example> FIG. 1(B) is a cross-sectional view showing a part of the memory cell 100 shown in FIG. 1(A). FIG. 1(B) is a cross-sectional view showing a part of the memory cell 100 seen from the Y direction. FIG. 1(B) is a cross-sectional view of an XZ plane passing through a central axis 108. FIG. 3(A) is a cross-sectional view showing a portion A1-A2 shown by a dashed line in FIG. 1(B) seen from the Z direction. FIG. 3(B) is a cross-sectional view showing a portion B1-B2 shown by a dashed line in FIG. 1(B) seen from the Z direction.

[0057] The memory cell 100 has a plurality of insulators 101 arranged above a substrate (not shown). The plurality of insulators 101 are stacked in order from the substrate side. In the present embodiment and the like, the i-th (i is an integer of 1 or more) insulator 101 is indicated as insulator 101[i]. FIG. 1(B) shows an insulator 101[i+1] arranged above the insulator 101[i] and an insulator 101[i+2] arranged above the insulator 101[i+1]. In addition, the memory cell 100 has a conductor 102 between the insulator 101[i] and the insulator 101[i+1], and has a conductor 103 between the insulator 101[i+1] and the insulator 101[i+2]. The insulator 101, the conductor 102, and the conductor 103 extend along the Y direction.

[0058] The memory cell 100 also has a structure 130. The structure 130 extends in the Z direction along the central axis 108. The structure 130 has a columnar or cylindrical shape. The structure 130 shown in FIGS. 1 to 3 includes an insulator 111, a conductor 112, a semiconductor 113, a semiconductor 114, an insulator 115, a semiconductor 116, an insulator 117, and a conductor 118. FIG. 2(A) shows a cross-sectional view in which the structure 130 is omitted.

[0059] In the present embodiment and the like, the outer peripheral shape of the structure 130 is shown as being circular when viewed from the Z direction, but the outer peripheral shape of the structure 130 does not have to be circular. For example, it may be a polygon such as a triangle or a rectangle. In addition, the outer peripheral shape of the structure 130 may be formed by curved lines, or may be formed by a combination of curved lines and straight lines. In addition, as shown in FIG. 1 and FIG. 2, the structure 130 has unevenness on the side surface extending in the Z direction.

[0060] The memory cell 100 also has a region 132. The region 132 is a region formed by removing parts of the insulator 101 and the conductor 103 during the manufacturing process of the memory cell 100. The region 132 includes a semiconductor 121, an insulator 122, an insulator 123, a conductor 102, and the like. To make the region 132 easier to recognize, FIG. 2B shows a cross-sectional view in which components provided in the region 132 are not illustrated.

[0061] Region 132 is provided around structure 130. Region 132 has region 135 overlapping with a recess of structure 130 and region 136 overlapping with a protrusion of structure 130 when viewed from a direction perpendicular to the Z direction (see FIGS. 2(A) and 2(B)). Region 136 has a region overlapping with structure 130 via insulator 101 and a region overlapping with structure 130 via conductor 103.

[0062] As described above, the structure 130 has a columnar or cylindrical shape. Specifically, the conductor 118 extends in the Z direction along the central axis 108, and the insulator 117 is provided adjacent to the conductor 118. The semiconductor 116 is provided adjacent to the insulator 117. The insulator 115 is provided adjacent to the semiconductor 116. The semiconductor 114 is provided adjacent to the insulator 115. In addition, in the convex portion of the structure 130, the semiconductor 113 is provided adjacent to the semiconductor 114, the conductor 112 is provided adjacent to the semiconductor 113, and the insulator 111 is provided adjacent to the conductor 112.

[0063] 3A, in the recess of structure 130, insulator 117, semiconductor 116, insulator 115, and semiconductor 114 are provided concentrically outside conductor 118. In addition, in the recess of structure 130, semiconductor 121 is provided adjacent to semiconductor 114, and insulator 122 is provided adjacent to semiconductor 121. In addition, conductor 102 extending in the Y direction intersects with the recess of structure 130.

[0064] In the region where the structure 130 intersects with the conductor 102 (overlapping region), the conductor 118, the insulator 117, the semiconductor 116, the insulator 115, and the semiconductor 114, as well as the semiconductor 121, the insulator 122, and the conductor 102 function as a transistor WTr. Therefore, it can be said that the transistor WTr is formed at the intersection of the structure 130 and the conductor 102.

[0065] In the memory cell 100, the conductor 102 functions as a gate electrode of the transistor WTr. Thus, the insulator 122 functions as a gate insulator. The semiconductor 121 can also function as a gate insulator. The semiconductor 114 functions as a semiconductor in which a channel is formed. The conductor 118 may function as a backgate electrode. Thus, the insulator 117, the semiconductor 116, and the insulator 115 may function as a backgate insulator. FIG. 3A is also a cross-sectional view of the transistor WTr as viewed from the Z direction.

[0066] 3B, insulator 117, semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, conductor 112, and insulator 111 are provided concentrically outside conductor 118 in the convex portion of structure 130. In addition, conductor 103 extending in the Y direction intersects with the convex portion of structure 130.

[0067] The conductor 118, insulator 117, semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, and conductor 112 in the region of the structure 130 that intersects with the conductor 103 (overlapping region) function as a transistor RTr. In addition, the region where the conductor 103, insulator 111, and conductor 112 overlap functions as a capacitance element Cs. In other words, it can be said that the transistor RTr and the capacitance element Cs are formed at the intersection of the structure 130 and the conductor 103.

[0068] In the transistor RTr, the conductor 112 functions as the gate electrode of the transistor RTr. The semiconductor 113 and the semiconductor 114 may also function as the gate electrode of the transistor RTr. In the transistor RTr, the insulator 115 functions as a gate insulating layer, and the semiconductor 116 functions as a semiconductor in which a channel is formed. As described above, the conductor 118 may function as a back gate electrode. Therefore, the insulator 117 may function as a back gate insulating layer. FIG. 3B is also a cross-sectional view of the transistor RTr and the capacitor Cs as viewed from the Z direction.

[0069] 4A shows an equivalent circuit diagram of the memory cell 100. In FIG. 4A, one of the source and the drain of the transistor WTr is electrically connected to a conductor 112, and the other of the source and the drain of the transistor WTr is electrically connected to the gate of the transistor RTr. The gate of the transistor WTr is electrically connected to a conductor 102. One electrode of the capacitance element Cs is electrically connected to the gate of the transistor RTr, and the other electrode of the capacitance element Cs is electrically connected to a conductor 103.

[0070] In this specification and the like, a node at which the gate of the transistor RTr, the other of the source or drain of the transistor WTr, and one electrode of the capacitance element Cs are electrically connected is called a node ND.

[0071] A part of the semiconductor 116 functions as a channel formation region of the transistor RTr. Another part of the semiconductor 116 functions as the source or drain of the transistor RTr. The transistor RTr shown in FIG. 4A is a transistor having a backgate. In this embodiment, a part of the conductor 118 functions as the backgate of the transistor RTr. A part of the conductor 102 functions as the gate of the transistor WTr. A part of the conductor 103 functions as the other electrode of the capacitance element Cs. A part of the conductor 112 functions as one of the source or drain of the transistor WTr.

[0072] Also, as shown in FIG. 4B, a backgate may not be provided in the transistor RTr. FIG. 4B corresponds to an equivalent circuit diagram of a memory cell 100H described later. Also, as shown in FIG. 4C, a backgate may be provided in the transistor WTr. Although FIG. 4C shows an example of a circuit configuration in which the backgate of the transistor WTr is electrically connected to the conductor 118, a conductor other than the conductor 118 may be provided to electrically connect to the backgate of the transistor WTr. Alternatively, a circuit configuration as shown in FIG. 5A or FIG. 5B may be used.

[0073] FIG. 6 shows a cross-sectional view of a memory string 200 including four memory cells 100 (memory cell 100[1] to memory cell 100[4]). FIG. 7 shows an equivalent circuit diagram of the memory string 200. The memory string 200 has a configuration in which four memory cells 100 are connected in series. Thus, the memory string 200 is a storage device such as a NAND type.

[0074] In addition, in an equivalent circuit diagram or the like, in order to clearly indicate that the transistor is preferably an OS transistor, "OS" may be added to the circuit symbol of the transistor. Similarly, in order to clearly indicate that the transistor is preferably a Si transistor (a transistor using silicon in a semiconductor layer in which a channel is formed), "Si" may be added to the circuit symbol of the transistor. In FIG. 7, the transistors WTr and RTr are shown to be OS transistors.

[0075] Moreover, the memory string 200 shown in FIG. 6 includes nine layers of insulators 101 (insulator 101[1] to insulator 101[9]), four layers of conductors 102 (conductor 102[1] to conductor 102[4]), and four layers of conductors 103 (conductor 103[1] to conductor 103[4]).

[0076] 7, the transistor WTr, the transistor RTr, and the capacitance element Cs of the memory cell 100[1] are shown as the transistor WTr[1], the transistor RTr[1], and the capacitance element Cs[1], respectively. The transistors WTr, the transistors RTr, and the capacitance elements Cs of the memory cells 100[2] to 100[4] are also shown in the same manner.

[0077] It should be noted that the number of memory cells 100 included in the memory string 200 is not limited to 4. If the number of memory cells 100 included in the memory string 200 is n, n may be any integer equal to or greater than 2.

[0078] In addition, "a configuration in which multiple memory cells 100 are connected in series" refers to a configuration in which the drain (or source) of transistor WTr[k] included in memory cell 100[k] (k is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the source (or drain) of transistor WTr[k+1] included in memory cell 100[k+1], and the drain (or source) of transistor RTr[k] included in memory cell 100[k] is electrically connected to the source (or drain) of transistor RTr[k+1] included in memory cell 100[k+1].

[0079] The semiconductor in which the channels of the transistors WTr and RTr are formed may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, either alone or in combination. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0080] Note that the semiconductor used in the transistor may be a stack of semiconductors. When semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used.

[0081] In particular, the transistor WTr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. An oxide semiconductor has a band gap of 2 eV or more, and therefore has an extremely low off-state current. When an OS transistor is used for the transistor WTr, charge written to the node ND (also referred to as a "storage node") can be held for a long period of time. When an OS transistor is used as a transistor constituting the memory cell 100, the memory cell 100 can be called an "OS memory." In addition, a memory string 200 including the memory cell 100 can also be called an "OS memory."

[0082] A NAND type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device that has multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0083] The transistor RTr may be a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a "Si transistor"). The transistor RTr may be a Si transistor, and the transistor WTr may be an OS transistor. FIG. 8 shows an equivalent circuit diagram of a memory string 200 in which an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr.

[0084] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0085] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0086] In addition, since OS memory writes charge to a node via an OS transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration and is highly reliable compared to conventional flash memory.

[0087] In addition, unlike magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), OS memory does not undergo structural changes at the atomic level when data is rewritten. Therefore, OS memory has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0088] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation even in a high-temperature environment, and is highly reliable. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation even in a high-temperature environment and has good reliability can be realized.

[0089] Note that, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr as shown in Fig. 9. Also, depending on the purpose or application, a Si transistor may be used as both the transistor WTr and the transistor RTr as shown in Fig. 10.

[0090] By providing a plurality of memory cells 100 consecutively in the Z direction, like the memory string 200, the storage capacity per unit area can be increased.

[0091] Furthermore, when it is desired to increase the storage capacity of a semiconductor device using memory cells 100 or memory strings 200, a plurality of memory cells 100 or a plurality of memory strings 200 may be arranged in a staggered pattern (see FIG. 11A) or a lattice pattern (see FIG. 11B). FIG. 11 is a top view of a memory string.

[0092] Table 1 shows a comparison table between 3D NAND type memory devices made with Si transistors and 3D OS NAND type memory devices.

[0093] [Table 1]

[0094] [Modifications] Next, a description will be given of modified examples of the memory cell 100. The modified examples of the memory cell described below can be appropriately combined with other memory cells shown in this specification and the like.

[0095] 12A shows a cross-sectional view of a memory cell 100A. The memory cell 100A is a modified example of the memory cell 100. Therefore, in this embodiment and the like, differences between the memory cell 100A and the memory cell 100 will be mainly described.

[0096] 12A, a memory cell according to one embodiment of the present invention may be obtained by removing the semiconductor 121, the insulator 122, and the conductor 102 from regions that do not overlap with the insulator 101 and / or the conductor 103 when viewed in the Z direction. Thus, the insulator 123 in the memory cell 100A may have a region in contact with the insulator 101, a region in contact with the conductor 103, a region in contact with the semiconductor 121, a region in contact with the insulator 122, and a region in contact with the conductor 102.

[0097] 12B shows a cross-sectional view of memory cell 100B. Memory cell 100B is a modified example of memory cell 100A. As in memory cell 100B, the formation of semiconductor 121 may be omitted. In memory cell 100B, the conductor 118, insulator 117, semiconductor 116, insulator 115, and semiconductor 114, as well as the insulator 122 and conductor 102 in a region that intersects with the conductor 102 of the structure 130 (overlapping region) function as a transistor WTr. By not providing the semiconductor 121, the manufacturing process can be simplified and the productivity of the memory device can be improved.

[0098] 13A shows a cross-sectional view of a memory cell 100C. The memory cell 100C is a modified example of the memory cell 100A. As in the memory cell 100C, the formation of the semiconductor 113 may be omitted, and the conductor 112 and the semiconductor 114 may be in contact with each other. In the memory cell 100C, the conductor 118, the insulator 117, the semiconductor 116, the insulator 115, the semiconductor 114, and the conductor 112 in a region that intersects with the conductor 103 of the structure 130 (an overlapping region) function as a transistor RTr. By not providing the semiconductor 113, the manufacturing process can be simplified, and the productivity of the memory device can be improved.

[0099] FIG. 13B shows a cross-sectional view of memory cell 100D. Memory cell 100D is a modified example of memory cell 100B and also a modified example of memory cell 100C. Like memory cell 100D, the formation of semiconductor 113 may be omitted, and the conductor 112 and semiconductor 114 may be in contact with each other. The transistor WTr in memory cell 100D has the same structure as memory cell 100B. Moreover, the transistor RTr in memory cell 100D has the same structure as memory cell 100C. By not providing the semiconductor 113 and the semiconductor 121, the manufacturing process can be simplified, and the productivity of the memory device can be improved.

[0100] FIG. 14 shows a cross-sectional view of memory cell 100E. FIG. 14 shows cross-sectional views of memory cell 100E[k] and memory cell 100E[k+1] adjacent to memory cell 100E[k]. Memory cell 100E is a modified example of memory cell 100A. As in memory cell 100E, the formation of insulator 101 may be omitted and the conductor 103 and semiconductor 121 may be in contact with each other. By not providing insulator 101, the manufacturing process can be simplified and the productivity of the memory device can be improved.

[0101] FIG. 15 shows a cross-sectional view of memory cell 100F. FIG. 15 shows cross-sectional views of memory cell 100F[k] and memory cell 100F[k+1] adjacent to memory cell 100F[k]. Memory cell 100F is a modified example of memory cell 100B. Like memory cell 100F, the formation of insulator 101 may be omitted, and conductor 103 and insulator 122 may be in contact with each other. Also, like memory cell 100D, the formation of semiconductor 113 may be omitted. By not providing insulator 101 and / or semiconductor 113, the manufacturing process can be simplified, and the productivity of the memory device can be improved.

[0102] FIG. 16A shows a cross-sectional view of a memory cell 100G. The memory cell 100G is a modification of the memory cell 100A. As in the memory cell 100G, the semiconductor 114 may be a stack of a semiconductor 114a and a semiconductor 114b. FIG. 16A shows an example in which the semiconductor 114a is provided in contact with the insulator 115, and the semiconductor 114b is provided in contact with the semiconductor 114a. The stacked structure is not limited to two layers, and may be three or more layers. The semiconductor 116 may also be a stack of multiple semiconductor layers. The composition of the semiconductor 114 when it is a stack of oxide semiconductors will be described in detail later.

[0103] FIG 16B shows a cross-sectional view of memory cell 100H. Memory cell 100H is a modified example of memory cell 100A. Unlike memory cell 100H, the conductor 118 does not have to be provided. In FIG 16B, an insulator 117 is used instead of the conductor 118. The conductor 118 may be omitted and a cavity may be formed. By not providing the conductor 118, the manufacturing process can be simplified and the productivity of the memory device can be improved.

[0104] In the memory cell 100H, the semiconductor 116, the insulator 115, and the semiconductor 114, and the semiconductor 121, the insulator 122, and the conductor 102 in the region intersecting (overlapping) with the conductor 102 of the structure 130 function as a transistor WTr. In the memory cell 100H, the semiconductor 116, the insulator 115, the semiconductor 114, the semiconductor 113, and the conductor 112 in the region intersecting (overlapping) with the conductor 103 of the structure 130 function as a transistor RTr.

[0105] FIG. 17A shows a cross-sectional view of memory cell 100I. Memory cell 100I is a modified example of memory cell 100. Unlike memory cell 100I, the semiconductor 121 does not need to be provided. By not providing the semiconductor 121, the manufacturing process can be simplified and the productivity of the memory device can be improved. Memory cell 100I is also a modified example of memory cell 100B. The transistors WTr and RTr in memory cell 100I have the same configuration as those in memory cell 100B.

[0106] FIG. 17B shows a cross-sectional view of memory cell 100J. Memory cell 100J is a modified example of memory cell 100 and is also a modified example of memory cell 100D. Unlike memory cell 100J, semiconductor 121 and semiconductor 113 do not need to be provided. By not providing semiconductor 121 and semiconductor 113, the manufacturing process can be simplified and the productivity of the memory device can be improved. Memory cell 100J is also a modified example of memory cell 100I. Transistor WTr and transistor RTr in memory cell 100J have the same configuration as memory cell 100D.

[0107] Fig. 18(A) shows a perspective view of memory cell 100K. Fig. 18(B) shows a cross-sectional view of a portion of memory cell 100K. Note that in Fig. 18(A), a portion of memory cell 100K is omitted in order to make the internal structure of memory cell 100K easier to understand.

[0108] The memory cell 100K is a modified example of the memory cell 100G. In the memory cell 100G, the semiconductor 114 is a stack of semiconductors 114a and 114b, but in the memory cell 100K, the semiconductor 116 is further formed into a stack of semiconductors 116a, 116b, and 116c. Note that the composition and other details of the case where the semiconductor 116 is a stack of oxide semiconductors will be described later.

[0109] 18 shows an example in which a semiconductor 116a is provided in contact with the insulator 117, a semiconductor 116b is provided in contact with the semiconductor 116a, a semiconductor 116c is provided in contact with the semiconductor 116b, and an insulator 115 is provided in contact with the semiconductor 116c. The insulator 115 may have a layered structure in which a plurality of insulators are combined. Note that a combination in the case where the insulator 115 is a layered structure of a plurality of insulators will be described in detail later.

[0110] The memory cell 100K has a stacked structure of a semiconductor 116a, a semiconductor 116b, a semiconductor 116c, an insulator 115, a semiconductor 114a, a semiconductor 114b, a semiconductor 121, and an insulator 122. This region may function like a superlattice. The insulator 122 may have a stacked structure combining a plurality of insulators. The combination of the insulator 122 as a stack of a plurality of insulators will be described in detail later.

[0111] In addition, in the memory cell 100K, the conductor 102 is a stack of conductors 102f and 102s. In Fig. 18, the conductor 102f is provided in contact with the insulator 122, and the conductor 102s is provided in contact with the conductor 102f. The configuration in the case where the conductor 102 has a stacked structure will be described in detail later.

[0112] Fig. 19(A) shows a perspective view of the memory cell 100L. Fig. 19(B) shows a cross-sectional view of a portion of the memory cell 100L. Note that in Fig. 19(A), a portion of the memory cell 100L is omitted in order to make the internal structure of the memory cell 100L easier to understand.

[0113] The memory cell 100L is a modified example of the memory cell 100. Therefore, in this embodiment and the like, differences between the memory cell 100L and the memory cell 100 will be mainly described. The memory cell 100L has a structure in which the semiconductor 113 and the semiconductor 114 are omitted from the memory cell 100. By not providing the semiconductor 113 and the semiconductor 114, the manufacturing process can be simplified and the productivity of the memory device can be increased.

[0114] In the memory cell 100L, a part of the semiconductor 121 functions as a channel formation region of the transistor WTr. Therefore, the semiconductor 121 used in the memory cell 100L may be made of the same material as the semiconductor 114 in the memory cell 100 or the semiconductor 114b in the memory cell 100G.

[0115] 20A shows a cross-sectional view of memory cell 100M. FIG. 20B shows a cross-sectional view of memory cell 100N. Both memory cell 100M and memory cell 100N are modifications of memory cell 100A. Therefore, in the present embodiment and the like, differences between memory cell 100M and memory cell 100N and memory cell 100A will be mainly described.

[0116] The memory cell 100M has a structure obtained by omitting the semiconductor 113 and the semiconductor 114 from the memory cell 100A. The memory cell 100N has a structure obtained by omitting the semiconductor 114 from the memory cell 100A. By not providing the semiconductor 113 and / or the semiconductor 114, the manufacturing process can be simplified and the productivity of the memory device can be increased.

[0117] Note that the memory cells 100M and 100N are also modified versions of the memory cell 100L. Therefore, in the memory cells 100M and 100N, a part of the semiconductor 121 functions as a channel formation region of the transistor WTr. The semiconductor 121 used in the memory cell 100M or the memory cell 100N may be made of the same material as the semiconductor 114 in the memory cell 100 or the semiconductor 114b in the memory cell 100G.

[0118] FIG. 21 shows a cross-sectional view of memory cell 100P. FIG. 22(A) is a cross-sectional view of portion C1-C2 indicated by a dashed line in FIG. 21, as viewed from the Z direction. FIG. 22(B) is a cross-sectional view of portion D1-D2 indicated by a dashed line in FIG. 21, as viewed from the Z direction. Memory cell 100P is a modified version of memory cell 100. Therefore, in this embodiment and the like, differences between memory cell 100P and memory cell 100 will be mainly described.

[0119] Memory cell 100P has a configuration in which memory cell 100, conductor 102, conductor 103, etc. are divided along the direction in which conductor 102 and conductor 103 extend, passing through the center of memory cell 100. Note that in this embodiment and the like, insulator 124 is provided in the divided region, but insulator 124 may be provided as necessary.

[0120] Each of insulator 101, conductor 102, conductor 103, semiconductor 121, insulator 122, and structure 130 is divided into insulator 101a (not shown) and insulator 101b (not shown), conductor 102a and conductor 102b, conductor 103a and conductor 103b, semiconductor 121a and semiconductor 121b, insulator 122a and insulator 122b, and structure 130a and structure 130b.

[0121] Each of the insulator 111, conductor 112, semiconductor 113, semiconductor 114, insulator 115, semiconductor 116, insulator 117, and conductor 118 contained in structure 130 is divided into insulator 111a and insulator 111b, conductor 112a and conductor 112b, semiconductor 113a and semiconductor 113b, semiconductor 114a and semiconductor 114b, insulator 115a and insulator 115b, semiconductor 116a and semiconductor 116b, insulator 117a and insulator 117b, and conductor 118a and conductor 118b.

[0122] Thus, the structure 130a includes an insulator 111a, a conductor 112a, a semiconductor 113a, a semiconductor 114a, an insulator 115a, a semiconductor 116a, an insulator 117a, and a conductor 118a. Additionally, the structure 130b includes an insulator 111b, a conductor 112b, a semiconductor 113b, a semiconductor 114b, an insulator 115b, a semiconductor 116b, an insulator 117b, and a conductor 118b.

[0123] Also, memory cell 100P is divided into memory cell 100Pa and memory cell 100Pb. Therefore, it can be said that memory cell 100P has a region that functions as memory cell 100Pa and a region that functions as memory cell 100Pb. Memory cell 100Pa includes structure 130a and the like, and memory cell 100Pb includes structure 130b and the like.

[0124] Therefore, in the memory cell 100P, the transistor RTr, the transistor WTr, and the capacitance element Cs are divided into the transistors RTrA and RTrB, the transistors WTrA and WTrB, and the capacitance elements CsA and CsB. The transistors RTrA, WTrA, and the capacitance element CsA are included in the memory cell 100Pa. The transistors RTrB, WTrB, and the capacitance element CsB are included in the memory cell 100Pb.

[0125] The overlapping region of the conductor 112a, the semiconductor 113a, the semiconductor 114a, the insulator 115a, the semiconductor 116a, the insulator 117a, and the conductor 118a functions as the transistor RTrA. The overlapping region of the conductor 112b, the semiconductor 113b, the semiconductor 114b, the insulator 115b, the semiconductor 116b, the insulator 117b, and the conductor 118b functions as the transistor RTrB. The overlapping region of the conductor 103a, the insulator 111a, and the conductor 112a functions as the capacitance element CsA. The overlapping region of the conductor 103b, the insulator 111b, and the conductor 112b functions as the capacitance element CsB. The overlapping region of the conductor 102a, the conductor 112a, the semiconductor 121a, the semiconductor 114a, the insulator 115a, the semiconductor 116a, the insulator 117a, and the conductor 118a functions as the transistor WTrA. The overlapping region of the conductor 102b, the conductor 112b, the semiconductor 121b, the semiconductor 114b, the insulator 115b, the semiconductor 116b, the insulator 117b, and the conductor 118b functions as the transistor WTrB.

[0126] Dividing the memory cell 100 into memory cell 100P can increase the memory density (storage capacity per unit area). Thus, it is possible to increase the memory capacity of a semiconductor device including the memory cell 100. The memory cells 100A to 100N can also be divided into memory cells in the same manner as the memory cell 100P.

[0127] Moreover, the memory cell may be divided along the X direction (see FIG. 23A). When dividing the memory cell along the X direction, the insulator 124 should not completely cross the conductor 102 and the conductor 103.

[0128] Also, the memory cells may be divided along a diagonal direction (a direction intersecting the X and Y directions) when viewed from the Z direction (see FIG. 23(B)). When dividing the memory cells along a diagonal direction, the insulator 124 should not completely cross the conductor 102 and the conductor 103.

[0129] The number of divisions of the memory cell is not limited to two. For example, the memory cell may be divided into three as shown in Fig. 24(A). Fig. 24(A) shows a state in which the structure 130, the semiconductor 121, and the insulator 122 are divided into a structure 130a, a structure 130b, a structure 130c, a semiconductor 121a, a semiconductor 121b, a semiconductor 121c, an insulator 122a, an insulator 122b, and an insulator 122c with the Y-shaped insulator 124 as a boundary.

[0130] As shown in FIG. 24(B), the shape of the insulator 124 when viewed from the Z direction may have a curved portion.

[0131] Furthermore, the memory cell may be divided into four parts as shown in Fig. 25(A) . Fig. 25(A) shows a state in which the structure 130, the semiconductor 121, and the insulator 122 are divided into a structure 130a, a structure 130b, a structure 130c, a structure 130d, a semiconductor 121a, a semiconductor 121b, a semiconductor 121c, a semiconductor 121d, an insulator 122a, an insulator 122b, an insulator 122c, and an insulator 122d, with a cross-shaped insulator 124 as a boundary.

[0132] 25(B), the insulator 124 may be provided so as not to completely cross the conductors 102a and 102b. Similarly, the insulator 124 may be provided so as not to completely cross the conductors 103a and 103b. As long as it does not completely cross the X direction, the insulator 124 may have an element extending in the Y direction.

[0133] 11(A) and 11(B), when a plurality of memory cells 100 or a plurality of memory strings 200 are provided, the shape of the insulator 124 used to divide the memory cells 100 or the memory strings 200 may be different depending on the memory cells 100 or the memory strings 200, as shown in FIG. 26. Also, the division of different memory cells 100 or memory strings 200 may be performed by a common insulator 124.

[0134] [Memory cell constituent materials] Next, constituent materials that can be used for the memory cell 100 and the like will be described.

[0135] [substrate] The memory cell 100 and the memory string 200 can be provided on a substrate. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. For example, the insulating substrate may be a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), or a resin substrate. For example, the semiconductor substrate may be a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride (GaN). Furthermore, there is a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. For example, the conductive substrate may be a graphite substrate, a metal substrate, an alloy substrate, or a conductive resin substrate. Alternatively, there is a substrate having a metal nitride, or a substrate having a metal oxide. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Alternatively, a substrate provided with an element on such a substrate may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switching element, a light-emitting element, a memory element, etc.

[0136] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0137] In this specification, etc., the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In this specification, etc., the term "nitride oxide" refers to a material that contains more nitrogen than oxygen, and the term "aluminum nitride oxide" refers to an aluminum material that contains more nitrogen than oxygen.

[0138] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0139] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0140] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0141] In addition, the electrical characteristics of the OS transistor can be stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0142] When an oxide semiconductor is used for the semiconductor 116, the semiconductor 114, the semiconductor 113, and / or the semiconductor 121, the insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 114 and / or the semiconductor 116, oxygen vacancies in the semiconductor 114 and / or the semiconductor 116 can be compensated for.

[0143] Further, as the insulator, a single insulating layer made of the above-mentioned material may be used, or a plurality of insulating layers made of the above-mentioned material may be stacked.

[0144] For example, when an insulator is provided in contact with a conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in order to prevent oxidation of the conductor, such as hafnium oxide, aluminum oxide, or silicon nitride.

[0145] In addition, when an insulator is stacked adjacent to a conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in contact with the conductor. For example, an insulator in contact with the conductor may be formed using hafnium oxide, and an insulator in contact with the insulator using silicon oxynitride may be formed.

[0146] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0147] A single conductive layer formed of the above material may be used as the conductor, or multiple conductive layers formed of the above material may be stacked. For example, a laminate structure may be used in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. A laminate structure may be used in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. A laminate structure may be used in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0148] In the case where an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0149] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in an oxide semiconductor in which a channel is formed. The conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in an oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator or the like may be captured.

[0150] [Oxide semiconductor] A metal oxide (oxide semiconductor) functioning as a semiconductor is preferably used as the semiconductor 116, the semiconductor 114, the semiconductor 113, and / or the semiconductor 121. In particular, an oxide semiconductor is preferably used as the semiconductor 114. An oxide semiconductor that can be used in the memory cell 100 will be described below.

[0151] The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable that the oxide semiconductor contains indium and zinc. In addition to these, it is preferable that the oxide semiconductor contains aluminum, gallium, yttrium, tin, etc. Furthermore, the oxide semiconductor may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0152] Here, the case where the oxide semiconductor is an In-M-Zn oxide having indium, an element M, and zinc is considered. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of a plurality of the above-mentioned elements.

[0153] [Classification of crystal structures] First, classification of crystal structures of oxide semiconductors will be described with reference to Fig. 27A, which illustrates classification of the crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0154] As shown in FIG. 27(A), oxide semiconductors are roughly classified into "amorphous", "crystalline", and "crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystalline" includes single crystal and poly crystal.

[0155] The structure in the bold frame shown in Fig. 27(A) is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0156] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 27(B). The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 27(B) will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 27(B) is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 27(B) is 500 nm.

[0157] As shown in Figure 27(B), a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 27(B), the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0158] The crystal structure of the film or substrate can be evaluated from a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 27(C). FIG. 27(C) is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 27(C) is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0159] As shown in FIG. 27(C), multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0160] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from that shown in FIG. 27A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) and nanocrystalline oxide semiconductor (nc-OS). Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0161] Next, we will explain the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS.

[0162] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0163] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0164] In addition, in the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0165] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0166] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0167] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0168] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0169] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0170] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0171] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0172] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0173] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0174] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0175] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0176] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0177] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0178] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0179] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0180] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0181] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0182] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0183] It is preferable to use an oxide semiconductor having a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100%. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0184] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0185] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0186] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0187] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0188] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0189] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0190] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17atoms / cm 3 To the following:

[0191] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0192] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0193] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 116, the semiconductor 114, the semiconductor 113, and the semiconductor 121 is not limited to the above-mentioned oxide semiconductors. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor 116, the semiconductor 114, the semiconductor 113, and the semiconductor 121. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0194] In this specification, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0195] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0196] As a semiconductor material used in the semiconductor device according to one embodiment of the present invention, for example, transition metal chalcogenides functioning as semiconductors may be used.Specific examples thereof include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), zirconium selenide (representatively ZrSe2), and the like.

[0197] [Film formation method] Conductors, insulators, and semiconductors can be formed using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0198] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0199] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0200] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. Also, since the ALD method does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0201] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0202] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0203] In addition, in the ALD method, the chamber may be under atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, two or more types of raw material gases may be sequentially supplied to the chamber by switching each switching valve (also called a high-speed valve), and an inert gas (argon, nitrogen, etc.) may be introduced simultaneously with or after the first raw material gas so that the multiple raw material gases are not mixed, and then the second raw material gas is introduced. When the inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas may be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the first raw material gas may be exhausted by vacuum evacuation, and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction order multiple times until a desired thickness is obtained while controlling the gas introduction order, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise adjustment of the film thickness, making this method suitable for fabricating fine FETs.

[0204] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. In addition, the combination is not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0205] For example, when forming a hafnium oxide film using a film formation device that uses ALD, two types of gas are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0206] For example, when forming an aluminum oxide film using a film formation device that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0207] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be formed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0208] For example, when forming a tungsten film using a film forming apparatus that uses ALD, WF6 gas and B2H6 gas are repeatedly introduced in sequence to form an initial tungsten film, and then WF6 gas and H2 gas are repeatedly introduced in sequence to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0209] For example, when an oxide semiconductor film, such as an In-Ga-Zn-O film, is formed by a film forming apparatus using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Also, mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer may be formed using these gases. Note that, instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Moreover, Zn(C2H5)2 gas may be used in place of Zn(CH3)2 gas.

[0210] <Example of how to make a memory device> Next, an example of a method for manufacturing the memory cell 100 will be described.

[0211] 28(A) is fabricated. The laminate 140 includes an insulator 101, a sacrificial layer 141, and a conductor 103. The insulator 101[i] is disposed above a substrate (not shown), the sacrificial layer 141 is disposed on the insulator 101[i], the insulator 101[i+1] is disposed on the sacrificial layer 141, the conductor 103 is disposed on the insulator 101[i+1], and the insulator 101[i+2] is disposed on the conductor 103.

[0212] Various materials can be used for the sacrificial layer 141. For example, an insulator such as silicon nitride, silicon oxide, or aluminum oxide may be used. Alternatively, a semiconductor such as silicon, gallium, or germanium may be used. Alternatively, a conductor such as aluminum, copper, titanium, tungsten, or tantalum may be used. Alternatively, an organic material such as acrylic resin, polyimide, phenolic resin, or epoxy resin may be used. In other words, since the sacrificial layer is removed later, the sacrificial layer 141 may be made of a material that has a selectivity with respect to materials used in other parts during a later etching process.

[0213] It is preferable that the insulator 101 is made of a material with a reduced concentration of impurities such as water or hydrogen. For example, the amount of desorption of hydrogen molecules per unit area of ​​the insulator 101 is 2×10 15 molecules / cm 2 Less than or equal to 1×10 15 molecules / cm 2 Less than or equal to 5×10 14 molecules / cm 2 The material may be any material that releases oxygen when heated. However, the material that can be used for the insulator 101 is not limited to the above.

[0214] Note that the insulator 101 may have a stacked structure of multiple insulators. For example, the insulator 101 may be a stacked structure of hafnium oxide and silicon oxynitride. Of the multiple insulators constituting the insulator 101, it is preferable to use an insulator having the above-mentioned function of suppressing oxygen permeation as the insulator in contact with the conductor 103.

[0215] Next, a resist mask is formed over the stack 140, and parts of the insulator 101, the conductor 103, and the sacrificial layer 141 are removed by etching using the resist mask to form an opening 131 in the stack 140 (see Figure 28(B)).

[0216] The resist mask can be formed by, for example, a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced in some cases. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used. Processing by the dry etching method is suitable for fine processing.

[0217] In the formation of a resist mask by lithography, a resist is first formed, and then the resist is exposed to light through a photomask. Next, the exposed area is removed or left using a developer to form a resist mask.

[0218] Conductors, semiconductors, insulators, etc. can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. Note that, when an electron beam or an ion beam is used, a photomask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after the dry etching process, or a dry etching process after the wet etching process.

[0219] Instead of the resist mask, a hard mask made of an insulator or a conductor may be used. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape.

[0220] As a dry etching apparatus for performing an etching process by the dry etching method, for example, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As a dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0221] Next, the insulator 111 is formed along the side surface of the opening 131 (see FIG. 29(A)). The side surfaces of the insulator 101, the conductor 103, and the sacrificial layer 141 exposed in the opening 131 are covered with the insulator 111.

[0222] The insulator 111 may have a laminated structure of a plurality of insulators. Of the plurality of insulators constituting the insulator 111, it is preferable to use an insulator having the function of suppressing oxygen permeation as described above for the insulator in contact with the conductor 103 and / or the conductor 112. For example, the insulator 111 may be a laminated structure of hafnium oxide and silicon oxynitride. Also, for example, the insulator 111 may have a three-layer structure in which hafnium oxide is sandwiched between two layers of silicon oxynitride. Also, for example, the insulator 111 may have a three-layer structure in which silicon oxynitride is sandwiched between two layers of hafnium oxide.

[0223] Next, the conductor 112 is formed along the surface of the insulator 111 (see FIG. 29(B)). The conductor 112 is processed in a later step and functions as the source and / or drain of the transistor WTr and / or the transistor RTr, functions as the gate of the transistor RTr, and functions as one electrode of the capacitance element Cs.

[0224] The conductor 112 is preferably a material with high conductivity. For example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used as the conductor 112. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. In addition, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0225] In particular, when an oxide semiconductor is used as a semiconductor, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used as the conductor 112. In this case, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like as the conductor 112.

[0226] For example, when the conductor 112 is a stack of multiple layers, a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen may be used on the insulator 111 side, and a conductive material that is not easily oxidized or a material that maintains its conductivity even when it absorbs oxygen may be used on the semiconductor 113 side.

[0227] Next, the semiconductor 113 is formed along the surface of the conductor 112 (see FIG. 30A). In this embodiment, an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:3:4 or a composition therearound is used as the semiconductor 113. Note that the term "atomic ratio therearound" refers to a range of ±30% of the desired atomic ratio.

[0228] As a semiconductor material for the semiconductor 113, for example, a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1 or a composition close to the above may be used.

[0229] Next, the semiconductor 114 is formed along the surface of the semiconductor 113 (see FIG. 30B). In this embodiment, an oxide semiconductor having an atomic ratio of In:Ga:Zn=4:2:3 or a composition thereof is used as the semiconductor 114.

[0230] Note that, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these may be used as a semiconductor material used for the semiconductor 114. Furthermore, a metal oxide having a composition of In:Zn=5:1 or In:Zn=10:1, or a composition close to these may be used as a semiconductor material used for the semiconductor 114. Furthermore, indium oxide may be used for the semiconductor 114.

[0231] As a semiconductor material for the semiconductor 121 to be formed later, for example, a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1 or a composition close to the above may be used.

[0232] When an oxide semiconductor is used for the semiconductor 121 and the semiconductor 114, the semiconductor 121 and the semiconductor 114 preferably contain a common metal element. More preferably, the semiconductor 121 and the semiconductor 114 preferably contain a plurality of common metal elements. In addition, the semiconductor 121 and the semiconductor 114 preferably contain a plurality of common metal elements, and the atomic ratio of the plurality of metal elements is preferably different between the semiconductor 121 and the semiconductor 114.

[0233] For example, when an In-M-Zn oxide having indium, the element M, and zinc is used for the semiconductors 121 and 114, the atomic ratio of the element M among the metal elements contained in the semiconductor 121 is preferably greater than the atomic ratio of the element M among the metal elements contained in the semiconductor 114. Moreover, the atomic ratio of the element M to In in the semiconductor 121 is preferably greater than the atomic ratio of the element M to In in the semiconductor 114. Moreover, the atomic ratio of In to the element M in the semiconductor 114 is preferably greater than the atomic ratio of In to the element M in the semiconductor 121.

[0234] In addition, it is preferable that the energy of the conduction band minimum of the semiconductor 121 is higher than the energy of the conduction band minimum of the semiconductor 114. In other words, it is preferable that the electron affinity of the semiconductor 121 is smaller than the electron affinity of the semiconductor 114.

[0235] Here, the energy level of the conduction band minimum changes smoothly at the junction between the semiconductor 121 and the semiconductor 114. In other words, it can be said that the energy level of the conduction band minimum at the junction between the semiconductor 121 and the semiconductor 114 changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the semiconductor 121 and the semiconductor 114.

[0236] Specifically, a mixed layer with a low defect level density can be formed by having a common element (main component) other than oxygen between the semiconductor 121 and the semiconductor 114. For example, when the semiconductor 114 is an In-Ga-Zn oxide, the semiconductor 121 may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0237] At this time, the main path of carriers is the semiconductor 114. By configuring the semiconductor 121 as described above, it is possible to reduce the defect state density at the interface between the semiconductor 121 and the semiconductor 114. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor WTr can obtain a high on-current.

[0238] Furthermore, by including the semiconductor 121, it is possible to suppress diffusion of impurities from the semiconductor 121 side to the semiconductor 114. The thickness of the semiconductor 121 may be 1 nm or more and 10 nm or less, or 1 nm or more and 5 nm or less.

[0239] When the semiconductor 114 is a stack of the semiconductor 114a and the semiconductor 114b as in the memory cell 100G illustrated in FIG. 16A, the semiconductor 114b may have a structure similar to that of the semiconductor 114 described above, and the semiconductor 114a may have a structure similar to that of the semiconductor 121.

[0240] For example, the semiconductor 114a may be an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout. The thickness of the semiconductor 114a may be 1 nm or more and 10 nm or less, or 1 nm or more and 5 nm or less. For example, the semiconductor 114b may be an oxide semiconductor having an atomic ratio of In:Ga:Zn=4:2:3 or a composition thereabout. As described above, the semiconductor 114b may be an oxide semiconductor having an atomic ratio of In:Ga:Zn=5:1:3 or a composition thereabout. The thickness of the semiconductor 114b may be 5 nm or more and 20 nm or less, or 5 nm or more and 15 nm or less.

[0241] In this way, the energy level of the conduction band minimum changes smoothly at the junction between the semiconductor 121 and the semiconductor 114b and at the junction between the semiconductor 114b and the semiconductor 114a. Also, a mixed layer with a low density of defect states can be formed at each interface between the semiconductor 121 and the semiconductor 114b and at the interface between the semiconductor 114b and the semiconductor 114a.

[0242] By providing the semiconductor 121 and the semiconductor 114a with the semiconductor 114b sandwiched therebetween, the influence of interface scattering on carrier conduction can be reduced, and the on-state current of the transistor can be increased.

[0243] In addition, by including the semiconductor 114a, diffusion of impurities from the semiconductor 114a to the semiconductor 114b can be suppressed.

[0244] In addition, in a manufacturing process of the memory cell, it is preferable to perform heat treatment while the surface of the semiconductor 114 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the semiconductor 114 to reduce oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0245] Note that by performing a treatment for supplying oxygen to the semiconductor 114 (also referred to as an “oxygenation treatment”), oxygen vacancies in the semiconductor 114 are repaired by the supplied oxygen. In other words, a “V O In addition, the reaction of the hydrogen remaining in the semiconductor 114 with the supplied oxygen can be promoted, and the hydrogen can be removed as HO (dehydration). As a result, the hydrogen remaining in the semiconductor 114 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0246] Also, the oxygen-adding process can be performed by performing microwave processing in an atmosphere containing oxygen. In this case, the semiconductor 114 is irradiated with microwaves, high frequency waves such as RF, oxygen plasma, oxygen radicals, or the like. For the microwave processing, it is preferable to use a microwave processing device having a power source that generates high-density plasma using microwaves. Also, the microwave processing device may have a power source that applies RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Also, by applying RF to the substrate (not shown) side, oxygen ions generated by high-density plasma can be efficiently guided into the opening 131. Also, the microwave processing is preferably performed under reduced pressure, and the pressure may be set to 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Also, it is preferable to perform the process at an oxygen flow rate ratio O2 / (O2+Ar) of 50% or less, preferably 10% or more and 30% or less. Also, the process temperature may be set to 750° C. or less, preferably 500° C. or less, for example, about 400° C. Furthermore, after the microwave treatment, a heat treatment may be carried out successively without exposure to the outside air.

[0247] The V contained in the semiconductor 114 is O H can be split off, and hydrogen H can be removed from the semiconductor 114. O H→H+V O )" and "V O +O→null” occurs, and the hydrogen concentration in the semiconductor 114 can be reduced. O H can be reduced, lowering the carrier concentration.

[0248] Next, the insulator 115 is formed along the surface of the semiconductor 114 (see FIG. 31A). In the case where an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 115 as appropriate. By providing an insulator containing oxygen in contact with the semiconductor 114, oxygen vacancies in the semiconductor 114 can be reduced and the reliability of the transistor can be improved.

[0249] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulating material having an excess oxygen region, as the insulator 115. An oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 The oxide film is one having a temperature of at least 100° C. and at most 700° C., or at most 100° C. and at most 400° C., during the TDS analysis. The thickness of the insulator 115 may be at least 3 nm and at most 15 nm, or at most 3 nm and at most 10 nm.

[0250] After the insulator 115 is formed, the above-mentioned oxygen-adding treatment may be performed.

[0251] When an oxide semiconductor is used for the semiconductor 116 and the semiconductor 114, the insulator 115 is preferably an insulator having a region containing oxygen that is released by heating. The insulator 115 may have a stacked structure of a plurality of insulators. For example, when an oxide semiconductor is used for the semiconductor 116 and the semiconductor 114, the insulator 115 may have a three-layer structure of silicon oxide or silicon oxynitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride. That is, a structure in which one layer of hafnium oxide or aluminum oxide is sandwiched between two layers of silicon oxide or silicon oxynitride may be used. Note that the insulator 115 may have a two-layer structure or a four-layer or more layer structure.

[0252] Next, the semiconductor 116 is formed along the surface of the insulator 115 (see FIG. 31B). In this embodiment, an oxide semiconductor having a composition of In:Ga:Zn=4:2:3 (atomic ratio) or a composition close to that range is used as the semiconductor 116.

[0253] Note that, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these may be used as a semiconductor material used for the semiconductor 116. Furthermore, a metal oxide having a composition of In:Zn=5:1 or In:Zn=10:1, or a composition close to these may be used as a semiconductor material used for the semiconductor 116. Furthermore, indium oxide may be used for the semiconductor 116.

[0254] In the case where an oxide semiconductor is used as the semiconductor 116, oxygen addition treatment may be performed after the semiconductor 116 is formed.

[0255] When a Si transistor is used as the transistor RTr, the semiconductor 116 may be formed of silicon.

[0256] When the semiconductor 116 is a stack of semiconductors 116a, 116b, and 116c as in the memory cell 100K shown in FIG. 18, the semiconductor 116a and the semiconductor 116c may have the same structure as the semiconductor 114a, and the semiconductor 116b may have the same structure as the semiconductor 114b.

[0257] Next, the insulator 117 is formed along the surface of the semiconductor 116 (see FIG. 32A). The insulator 117 may be formed using a material and method similar to those of the insulator 115. After the insulator 117 is formed, oxygen addition treatment may be performed.

[0258] The insulator 117 may have a stacked structure of multiple insulators. When an oxide semiconductor is used for the semiconductor 116, the insulator in contact with the semiconductor 116 among the multiple insulators constituting the insulator 117 preferably has a region containing oxygen that is released by heating. The insulator in contact with the conductor 118 preferably has the above-described function of suppressing oxygen permeation. For example, silicon oxide or silicon oxynitride may be used as the insulator in contact with the semiconductor 116 among the multiple insulators constituting the insulator 117. Hafnium oxide or aluminum oxide may be used as the insulator in contact with the conductor 118 among the multiple insulators constituting the insulator 117.

[0259] Alternatively, for example, the insulator 117 may be a stack of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. When silicon nitride is used for the insulator 117, it is preferable to use silicon nitride with a low hydrogen content.

[0260] Next, after the insulator 117 is formed, the conductor 118 is formed (see FIG. 32B). In this embodiment, tungsten is used as the conductor 118. Note that the conductor 118 may have a stacked-layer structure of a plurality of conductors. Of the plurality of conductors constituting the conductor 118, the conductor in contact with the insulator 117 is preferably made of a conductive material that is not easily oxidized. For example, titanium nitride may be used as the conductor in contact with the insulator 117 of the conductor 118. For example, the conductor 118 may be a stacked-layer structure of titanium nitride and tungsten.

[0261] The formation of insulator 111, conductor 112, semiconductor 113, semiconductor 114 (semiconductor 114a, semiconductor 114b), insulator 115, semiconductor 116 (semiconductor 116a, semiconductor 116b, semiconductor 116c), insulator 117, and conductor 118 can be performed successively using a CVD method (such as an MOCVD method) or an ALD method.

[0262] In this manner, structures 130a are formed in openings 131. Next, a portion of stacked body 140 is removed from a region that does not overlap with structures 130a when viewed from the Z direction to form region 132 (see FIG. 33(A)). Region 132 can be formed in the same manner as opening 131.

[0263] Next, the sacrificial layer 141 is removed (see FIG. 33(B)). The sacrificial layer 141 may be removed by dry etching or wet etching, or may be removed by both.

[0264] Next, the insulator 111, the conductor 112, and the semiconductor 113 that overlap with the region where the sacrificial layer 141 has been removed are removed to expose a part of the semiconductor 114 (see FIG. 34(A)). The insulator 111, the conductor 112, and the semiconductor 113 may be removed by dry etching or wet etching, or both. The etching method and etching conditions may be changed depending on the material to be removed. The removal of the sacrificial layer 141 and the removal of the insulator 111, the conductor 112, and the semiconductor 113 may be performed successively. Furthermore, the process from the formation of the region 132 to the removal of the semiconductor 113 may be performed successively. In this manner, the structure 130 is formed.

[0265] After that, an oxygen-adding process may be performed. For example, a microwave process may be performed in an atmosphere containing oxygen 10. At this time, oxygen 10 is supplied from region 132, but oxygen 10 may also be supplied via the terminal outlet shown in Fig. 34(B). Fig. 34(B) is a perspective view of stack 140 in the vicinity of the terminal outlet.

[0266] Next, a semiconductor 121 is formed along the surfaces of the insulator 101, the conductor 103, the insulator 111, the conductor 112, the semiconductor 113, and the semiconductor 114 that are exposed by the formation of the region 132 (see FIG. 35(A)). After the formation of the semiconductor 121, an oxygen-adding treatment may be performed.

[0267] Next, the insulator 122 is formed along the surface of the semiconductor 121 (see FIG. 35A). After the insulator 122 is formed, oxygen addition treatment may be performed. The insulator 122 may be formed using a material similar to that of the insulator 115.

[0268] Note that the insulator 122 may have a stacked structure of multiple insulators. When an oxide semiconductor is used for the semiconductor 121, the insulator in contact with the semiconductor 121 is preferably an insulator having a region containing oxygen that is released by heating, as described above, among the multiple insulators constituting the insulator 122. The insulator in contact with the conductor 102 is preferably an insulator having a function of suppressing oxygen permeation, as described above. For example, silicon oxide or silicon oxynitride may be used as the insulator in contact with the semiconductor 121, as described above, among the multiple insulators constituting the insulator 122. Hafnium oxide may be used as the insulator in contact with the conductor 102, as described above, among the multiple insulators constituting the insulator 122.

[0269] Alternatively, for example, the insulator 122 may be a stack of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. When silicon nitride is used for the insulator 122, it is preferable to use silicon nitride with a low hydrogen content.

[0270] Next, the conductor 102 is formed along the surface of the insulator 122 (see FIG. 35B). Although the conductor 102 is shown as a single layer in this embodiment, it may be a stack of multiple layers.

[0271] 18, when the conductor 102 is a stack of the conductor 102f and the conductor 102s, it is preferable to use a conductive material that is not easily oxidized for the conductor 102f that is in contact with the insulator 122. For example, titanium nitride may be used for the conductor 102f, and tungsten may be used for the conductor 102s.

[0272] Next, a part of the conductor 102 is removed to expose a part of the insulator 122 (see FIG. 36(A)).

[0273] Next, the insulator 123 is formed along part of the exposed insulator 122 and the surface of the conductor 102 (see FIG. 36B). For example, an insulating material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used as the insulator 123. For example, aluminum oxide or the like can be used as the insulator 123.

[0274] Note that the insulator 123 may have a stacked structure of multiple insulators. For example, the insulator 123 may be a stacked structure of hafnium oxide and silicon oxynitride. Of the multiple insulators that constitute the insulator 123, the insulator in contact with the conductor 102 is preferably an insulator having the above-mentioned function of suppressing oxygen permeation.

[0275] In this manner, the memory cell 100 can be fabricated.

[0276] 21 and 22, when the memory cell 100 is divided into a plurality of memory cells, slits (not shown) for dividing the memory cell 100 into a plurality of memory cells may be formed thereafter. After the slits are formed, an insulator 124 may be provided in the slits. The insulator 124 may be formed using the same material as the insulator 123.

[0277] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0278] (Embodiment 2) In this embodiment, an example of a circuit configuration and an example of an operation method of a semiconductor device 300 including a plurality of memory strings 200 will be described with reference to the drawings.

[0279] <Circuit configuration example> The circuit configuration of the semiconductor device 300 will be described with reference to Fig. 37. The semiconductor device 300 has m memory strings 200. In this embodiment and the like, the first memory string 200 is indicated as memory string 200[1], the mth memory string 200 is indicated as memory string 200[m] (m is an integer equal to or greater than 1), and the jth memory string 200 is indicated as memory string 200[j] (j is an integer equal to or greater than 1 and equal to or less than m).

[0280] Further, the memory string 200 has n memory cells 100. In Fig. 37, the memory cell 100 has the circuit configuration shown in Fig. 4(A), but the memory cell 100 may have the circuit configuration shown in Fig. 4(B), Fig. 4(C), Fig. 5(A), and Fig. 5(B). In the present embodiment and the like, the kth memory cell 100 included in the jth memory string 200 is indicated as memory cell 100[k,j].

[0281] 37 has n wirings WWL, n wirings RWL, m wirings WBL, m wirings RBL, and m wirings BGL. In the present embodiment and the like, the k-th wirings WWL and RWL are respectively indicated as wiring WWL[k] and wiring RWL[k]. Also, the j-th wirings WBL, RBL, and BGL are respectively indicated as wiring WBL[j], wiring RBL[j], and wiring BGL[j].

[0282] The wiring WWL[1] is electrically connected to the gates (conductors 102) of the transistors WTr included in each of the memory cells 100[1,1] to 100[1,m]. The wiring WWL[k] is electrically connected to the gates (conductors 102) of the transistors WTr included in each of the memory cells 100[k,1] to 100[k,m]. The wiring WWL[n] is electrically connected to the gates (conductors 102) of the transistors WTr included in each of the memory cells 100[n,1] to 100[n,m].

[0283] The wiring RWL[1] is electrically connected to the capacitor Cs included in each of the memory cells 100[1,1] to 100[1,m]. The wiring RWL[k] is electrically connected to the capacitor Cs included in each of the memory cells 100[k,1] to 100[k,m]. The wiring RWL[n] is electrically connected to the capacitor Cs included in each of the memory cells 100[n,1] to 100[n,m]. The wiring RWL is connected to the gate (conductor 112) of the transistor RTr through the capacitor Cs.

[0284] The wiring WBL[1] is electrically connected to one of the source and drain (conductor 112) of the transistor WTr included in the memory cell 100[1,1]. The wiring WBL[j] is electrically connected to one of the source and drain (conductor 112) of the transistor WTr included in the memory cell 100[1,j]. The wiring WBL[m] is electrically connected to one of the source and drain (conductor 112) of the transistor WTr included in the memory cell 100[1,m].

[0285] The wiring RBL[1] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTr included in the memory cell 100[1,1]. The wiring RBL[j] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTr included in the memory cell 100[1,j]. The wiring RBL[m] is electrically connected to one of the source and drain (semiconductor 116) of the transistor RTr included in the memory cell 100[1,m].

[0286] The wiring BGL[1] is electrically connected to the backgates (conductors 118) of the transistors RTr included in each of the memory cells 100[1,1] to 100[n,1]. The wiring BGL[j] is electrically connected to the backgates (conductors 118) of the transistors RTr included in each of the memory cells 100[1,j] to 100[n,j]. The wiring BGL[m] is electrically connected to the backgates (conductors 118) of the transistors RTr included in each of the memory cells 100[1,m] to 100[n,m].

[0287] The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0288] 37, the region electrically connected to the other of the source or drain of the transistor RTr included in the memory cell 100[1,1] is indicated as node N1[1], and the region electrically connected to one of the source or drain of the transistor RTr included in the memory cell 100[n,1] is indicated as node N2[1]. Similarly, the nodes N1 and N2 of the memory string 200[j] are indicated as nodes N1[j] and N2[j], respectively. The nodes N1 and N2 of the memory string 200[m] are indicated as nodes N1[m] and N2[m], respectively.

[0289] <Example of operation method> Next, a description will be given of an example of a method for operating the semiconductor device 300 shown in Fig. 37. In this embodiment, an example of an operation for writing data to the memory cells 100 included in the memory string 200[1] and an example of an operation for reading data will be described.

[0290] In addition, the low-level potential (Low) and the high-level potential (High) used in the following description do not mean specific potentials, and the specific potentials may be different depending on the wiring. For example, the low-level potential and the high-level potential applied to the wiring WWL may be different from the low-level potential and the high-level potential applied to the wiring RWL.

[0291] In addition, in this example of the operation method, it is assumed that a potential within a range in which the transistors RTr and WTr operate normally is applied in advance to the wiring BGL.

[0292] Fig. 38(A) is a timing chart for explaining an example of an operation of writing data to the memory string 200[1], and Fig. 38(B) is a timing chart for explaining an example of an operation of reading data from the memory string 200[1]. The timing charts in Fig. 38(A) and (B) each show changes in the magnitude of the potential of the wiring WWL[1], the wiring WWL[2] or the wiring WWL[n-1], the wiring WWL[n], the wiring RWL[1], the wiring RWL[2] or the wiring RWL[n-1], the wiring RWL[n], the node N1[1], and the node N2[1]. The wiring WBL[1] shows data supplied to the wiring WBL[1].

[0293] 38A shows an example in which data D[1] to data D[n] are written to memory cells 100[1,1] to 100[n,1], respectively. Note that data D[1] to data D[n] can be binary or multi-valued. Data D[1] to data D[n] are supplied from wiring WBL[1].

[0294] Data is written to the memory string 200[1] sequentially from the memory cell 100[n,1] to the memory cell 100[1,1]. If data is written to the memory cell 100[2,1] after data has been written to the memory cell 100[1,1], the data held in the memory cell 100[1,1] will be lost when the data is written to the memory cell 100[2,1]. Therefore, it is necessary to read the data written to the memory cell 100[1,1] and store it in another location.

[0295] In the circuit configuration of the memory string 200, when data is written to the memory cell 100[k,1], in order to prevent the data stored in the memory cells 100[n,1] to 100[k+1,1] from being rewritten, a low-level potential is supplied to the wirings WWL[n] to WWL[k+1] to turn off the transistors WTr included in each of the memory cells 100[n,1] to 100[k+1,1]. This makes it possible to protect the data stored in the memory cells 100[n,1] to 100[k+1,1].

[0296] When data is written to the memory cell 100[k,1], the data is supplied from the wiring WBL[1], so that a high-level potential is supplied to the wirings WWL[1] to WWL[k] to turn on the transistors WTr included in each of the memory cells 100[1,1] to 100[k,1] sufficiently. This allows data to be held in the storage node of the memory cell 100[k,1].

[0297] When writing data to the memory cells 100[1,1] to 100[n,1], the wiring RBL[1] can be controlled independently and does not need to be set to a specific potential. For example, the potential of the wiring RBL[1] may be set to a low-level potential. The potentials of the nodes N1[1] and N2[1] may be set to a low-level potential.

[0298] <<Write operation>> Based on the above, an example of a write operation will be described with reference to the timing chart in Fig. 38A. In a period T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL[1], the node N1[1], and the node N2[1] are all low-level potentials.

[0299] In a period T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. As a result, the transistors WTr included in each of the memory cells 100[1,1] to 100[n,1] are fully on. Then, data D[n] is supplied to the wiring WBL[1]. Since the transistors WTr included in each of the memory cells 100[1,1] to 100[n,1] are fully on, the data D[n] is supplied to the storage node of the memory cell 100[n,1].

[0300] In the period T12, a low-level potential is supplied to the wiring WWL[n], and a high-level potential is continuously supplied to the wirings WWL[n-1] to WWL[1]. As a result, the transistor WTr included in the memory cell 100[n,1] is turned off, and the transistors WTr included in each of the memory cells 100[n-1,1] to 100[1,1] are maintained in an on state. Then, data D[n-1] is supplied to the wiring WBL[1]. Since the transistors WTr included in each of the memory cells 100[n-1,1] to 100[1,1] are fully on, the data D[n-1] is supplied to the storage node of the memory cell 100[n-1,1]. Since the transistor WTr of the memory cell 100[n,1] is turned off, the data D[n] written to the memory cell 100[n,1] in the period T11 is held.

[0301] In the period T13, similarly to the periods T11 and T12, data D[n-2] to D[2] are sequentially written to the memory cells 100[n-2,1] to 100[2,1], respectively.

[0302] Specifically, the transistors WTr of the memory cells 100[n,1] to 100[k+1,1] to which data has already been written are turned off, the transistors WTr of the memory cells 100[k,1] to 100[1,1] to which data has not been written are turned on fully, and data D[k] is supplied from the wiring WBL and written to the memory node of the memory cell 100[k,1]. After writing of the data D[k] to the memory cell 100[k,1] is completed, the transistor WTr of the memory cell 100[k,1] is turned off. Then, data D[k-1] is supplied from the wiring WBL[1] and written to the memory node of the memory cell 100[k-1,1].

[0303] A write operation when k is 1 will be described in the period T14. In the period T14, a low-level potential is supplied to the wirings WWL[n] to WWL[2], and a high-level potential is continuously supplied to the wiring WWL[1]. As a result, the transistors WTr in the memory cells 100[n,1] to 100[2,1] are turned off, and the transistor WTr in the memory cell 100[1,1] remains on. Then, data D[1] is supplied to the wiring WBL[1]. Since the transistor WTr in the memory cell 100[1,1] is fully on, the data D[1] reaches the memory node of the memory cell 100[1,1] and is written therein. In addition, since the transistors WTr of the memory cells 100[n,1] to 100[2,1] are in the off state, the data D[n] to D[2] stored in the memory cells 100[n,1] to 100[2,1], respectively, are retained.

[0304] In this manner, data can be written to the memory cells 100[1,1] to 100[n,1].

[0305] In the present embodiment, the write operation has been described with a focus on the memory string 200[1], but in the circuit configuration of the semiconductor device 300, when a high-level potential is supplied to the wiring WWL[k], all of the transistors WTr electrically connected to the wiring WWL[k] are turned on. Therefore, data is written not only to the memory string 200[1], but also to the memory strings 200[2] to 200[m] at the same time.

[0306] The memory cell 100 described in this embodiment is an OS memory. Therefore, the semiconductor device 300 including the memory cell 100 does not require an erase operation before rewriting data, and can achieve a high-speed write operation.

[0307] Furthermore, when data is written (rewritten) to a memory cell 100 close to the wiring WBL, the operation of writing data to a memory cell 100 farther from the wiring WBL than the memory cell 100 can be omitted. For example, when data is written (rewritten) to the memory cell 100[1,1], the operation of writing data to the memory cells 100[2,1] to 100[n,1] can be omitted. When data is written to the memory cell 100[2,1], the operation of writing data to the memory cells 100[3,1] to 100[n,1] can be omitted.

[0308] By storing data that is frequently rewritten in the memory cell 100 close to the wiring WBL, the time required to write (rewrite) the data can be shortened, that is, the data writing (rewriting) speed can be increased.

[0309] By operating in this way, OS NAND type (including 3D OS NAND type) storage devices can be made to operate like RAM.

[0310] <<Read operation>> 38B shows an example in which data D[1] to data D[n] are read from memory cells 100[1,1] to 100[n,1], respectively. Note that at this time, the transistors WTr are required to be in an off state in order to maintain the data held in each memory cell 100. Therefore, during the operation of reading data from the memory cells 100[1,1] to 100[n,1], the potentials of the wirings WWL[1] to WWL[n] are set to low-level potentials.

[0311] 37, when reading data from a specific memory cell 100, the transistor RTr of the memory cell 100 to be read is operated in a saturated region after the transistor RTr of the other memory cells 100 is fully on. In other words, the magnitude of the current flowing between the source and drain of the transistor RTr of the memory cell 100 to be read is determined according to the voltage between the source and drain and the data held in the memory cell 100 to be read.

[0312] For example, consider a case where data stored in the memory cell 100[k,1] is read out. In the read operation, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] in order to turn on the transistors RTr included in each of the memory cells 100[1,1] to 100[n,1] excluding the memory cell 100[k,1].

[0313] On the other hand, since the transistor RTr in the memory cell 100[k,1] switches between an on state and an off state depending on the data stored in the memory cell 100[k,1], the potential of the wiring RWL[k] needs to be the same as that when the data is written to the memory cell 100[k,1]. Note that the potential of the wiring RWL[k] during the write operation and the read operation is considered to be a low-level potential here.

[0314] For example, a potential of +3 V is applied to the node N1[1], and a potential of 0 V is applied to the node N2[1]. Then, the node N2[1] is set in a floating state, and the potential of the node N2[1] is measured thereafter. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high level potential, the transistors RTr included in each of the memory cells 100[1,1] to 100[n,1] excluding the memory cell 100[k,1] are fully turned on.

[0315] On the other hand, since the voltage between the source and drain of transistor RTr in memory cell 100[k,1] is determined by the gate potential of transistor RTr and the potential of node N1[1], the potential of node N2[1] is determined according to the data held in the memory node of memory cell 100[k,1].

[0316] In this manner, the data stored in the memory cell 100[k,1] can be read.

[0317] Based on the above, an example of a read operation will be described with reference to the timing chart in Figure 38(B). In the period T20, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1[1], and the node N2[1] are all low-level potentials. In particular, the node N2[1] is in a floating state. Data D[1] to D[n] are stored in the storage nodes of the memory cells 100[1,1] to 100[n,1], respectively.

[0318] In the period T21, a low-level potential is supplied to the wiring RWL[1], and a high-level potential is supplied to the wirings RWL[2] to RWL[n]. This causes the transistors RTr in each of the memory cells 100[2,1] to 100[n,1] to be fully on. The on or off state of the transistor RTr in the memory cell 100[1,1] is determined according to the data D[1] stored in the memory node of the memory cell 100[1,1].

[0319] In addition, the potential V R This causes the potential of node N1[1] to rise to V R The potential of the node N2[1] is V R and the data held in the memory node of the memory cell 100[1,1]. Here, the potential of the node N2[1] is V D[1] Then, the potential V of the node N2[1] D[1] By measuring the potential difference, the data D[1] stored in the storage node of the memory cell 100[1,1] can be read.

[0320] In the period T22, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. A low-level potential is supplied to the node N2[1], and then the node N2[1] is in a floating state. That is, in the period T22, the potentials of the wirings RWL[1] to RWL[n] and the node N2[1] are the same as those in the period T20. The wiring RWL[1] continues to be supplied with the potential V R In this operation example, the wiring RBL[1] is supplied with a potential V R Therefore, the potential V R will continue to be supplied.

[0321] In the period T23, a low-level potential is supplied to the wiring RWL[2], and a high-level potential is supplied to the wiring RWL[1], the wiring RWL[3] to the wiring RWL[n]. As a result, the transistors RTr in the memory cell 100[1,1], the memory cell 100[3,1] to the memory cell 100[n,1] are fully turned on. The on or off state of the transistor RTr in the memory cell 100[2,1] is determined according to the data D[2] stored in the memory node of the memory cell 100[2,1]. The potential V RAs a result, the potential of the node N2[1] is equal to the potential V R The potential of the node N2[1] is determined according to the data stored in the memory node of the memory cell 100[2,1]. D[2] Then, the potential V of the node N2[1] D[2] By measuring the potential difference, the data D[2] stored in the storage node of the memory cell 100[2,1] can be read.

[0322] In the period T24, similar to the read operations in the periods T22 and T23, data D[3] to D[n-1] are sequentially read from the memory cells 100[3,1] to 100[n-1,1], respectively.

[0323] Specifically, when data D[k] is read from the memory cell 100[k,1], the potential of the node N2[1] is set to a low level potential, and the node N2[1] is set to a floating state, and then a high level potential is supplied to the wirings RWL[1] to RWL[n] except for the wiring RWL[k], so that the transistors RTr included in the memory cells 100[1,1] to 100[n,1] except for the memory cell 100[k,1] are fully turned on, and the transistor RTr included in the memory cell 100[k,1] is turned on according to the data D[k]. Next, the potential of the node N1[1] is set to V R By setting the node N2[1] to the low potential, the potential of the node N2[1] becomes a potential corresponding to the data D[k], and the data D[k] can be read by measuring this potential. After the data D[k] stored in the memory cell 100[k,1] is read, in preparation for the next read operation, low-level potentials are supplied to the wirings RWL[1] to RWL[n] and a low-level potential is supplied to the node N2[1], and then the node N2[1] is set to a floating state.

[0324] In the period T25, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. In addition, a low-level potential is supplied to the node N2[1], and then the node N2[1] is put into a floating state. In other words, in the period T25, the potentials of the wirings RWL[1] to RWL[n] and the node N2[1] are the same as those in the period T20.

[0325] In the period T26, a low-level potential is supplied to the wiring RWL[n], and a high-level potential is supplied to the wirings RWL[1] to RWL[n-1]. As a result, the transistors RTr in the memory cells 100[1,1] to 100[n-1,1] are fully turned on. The transistor RTr in the memory cell 100[n,1] is turned on in accordance with the data D[n] stored in the memory node of the memory cell 100[n,1]. The wiring RBL[1] is supplied with a potential V R As a result, the potential of the node N2[1] is equal to the potential V R and the data held in the memory node of the memory cell 100[n,1]. Here, the potential of the node N2[1] is V D[n] Then, the potential V of the node N2[1] D[n] By measuring the potential difference, the data D[n] stored in the storage node of the memory cell 100[n,1] can be read.

[0326] In this manner, the data stored in the memory cells 100[1,1] to 100[n,1] can be read.

[0327] In this embodiment, the read operation has been described with a focus on the memory string 200[1], but the circuit configuration of the semiconductor device 300 allows data to be read not only from the memory string 200[1], but also from the memory strings 200[2] to 200[m] at the same time. In addition, by turning off the transistor WTr, the data held in the memory node is not damaged even during the data read operation. Therefore, only the data contained in any memory string 200 can be read.

[0328] <Structural example of semiconductor device> Next, a structural example of the semiconductor device 300 will be described.

[0329] Fig. 39(A) to Fig. 39(C) are schematic diagrams showing an example of a portion of a semiconductor device 300. Fig. 39(A) shows a perspective view of a portion of the semiconductor device, and Fig. 39(B) shows a top view of a portion of the semiconductor device. Furthermore, Fig. 39(C) shows a cross-sectional view corresponding to the dashed line Z1-Z2 in Fig. 39(B).

[0330] The semiconductor device has a structure in which a wiring WL (a wiring WWL or a wiring RWL) and an insulator (a region not hatched in FIGS. 39A to 39C) are stacked.

[0331] An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. Then, in order to provide a memory cell 100 in a region AR through which the wiring WL penetrates, an insulator, a conductor, and a semiconductor are formed in the opening. Note that the conductor functions as a source electrode or a drain electrode of a transistor included in the memory cell 100, and the semiconductor functions as a channel formation region of the transistor included in the memory cell 100. Alternatively, instead of forming the conductor, a channel formation region and a low resistance region may be formed in the semiconductor, and the low resistance region may be used as a source or drain of a transistor.

[0332] In Figures 39(A) to (C), the region in which the insulator, the conductor, and the semiconductor are formed in the opening is illustrated as a region HL. In particular, in Figure 39(A), the region HL inside the structure is illustrated by a dashed line. Note that, when a backgate is provided in the transistor of the memory cell 100, the conductor in the region HL may also function as a wiring BGL for electrically connecting to the backgate. That is, the memory string 200 is formed in the region HL. Also, the memory string 200 is formed in the region SA.

[0333] The region TM where the wiring WL is exposed functions as a connection terminal for applying a potential to the wiring WL. That is, by electrically connecting the wiring WL to an arbitrary wiring in the region TM, a potential can be applied to the gate of the transistor included in the memory cell 100. The wiring WL corresponds to the conductor 102 or 103 in FIG. 1A.

[0334] Note that the shape of the region TM is not limited to the configuration examples shown in Fig. 39(A) to Fig. 39(C). For example, the configuration of the semiconductor device 300 according to one embodiment of the present invention may be such that an insulator is formed on the region TM, an opening is provided in the insulator, and a conductor PG is formed to fill the opening, as shown in Fig. 40(A) to Fig. 40(C).

[0335] Fig. 40(A) shows a perspective view of a portion of the semiconductor device, and Fig. 40(B) shows a top view of a portion of the semiconductor device. Furthermore, Fig. 40(C) shows a cross-sectional view corresponding to the dashed line Z1-Z2 in Fig. 40(B). Note that wiring ER is formed on the conductor PG, and this electrically connects the wiring ER and wiring WL. In Fig. 40(A), the conductor PG provided inside the structure is shown by a dashed line, and the dashed line of the region HL is omitted.

[0336] <Example of connection to peripheral circuits> The semiconductor device 300 according to an embodiment of the present invention may have peripheral circuits of a memory cell array, such as a read circuit and a precharge circuit, formed in a lower layer. In this case, Si transistors may be formed on a silicon substrate or the like to configure the peripheral circuits, and then the semiconductor device 300 according to an embodiment of the present invention may be formed on the peripheral circuits. Fig. 41(A) is a cross-sectional view in which the peripheral circuits are configured with planar type Si transistors, and the semiconductor device 300 according to an embodiment of the present invention is formed in an upper layer thereof. Fig. 42(A) is a cross-sectional view in which the peripheral circuits are configured with FIN type Si transistors, and the semiconductor device 300 according to an embodiment of the present invention is formed in an upper layer thereof.

[0337] 41(A) and 42(A), Si transistors constituting the peripheral circuit are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors. Conductors 1730 are formed to extend in the channel width direction, and are connected to other Si transistors or the conductors 1712 (not shown).

[0338] The substrate described in the above embodiment can be used as the substrate 1700. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

[0339] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. A semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. In Fig. 41(A) and Fig. 42(A), a single crystal silicon wafer is used as the substrate 1700.

[0340] 41(A) and 42(A) show a conductor 1221, a conductor 1222, a conductor 1223, and an insulator 1202 provided on the memory string 200 in the region SA. The conductor 1221 is electrically connected to the source or drain of the transistor RTr located at the end of the memory string 200.

[0341] The insulator 1202 is provided to cover the conductor 1221. The conductor 1222 is provided so as to be embedded in the insulator 1202 in a region overlapping with the conductor 118. The conductor 1223 is provided above the insulator 1202 and is electrically connected to the conductor 118 via the conductor 1222.

[0342] 41(A) and 42(A), an insulator 1203 is formed to cover the conductor 1223, the insulator 1202, the memory string 200, and the like. It is preferable to use an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203. By using an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203, it is possible to suppress the diffusion of impurities from the outside (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into the memory string 200.

[0343] Here, the details of the Si transistor will be described. The planar type Si transistor shown in FIG. 41(A) is a cross-sectional view in the channel length direction, and the planar type Si transistor shown in FIG. 41(B) is a cross-sectional view in the channel width direction. The Si transistor has a channel formation region 1793 provided in a well 1792, a low concentration impurity region 1794 and a high concentration impurity region 1795 (collectively simply referred to as impurity regions), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of metal silicide or the like.

[0344] The FIN type Si transistor shown in FIG. 42(A) is a cross-sectional view in the channel length direction, and the FIN type Si transistor shown in FIG. 42(B) is a cross-sectional view in the channel width direction. In the Si transistor shown in FIG. 42(A) and (B), the channel formation region 1793 has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and upper surface of the channel formation region 1793. In this embodiment, a case has been shown in which a convex portion is formed by processing a part of a semiconductor substrate, but a semiconductor layer having a convex shape may be formed by processing an SOI substrate. Note that the symbols shown in FIG. 42(A) and (B) are the same as those shown in FIG. 41(A) and (B).

[0345] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0346] (Embodiment 3) In this embodiment, a semiconductor device 400 including a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 400 can function as a memory device.

[0347] Fig. 43 shows a block diagram illustrating a configuration example of a semiconductor device 400. The semiconductor device 400 shown in Fig. 43 has a driver circuit 410 and a memory array 420. The memory array 420 has one or more memory cells 30. Fig. 43 shows an example in which the memory array 420 has a plurality of memory cells 30 arranged in a matrix.

[0348] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412, and a voltage generating circuit 428.

[0349] In the semiconductor device 400, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0350] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 412.

[0351] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit 412 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal for the peripheral circuit 411 so that this operation mode is executed.

[0352] The voltage generating circuit 428 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 428. For example, when an H-level signal is provided as the signal WAKE, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

[0353] The peripheral circuit 411 is a circuit for writing and reading data to and from the memory cells 30. The peripheral circuit 411 has a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

[0354] The row decoder 441 and the column decoder 442 have a function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to be accessed, and the column decoder 442 is a circuit for specifying a column to be accessed. The row driver 423 has a function of selecting the wiring WL specified by the row decoder 441. The column driver 424 has a function of writing data to the memory cell 30, a function of reading data from the memory cell 30, a function of holding the read data, and the like.

[0355] The input circuit 425 has a function of holding a signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) to be written to the memory cell 30. The data (Dout) read from the memory cell 30 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.

[0356] PSW241 is the V to the peripheral circuit 415DD The PSW 242 has the function of controlling the supply of V HM In this embodiment, the high power supply voltage of the semiconductor device 400 is V DD and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to drive the word line high, and V DD The on / off state of the PSW 241 is controlled by the signal PON1, and the on / off state of the PSW 242 is controlled by the signal PON2. DD Although the number of power domains to which the power is supplied is set to one, it is also possible to set it to multiple. In this case, a power switch may be provided for each power domain.

[0357] The memory string 200 can be used as the memory cell 30. Also, a memory cell other than the memory string 200 may be used as the memory cell 30. An example of the configuration of a memory cell applicable to the memory cell 30 will be described with reference to Figs. 44 and 45.

[0358] [DOSRAM] 44A shows an example of a circuit configuration of a memory cell of a DRAM. In this specification and the like, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 31 includes a transistor M1 and a capacitance element CA. The transistor M1 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0359] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring CAL.

[0360] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0361] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0362] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0363] Furthermore, the memory cell that can be used for the memory cell 30 is not limited to the memory cell 31, and the circuit configuration can be changed. For example, the memory cell 32 shown in FIG. 44B may be used. In the memory cell 32, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. With this configuration, the same potential as that of the gate of the transistor M1 can be applied to the back gate of the transistor M1, and therefore, when the transistor M1 is in a conductive state, the current flowing through the transistor M1 can be increased.

[0364] Also, for example, a memory cell that can be used for memory cell 30 may be a memory cell configured with a transistor having a single gate structure, that is, a transistor M1 without a back gate. An example of the circuit configuration of such a memory cell is shown in FIG. 44C. Memory cell 33 shown in FIG. 44C has a configuration in which the back gate is removed from transistor M1 of memory cell 31. Note that by applying memory cell 33 to memory cell 30, the manufacturing process of memory cell 30 can be shortened compared to memory cell 31 and memory cell 32, since transistor M1 does not have a back gate.

[0365] Note that it is preferable to use an OS transistor as the transistor M1. An OS transistor has a characteristic that its off-state current is extremely small. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 31, the memory cell 32, and the memory cell 33.

[0366] [NOSRAM] 44D shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 34 has a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a front gate and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0367] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0368] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL.

[0369] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be controlled by applying an arbitrary potential to the wiring BGL.

[0370] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby holding the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0371] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, so the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3).

[0372] Furthermore, the memory cells that can be used for the memory cells 30 are not limited to the memory cells 34, and the circuit configuration can be changed as appropriate.

[0373] For example, a memory cell that can be used for the memory cell 30 may have the configuration of a memory cell 35 shown in Fig. 44(E). Like the transistor M1 included in the memory cell 32 in Fig. 44(B), the memory cell 35 has a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. With this configuration, the same potential as that of the gate of the transistor M2 can be applied to the back gate of the transistor M2, and therefore the current flowing through the transistor M2 can be increased when the transistor M2 is in a conductive state.

[0374] Furthermore, for example, a memory cell that can be used for memory cell 30 may be a memory cell configured with a transistor M2 that does not have a backgate. An example of the circuit configuration of the memory cell is shown in Fig. 44(F). Memory cell 36 has a configuration in which the backgate is removed from transistor M2 of memory cell 34. By applying memory cell 36 to memory cell 30, the manufacturing process of memory cell 30 can be shortened compared to memory cell 34 and memory cell 35, since transistor M2 does not have a backgate.

[0375] Also, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Fig. 44(G). The memory cell 37 is configured such that the wiring WBL and the wiring RBL of the memory cell 34 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 37 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0376] Note that an oxide semiconductor containing at least one of indium, the element M, and zinc can be used for the channel formation region of the transistor M2 and / or the transistor M3. That is, an OS transistor is preferably used as the transistor M2 and / or the transistor M3. In particular, it is preferable that the channel formation region of the transistor M2 and / or the transistor M3 contain an oxide semiconductor containing indium, gallium, or zinc.

[0377] Since an OS transistor has a characteristic that its off-state current is extremely small, by using an OS transistor as the transistor M2 and / or the transistor M3, the leakage current of the transistor M2 and / or the transistor M3 can be made extremely low. In particular, since written data can be held for a long time by the transistor M2, the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be made unnecessary. In addition, since the leakage current is extremely low, multi-level data or analog data can be held in the memory cells 34, 35, 36, and 37.

[0378] The memory cell 34, the memory cell 35, the memory cell 36, and the memory cell 37 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0379] Note that a Si transistor may be used as the transistor M3. A Si transistor may have higher field-effect mobility than an OS transistor depending on the crystal state of silicon used in a semiconductor layer.

[0380] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0381] 45A shows a three-transistor, one-capacitor gain cell type memory cell. The memory cell 38 includes transistors M4 to M6 and a capacitative element CC. The transistor M4 has a front gate and a back gate.

[0382] A first terminal of the transistor M4 is connected to a first terminal of the capacitance element CC, a second terminal of the transistor M4 is connected to the wiring BIL, a gate of the transistor M4 is connected to the wiring WWL, and a back gate of the transistor M4 is electrically connected to the wiring BGL. A second terminal of the capacitance element CC is electrically connected to a first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to a first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitance element CC. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RWL.

[0383] The wiring BIL functions as a bit line, the wiring WWL functions as a write word line, and the wiring RWL functions as a read word line.

[0384] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M4. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M4 can be increased or decreased.

[0385] The wiring GNDL is a wiring that provides a low level potential.

[0386] Data is written by applying a high-level potential to the wiring WWL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitance element CC. Specifically, when the transistor M4 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitance element CC and the gate of the transistor M5. After that, a low-level potential is applied to the wiring WWL, turning off the transistor M4, thereby holding the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5.

[0387] Data is read by precharging the wiring BIL with a predetermined potential, then putting the wiring BIL in an electrically floating state, and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5). Here, by reading the potential of the wiring BIL, the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).

[0388] In addition, the circuit configuration of the memory cell that can be used for the memory cell 30 can be appropriately changed. For example, like the transistor M1 of the memory cell 32 shown in FIG. 44(B) and the transistor M2 of the memory cell 35 shown in FIG. 44(E), the back gate of the transistor M4 of the memory cell 38 may be connected to the wiring WOL instead of the wiring BGL (not shown). With this configuration, the same potential as that of the gate of the transistor M4 can be applied to the back gate of the transistor M4, so that the current flowing through the transistor M4 when the transistor M4 is in a conductive state can be increased. Also, like the transistor M1 of the memory cell 33 shown in FIG. 44(C) and the transistor M2 of the memory cell 36 shown in FIG. 44(F), the memory cell 38 may have a configuration in which the transistor M4 does not have a back gate. With this configuration, the transistor M4 does not have a back gate, and the manufacturing process of the memory cell can be shortened.

[0389] Note that it is preferable to use OS transistors as the transistors M4 to M6. Since OS transistors have characteristics of extremely low off-state current, the use of OS transistors as the transistors M4 to M6 can significantly reduce the leakage current of the transistors M4 to M6. In particular, since written data can be held for a long time by the transistor M4, the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be eliminated.

[0390] Note that Si transistors may be used as the transistors M5 and M6 described in this embodiment. As described above, a Si transistor may have higher field-effect mobility than an OS transistor depending on the crystal state of silicon used in a semiconductor layer.

[0391] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0392] [OS-SRAM] FIG. 45B shows an example of a static random access memory (SRAM) using OS transistors. In this specification and the like, an SRAM using OS transistors is called an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 39 shown in FIG. 45B is a memory cell of an SRAM capable of backing up data.

[0393] The memory cell 39 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. The transistors M7 to M10 have a front gate and a back gate. The transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0394] A first terminal of the transistor M7 is connected to the wiring BIL, and a second terminal of the transistor M7 is connected to a first terminal of the transistor MS1, a first terminal of the transistor MS3, a gate of the transistor MS2, a gate of the transistor MS4, and a first terminal of the transistor M10. A gate of the transistor M7 is connected to the wiring WOL, and a back gate of the transistor M7 is connected to the wiring BGL1. A first terminal of the transistor M8 is connected to the wiring BILB, and a second terminal of the transistor M8 is connected to a first terminal of the transistor MS2, a first terminal of the transistor MS4, a gate of the transistor MS1, a gate of the transistor MS3, and a first terminal of the transistor M9. A gate of the transistor M8 is connected to the wiring WOL, and a back gate of the transistor M8 is connected to the wiring BGL2.

[0395] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0396] A second terminal of the transistor M9 is connected to a first terminal of the capacitance element CD1, a gate of the transistor M9 is connected to the wiring BRL, and a back gate of the transistor M9 is connected to the wiring BGL3. A second terminal of the transistor M10 is connected to a first terminal of the capacitance element CD2, a gate of the transistor M10 is connected to the wiring BRL, and a back gate of the transistor M10 is connected to the wiring BGL4.

[0397] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0398] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0399] The wirings BGL1 to BGL4 function as wirings for applying a potential to the back gates of the transistors M7 to M10, respectively. By applying any potential to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 can be increased or decreased, respectively.

[0400] The line VDL is a line that applies a high-level potential, and the line GNDL is a line that applies a low-level potential.

[0401] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0402] Incidentally, since the memory cell 39 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is in a conductive state, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are in a conductive state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to make the transistors M7 to M10 non-conductive, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.

[0403] Data is read out by precharging the wirings BIL and BILB to a predetermined potential beforehand, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 39 and output to the wiring BILB. Also, the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 39 and output to the wiring BIL. In the wirings BIL and BILB, the potentials change from the precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read out from the potential of the wiring BIL or wiring BILB.

[0404] Note that it is preferable to use OS transistors as the transistors M7 to M10. In particular, it is preferable that the transistors M7 to M10 include an oxide semiconductor containing indium, gallium, or zinc in a channel formation region. An OS transistor using an oxide semiconductor containing indium, gallium, or zinc has a characteristic of having an extremely small off-state current. Therefore, by using OS transistors as the transistors M7 to M10, the leakage current of the transistors M7 to M10 can be significantly reduced. In particular, written data can be held for a long time by the transistors M7 to M10, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be eliminated.

[0405] Note that Si transistors may be used as the transistors MS1 to MS4.

[0406] The semiconductor device 400 can be used as a NAND type memory device by using the memory string 200 as the memory cell 30. Also, the semiconductor device 400 can be used as a NOR type memory device by using the memory cells 31 to 39 as the memory cells 30.

[0407] The driver circuit 410 and the memory array 420 of the semiconductor device 400 may be provided on the same plane. Alternatively, as shown in Fig. 46(A), the driver circuit 410 and the memory array 420 may be provided so as to overlap each other. By providing the driver circuit 410 and the memory array 420 so as to overlap each other, the signal propagation distance can be shortened. Alternatively, as shown in Fig. 46(B), the memory array 420 may be provided in multiple layers on the driver circuit 410.

[0408] Also, as shown in FIG. 46(C), memory arrays 420 may be provided above and below the driving circuit 410. FIG. 46(C) shows an example in which one memory array 420 is provided above and below the driving circuit 410. By arranging the driving circuit 410 between a plurality of memory arrays 420, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 420 stacked above the driving circuit 410 and the memory array 420 stacked below the driving circuit 410 may each be one or more. It is preferable that the number of memory arrays 420 stacked above the driving circuit 410 and the number of memory arrays 420 stacked below the driving circuit 410 are equal.

[0409] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0410] (Embodiment 4) In this embodiment mode, an example of a semiconductor wafer on which a semiconductor device or the like described in the above embodiment is formed and an electronic component in which the semiconductor device is incorporated will be described.

[0411] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG.

[0412] 47A includes a wafer 4801 and a plurality of circuit portions 4802 provided on an upper surface of the wafer 4801. Note that a portion of the upper surface of the wafer 4801 where the circuit portions 4802 do not exist is a spacing 4803, which is a region for dicing.

[0413] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0414] The next step is a dicing step. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) shown by dashed lines. In order to facilitate the dicing step, it is preferable that the spacing 4803 is arranged so that the multiple scribe lines SCL1 are parallel to each other, the multiple scribe lines SCL2 are parallel to each other, and the scribe lines SCL1 and SCL2 are perpendicular to each other.

[0415] By performing a dicing process, a chip 4800a as shown in Fig. 47(B) can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that it is preferable to make the spacing 4803a as small as possible. In this case, it is sufficient that the width of the spacing 4803 between adjacent circuit portions 4802 is approximately equal to the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.

[0416] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 47 (A). For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on a manufacturing process of the element and an apparatus for manufacturing the element.

[0417] <Electronic components> 47C shows a perspective view of an electronic component 4700 and a substrate (a mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Fig. 47C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0418] 47(C) is partially omitted in order to show the inside of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0419] 47D shows a perspective view of an electronic component 4730. The electronic component 4730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 4730 includes an interposer 4731 provided on a package substrate 4732 (printed substrate), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 provided on the interposer 4731.

[0420] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), etc. The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0421] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0422] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 4731, and the integrated circuits and the package substrate 4732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0423] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0424] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0425] In addition, in SiPs and MCMs that use silicon interposers, reliability is less likely to decrease due to differences in the expansion coefficient between the integrated circuit and the interposer. In addition, because the surface of the silicon interposer is highly flat, connection defects are less likely to occur between the integrated circuit mounted on the silicon interposer and the silicon interposer. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0426] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 4730. When providing a heat sink, it is preferable to make the height of an integrated circuit provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in this embodiment, it is preferable to make the height of the semiconductor device 4710 and the height of the semiconductor device 4735 uniform.

[0427] In order to mount the electronic component 4730 on another substrate, an electrode 4733 may be provided on the bottom of the package substrate 4732. FIG. 47D shows an example in which the electrode 4733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. The electrode 4733 may also be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0428] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. For example, a mounting method such as a Staggered Pin Grid Array (SPGA), a Land Grid Array (LGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN) can be used.

[0429] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0430] (Embodiment 5) In this embodiment mode, an example of a processing device that can include a semiconductor device such as the memory device described in the above embodiment mode will be described.

[0431] Fig. 48 shows a block diagram of the central processing unit 1100. In Fig. 48, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the central processing unit 1100.

[0432] The central processing unit 1100 shown in Fig. 48 has an ALU 1191 (ALU: arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may be provided on separate chips.

[0433] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0434] The central processing unit 1100 shown in Fig. 48 is merely one example of a simplified configuration, and the actual central processing unit 1100 has a wide variety of configurations depending on its application. For example, the central processing unit 1100 shown in Fig. 48 or a configuration including an arithmetic circuit may be one core, and a configuration including multiple such cores may be configured so that each core operates in parallel, that is, a configuration like a GPU. In addition, the number of bits that the central processing unit 1100 can handle in the internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0435] An instruction input to the central processing unit 1100 via the bus interface 1198 is input to the instruction decoder 1193 , decoded, and then input to the ALU controller 1192 , the interrupt controller 1194 , the register controller 1197 , and the timing controller 1195 .

[0436] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits based on their priority and mask state while the central processing unit 1100 is executing a program. The register controller 1197 generates an address for the register 1196, and reads from and writes to the register 1196 depending on the state of the central processing unit 1100.

[0437] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0438] 48, a memory device is provided in the register 1196 and the cache 1199. As the memory device, for example, the memory devices described in the above embodiments can be used.

[0439] In the central processing unit 1100 shown in FIG. 48, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, it selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 1196. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0440] The semiconductor device 400 and the central processing unit 1100 shown in the above embodiment can be provided overlapping each other. Figures 49(A) and (B) show perspective views of a semiconductor device 1150A. The semiconductor device 1150A has a semiconductor device 400 functioning as a memory device on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 have an overlapping area. In order to make the configuration of the semiconductor device 1150A easier to understand, the central processing unit 1100 and the semiconductor device 400 are shown separately in Figure 49(B).

[0441] By stacking the semiconductor device 400 and the central processing unit 1100, the connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows power consumption to be reduced.

[0442] As described in the above embodiment, by using an OS NAND type memory device for the semiconductor device 400, some or all of the memory cells 30 included in the semiconductor device 400 can function as RAM. Therefore, the semiconductor device 400 can function as a main memory. The semiconductor device 400 functioning as the main memory is connected to a cache 1199 via a cache interface 1189.

[0443] Whether the semiconductor device 400 functions as a main memory (RAM) or as a storage is determined by a control circuit 412 shown in Fig. 43. The control circuit 412 can cause some of the memory cells 30 of the semiconductor device 400 to function as RAM based on a signal supplied from the central processing unit 1100.

[0444] The semiconductor device 400 can cause some of the multiple memory cells 30 to function as RAM and the other to function as storage. By using an OS NAND type storage device for the semiconductor device 400, the semiconductor device 400 can have both a function as a main memory and a function as a storage. The semiconductor device 400 according to one embodiment of the present invention can function as, for example, a universal memory.

[0445] Furthermore, when the semiconductor device 400 is used as a main memory, the storage capacity can be increased or decreased as required. Furthermore, when the semiconductor device 400 is used as a cache, the storage capacity can be increased or decreased as required.

[0446] 43 may have a function of performing error detection and correction (also called ECC: Error Check and Correct) when data is moved or copied between an area functioning as a storage and an area functioning as a main memory of the semiconductor device 400. The control circuit 412 may have a function of performing ECC when data is moved or copied between an area functioning as a main memory of the semiconductor device 400 and the cache 1199.

[0447] Also, a plurality of semiconductor devices 400 may be provided overlapping the central processing unit 1100. FIGS. 50(A) and (B) show perspective views of a semiconductor device 1150B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the central processing unit 1100. The central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. In order to make the configuration of the semiconductor device 1150B easier to understand, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 50(B).

[0448] The semiconductor device 400a and the semiconductor device 400b function as memory devices. For example, a NOR type memory device may be used as the semiconductor device 400a. Also, a NAND type memory device may be used as the semiconductor device 400b. Since a NOR type memory device can operate faster than a NAND type memory device, for example, a part of the semiconductor device 400a may be used as a main memory and / or a cache 1199. Note that the semiconductor device 400a and the semiconductor device 400b may be stacked in the reverse order.

[0449] 51(A) and (B) show perspective views of the semiconductor device 1150C. The semiconductor device 1150C has a configuration in which the central processing unit 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. Therefore, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. In order to make the configuration of the semiconductor device 1150C easier to understand, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 51(B).

[0450] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 400a and the central processing unit 1100 and the communication speed between the semiconductor device 400b and the central processing unit 1100. In addition, the power consumption can be reduced compared to the semiconductor device 1150B.

[0451] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0452] (Embodiment 6) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0453] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 52(A) shows various memory devices used in semiconductor devices by hierarchy. The higher the layer, the faster the operating speed is required for the memory device, and the lower the layer, the larger the memory capacity and the higher the recording density are required for the memory device. Figure 52(A) shows, from the top layer, memories embedded as registers in arithmetic processing devices such as CPUs, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), and 3D NAND memories.

[0454] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0455] SRAM is used, for example, in caches. Caches have the function of duplicating and storing part of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate faster than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0456] DRAM is used, for example, as a main memory. The main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 Gbit / mm 2 More than 0.3Gbit / mm 2 The following is the result.

[0457] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time and various programs used in computing devices. Therefore, storage requires a larger memory capacity and a higher recording density than the operating speed. The recording density of memory devices used in storage is approximately 0.6 Gbit / mm 2 More than 6.0Gbit / mm 2 The following is the result.

[0458] A storage device according to an embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device according to an embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 including both a hierarchical level where a cache is located and a hierarchical level where a main memory is located. The storage device according to an embodiment of the present invention can be suitably used as a storage device located in a boundary area 902 including both a hierarchical level where a main memory is located and a hierarchical level where a storage is located.

[0459] Moreover, a storage device according to one embodiment of the present invention can be preferably used in both a hierarchy where a main memory is located and a hierarchy where a storage is located. Moreover, a storage device according to one embodiment of the present invention can be preferably used in a hierarchy where a cache is located. Fig. 52(B) shows various hierarchies of storage devices different from those in Fig. 52(A).

[0460] 52B shows, from the top layer, a memory embedded as a register in an arithmetic processing unit such as a CPU, an SRAM used as a cache, and a 3D OS NAND memory. A storage device according to one embodiment of the present invention can be used for the cache, main memory, and storage. Note that when a high-speed memory of 1 GHz or higher is required as the cache, the cache is embedded in an arithmetic processing unit such as a CPU.

[0461] Furthermore, the memory device according to one embodiment of the present invention is not limited to a NAND type and may be a NOR type. Furthermore, a NAND type and a NOR type may be used in combination.

[0462] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0463] An example of an electronic device including a memory device of one embodiment of the present invention will be described. Note that each of FIGS. 53(A) to 53(J) and 54(A) to 54(E) illustrates an electronic device including an electronic component 4700 or an electronic component 4730 including the memory device.

[0464] [mobile phone] 53A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0465] The information terminal 5500 can store temporary files (eg, caches when using a web browser) generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0466] [Wearable devices] 53B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0467] Like the information terminal 5500 described above, the wearable device can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0468] [Information terminal] 53C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0469] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0470] In the above description, a smartphone, a wearable terminal, and a desktop information terminal are illustrated in Fig. 53(A) to (C) as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0471] [electric appliances] 53(D) illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with the Internet of Things (IoT).

[0472] A storage device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the ingredients to an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can hold in the storage device a temporary file that is generated when transmitting the information.

[0473] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0474] [Game consoles] 53(E) illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0475] Furthermore, FIG. 53(F) illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not illustrated in FIG. 53(F), the controller 7522 can include a display unit for displaying game images, a touch panel or stick as an input interface other than buttons, a rotary knob, a sliding knob, and the like. The shape of the controller 7522 is not limited to that shown in FIG. 53(F), and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger as a button and a shape imitating a gun can be used. In addition, for example, in a music game, a controller with a shape imitating a musical instrument, a musical device, or the like can be used. Furthermore, a stationary game machine may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0476] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

[0477] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0478] Furthermore, by applying the storage device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500, temporary files necessary for calculations that occur during game execution can be stored.

[0479] As an example of a game machine, a portable game machine is shown in Fig. 53(E). Also, a home-use stationary game machine is shown in Fig. 53(F). Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as a game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0480] [Mobile object] The storage device described in the above embodiment can be applied to a moving object, such as an automobile, and to the vicinity of the driver's seat of the automobile.

[0481] FIG. 53(G) shows an automobile 5700 as an example of a moving object.

[0482] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0483] In particular, the display device can display an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for visibility blocked by pillars and blind spots around the driver's seat, thereby improving safety. In other words, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0484] The storage device described in the above embodiment can temporarily hold information, and therefore, for example, the storage device can be used to hold necessary temporary information in an automatic driving system of the automobile 5700, a system that performs road guidance, risk prediction, and the like. The display device may be configured to display temporary information such as road guidance and risk prediction. In addition, the display device may be configured to hold video of a driving recorder installed in the automobile 5700.

[0485] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0486] [camera] The storage device described in the above embodiment can be applied to a camera.

[0487] 53(H) shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may be configured such that a strobe device, a viewfinder, and the like can be separately attached.

[0488] A low power consumption digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. In addition, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0489] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0490] FIG. 53(I) illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0491] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0492] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0493] 53(J) is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0494] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0495] The ICD main body 5400 has a function as a pacemaker, and performs pacing on the heart when the heart rate is out of a specified range. In addition, if the heart rate does not improve by pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is performed.

[0496] The ICD main body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. In addition, the ICD main body 5400 can store in the electronic component 4700 the heart rate data acquired by the sensor, the number of times pacing treatment was performed, the time, and the like.

[0497] Moreover, the antenna 5404 can receive power, which is then charged in the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so that the ICD main body 5400 also functions as an auxiliary power source.

[0498] In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0499] [Extension device for PC] The storage device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0500] FIG. 54(A) shows, as an example of such an expansion device, an expansion device 6100 that is portable and equipped with a chip capable of storing information and that is attached externally to a PC. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via a Universal Serial Bus (USB). Note that, although FIG. 54(A) shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0501] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the storage device and the like described in the above embodiment. For example, the electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0502] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0503] FIG. 54(B) is a schematic diagram of the appearance of an SD card, and FIG. 54(C) is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a memory device and a circuit for driving the memory device. For example, the substrate 5113 is provided with an electronic component 4700 and a controller chip 5115. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, and the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0504] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip having a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and allows data to be read and written to the electronic component 4700.

[0505] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0506] FIG. 54(D) is a schematic diagram of the appearance of an SSD, and FIG. 54(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 4700 on the back side of the board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0507] [Calculator] 55A is an example of a large-scale computer 5600. The computer 5600 includes a rack 5610 and a plurality of rack-mounted computers 5620 stored therein.

[0508] The computer 5620 can have the configuration shown in the perspective view of Fig. 55(B), for example. In Fig. 55(B), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0509] A PC card 5621 shown in FIG. 55C is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 55C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0510] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0511] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power and inputting signals to the PC card 5621. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0512] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0513] The semiconductor device 5627 has a plurality of terminals, and the terminals can be soldered, for example, by reflow soldering, to wiring provided on the board 5622, so that the semiconductor device 5627 and the board 5622 can be electrically connected to each other. Examples of the semiconductor device 5627 include a field programmable gate array (FPGA), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0514] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring of the board 5622. The semiconductor device 5628 can be, for example, a memory device. For example, the electronic component 4700 can be used as the semiconductor device 5628.

[0515] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference of artificial intelligence, for example.

[0516] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. In addition, the semiconductor device of one embodiment of the present invention consumes less power, and thus heat generation from a circuit can be reduced. Therefore, adverse effects of the heat on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0517] Next, a configuration example of a computer system applicable to the calculator 5600 will be described. Fig. 56 is a diagram for explaining a configuration example of a computer system 700. The computer system 700 is configured to include software and hardware. Note that the hardware included in the computer system may be called an information processing device.

[0518] The software that constitutes the computer system 700 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI Applications), and AI-unrelated application programs (Applications).

[0519] The device driver includes application programs for controlling externally connected devices such as auxiliary storage devices, display devices, and printers.

[0520] The hardware constituting the computer system 700 includes a first processor, a second processor, a first storage device, etc. The second processor includes a second storage device.

[0521] The first arithmetic processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (for example, a non-volatile memory) using OS transistors, and has a function of holding necessary information in the storage means and stopping the power supply to the central processing unit when no operation is required. By using a Noff OS CPU as the first arithmetic processing unit, the power consumption of the computer system 700 can be reduced.

[0522] As the second arithmetic processing device, for example, a GPU or an FPGA can be used. It is preferable to use an AI OS Accelerator as the second arithmetic processing device. The AI ​​OS Accelerator is configured using OS transistors and has an arithmetic means such as a product-sum operation circuit. The AI ​​OS Accelerator consumes less power than a general GPU. By using the AI ​​OS Accelerator as the second arithmetic processing device, the power consumption of the computer system 700 can be reduced.

[0523] It is preferable to use a storage device according to an embodiment of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. In addition, the use of the 3D OS NAND type storage device makes it easier to realize a non-von Neumann type computer system.

[0524] A 3D OS NAND type storage device consumes less power than a 3D NAND type storage device using Si transistors. By using a 3D OS NAND type storage device as a storage device, the power consumption of the computer system 700 can be reduced. In addition, since a 3D OS NAND type storage device can function as a universal memory, the number of storage device parts required to configure the computer system 700 can be reduced.

[0525] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the arithmetic processing unit, and the memory device. By monolithically integrating the hardware, it becomes easy to further reduce power consumption as well as to reduce the size, weight, and thickness of the hardware.

[0526] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0527] (Embodiment 7) A normally-off CPU (also referred to as an "Noff-CPU") can be realized by using a memory device according to one embodiment of the present invention. Note that an Noff-CPU is an integrated circuit including a normally-off transistor that is in a non-conducting state (also referred to as an off state) even when a gate voltage of 0 V is applied.

[0528] The Noff-CPU can stop the power supply to circuits in the Noff-CPU that are not required to operate, and put the circuits into a standby state. When the power supply is stopped and the circuits are in a standby state, no power is consumed. Thus, the Noff-CPU can minimize power consumption. The Noff-CPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0529] A storage device according to one embodiment of the present invention can be used as a storage device for holding information such as setting conditions when power to a Noff-CPU is stopped. The storage device according to one embodiment of the present invention can also be used as a cache for the Noff-CPU. The storage device according to one embodiment of the present invention can also be used as a main memory for the Noff-CPU.

[0530] The Noff-CPU can be suitably used in small-scale systems such as an IoT terminal device (also called an "endpoint microcomputer") 803 in the Internet of Things (IoT) field.

[0531] Figure 57 shows the hierarchical structure of an IoT network and trends in required specifications. In Figure 57, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of an IoT network is broadly divided into an upper layer, the cloud field 801, and a lower layer, the embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, home appliances, etc.

[0532] The higher the layer, the more the processing performance is required rather than the low power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), etc. are used. Also, the lower the layer, the more the processing performance is required rather than the low power consumption, and the number of devices increases explosively. The semiconductor device according to one embodiment of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0533] Incidentally, the term "endpoint" refers to a terminal area of ​​the embedded field 802. Devices used as end points include, for example, microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.

[0534] FIG. 58 illustrates an image of factory automation as an application example of an endpoint microcomputer. A factory 884 is connected to a cloud 883 (server) via an Internet line. The cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, a semiconductor device according to one embodiment of the present invention may be used in a communication device to perform wireless communication according to a communication standard such as a fourth generation mobile communication system (4G) or a fifth generation mobile communication system (5G). The factory 884 may be connected to a factory 885 and a factory 886 via the Internet line.

[0535] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in an IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0536] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or an office 882 and know the operation status, etc. Also, he can check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0537] In recent years, the introduction of IoT into factories, labelled as "smart factories," has been progressing worldwide. Examples of smart factories have been reported in which endpoint microcomputers are used not only for simple inspection and auditing, but also for fault detection and anomaly prediction.

[0538] Small-scale systems such as endpoint microcontrollers tend to consume a small amount of power overall when in operation, meaning that the proportion of power consumed by the CPU tends to be large. For this reason, the power reduction effect of Noff-CPUs during standby operation is large in small-scale systems such as endpoint microcontrollers. On the other hand, in the field of embedded IoT, quick response is sometimes required, and the use of Noff-CPUs makes it possible to achieve high-speed recovery from standby operation.

[0539] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments. [Explanation of symbols]

[0540] 100 memory cells 101 Insulators 102 Conductor 103 Conductors 108 Center axis 111 Insulators 112 Conductors 113 Semiconductors 114 Semiconductors 115 Insulators 116 Semiconductors 117 Insulators 118 Conductor 121 Semiconductors 122 Insulators 123 Insulator 130 Structure 131 Aperture 132 areas 135 areas 136 areas 140 Laminate 141 Sacrificial Layer

Claims

1. a structure extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction; the structure includes a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor; a second semiconductor adjacent to the second insulator and a third insulator adjacent to the second semiconductor are provided between the structure and the first conductor at a first intersection where the structure and the first conductor intersect, At a second intersection where the structure and the second conductor intersect, the structure has a fourth conductor adjacent to the second insulator and a fourth insulator adjacent to the fourth conductor, At the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are provided concentrically outside the third conductor, At the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor, and the fourth insulator are provided concentrically outside the third conductor, the third insulator does not have a region in contact with the fourth conductor and a region in contact with the fourth insulator, The second semiconductor has a region in contact with the fourth conductor and a region in contact with the fourth insulator.

2. In claim 1, The first direction is a direction perpendicular to the second direction.

3. In claim 1 or 2, the first intersection functions as a first transistor; The second intersection portion functions as a second transistor and a capacitive element.

4. In any one of claims 1 to 3, The semiconductor device, wherein the first semiconductor is an oxide semiconductor.

5. In claim 4, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

6. In any one of claims 1 to 5, The semiconductor device wherein the second semiconductor is an oxide semiconductor.

7. In claim 6, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

8. In any one of claims 1 to 7, A semiconductor device that functions as a NAND type memory device.

9. A semiconductor device according to any one of claims 1 to 8, An electronic device having at least one of an operation switch, a battery, and a display unit.

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