Oscillator Circuit

Abstract

A technique is provided for stabilizing the oscillation frequency of a multi-vibration type oscillation circuit with a simple configuration. [Solution] A first capacitor 31 and a second capacitor 41 are charged by a charging current I. A sampling circuit 6 samples a first charging voltage CP when the supply of the charging current I to the first capacitor 31 is stopped. Also, a sampling circuit 6 samples a second charging voltage CN when the supply of the charging current I to the second capacitor 41 is stopped. A current supply circuit 2 generates a charging current I according to a reference voltage VR, which is the voltage sampled by the sampling circuit 6.

Description

[Technical field]

[0001] The present disclosure relates to a multivibration type oscillator circuit. [Background technology]

[0002] A multi-vibration type oscillation circuit is described in the following Patent Document 1. The multi-vibration type oscillation circuit includes a first charging circuit, a second charging circuit, and a signal generating circuit. The first charging circuit charges and discharges the first capacitor, and uses a current supplied from a constant current source for charging. The second charging circuit charges and discharges the second capacitor, and uses a current supplied from a constant current source for charging. The first charging circuit and the second charging circuit operate complementarily such that one is in a charging period and the other is in a non-charging period including discharging, and the charging period and discharging period alternate. The signal generating circuit generates a clock signal whose signal level is inverted according to a first reaching timing AR1 when the charging voltage V1 of the first capacitor reaches the reference voltage Vref, and a second reaching timing AR2 when the charging voltage V2 of the second capacitor reaches the reference voltage Vref.

[0003] In this type of oscillator circuit, as shown in the upper part of FIG. 3, during the charging period, the first capacitor is charged at a constant rate by a constant current I. Then, at a first arrival time AR1 when the charging voltage of the first capacitor reaches the reference voltage Vref, the first capacitor is discharged and charging of the second capacitor begins. Then, the second capacitor is charged at a constant rate by the constant current I. At a second arrival time AR2 when the charging voltage V2 of the second capacitor reaches the reference voltage Vref, the second capacitor is discharged and charging of the first capacitor begins. Thereafter, the same operation is repeated to generate a clock signal whose signal level is inverted depending on the first arrival time AR1 and the second arrival time AR2. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6498481 Summary of the Invention [Problem to be solved by the invention]

[0005] The frequency f (=1 / T) of the clock signal generated by the above-mentioned multivibration type oscillator circuit is calculated by equation (1), where T is the period of the clock signal, C is the capacitance of the first capacitor and the second capacitor, I is the constant charging current supplied by the constant current source, and Vref is a set reference voltage. Then, by setting the constant charging current I as expressed by equation (2) with R as the resistance value, the frequency f of the clock signal can theoretically be determined by RC alone, as shown in equation (3).

[0006]

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[0007] However, in reality, the timing at which the signal level of the clock signal changes does not coincide with the first arrival timing AR1 and the second arrival timing AR2, and is delayed from the first arrival timing AR1 and the second arrival timing AR2 by the operation delay ΔT in the signal generating circuit, as shown in the lower part of FIG. 3. Accordingly, the charging voltages V1 and V2 of the first and second capacitors at the time of inversion of the clock signal also increase by ΔV. In other words, the actual frequency f of the clock signal is expressed by equation (4) in which Vref in equation (1) is replaced by Vref+ΔV. By substituting the constant charging current I shown in equation (2) into this equation (4), equation (5) is obtained. In other words, it can be seen that the frequency f of the clock signal is not determined only by CR, but is also affected by the operation delay ΔT.

[0008]

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[0009] The delay time ΔT changes due to fluctuations in temperature and power supply voltage, and the voltage fluctuation amount ΔV also changes according to the delay time ΔT. In other words, the conventional technology had the problem that the frequency f of the clock signal fluctuates according to fluctuations in temperature and power supply voltage.

[0010] Patent Document 1 also describes using a variable current circuit instead of a constant current circuit, detecting the period of a clock signal, generating a control signal according to the clock period, and feedback-controlling the charging current generated by the variable current circuit so that the clock period is constant. However, there is a problem in that it is necessary to add a circuit for detecting the clock period and generating a control signal according to the clock period, which complicates the device configuration.

[0011] The present disclosure provides a technique for stabilizing the oscillation frequency of a multivibration type oscillation circuit with a simple configuration. [Means for solving the problem]

[0012] One aspect of the present disclosure is an oscillator circuit, comprising a current supply circuit, a first charging circuit, a second charging circuit, a signal generating circuit, and a sampling circuit. The current supply circuit is configured to supply a charging current determined by a reference voltage and a resistance value. The first charging circuit is configured to charge a first capacitor with the charging current when a clock signal is at a first signal level, and to discharge the first capacitor when the clock signal is at a second signal level. The second charging circuit is configured to charge a second capacitor with the charging current when the clock signal is at the second signal level, and to discharge the second capacitor when the clock signal is at the first signal level. The signal generating circuit is configured to generate a clock signal. The clock signal changes to a second signal level according to a first arrival timing when the charging voltage of the first capacitor reaches a preset threshold, and changes to the first signal level according to a second arrival timing when the charging voltage of the second capacitor reaches the threshold. The sampling circuit is configured to perform at least one of a first sampling and a second sampling. In the first sampling, a first charging voltage that is a charging voltage of the first capacitor is sampled at a first clock timing when the clock signal changes from a first signal level to a second signal level. In the second sampling, a second charging voltage that is a charging voltage of the second capacitor is sampled at a second clock timing when the clock signal changes from the second signal level to the first signal level. The current supply circuit is configured to use the sampled value by the sampling circuit as a reference voltage.

[0013] According to this configuration, the oscillation frequency of the oscillation circuit can be stabilized with a simple configuration. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a multi-vibration type oscillation circuit. [Diagram 2] 4 is a timing diagram illustrating signals generated by a control circuit and the overall operation of the multivibration type oscillator circuit. FIG. [Diagram 3] FIG. 1 is a timing diagram illustrating a problem with the conventional technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1. Configuration] A multi-vibration type oscillator circuit (hereinafter, oscillator circuit) 1 shown in FIG. 1 includes a current supply circuit 2, a first charging circuit 3, a second charging circuit 4, a signal generating circuit 5, a sampling circuit 6, and a control circuit .

[0016] The current supply circuit 2 includes a first FET 21, a second FET 22, an operational amplifier 23, and a resistor 24. The first FET 21 and the second FET 22 are both P-channel MOSFETs, with their sources connected to a power supply line and their gates connected to each other. The drain of the first FET 21 is grounded via a resistor 24, and the drain of the second FET 22 is connected to the first charging circuit 3 and the second charging circuit 4. In the following, the resistance value of the resistor 24 is represented as R.

[0017] The operational amplifier 23 has a non-inverting input terminal connected to the drain of the first FET 21 , an inverting input terminal connected to the sampling circuit 6 , and an output terminal connected to the gates of the first FET 21 and the second FET 22 .

[0018] Here, the voltage applied to the inverting input terminal of the operational amplifier 23, i.e., the output voltage of the sampling circuit 6, is the reference voltage VR, and the voltage applied to the non-inverting input terminal of the operational amplifier 23 is the feedback voltage VFB. The operational amplifier 23 drives the first FET 21 and the second FET 22 so that the feedback voltage VFB matches the reference voltage VR, i.e., so that the drain current I of the first FET 21 becomes I=VR / R. A charging current I having the same magnitude as the drain current I of the first FET 21 is supplied to the first charging circuit 3 and the second charging circuit 4 from the second FET 22 which forms a current mirror circuit together with the first FET 21.

[0019] The first charging circuit 3 includes a first capacitor 31 , a first charging switch 32 , and a first discharging switch 33 . One end of the first capacitor 31 is grounded. The non-grounded end of the first capacitor 31 is connected to the drain of the second FET 22 of the current supply circuit 2 via the first charging switch 32, and is also grounded via the first discharging switch 33. The first capacitor 31 is charged by the charging current I supplied from the current supply circuit 2 while the first charging switch 32 is on and the first discharging switch 33 is off. The first capacitor 31 is discharged while the first discharging switch 33 is on. The first charging switch 32 is operated by a first clock signal CK_P, and the first discharging switch 33 is operated by a first discharging signal DC_P.

[0020] The second charging circuit 4 includes a second capacitor 41, a second charging switch 42, and a second discharging switch 43, which operate similarly to the first capacitor 31, the first charging switch 32, and the first discharging switch 33, respectively. However, the second charging switch 42 is operated by a second clock signal CK_N, and the second discharging switch 43 is operated by a second discharging signal DC_N.

[0021] The signal generating circuit 5 includes comparison circuits 51 and 52, a clock generating circuit 53, and buffer circuits 54 and 55. The comparison circuit 51 is an inverter circuit that compares a first charging voltage CP, which is the voltage at the non-grounded end of the first capacitor 31, with a threshold voltage Vref, and outputs a first judgment signal CM_P that is at a low level if CP>Vref, and at a high level if CP≦Vref.

[0022] The comparison circuit 52 is an inverter circuit that compares the second charging voltage CN, which is the voltage at the non-grounded end of the second capacitor 41, with a threshold voltage Vref, and outputs a second determination signal CM_N that is at a low level if CN>Vref, and at a high level if CN≦Vref.

[0023] The comparison circuits 51 and 52 do not necessarily have to be inverter circuits, and may be, for example, comparators. The clock generation circuit 53 is a known SR flip-flop circuit that combines two NAND circuits and two inverter circuits. The clock generation circuit 53 generates a first clock signal CK_P and a second clock signal CK_N in accordance with the first determination signal CM_P and the second determination signal CM_N.

[0024] 2, the timing when the first determination signal CM_P changes from a high level to a low level is defined as a first arrival timing AR1, and the timing when the second determination signal CM_N changes from a high level to a low level is defined as a second arrival timing AR2. The first clock signal CK_P changes from a high level to a low level according to the first arrival timing AR1, and changes from a low level to a high level according to the second arrival timing AR2. The second clock signal CK_N, in contrast to the first clock signal CK_P, changes from a high level to a low level according to the second arrival timing AR2, and changes from a low level to a high level according to the first arrival timing AR1.

[0025] The signal levels of the first clock signal CK_P and the second clock signal CK_N are inverted at a timing delayed by an operation delay ΔT in the clock generation circuit 53 from the first arrival timing AR1 and the second arrival timing AR2.

[0026] The buffer circuits 54 and 55 are inverter circuits provided to improve the current driving capability of the first clock signal CK_P and the second clock signal CK_N. The buffer circuits 54 and 55 may be configured by, for example, a source follower circuit.

[0027] The sampling circuit 6 includes a holding capacitor 61, a first sampling switch 62, and a second sampling switch 63. One end of the holding capacitor 61 is grounded. The non-grounded end of the holding capacitor 61 is connected to the non-grounded end of the first capacitor 31 via the first sampling switch 62, and is also connected to the non-grounded end of the second capacitor 41 via the second sampling switch 63. In addition, the non-grounded end of the holding capacitor 61 is connected to the inverting input terminal of the operational amplifier 23.

[0028] The first sampling switch 62 is operated by a first sampling signal SP_P, and the second sampling switch 63 is operated by a second sampling signal SP_N. When the first sampling switch 62 is turned on, the holding capacitor 61 and the first capacitor 31 are connected in parallel, and the sampled value of the first charging voltage CP is held in the holding capacitor 61. When the second sampling switch 63 is turned on, the holding capacitor 61 and the second capacitor 41 are connected in parallel, and the sampled value of the second charging voltage CN is held in the holding capacitor 61. The sampled value held in this holding capacitor 61 is supplied to the current supply circuit 2 as the reference voltage VR.

[0029] The control circuit 7 generates first and second discharge signals DC_P, DC_N and first and second sampling signals SP_P, SP_N in accordance with the first and second determination signals CM_P, CM_N and the first and second clock signals CK_P, CK_N.

[0030] [2. Operation] The timing of each signal generated by the control circuit 7 and the overall operation of the oscillation circuit will be described with reference to the timing diagram of Fig. 2. The control circuit 7 may be formed of a logic circuit.

[0031] The waveforms of the first clock signal CK_P, the first determination signal CM_P, the first discharge signal DC_P, the first sampling signal SP_P, and the first charging voltage CP are similar to those of the second clock signal CK_N, the second determination signal CM_N, the second discharge signal DC_N, the second sampling signal SP_N, and the second charging voltage CN, and have timings that are shifted by a half period of the first clock signal CK_P and the second clock signal CK_N. Hereinafter, the first clock signal CK_P and the second clock signal CK_N will be collectively referred to simply as clock signals.

[0032] Since the first clock signal CK_P and the second clock signal CK_N have complementary signal levels, one of the first charging switch 32 and the second charging switch 42 is always on and the other is always off. As a result, the supply destination of the charging current I alternates between the first charging circuit 3 and the second charging circuit 4 every half clock cycle.

[0033] In the following, the timing at which the signal level of the clock signal changes in accordance with the first arrival timing AR1 is referred to as first clock timing TM1, and the timing at which the signal level of the clock signal changes in accordance with the second arrival timing AR2 is referred to as second clock timing TM2.

[0034] 2, while the first clock signal CK_P is at a high level and the first charging switch 32 is on, the first capacitor 31 is charged by the charging current I, and the first charging voltage CP increases at a constant rate. When the first charging voltage CP exceeds the threshold value Vref of the comparison circuit 51, the first determination signal CM_P changes from a high level to a low level. This timing is the first arrival timing AR1. At a timing delayed from the first arrival timing AR1 by the delay time ΔT in the clock generation circuit 53, the first clock signal CK_P changes from a high level to a low level. This timing is the first clock timing TM1.

[0035] In the first charging circuit 3, charging of the first capacitor 31 by the charging current I continues between the first arrival timing AR1 and the first clock timing TM1, so the first charging voltage CP continues to increase. After the first clock timing TM1, the first clock signal CK_P goes low, and the supply of the charging current I to the first capacitor 31 via the first charging switch 32 is cut off. Therefore, the first charging voltage CP is held at the voltage level at the first clock timing TM1.

[0036] The control circuit 7 changes the first sampling signal SP_P from low level to high level at the first clock timing TM1, and charges the holding capacitor 61 to the first charging voltage CP via the first sampling switch 62. The control circuit 7 holds the first sampling signal SP_P at high level only for the waiting period required to charge the holding capacitor 61, and changes the first sampling signal SP_P to low level after the waiting period has elapsed. As a result, the holding capacitor 61 holds the first charging voltage CP at the first clock timing TM1 when the supply of the charging current I to the first capacitor 31 is stopped. In addition, the voltage held in the holding capacitor 61 is supplied to the current supply circuit 2 as the reference voltage VR. In other words, the magnitude of the charging current I supplied by the current supply circuit 2 is appropriately corrected by the reference voltage VR held in the holding capacitor 61.

[0037] Furthermore, the control circuit 7 changes the first discharging signal DC_P from low level to high level after returning the first sampling signal SP_P to low level. Then, the charge stored in the first capacitor 31 is discharged via the first discharging switch 33, and the first charging voltage CP becomes 0V (ground potential). In accordance with this change in the first charging voltage CP, the first determination signal CM_P which is the output of the comparison circuit 51 changes from low level to high level.

[0038] After that, the control circuit 7 changes the first discharge signal DC_P from high level to low level at the second clock timing TM2. After the second clock timing TM2, the first charging switch 32 turns on, and the above-mentioned operation is repeated.

[0039] In addition, while the second clock signal CK_N is at a high level (i.e., the first clock signal CK_P is at a low level) and the second charging switch 42 is on, the second capacitor 41 is charged by the charging current I, and the second charging voltage CN increases at a constant rate.

[0040] Thereafter, an operation similar to that when the first capacitor 31 is charged by the charging current I is executed with a delay of a half cycle of the clock signal. However, in this case, in the above description, the first clock signal CK_P, the first determination signal CM_P, the first discharge signal DC_P, the first sampling signal SP_P, the first charging voltage CP, the first capacitor 31, the first charging switch 32, the first discharging switch 33, the comparison circuit 51, and the first sampling switch 62 are replaced with the second clock signal CK_N, the second determination signal CM_N, the second discharging signal DC_N, the second sampling signal SP_N, the second charging voltage CN, the second capacitor 41, the second charging switch 42, the second discharging switch 43, the comparison circuit 52, and the second sampling switch 63, respectively.

[0041] [3. Clock signal frequency] In the oscillator circuit 1, the reference voltage VR held in the holding capacitor 61 is expressed by the following equation (6): Vref is the threshold voltage of the comparator circuits 51 and 52, and ΔV is the voltage fluctuation ΔV of the first charging voltage CP or the second charging voltage CN caused by the operation delay ΔT in the clock generating circuit 53.

[0042]

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[0043] In the oscillator circuit 1, unlike the conventional device in which the charging current I is fixed at I=R / Vref, it is determined according to the reference voltage VR held in the holding capacitor 61, as shown in equation (7).

[0044]

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[0045] Therefore, the frequency of the clock signal in the oscillator circuit 1 (hereinafter, the oscillation frequency) f is calculated by substituting the charging current I expressed by equation (7) into equation (4) which takes into account the operation delay ΔT in the signal generating circuit 5. In other words, the oscillation frequency f is expressed by equation (3).

[0046] [4. Correspondence of terminology] In this embodiment, the first clock signal CK_P or the second clock signal CK_N corresponds to the clock signal in this disclosure. The high level of the first clock signal CK_P or the low level of the second clock signal CK_N corresponds to the first signal level in this disclosure, and the low level of the first clock signal CK_P or the high level of the second clock signal CK_N corresponds to the second signal level in this disclosure.

[0047] [5. Effects] According to the embodiment described above in detail, the following effects are achieved. The oscillator circuit 1 newly includes a configuration for sampling the charging voltage CP of the first capacitor 31 at the first clock timing TM1 and sampling the charging voltage CN of the second capacitor 41 at the second clock timing TM2. Then, a charging current I for charging the first capacitor 31 and the second capacitor 41 is generated according to the sampled voltage. As a result, in the oscillator circuit 1, the oscillation frequency f is determined only by the resistance value R of the resistor 24 and the capacitance C of the first capacitor 31 and the second capacitor 41. In other words, according to the oscillator circuit 1, the oscillation frequency f is not affected by the voltage fluctuation amount ΔV based on the operation delay ΔT, so that the oscillation frequency f can be stabilized regardless of fluctuations in temperature or power supply voltage, and this effect can be achieved with a simple configuration.

[0048] 6. Other embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0049] (a) In the above embodiment, an SR flip-flop circuit is used as the clock generation circuit 53, but this is not limited to this. Any circuit configuration may be used as long as it can generate a clock signal whose signal level is inverted at the first arrival timing AR1 and the second arrival timing AR2 based on the first determination signal CM_P and the second determination signal CM_N.

[0050] (b) In the above embodiment, the sampling circuit 6 is configured to sample both the first charging voltage CP and the second charging voltage CN, but it may be configured to sample only one of them.

[0051] (c) In the above embodiment, the sampling circuit 6 is configured to sample at every first clock timing TM1 and every second clock timing TM2, but it may be configured to sample only when a preset condition is met.

[0052] (d) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be replaced with another configuration having an equivalent function.

[0053] (e) In addition to the oscillator circuit 1 described above, the present disclosure can also be realized in the form of a system including the oscillator circuit 1 as a component, a frequency stabilization method, and the like. [Explanation of symbols]

[0054] 1...oscillator circuit, 2...current supply circuit, 3,4...charging circuit, 5...signal generating circuit, 6...sampling circuit, 7...control circuit, 21,22...FET, 23...operational amplifier, 24...resistor, 31,41...capacitor, 32,42...charging switch, 33,43 discharging switch, 51,52...comparison circuit, 53...clock generating circuit, 54,55...buffer circuit, 61...holding capacitor, 62,63...sampling switch.

Claims

1. a current supply circuit configured to supply a charging current determined by a reference voltage and a resistance value; a first charging circuit configured to charge a first capacitor with the charging current when a clock signal is at a first signal level and to discharge the first capacitor when the clock signal is at a second signal level; a second charging circuit configured to charge a second capacitor with the charging current when the clock signal is at the second signal level and to discharge the second capacitor when the clock signal is at the first signal level; a signal generating circuit configured to generate the clock signal, the clock signal changing to the second signal level in accordance with a first reaching timing when the charging voltage of the first capacitor reaches a preset threshold, and changing to the first signal level in accordance with a second reaching timing when the charging voltage of the second capacitor reaches the threshold; a sampling circuit configured to perform at least one of a first sampling for sampling a first charging voltage, which is a charging voltage of the first capacitor, at a first clock timing when the clock signal changes from the first signal level to the second signal level, and a second sampling for sampling a second charging voltage, which is a charging voltage of the second capacitor, at a second clock timing when the clock signal changes from the second signal level to the first signal level; Equipped with the current supply circuit is configured to set a sampled value by the sampling circuit as the reference voltage; Oscillator circuit.

2. 2. The oscillator circuit of claim 1, the sampling circuit includes a holding capacitor for holding the sampling value, and is configured to connect the holding capacitor in parallel to the first capacitor or the second capacitor during a waiting period required from the first clock timing and the second clock timing until a charging voltage of the holding capacitor reaches the first charging voltage or the second charging voltage; the first charging circuit is configured to discharge the first capacitor after the waiting period has elapsed from the first clock timing; the second charging circuit is configured to discharge the second capacitor after the waiting period has elapsed from the second clock timing. Oscillator circuit.

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