Semiconductor device and power conversion device

Abstract

To provide a technology capable of achieving both miniaturization of a semiconductor device and reduction in wiring inductance.SOLUTION: A semiconductor device comprises: an insulating layer 1; a conductor foil 2; a circuit pattern 3; a plurality of semiconductor elements 4 and 5; a wiring plate 6 that applies a current inputted from the exterior to the circuit pattern 3; and a wiring plate 7 that connects between the plurality of semiconductor elements 4 and 5, and applies a current that has flowed in the plurality of semiconductor elements 4 and 5 via the circuit pattern 3. The plurality of semiconductor elements 4 and 5 are arranged in an extending direction of the wiring plate 7. In a current path passing through the wiring plate 7 from the wiring plate 6 via the circuit pattern 3 and the plurality of semiconductor elements 4 and 5, an electric resistance of a current path passing through the semiconductor element 5 arranged at the downstream side is smaller than that of a current path passing through the semiconductor element 4 arranged at the upstream side.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Conventionally, there has been a demand for reducing wiring inductance in semiconductor devices. For example, Patent Document 1 discloses a technology for reducing wiring inductance in a power semiconductor module including a first wiring layer that is in electrical contact with an electrode of a semiconductor element and a second wiring layer that faces the first wiring layer and is electrically connected to the first wiring layer, by making the direction of current flowing in the first wiring layer opposite to the direction of current flowing in the second wiring layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-18943 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology described in Patent Document 1 requires the first wiring layer and the second wiring layer to be opposed to each other above and below, which limits the freedom of layout, making it difficult to achieve miniaturization of the device.

[0005] Therefore, an object of the present disclosure is to provide a technique that can achieve both miniaturization of a semiconductor device and reduction in wiring inductance. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes an insulating layer, a conductor foil provided on a lower surface of the insulating layer, a circuit pattern provided on an upper surface of the insulating layer, a plurality of semiconductor elements mounted on the upper surface of the circuit pattern, a first wiring board connected to the upper surface of the circuit pattern and causing a current input from outside to flow through the circuit pattern, and a second wiring board connecting the plurality of semiconductor elements and causing a current to flow through the plurality of semiconductor elements via the circuit pattern, the plurality of semiconductor elements being arranged along an extension direction of the second wiring board, and in a current path passing from the first wiring board through the circuit pattern and the plurality of semiconductor elements to the second wiring board, an electrical resistance of the current path passing through the semiconductor elements arranged on the downstream side is smaller than an electrical resistance of the current path passing through the semiconductor elements arranged on the upstream side. The current path from the first wiring board to the second wiring board is U-shaped in top view. . Effect of the Invention

[0007] According to the present disclosure, in a current path that runs from a first wiring board through a circuit pattern and multiple semiconductor elements to a second wiring board, more current flows through the current path that runs through the semiconductor elements arranged downstream, which are located closer to the conductor foil, than through the current path that runs through the semiconductor elements arranged upstream, and this increases the cancellation effect of the inductance caused by the magnetic flux formed by the conductor foil, thereby making it possible to reduce wiring inductance.

[0008] In addition, since it is not necessary to arrange the first and second wiring boards opposite each other, the degree of freedom in layout is ensured, and it is possible to achieve both miniaturization of the semiconductor device and reduction in wiring inductance. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a perspective view showing an example of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 4 is a perspective view showing another example of the semiconductor device according to the first embodiment. [Figure 4] FIG. 13 is a perspective view of a semiconductor device according to a modified example of the first embodiment. [Diagram 5] FIG. 11 is a perspective view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 7] FIG. 11 is a perspective view of a semiconductor device according to a third embodiment. [Figure 8] FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> <Configuration of Semiconductor Device> First embodiment will be described below with reference to the drawings. Fig. 1 is a cross-sectional view showing an example of a semiconductor device according to the first embodiment.

[0011] 1, the semiconductor device includes an insulating layer 1, a conductor foil 2, a circuit pattern 3, a plurality of semiconductor elements, a wiring board 6 as a first wiring board, a wiring board 7 as a second wiring board, a sealing material 9, and a cooler 10. First, an example in which the plurality of semiconductor elements are a pair of semiconductor elements 4 and 5 will be described.

[0012] The conductor foil 2 is provided on the lower surface of the insulating layer 1. The insulating layer 1 and the conductor foil 2 are formed into elongated rectangular shapes of the same size when viewed from above. The circuit pattern 3 is made of copper, which has low conductor resistance, and is provided on the upper surface of the insulating layer 1. The circuit pattern 3 is formed into an elongated rectangular shape that is smaller than the insulating layer 1 when viewed from above.

[0013] The pair of semiconductor elements 4 and 5 are mounted by being bonded to the upper surface of the circuit pattern 3 with bonding materials 8c and 8f, respectively. The pair of semiconductor elements 4 and 5 are also arranged along the extending direction of the wiring board 7. The semiconductor material of the pair of semiconductor elements 4 and 5 is, for example, silicon (Si) or silicon carbide (SiC).

[0014] Wiring board 6 is bonded to the upper surface of circuit pattern 3 with bonding material 8b, and passes a current input from the outside to circuit pattern 3. Wiring board 7 connects the pair of semiconductor elements 4, 5 with bonding materials 8d, 8f, respectively, and passes a current that has flowed between circuit pattern 3 and the pair of semiconductor elements 4, 5. The current that has flowed through wiring board 7 may or may not be output to the outside.

[0015] The sealing material 9 is an epoxy resin or the like, and seals all parts except the underside of the conductor foil 2, the insulating layer 1, the circuit pattern 3, the pair of semiconductor elements 4, 5, all parts except one end of the wiring board 6, and all parts except one end of the wiring board 7.

[0016] The cooler 10 is made of copper or aluminum, and is joined to the lower surface of the conductor foil 2 by a joining material 8a. The joining materials 8a to 8f are solder, silver, or the like.

[0017] Next, a current path of the semiconductor device will be described with reference to Fig. 2. Fig. 2 is a perspective view showing an example of a semiconductor device according to the first embodiment, and is a perspective view in which the sealing material 9 and the cooler 10 are omitted. Note that the sealing material 9 and the cooler 10 are also omitted from the subsequent perspective views.

[0018] 2, a current input from wiring board 6 passes through circuit pattern 3, flows through the pair of semiconductor elements 4 and 5, and is then output from wiring board 7. In the current path from wiring board 6 through circuit pattern 3 and the pair of semiconductor elements 4 and 5 to wiring board 7, the electrical resistance of the current path passing through semiconductor element 5 arranged on the downstream side is smaller than the electrical resistance of the current path passing through semiconductor element 4 arranged on the upstream side.

[0019] This will be explained in detail. The current path between the pair of semiconductor elements 4, 5 branches into two on the underside of the semiconductor element 4. The first current path is a current path that passes through the semiconductor element 5 via the circuit pattern 3 without passing through the semiconductor element 4. The second current path is a current path that passes through the wiring board 7 via the semiconductor element 4.

[0020] When the electrical resistance of the first current path is R1 and the electrical resistance of the second current path is R2, the relationship R1 < R2 is satisfied. As a result, since more current flows through the first current path located closer to the conductor foil 2 than the second current path, the inductance cancellation effect due to the magnetic flux formed by the conductor foil 2 becomes larger. Thereby, reduction of the wiring inductance can be realized.

[0021] There are several ways to form the relationship R1 < R2. One is to increase the thickness of the circuit pattern 3. For example, by setting the thickness of the circuit pattern 3 to 0.2 mm or more, the conductor resistance flowing through the circuit pattern 3 can be reduced, making it easier to form the relationship R1 < R2. In addition, there are methods of changing the thickness of the wiring board 7, the semiconductor element 4, or the bonding materials 8c, 8d, and methods of changing the materials of the circuit pattern 3, the wiring board 7, the semiconductor element 4, or the bonding materials 8c, 8d. Also, as a method of realizing reduction of the wiring inductance, in order to enhance the inductance cancellation effect due to the magnetic flux formed by the conductor foil 2, for example, setting the thickness of the insulating layer 1 to 0.5 mm or less can be mentioned.

[0022] The pair of semiconductor elements 4 and 5 is an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode). The FWD is the semiconductor element 4 mounted on the upstream side of the current path between the pair of semiconductor elements 4 and 5. The IGBT is the semiconductor element 5 mounted on the downstream side of the current path between the pair of semiconductor elements 4 and 5. That is, the semiconductor element 4 which is an FWD is arranged on the current inlet (collector terminal) side, and the semiconductor element 5 which is an IGBT is arranged on the current outlet (emitter terminal) side. Since the electrical resistance of the semiconductor element 4 which is an FWD is larger than the electrical resistance of the semiconductor element 5 which is an IGBT, the relationship R1 < R2 can be easily formed.

[0023] Next, with reference to FIG. 3, the case where the plurality of semiconductor elements are three semiconductor elements 4, 5, and 16 will be described. FIG. 3 is a perspective view showing another example of the semiconductor device according to the first embodiment.

[0024] As shown in FIG. 3, the current input from the wiring board 6 flows through the circuit patterns 3 and the semiconductor elements 4, 5, and 16, and then is output from the wiring board 7. The current path between the semiconductor elements 4, 5, and 16 branches into three at the lower surface of the semiconductor element 4. The first current path is a current path that passes through the semiconductor element 16 via the circuit pattern 3 without passing through the semiconductor elements 4 and 5. The second current path is a current path that passes through the wiring board 7 via the circuit pattern 3 and the semiconductor element 5 without passing through the semiconductor element 4. The third current path is a current path that passes through the wiring board 7 via the semiconductor element 4.

[0025] When the electrical resistance of the first current path is R1, the electrical resistance of the second current path is R2, and the electrical resistance of the third current path is R3, the relationship R1 < R2 < R3 is satisfied. As a result, more current flows through the second current path located closer to the conductor foil 2 than the third current path, and furthermore, more current flows through the first current path located closer to the conductor foil 2 than the second current path. Therefore, the canceling effect of the inductance due to the magnetic flux formed by the conductor foil 2 increases. Thereby, reduction of the wiring inductance can be realized.

[0026] In FIGS. 1 and 2, the case where a plurality of semiconductor elements are pairs of the semiconductor elements 4 and 5 has been described, and in FIG. 3, the case where a plurality of semiconductor elements are the three semiconductor elements 4, 5, and 16 has been described. However, the number of a plurality of semiconductor elements is not particularly limited as long as it is two or more. This also applies to the modification of Embodiment 1 and Embodiments 2 and 3 described later.

[0027] <Effect> As described above, the semiconductor device according to Embodiment 1 includes an insulating layer 1, a conductor foil 2 provided on the lower surface of the insulating layer 1, a circuit pattern 3 provided on the upper surface of the insulating layer 1, a plurality of semiconductor elements mounted on the upper surface of the circuit pattern 3, a wiring board 6 connected to the upper surface of the circuit pattern 3 and flowing an externally input current through the circuit pattern 3, and a wiring board 7 connecting the plurality of semiconductor elements and flowing the current that has flowed through the plurality of semiconductor elements via the circuit pattern 3. The plurality of semiconductor elements are arranged along the extending direction of the wiring board 7. In the current path from the wiring board 6 through the circuit pattern 3 and the plurality of semiconductor elements to the wiring board 7, the electrical resistance of the current path passing through the semiconductor element arranged on the downstream side is smaller than the electrical resistance of the current path passing through the semiconductor element arranged on the upstream side.

[0028] Therefore, in the current path from the wiring board 6 through the circuit pattern 3 and the plurality of semiconductor elements to the wiring board 7, since more current flows through the current path passing through the semiconductor element arranged on the downstream side, which is located closer to the conductor foil 2 than the current path passing through the semiconductor element arranged on the upstream side, the canceling effect of the inductance due to the magnetic flux formed by the conductor foil 2 becomes larger. Thereby, reduction of the wiring inductance can be realized.

[0029] In addition, since it is not necessary to oppose the wiring board 6 and the wiring board 7 vertically, the degree of freedom in layout can be ensured. Therefore, both miniaturization of the semiconductor device and reduction of the wiring inductance can be achieved.

[0030] For example, as shown in FIG. 2, the plurality of semiconductor elements are a pair of semiconductor elements 4 and 5. The current path between the pair of semiconductor elements 4 and 5 branches into a first current path that passes through the other semiconductor element 5 arranged on the downstream side via the circuit pattern 3 without passing through one semiconductor element 4 arranged on the upstream side, and a second current path that passes through the wiring board 7 via one semiconductor element 4. When the electrical resistance of the first current path is R1 and the electrical resistance of the second current path is R2, the relationship R1 < R2 is satisfied.

[0031] Therefore, more current flows through the first current path, which is located closer to the conductor foil 2 than the second current path, and this increases the effect of canceling out the inductance caused by the magnetic flux formed by the conductor foil 2. This makes it possible to reduce the wiring inductance.

[0032] In addition, the semiconductor elements include an IGBT and an FWD, and the FWD is mounted upstream of the IGBT. Since the electrical resistance of the FWD is greater than the electrical resistance of the IGBT, it is easy to form a relationship between the electrical resistance of the current path passing through the semiconductor element disposed downstream and the electrical resistance of the current path passing through the semiconductor element disposed upstream.

[0033] In addition, since the circuit pattern 3 contains copper, by using copper, which has low conductor resistance, as the material of the circuit pattern 3, it is possible to easily form a relationship between the electrical resistance of the current path passing through the semiconductor element arranged on the downstream side and the electrical resistance of the current path passing through the semiconductor element arranged on the upstream side.

[0034] Furthermore, since the thickness of the circuit pattern 3 is 0.2 mm or more, by ensuring the thickness of the circuit pattern 3, it is possible to easily form a relationship between the electrical resistance of the current path passing through the semiconductor element arranged on the downstream side and the electrical resistance of the current path passing through the semiconductor element arranged on the upstream side.

[0035] Furthermore, since the thickness of the insulating layer 1 is 0.5 mm or less, by making the thickness of the insulating layer 1 thin, when current flows from the current inlet (collector terminal) to the current outlet (emitter terminal), the cancellation effect of the magnetic flux formed by the conductor foil 2 becomes greater, thereby making it possible to reduce the wiring inductance.

[0036] In addition, since the semiconductor material of the multiple semiconductor elements is SiC, this leads to reduced loss in the high frequency range for which SiC excels, thereby improving the lifespan of the semiconductor device.

[0037] <Modification of the first embodiment> Next, a description will be given of a modification of the first embodiment. Fig. 4 is a perspective view of a semiconductor device according to a modification of the first embodiment.

[0038] As shown in FIG. 4, the insulating layer 1 and the conductor foil 2 are formed in a rectangular shape of the same size when viewed from above. The circuit pattern 3 is formed in a U-shape having two straight portions when viewed from above. The wiring board 6 and the wiring board 7 are each arranged along the two straight portions and joined to the upper surfaces of the two straight portions. The current inlet (collector terminal) and the current outlet (emitter terminal) protrude from the same surface of the sealing material 9 (see FIG. 1), and the current path from the wiring board 6 to the wiring board 7 is U-shaped when viewed from above, that is, in a loop shape. This reduces the leakage flux between the wiring board 6 and the wiring board 7, and can reduce the wiring inductance. Note that the current path from the wiring board 6 to the wiring board 7 being U-shaped when viewed from above contributes to reducing the wiring inductance, so the circuit pattern 3 and the wiring boards 6 and 7 do not have to be formed in a U-shape when viewed from above.

[0039] The plurality of semiconductor elements may include a reverse conducting IGBT, which makes it possible to reduce the number of semiconductor elements mounted on the semiconductor device, thereby enabling the semiconductor device to be further miniaturized.

[0040] The above modifications can also be applied to the second and third embodiments described below.

[0041] <Embodiment 2> Next, a semiconductor device according to a second embodiment will be described. Fig. 5 is a perspective view of the semiconductor device according to the second embodiment. Fig. 6 is a circuit diagram of the semiconductor device according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0042] As shown in Figures 5 and 6, in the second embodiment, the semiconductor device has multiple (for example, two) phases configured with pairs of semiconductor elements as multiple semiconductor elements. Although Figures 5 and 6 show an example having two phases, a high side and a low side, the semiconductor device may have three or more phases.

[0043] The semiconductor device includes an insulating layer 1, a conductor foil 2, circuit patterns 3a, 3b, a pair of semiconductor elements 4a, 5a, a pair of semiconductor elements 4b, 5b, a wiring board 6 as a first wiring board, wiring boards 7a, 7b as a second wiring board, a sealing material 9 (see Figure 1), and a cooler 10 (see Figure 1).

[0044] The conductor foil 2 is provided on the lower surface of the insulating layer 1. The insulating layer 1 and the conductor foil 2 are formed into rectangular shapes of the same size when viewed from above. The circuit patterns 3a and 3b are made of copper, which has low conductor resistance, and are provided on the upper surface of the insulating layer 1. The circuit patterns 3a and 3b are formed into elongated rectangular shapes that are smaller than the insulating layer 1 when viewed from above.

[0045] The pair of semiconductor elements 4a, 5a are mounted by being bonded to the upper surface of the circuit pattern 3a. The pair of semiconductor elements 4b, 5b are mounted by being bonded to the upper surface of the circuit pattern 3b. The semiconductor material of the pair of semiconductor elements 4a, 5a and the pair of semiconductor elements 4b, 5b is, for example, silicon (Si) or silicon carbide (SiC).

[0046] Wiring board 6 is bonded to the upper surface of circuit pattern 3a and passes a current input from the outside to circuit pattern 3a. Wiring board 7a connects the pair of semiconductor elements 4a, 5a and is bonded to the upper surface of circuit pattern 3b and outputs a current that has flowed through circuit pattern 3a and the pair of semiconductor elements 4a, 5a to the outside and to circuit pattern 3b. Wiring board 7b connects the pair of semiconductor elements 4b, 5b and outputs a current that has flowed through wiring board 7a and the pair of semiconductor elements 4b, 5b to the outside.

[0047] For bonding the various members, bonding materials are used as in the first embodiment. One end of wiring board 6 is a C1 terminal, one end of wiring board 7a is an E1C2 terminal, and one end of wiring board 7b is an E2 terminal.

[0048] As described above, the semiconductor device according to the second embodiment has multiple phases each composed of multiple semiconductor elements, and therefore it is possible to achieve a reduction in wiring inductance even in a semiconductor device incorporating multiple phases.

[0049] <Embodiment 3> Next, a semiconductor device according to embodiment 3 will be described. Fig. 7 is a perspective view of the semiconductor device according to embodiment 3. Note that in embodiment 3, the same components as those described in embodiments 1 and 2 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0050] 7, in the third embodiment, conductor foils 12a and 12b are laminated on the lower surfaces of wiring boards 6 and 7 via insulating films 11a and 11b, respectively. As a result, wiring boards 6 and 7 form parallel plates on top and bottom with insulating films 11a and 11b sandwiched therebetween.

[0051] As described above, in the semiconductor device according to the third embodiment, wiring board 6 and wiring board 7 have conductor foils 12a, 12b, separate from conductor foil 2, laminated on their lower surfaces with insulating films 11a, 11b interposed therebetween. This reduces the inductance of wiring boards 6, 7, thereby achieving a further reduction in wiring inductance.

[0052] <Fourth embodiment> In this embodiment, the semiconductor device according to the above-mentioned embodiments 1 to 3 is applied to a power conversion device. Although the application of the semiconductor device according to the embodiments 1 to 3 is not limited to a specific power conversion device, the case where the semiconductor device according to the embodiments 1 to 3 is applied to a three-phase inverter will be described below as embodiment 4.

[0053] FIG. 8 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to the fourth embodiment is applied.

[0054] The power conversion system shown in Fig. 8 is composed of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power source 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0055] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 8, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0056] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid car, an electric car, a railroad car, an elevator, or an air conditioner.

[0057] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and free wheel diodes (not shown), and converts DC power supplied from the power source 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element. At least one of the switching elements and free wheel diodes of the main conversion circuit 201 is configured by a semiconductor module 202 corresponding to any one of the above-mentioned embodiments 1 to 3. Two switching elements of the six switching elements are connected in series to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0058] The main conversion circuit 201 also includes a drive circuit (not shown) for driving each switching element, but the drive circuit may be built in the semiconductor module 202, or the drive circuit may be provided separately from the semiconductor module 202. The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0059] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, a control command (control signal) is output to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0060] In the power conversion device according to the present embodiment, the semiconductor modules according to the first to third embodiments are applied as the switching elements and free wheel diodes of the main conversion circuit 201, so that it is possible to achieve both miniaturization and reduced wiring inductance.

[0061] In the present embodiment, an example in which the semiconductor device according to the first to third embodiments is applied to a two-level three-phase inverter has been described, but the application of the semiconductor device according to the first to third embodiments is not limited to this, and the semiconductor device according to the first to third embodiments can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but the semiconductor device according to the first to third embodiments can be applied to a three-level or multi-level power conversion device, and when power is supplied to a single-phase load, the semiconductor device according to the first to third embodiments can be applied to a single-phase inverter. Also, when power is supplied to a DC load or the like, the semiconductor device according to the first to third embodiments can be applied to a DC / DC converter or an AC / DC converter.

[0062] Furthermore, the power conversion device to which the semiconductor device according to the first to third embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0063] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0064] 1 insulating layer, 2 conductor foil, 3, 3a, 3b circuit pattern, 4, 4a, 4b, 5, 5a, 5b semiconductor element, 6, 7, 7a, 7b wiring board, 11a, 11b insulating film, 12a, 12b conductor foil, 16 semiconductor element, 200 power conversion device, 201 main conversion circuit, 203 control circuit.

Claims

1. An insulating layer; A conductor foil provided on the lower surface of the insulating layer; A circuit pattern provided on an upper surface of the insulating layer; A plurality of semiconductor elements mounted on an upper surface of the circuit pattern; a first wiring board connected to an upper surface of the circuit pattern and configured to allow an externally input current to flow through the circuit pattern; a second wiring board that connects a plurality of the semiconductor elements and causes a current to flow through the plurality of the semiconductor elements via the circuit pattern; The semiconductor elements are arranged along an extending direction of the second wiring board, in a current path passing from the first wiring board through the circuit pattern and the plurality of semiconductor elements to the second wiring board, an electrical resistance of the current path passing through the semiconductor element arranged on a downstream side is smaller than an electrical resistance of the current path passing through the semiconductor element arranged on an upstream side, A semiconductor device, wherein a current path from the first wiring board to the second wiring board is U-shaped in a top view.

2. the plurality of semiconductor elements are pairs of the semiconductor elements; a current path between the pair of semiconductor elements is branched into a first current path that does not pass through one of the semiconductor elements arranged on the upstream side and passes through the other of the semiconductor elements arranged on the downstream side via the circuit pattern, and a second current path that passes through the second wiring board via one of the semiconductor elements, 2. The semiconductor device according to claim 1, wherein when an electric resistance of said first current path is R1 and an electric resistance of said second current path is R2, a relationship of R1<R2 is satisfied.

3. The semiconductor elements include an IGBT and an FWD, 3. The semiconductor device according to claim 1, wherein the FWD is mounted upstream of the IGBT.

4. The semiconductor device according to claim 1 , further comprising a plurality of phases each composed of a plurality of said semiconductor elements.

5. The semiconductor device according to claim 1 , wherein the circuit pattern contains copper.

6. 6. The semiconductor device according to claim 1, wherein the circuit pattern has a thickness of 0.2 mm or more.

7. 7. The semiconductor device according to claim 1, wherein the insulating layer has a thickness of 0.5 mm or less.

8. An insulating layer; A conductor foil provided on the lower surface of the insulating layer; A circuit pattern provided on an upper surface of the insulating layer; A plurality of semiconductor elements mounted on an upper surface of the circuit pattern; a first wiring board connected to an upper surface of the circuit pattern and configured to allow an externally input current to flow through the circuit pattern; a second wiring board that connects a plurality of the semiconductor elements and causes a current to flow through the plurality of the semiconductor elements via the circuit pattern; The semiconductor elements are arranged along an extending direction of the second wiring board, in a current path passing from the first wiring board through the circuit pattern and the plurality of semiconductor elements to the second wiring board, an electrical resistance of the current path passing through the semiconductor element arranged on a downstream side is smaller than an electrical resistance of the current path passing through the semiconductor element arranged on an upstream side, a conductive foil different from the conductive foil is laminated on the lower surfaces of the first wiring board and the second wiring board via an insulating film,

9. 9. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements include reverse conducting IGBTs.

10. The semiconductor device according to claim 1 , wherein a semiconductor material of the plurality of semiconductor elements is SiC.

11. A main conversion circuit having the semiconductor device according to any one of claims 1 to 10, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit; A power conversion device comprising:

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