Event-based vision sensor manufactured using 3D-IC technology

Abstract

To provide an event-based vision sensor by using an advanced stacking technology, known as Three-Dimensional Integrated Circuit technology.SOLUTION: In three-dimensional integration, many wafers (or dies) are stacked and are interconnected vertically. An electronic integrated circuit of a sensor is distributed between two or more electrically connected dice. On a wafer 1, a photosensitive device such as a PD is formed, and on a wafer 2, a pixel circuit such as a PR or an event generator is formed. Both wafers are bonded via a Cu-Cu bonded portion CC.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 62 / 642,838, filed March 14, 2018, which is incorporated herein by reference. [Background technology]

[0002] One of the important parameters in the design of an event-based pixel array (also called Dynamic Vision Sensor (DVS)) is the quantum efficiency (QE). QE is the ratio of the number of electrons generated for an optical signal to the number of photons of this optical signal. This parameter depends directly on the fill-factor (FF), which is the ratio of the area of ​​the photosensitive device exposed to light to the total area of ​​the integrated circuit exposed to light.

[0003] Today, event-based vision sensors are realized using silicon planar processes, so the exposed area is shared between the photosensitive device and other semiconductor devices that make up the pixel circuitry. This approach has two main drawbacks: first, the area of ​​the photosensitive device is limited, and second, circuits that do not need to be exposed are exposed to light, which reduces the circuit performance. Summary of the Invention

[0004] The main objective of this invention is to mitigate these two problems by using advanced stacking techniques in the manufacture of event-based vision sensors. Such advanced stacking techniques are known as Three-Dimensional Integrated Circuit (3D-IC) technology, which allows many wafers (or dies) to be stacked and interconnected vertically.

[0005] The current motivations are as follows:

[0006] To increase FF.

[0007] Shielding of circuits that do not need or should not receive light.

[0008] Different components of a pixel have different requirements that can best be met by realizing each of them in different IC processes (the photosensitive devices could theoretically be fabricated in non-silicon based technologies, e.g. GaAs).

[0009] In general, in one aspect, the invention features an event-based vision sensor (EBVS) that includes vertically connected stacked dies, such that the light sensitive device for each pixel of a pixel array can be located on the die that is exposed, while other devices not used to receive light can be located on other wafers or dies.

[0010] Preferably, there is at least one connection for every pixel in the pixel array between the die.

[0011] Typically, a photodiode for each pixel in the pixel array is on a first die, an event detector for each pixel in the pixel array is on a second die, and the photodiode is connected to each event detector by an interconnect between the first die and the second die.

[0012] This technique can be used for front-side illuminated and back-side illuminated structures.

[0013] Also, there are many different ways to implement the photoreceptor circuitry for each pixel in the pixel array: for example, the photoreceptor circuitry can be located on the second die, on the first die, or distributed between the first and second die.

[0014] Additional amplifier stages may be added to the first die.

[0015] Often, n-FET transistors are used in a first wafer or die, and both n-FET and p-FET transistors are used in a second die.

[0016] Also, the transistors on the first die and the transistors on the second die may have different transistor characteristics, different gate oxide thicknesses, or different implants.

[0017] In general, in one aspect, the invention features a method for manufacturing an event-based vision sensor. Typically, the method involves fabricating a different device at each pixel of a pixel array on a different wafer or die, and then stacking the wafers or dies.

[0018] The term "die" as used herein refers to a portion of a semiconductor wafer, typically having a rectangular shape such as a chip, where the portion of the semiconductor wafer includes a portion of an example integrated circuit device such as an event-based vision sensor. The reference to wafer or die is based on the possibility of different manufacturing techniques. The stacking may be performed at the wafer level before dicing into dies, or the stacking may be performed on individual dies after cutting (dicing) the dies from the wafer. As a result, the final device resulting from such a manufacturing process is a stacked die.

[0019] The method then involves connecting each pixel using, for example, Cu-Cu joints.

[0020] In one embodiment, the method further includes fabricating a photodiode for each pixel of the pixel array on the first wafer or die, and fabricating an event detector for each pixel of the pixel array on the second wafer or die.

[0021] These and other features and advantages of the invention, including various novel details of construction and combination of parts, are hereinafter particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and devices embodying the invention are shown by way of example only and not by way of limitation of the invention. The principles and features of the invention can be implemented in various embodiments without departing from the scope of the invention.

[0022] In the drawings, where like reference numbers refer to the same parts in different drawings, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a circuit diagram illustrating an embodiment of a prior art pixel for an event-based image sensor as described, for example, in PCT / IB2017 / 058526 and US Pub. No. 2018 / 0191972.

[0024] [Figure 2A] 2A to 2C show a conventional event-based image sensor implemented by a single wafer (FIGS. 2A and 2B show partial vertical cross-sectional views, and FIG. 2C shows a partial top view). FIG. 2A shows an example of application to front-side illumination (FSI). [Figure 2B] FIG. 2B shows an example of application to back-side illumination (BSI). [Figure 2C] FIG. 2C shows a partial top view.

[0025] [Figure 3A] FIG. 3A shows a partial cross-sectional view of two stacked wafers according to a preferred embodiment prior to dicing of the wafers. [Figure 3B]FIG. 3B is a partial cross-sectional view focused on one pixel, showing the back-side illuminated (BSI) top wafer containing only a photo-diode (PD) and one of the connections connecting each pixel to the bottom wafer. [Figure 3C] FIG. 3C is a block diagram showing details of the pixel front-end circuitry and how it is arranged across the wafer / die. [Figure 3D] Figure 3D is a schematic showing the details of the pixel front-end circuitry and how it is arranged between the wafers / dies.

[0026] [Figure 4A] FIG. 4A shows a partial cross-sectional view of two stacked wafers according to another embodiment, where the top wafer further contains two transistors of the front-end circuitry. [Figure 4B] FIG. 4B is a schematic showing details of the pixel front-end circuitry and how it is arranged between the wafer / die.

[0027] [Figure 5A] FIG. 5A is a partial cross-sectional view of two stacked wafers showing the entire front end on the top wafer, eventually including the source follower stage. [Figure 5B] Figure 5B is a partial cross section focused on one pixel, showing how the output from the first wafer can make a direct connection to one of the plates of the MIM (metal-insulator-metal) capacitor of the event detector on the bottom wafer (located between the first and second metal layers from the top). This is a simplified cross section that includes details regarding the silicon processing layers for the two stacked wafers. [Figure 5C] 5C and 5D are circuit diagrams showing details of the pixel front-end circuit. [Figure 5D] 5C and 5D are circuit diagrams showing details of the pixel front-end circuit.

[0028] [Figure 6A] FIG. 6A is a circuit diagram showing an alternative pixel front-end circuit that includes an additional p-FET for improved performance. [Figure 6B] FIG. 6B is a schematic diagram illustrating wafer / die isolation.

[0029] [Figure 7A] Figures 7A-7C are circuit diagrams showing various pixel front-end circuits that require multiple Cu-Cu junctions in every pixel. Figure 7A shows a preferred example. [Figure 7B] Figures 7B and 7C show how the circuit components can be arranged between the wafers / dies such that the top wafer does not contain p-FET devices, and why in this case more than two inter-wafer (or die) connections are required per pixel. [Figure 7C] Figures 7B and 7C show how the circuit components can be arranged between the wafers / dies such that the top wafer does not contain p-FET devices, and why in this case more than two inter-wafer (or die) connections are required per pixel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, which show illustrative examples of the invention. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein, but rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Additionally, the singular forms and articles "a", "an" and "the" are intended to include the plural forms unless expressly indicated otherwise. Additionally, when the terms "includes", "comprises", "including" and "comprising" are used within this specification, they are understood to specify the presence of stated features, integers, steps, operations, elements, and / or components, but not to preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, when elements, including components or subsystems, are referred to or illustrated as being connected or coupled to other elements, it is understood that they may be directly connected or joined or that there may be intervening elements.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms as defined in commonly used dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant art, and unless expressly defined herein, they should not be interpreted in an idealized or overly formal sense.

[0033] definition

[0034] An Event-Based Pixel Array (EBPA) is an array of pixels with light-sensitive devices, each of which is spatially and / or temporally independent and generates discretized data in response to the optical radiation it receives.

[0035] An Event-based Vision Sensor (EBVS) is a sensor that outputs data extracted and / or constructed from an EBPA.

[0036] The fill-factor (FF) is defined as the ratio of the area of ​​a pixel to the area of ​​the photosensitive device contained within it. It is a measure of how much of all the optical radiation that reaches the sensor's surface is efficiently received by the sensor.

[0037] Quantum efficiency (QE) is defined as the ratio of the number of photons that reach the surface of a photosensitive sensor to the number of electrons that are correspondingly generated and converted into an electrical signal.

[0038] 3D IC is an acronym for Three-Dimensional Integrated Circuit, a technology for manufacturing integrated circuits by stacking silicon wafers or dies and interconnecting them vertically.

[0039] Front-side illumination (FSI) is a type of image sensor realized as an integrated circuit (IC) so that light enters from the top of the die, the side where the planar process layers are implemented. All devices and metal interconnects, along with the light-sensitive devices, receive the optical radiation directly.

[0040] Back-side illumination (BSI) is a type of image sensor implemented as an integrated circuit so that light enters from the bottom of the die, the substrate side. The devices and metal interconnects do not receive optical radiation directly, only through the substrate.

[0041] Prior Art

[0042] Examples of event-based vision sensors are described, for example, in PCT / IB2017 / 058526, US7728269B2, and US Pub. No. 2018 / 0191972.

[0043] 1 shows an example pixel structure of an EBPA of an EBVS, which is used as a reference in this specification, based on PCT / IB2017 / 058526 and US Pub. No. 2018 / 0191972, which are incorporated by reference herein. However, the main concepts of the present invention can be applied to substantially any event-based vision sensor implemented as an IC, regardless of the particular pixel structure used.

[0044] The main components of the pixel circuit are listed below.

[0045] 1. Photoreceptor Module. As shown in the figure, pixel circuit 100 includes a photodiode PD or other photosensor for measuring impinging light and converting the light intensity into a current Iphoto, a photoreceptor circuit PRC for generating a photoreceptor signal Vpr that is dependent on the light intensity, and a memory capacitor C1 for storing past photoreceptor signals. The photosensor PD and the photoreceptor circuit PRC constitute the photoreceptor module PR.

[0046] 2. Memory capacitor C1: receives the photoreceptor signal Vpr such that a first plate of the capacitor carries a charge according to the photoreceptor signal Vpr and thus the light received by the photosensor PD. The memory capacitor C1 is part of the event detector ED. The second plate of the memory capacitor C1 is connected to the comparator node (inverting input) of A1. Thus, the voltage Vdiff at the comparator node varies with changes in the photoreceptor signal Vpr.

[0047] 3. Comparator A1: This is a means for comparing the difference between the current photoreceptor signal Vpr and the past photoreceptor signal with a threshold. The comparator A1 is part of the event detector ED. This comparator A1 may be in each pixel or may be shared between a subset of pixels (e.g. a pixel column). In the preferred embodiment, the comparators are integral to the pixels, each pixel having its own dedicated comparator A1.

[0048] 4. Memory: The memory 50 stores the comparator output based on the sample signal from the controller 60. The memory 50 is part of the event detector ED. The memory can be a sampling circuit (e.g., a switch and a parasitic or explicit capacitor) or a digital memory circuit (latch or flip-flop). In an embodiment, the memory is a sampling circuit and each pixel has two memories.

[0049] 5. Conditional Reset Circuit R1: The condition for a reset is the combination of the stored state of the comparator output and a reset signal applied by the controller 60. The conditional reset circuit R1 is part of the event detector ED.

[0050] 6. Peripheral circuit components: Comparator A1 and memory 50 can be located in the pixel or in the peripheral circuit (external to the pixel circuit).

[0051] The peripheral circuitry includes a controller 60 that applies a threshold signal to comparator A1 and sends a control signal to memory 50 to select the times when the conditional reset circuit R1 is active.

[0052] The peripheral circuitry may also include readout circuitry, which reads the contents of memory 50, determines whether the light intensity for a given pixel has increased, decreased, or remained unchanged, and sends an output (calculated from the current memory value) to a processor.

[0053] More specifically, the comparator tells if the light has increased and / or decreased. For an Off event: If Vdiff is below the threshold Voff (on Vb), the comparator output is high and this level is stored in memory. This means that a decrease is detected. If Vdiff is not below the threshold, the comparator output is low, meaning that a decrease is not detected.

[0054] The only difficulty is that for an On event, a low comparator output means an increase while a high comparator output means no change, but for an Off event, a high comparator output means a decrease while a low comparator output means no change.

[0055] Therefore, when reading, it is necessary to know the memory contents and which threshold has been applied.

[0056] The pixel circuit 100 and controller 60 operate as follows.

[0057] Changes in the light intensity received by the photosensor PD translate into changes in the photoreceptor signal Vpr. When the reset circuit R1 is not conducting, changes in Vpr are also reflected in the comparator node voltage Vdiff at the inverting input (-) to the comparator A1. This occurs because the voltage across the memory capacitor C1 remains constant.

[0058] At a time selected by the controller 60, the comparator A1 compares the voltage (Vdiff) of the comparator node at the second terminal of the memory capacitor C1 with a threshold voltage Vb (from the controller) applied to the non-inverting input (+) of the comparator A1.

[0059] The controller 60 operates the memory 50 to store the comparator output Vcomp. The memory 50 is typically implemented as part of the pixel circuit 100, as shown. However, in other embodiments, the memory 50 is implemented as part of the column logic circuits (peripheral circuits, one for each column of the pixel array).

[0060] If the state of the stored comparator output held in memory 50 indicates a change in light intensity, AND, the global reset signal, GlobalReset signal, from controller 60 is active, then conditional reset circuit R1 is conductive, where "AND" denotes a logical AND operator. When conditional reset circuit R1 is conductive, the comparator node voltage (Vdiff) at the inverting input of comparator A1 is reset to a known level. Comparator A1 therefore stores the current photoreceptor signal Vpr on memory capacitor C1.

[0061] Currently, such an EBVS with an EBPA of the pixel shown in Figure 1 is fabricated as an integrated circuit using a silicon planar process on a single wafer. With this technology, semiconductor devices (e.g., MOS transistors, diodes, photodiodes, polysilicon resistors, etc.) are located only on a single layer, and vertical stacking of semiconductor devices is not possible.

[0062] For this reason, the area of ​​the pixel 100 must be shared between the light-sensitive device (e.g., PD) and other elements of the circuit. In this regard, Fig. 2A shows a front-illuminated structure, Fig. 2B shows a back-illuminated structure, and in particular Fig. 2C shows a top view. This means that the photodetector PD cannot use all the light that reaches its surface. Although this problem can be mitigated by using a layer of microlenses, the surface of the sensor will always have parts that absorb the optical radiation without converting it into a useful electrical signal.

[0063] Also, light reaching non-photosensitive devices can have unwanted effects, since some of the characteristics of the non-photosensitive devices can be altered by light impinging on them. For example, MOS transistors contain several semiconductor pn junctions. Typically, the semiconductor pn junctions capture the photo-generated carriers and generate unwanted signals in response.

[0064] A more advanced process technique called back-side illumination (BSI) allows for better utilization of the available area by exposing the back side of the wafer or die, which is the silicon substrate. In this way, there is more freedom for wiring metal connections that can be located above the photosensitive devices in the pixels, whereas in front-side illumination (FSI) techniques, the photosensitive devices must be exposed to light toward the top of the wafer, so metal cannot be placed on top of the photosensitive devices to maximize the light captured. The present invention is superior to both BSI and FSI approaches performed on a single wafer or die.

[0065] As is well known, event-based vision sensors are based on an array of pixels, which generate data in response to the light that reaches them, with each pixel being spatially and / or temporally independent.

[0066] Each pixel includes a circuit. This circuit is divided into a light sensitive part (e.g. a photodiode PD) and a non-light sensitive part (e.g. a photoreceptor circuit PRC, a capacitor C1, a comparator A1, a memory 50, and a reset circuit R1). The non-light sensitive part biases the light sensitive circuit, receives the signal generated in response to light, and often performs a first signal conditioning or refinement. Examples of this type of pixel have been described above (in the prior art).

[0067] Typically, such sensors are manufactured as silicon integrated circuits (ICs) based on planar processes. This means that the light-sensitive part of the pixel and the remaining circuitry must be realized using a single layer of semiconductor devices. As a result, part of the pixel's area is taken up by non-light-sensitive circuitry, effectively reducing the pixel's fill factor (see Figures 2A, 2B and 2C) and therefore its quantum efficiency. The same is true for back-side illuminated (BSI) ICs manufactured on a single wafer or die.

[0068] In the present invention, the fill factor of the pixels of an event-based vision sensor can be maximized by stacking multiple wafers or dies using a technique known as three-dimensional integration (3DIC).

[0069] Since the photosensitive devices can be overlaid on the non-photosensitive parts of the circuitry, the above technique allows the circuitry of the pixel to be split between different wafers or dies, maximizing the area of ​​the photosensitive devices. Furthermore, the circuitry located on the wafer below the top wafer does not receive any (or most) of the optical radiation captured by the top wafer, allowing a significant reduction in undesirable behavior in the non-photosensitive circuits due to impinging light.

[0070] Another advantage of this approach is that the two wafers or dies can be manufactured using two different technological processes, making it possible to choose the best process available for both the photosensitive devices and the rest of the circuitry, the technological requirements of which often do not completely overlap.

[0071] Example of an embodiment

[0072] Figures 3A to 3C show a first embodiment (preferred embodiment) of the present invention. In Figures 3A and 3B, a vertical cross-section of an IC of an EBVS is shown. Figure 3A illustrates two stacked wafers (or dies). The connection to the bottom wafer (wafer 2) is provided as a wire bond pad 210 located on the top surface of the top wafer (wafer 1). Electrical connections are made through the body of the top wafer (wafer 1) by using Through-Silicon Vias (TSVs). The ends of the TSVs are Cu-Cu joints CC, such as copper ball bumps. In this way, electrical connections are made between the bottom surface of the top wafer and the electrical circuits on the top surface of the bottom wafer (wafer 2).

[0073] In this specification, the terms die and wafer are used interchangeably. Generally, a "die" refers to a portion of a semiconductor wafer, typically having a rectangular shape such as a chip. Here, the portion of the semiconductor wafer includes a portion of an example integrated circuit device such as an event-based vision sensor. The reference to wafer or die is based on the possibility of different manufacturing techniques. The stacking can be performed at the wafer level before dicing into dies. Alternatively, the stacking can be performed on individual dies after the dies are cut (diced) from the wafer. In either case, the final singulated device resulting from this manufacturing process, i.e., the EBVS, is a stack of multiple dies.

[0074] Figure 3B shows a detailed vertical cross-section of a pixel of the EBVS. It can be seen how light only strikes the surface of the top wafer (wafer 1) on the substrate side (BSI) and how this wafer only contains the light-sensitive device, the photodiode PD. For this reason, one Cu-Cu joint CC is used per pixel to connect to the bottom wafer (or die). The bottom wafer (wafer 2) implements the non-light-sensitive part of the pixel circuit, e.g. the comparator A1.

[0075] FIG. 3C shows the pixel circuit diagram. This example refers to the pixel circuit described in PCT / IB2017 / 058526 and US Pub. No. 2018 / 0191972 and FIG. 1, but different structures of the event detection pixel may be used. This illustrates how the circuitry is allocated between two wafers (or dies). The top wafer / die (wafer 1) is populated with only the photodiode PD, and the bottom wafer / die is populated with the remaining pixel circuitry. There is a Cu-Cu junction CC for every pixel. The Cu-Cu junction CC connects the photodiode and the light receiving circuitry. Also shown is the event detector on wafer 2. The readout circuitry RO may be located on wafer 2 or on the other wafer or die.

[0076] FIG. 3D shows in schematic form details of the photoreceptor circuit PRC implemented on wafer 2.

[0077] Figures 4A and 4B show another embodiment, where the circuitry selected for the pixel is the same as that shown in Figures 3C and 3D, but the components of the circuitry are arranged differently across the wafer / die.

[0078] Additionally, the segmented wafer / die as shown in FIG. 4B allows the circuitry in the bottom wafer to be implemented with all p-type MOSFET devices since the event detector can be implemented with only p-type devices. This approach allows the pixel area to be further reduced since the entire pixel area can be placed in the same n-well. Typically, a minimum clearance is required between the n-type MOSFET device and the n-well (where the p-type MOSFET device is located). If there are no n-type devices and the pixel is contained in a single n-well, the area required for the pixel can be smaller than if both n-type and p-type devices are used for all pixels.

[0079] As shown in FIG. 4B, the top wafer (wafer 1) includes two n-FET transistors (M1 and MA1) of the photoreceiver circuit PRC together with the photodiode PD. In this case, the Cu-Cu junction CC between the wafer / die is located between the node connecting the gate of the feedback transistor M1 to the drain of MA1 and the node connecting the drain of the bias p-FET transistor MA2 to the input of the event detector. The input of the event detector corresponds to one of the plates of the capacitor C1 shown in FIG. 1. Such an arrangement allows to improve the performance of the photodetection without excessively reducing the fill factor and without reducing the complexity of the top wafer (effectively limiting the number of process masks required for its manufacture). This performance is improved, especially with regard to noise. The Cu-Cu junction typically has some resistance due to the vias and metal layers required to reach the surface of one wafer and the devices of the other wafer. This resistance causes thermal noise. Moreover, the stacked metal layers and vias are usually manufactured using different metals, and this metal junction causes noise. For this reason, a solution such as that shown in Figures 4A and 4B is beneficial. This solution sacrifices less of the area occupation benefits initially provided by wafer / die stacking technology. Also, such a solution requires less area on the lower wafer (wafer 2) since fewer transistors are required. This allows for a smaller pixel size. An additional advantage of this solution (and other solutions with transistors on both wafers) is that the characteristics of the two transistors on the upper wafer can be optimized independently of the characteristics of the transistors on the lower wafer (wafer 2).

[0080] 5A to 5D show a third embodiment, which refers again to the circuits presented in the previous embodiments, but in which the top wafer (wafer 1) contains the bias transistors of the front-end circuit. Finally, it is also possible to add a buffer stage, preferably realized as a source follower amplifier stage.

[0081] The advantage of this embodiment is that it improves the driving capability of the circuit before bonding between the wafers (dies). In particular, when adding a buffer stage, the load on the output node is reduced, so that the resistance of the Cu-Cu junction CC has less impact on the performance of the front-end. In this case, the Cu-Cu junction is located between the output node of the front-end and the input of the event detection circuit. As an example, the output node of the front-end is composed of the gate of M1, the drain of MA1, and the drain of MA2. The input of the event detection circuit corresponds to one of the plates of the capacitor C1.

[0082] However, the biggest advantage of this approach has to do with the fact that the capacitor C1 is usually fabricated as a MIM (metal-insulator-metal) capacitor. This type of device is fabricated using two metal layers that are the top layers of a silicon planar process, or finally one metal layer below the top layer. Then, the output of the circuit implemented on the top wafer can be directly connected to the top plate of the MIM capacitor, maximizing the size of the capacitor. This is because the circuit on the top wafer does not need to be connected to any other node except the top plate of the MIM capacitor C1, and can be realized by occupying the entire area of ​​the pixel.

[0083] Therefore, this approach allows for a much easier pixel layout and ultimately smaller pixels by better distributing the devices between the two wafers / dies.

[0084] This is shown in Figure 5B, which is a schematic diagram of two stacked wafers (wafer 1 and wafer 2), realized in silicon planar processing technology, illustrating the various layers that form the wafers. This allows one to understand how the last metal layer of the top wafer can be directly connected to one of the plates of the MIM capacitor C1. In this example, the top wafer / die is arranged as a BSI (backside illuminated) structure, so that it receives light on the substrate side and is connected to the other wafer using a Cu-Cu junction CC, which bonds the two respective top metal layers of the two wafers / dies. To simplify the drawing, the photodiode junction shown in Figure 5 is realized as an n-well in a p-substrate, although in practice a more advanced structure would be preferred.

[0085] Figures 5C and 5D show two different circuit layouts. Specifically, Figure 5D shows a front end that includes a buffer amplifier B (preferably a source follower amplifier).

[0086] By connecting the top wafer to the bottom wafer using TSVs (Through Silicon Vias), a FSI (Front Side Illumination) approach to the top wafer can be realized.

[0087] Using this approach, the MIM capacitor C1 can also be placed on the top wafer (or die) (wafer 1) instead of the bottom wafer (or die) (wafer 2), using the same transistor placement between the two wafers (or dies). Such an approach can be reasonable, for example, by taking specific considerations regarding the metal layers to distribute them between the wafers (or dies) according to the most cost-effective solution. The two wafers can be realized in two different technologies. In one of these technology processes, it is possible to add metal layers and MIM-specific metal layers more cheaply than in the other process.

[0088] In all of the wafer examples shown in this specification, additional layers implementing microlenses and / or optical waveguides can be stacked on the exposure side, which can improve the QE of the photoreceptor, but these microlenses and / or optical waveguides are not shown to simplify the drawings.

[0089] Figure 6A shows another embodiment of a pixel front end, which again requires only one inter-wafer (or die) connection per pixel. The top wafer (wafer 1) contains the transistors that make up the pixel front end, including the photodiode PD, as well as the photoreceptor circuit PRC.

[0090] 6B shows how an amplifier stage B (preferably realized as a source follower amplifier) ​​can be added eventually and how it can be included in the top wafer (wafer 1). This has the advantage of improving the driving capability of the front-end and effectively limiting the loading on the output nodes of the front-end (gate of M1, drain of MA1, and drain of MA2). In fact, the Cu-Cu junctions CC may have a non-negligible resistance that would directly load the output of the front-end if there were no amplifier stage.

[0091] In Figure 7A, a pixel front-end circuit similar to that shown in Figure 5B is shown. The amplifier stage in Figure 7A is shown explicitly as a source-follower amplifier implemented with n-FET MOS devices. The solution proposed here does not include p-FET devices in the top wafer, so the number of inter-wafer (or die) connections required is more than one. Specifically, there are now two connections per pixel.

[0092] The choice to not have a p-FET MOS device in the top wafer has the advantage of improving QE, since if an n-well is present in the illuminated wafer, this n-well will attract carriers generated by the impinging light and act as a parasitic photodiode connected between the supply voltage and ground.

[0093] Figure 7C shows another implementation of a pixel front end, similar to that shown in Figure 6B. In this embodiment, as in Figure 7A, the illuminated top wafer does not contain p-FET MOS devices, and therefore multiple inter-wafer (or die) connections are required per pixel. In this embodiment, four connections per pixel are required. The buffer stage is implemented as a source follower amplifier made of n-FET devices.

[0094] In Figure 7C, we show the same pixel structure used in Figure 7B, but the source follower amplifier acting as a buffer is realized with a p-FET MOS device. In this way, one connection per pixel can be omitted, leaving only three connections required.

[0095] In general, many different ways of dividing the pixel circuit are available, all with their own advantages and disadvantages. For example, one can consider separating the digital and analog parts of the circuit, focusing on finding the best technology for each part of the circuit. Also, for example, by using Cu-Cu joints and TSVs, stacking techniques do not impose theoretical limits on the number of wafers / dies that can be stacked and connected vertically. Such connections can be located within every pixel, or at the edge of the pixel array, for example one connection per column and / or row.

[0096] While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as encompassed by the appended claims.

Claims

1. 1. An event-based vision sensor including a stacked first die and a stacked second die, A photodiode for each pixel of a pixel array is disposed on the first die; an event detector for each pixel of the pixel array disposed on the second die; and a photoreceptor circuit configured to generate a photoreceptor signal dependent on light intensity and input the photoreceptor signal to the event detector; the photoreceptor circuit is comprised of a plurality of transistors; the event detector includes a memory capacitor, a comparator, and a memory; the memory capacitor is comprised of a MIM (metal-insulator-metal) capacitor, a first plate of the MIM capacitor being connected to a photoreceptor signal generated by the photoreceptor circuit, a second plate of the MIM capacitor being connected to one input of the comparator, and the other input of the comparator being connected to a threshold signal applied by a controller; The output of the comparator is configured to be stored in the memory. Event-based vision sensor.

2. 2. The event-based vision sensor of claim 1, a conditional reset circuit connected between the second plate of the MIM capacitor and one input of the comparator, the conditional reset circuit configured to switch a conductive state based on a combination of an output of the comparator stored in the memory and a reset signal applied by a controller. Event-based vision sensor.

3. 2. The event-based vision sensor of claim 1, The first die has a backside illumination structure in which a wiring layer is disposed on the side opposite to the light incidence surface. Event-based vision sensor.

4. 2. The event-based vision sensor of claim 1, The first die and the second die are connected to each other using Cu-Cu joints. Event-based vision sensor.

5. 2. The event-based vision sensor of claim 1, The first die and / or the second die include a stacked die, the stacked die having a through silicon via connection. Event-based vision sensor.

6. 2. The event-based vision sensor of claim 1, The photoreceptor circuit includes an n-FET transistor and a p-FET transistor. Event-based vision sensor.

7. 2. The event-based vision sensor of claim 1, The photoreceptor circuit includes two n-FET transistors and a p-FET transistor. Event-based vision sensor.

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