Sample holder and superconducting quantum computer

Abstract

To increase the resonance frequency of resonance occurring upon input of a signal of a specific frequency to a chip when the chip is mounted in a sample holder.SOLUTION: A sample holder includes a pedestal and a PCB (Printed Circuit Board) 3 in contact with the pedestal. The PCB 3 has a through-hole 4. The PCB 3 has a cavity 5 at least at a part of the pedestal below the through-hole 4. The cavity 5 has a support structure which supports the surface of the chip and is in communication with the pedestal. At least a part of the portion of the support structure which supports the chip 7 is not parallel to the back surface of the chip. The support structure includes conductor posts 6 located at the four corners of the cavity 5. At least a part of the upper surface of the post 6 is not parallel to the upper surface of the pedestal.SELECTED DRAWING: Figure 10A

Description

[Technical field]

[0001] The present disclosure relates to sample holders and the like. [Background technology]

[0002] A superconducting quantum circuit is formed on a substrate such as a silicon substrate using a superconducting material such as Nb (niobium) or Al (aluminum). Here, a superconducting quantum circuit formed on a substrate is called a chip. A superconducting quantum circuit is mounted on a sample holder for operation. Sample holders come in various structures. Methods for mounting a chip include a method of mounting the chip without turning over the circuit surface of the chip on a printed circuit board as described in Non-Patent Document 1, and a method of mounting the chip with the circuit surface of the chip turned over on a printed circuit board (flip-chip mounting) as described in Patent Document 1. The following explanation will be given on the premise of the former mounting method.

[0003] For example, there are structures in which a printed circuit board (PCB) is placed on a metal base. A through hole is provided near the center of the PCB, and a chip is placed in the through hole, and the chip pad and PCB pad, as well as the chip ground and PCB ground, are electrically connected with bonding wires such as Al. In such cases, the back side of the chip is in contact with the metal base.

[0004] When a chip is mounted on the sample holder as described above, resonance occurs when a signal of a specific frequency is input to the chip. Here, this resonance is called the resonance of the chip mode. When the resonance of the chip mode is coupled with the superconducting quantum circuit on the chip, it causes decoherence of the superconducting quantum circuit. In order to reduce the effect of this decoherence, the resonance frequency of the chip mode is made as high as possible. For example, Non-Patent Document 1 describes that in order to suppress the effect of the chip mode, in the structure as described above, a cavity is formed directly below the chip by hollowing out a part of the metal pedestal directly below the chip. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-299503 A [Non-patent literature]

[0006] [Non-Patent Document 1] B. Lienhard, et al., “Microwave Packaging for Superconducting Qubits,” arXiv: 1906.05425v1 [quant-ph] 12 Jun 2019. Summary of the Invention [Problem to be solved by the invention]

[0007] When a chip is mounted on a sample holder, there is a demand for a higher resonant frequency than that of the technology described in Non-Patent Document 1, which occurs when a signal of a specific frequency is input to the chip.

[0008] One example of the object of the present disclosure is to provide a sample holder or the like that, when a chip is mounted on the sample holder, increases the resonant frequency of resonance that occurs when a signal of a specific frequency is input to the chip. [Means for solving the problem]

[0009] In one embodiment of the present disclosure, a sample holder comprises a base and a PCB in contact with the base, the PCB having a through hole, a cavity in at least a portion of the base below the through hole, the cavity having a support structure that is conductive to the base and supports a surface of a chip, and at least a portion of the portion of the support structure that supports the chip is not parallel to the surface of the chip.

[0010] A superconducting quantum computer in one embodiment of the present disclosure comprises a sample holder and a chip on which a superconducting quantum circuit is formed and stored in the sample holder, the sample holder comprising a base and a PCB in contact with the base, the PCB having a through hole, at least a portion of the base below the through hole having a cavity, the cavity having a support structure that is conductive to the base and supports a surface of the chip, and at least a portion of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Effect of the Invention

[0011] According to the present disclosure, when a chip is mounted on a sample holder, the resonant frequency of resonance that occurs when a signal of a specific frequency is input to the chip is increased. [Brief description of the drawings]

[0012] [Figure 1A] FIG. 1 is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. [Figure 1B] FIG. 1B is a side view of the sample holder shown in FIG. 1A. [Figure 2A] Top view of the PCB. [Figure 2B] This is a bottom view of the PCB. [Figure 2C] FIG. 2 is a side view of the PCB. [Figure 2D] This is an oblique view of the PCB. [Figure 2E] This is an enlarged view of the PCB's through hole area. [Figure 3A] FIG. 2 is a perspective view showing a configuration in which a superconducting quantum circuit chip is mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 3B] 3A is an end view of a configuration in which a superconducting quantum circuit chip is mounted on the sample holder shown in FIG. 1A and FIG. 1B, the end view being cut along a plane parallel to the xz plane including the cutting line A-AA (z-axis direction) shown in FIG. 3A. [Figure 4A] FIG. 1 is a top view of a chip used in a simulation. [Figure 4B] FIG. 2 is an enlarged view of the vicinity of the tip of the first coplanar waveguide. [Figure 5A] FIG. 4B is a perspective view showing an example in which the chip shown in FIGS. 4A and 4B is mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 5B] FIG. [Figure 6A] 5B is an explanatory diagram showing reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 5A. FIG. [Figure 6B] 5B is an explanatory diagram showing transmission (S21) to Port 2 when a high-frequency signal is input from Port 1 shown in FIG. 5A. FIG. [Figure 7A] FIG. 1 is a perspective view of a sample holder having a cavity formed in a base. [Figure 7B] FIG. 1 is a top view of a sample holder having a cavity formed in a base. [Figure 7C] 7B is an end view of a sample holder having a cavity formed in a base, the end view being cut along a plane parallel to the xz plane including the cutting line B-BB shown in FIG. 7B. [Figure 8] FIG. 5B is an explanatory diagram showing a simulation result of reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 5A in the case where the chip shown in FIG. 4A and FIG. 4B is mounted with bonding wires on the sample holder shown in FIG. 7A, FIG. 7B, and FIG. 7C. [Figure 9] FIG. 2 is an explanatory diagram showing a sample holder according to the first embodiment. [Figure 10A] FIG. 2 is a perspective view showing a sample holder according to the first embodiment. [Figure 10B] FIG. 2 is a top view of the sample holder of the first embodiment. [Figure 10C] 10C is an end view of the sample holder of the first embodiment cut along a plane parallel to the xz plane including the cutting line C-CC shown in FIG. 10B. [Figure 11A] FIG. 2 is a top view of a PCB used in the sample holder of the first embodiment. [Figure 11B] FIG. 2 is a bottom view of a PCB used in the sample holder of the first embodiment. [Figure 11C] FIG. 2 is a side view of a PCB used in the sample holder of the first embodiment. [Figure 11D] FIG. 2 is a perspective view of a PCB used in the sample holder of the first embodiment. [Figure 11E] 4 is an enlarged view of the vicinity of a through hole of a PCB used in the sample holder of the first embodiment. FIG. [Figure 12] 11 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder according to the first embodiment with a bonding wire; FIG. [Figure 13A] FIG. 13 is a perspective view of a sample holder according to another example of the first embodiment. [Figure 13B] FIG. 13 is a top view of a sample holder according to another example of the first embodiment. [Figure 13C] 13C is an end view of a sample holder according to another example of the first embodiment, cut along a plane parallel to the xz plane including the cutting line D-DD shown in FIG. 13B. [Figure 14] FIG. 11 is an explanatory diagram showing a simulation result of S11 according to another example of the first embodiment. [Figure 15A] FIG. 13 is a perspective view of a sample holder according to a modified example of the first embodiment. [Figure 15B] FIG. 13 is a top view of a sample holder according to a modified example of the first embodiment. [Figure 15C] 15C is an end view of the sample holder according to the modified example of the first embodiment, cut along a plane parallel to the xz plane including the cutting line E-EE shown in FIG. 15B. [Figure 16] FIG. 15C is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder using a pedestal having a cavity formed therein. [Figure 17A] FIG. 13 is a perspective view of a sample holder according to a second embodiment. [Figure 17B] FIG. 11 is a top view of a sample holder according to a second embodiment. [Figure 17C] 17C is an end view of the sample holder according to the second embodiment cut along a plane parallel to the xz plane including the cutting line F-FF shown in FIG. 17B. [Figure 18] FIG. 11 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder according to the second embodiment with a bonding wire; [Figure 19A] FIG. 13 is a perspective view of a sample holder according to a modified example of the second embodiment. [Figure 19B] FIG. 11 is a top view of a sample holder according to a modified example of the second embodiment. [Figure 19C] 19C is an end view of a sample holder according to a modified example of the second embodiment, cut along a plane parallel to the xz plane including the cutting line G-GG shown in FIG. 19B. [Figure 20] FIG. 20 is an explanatory diagram showing a simulation result of S11 when a chip is mounted with bonding wires on a sample holder using a base with a cavity formed therein shown in FIGS. 19A to 19C. [Figure 21A] FIG. 13 is a perspective view of a sample holder according to the third embodiment. [Figure 21B] FIG. 13 is a top view of the sample holder of the third embodiment. [Figure 21C] 21C is a cross-sectional view of the sample holder of the third embodiment taken along a plane parallel to the xz plane including the cutting line H-HH shown in FIG. 21B. [Figure 22A] FIG. 11 is a perspective view showing a first example of the shape of a cavity of a sample holder according to the third embodiment. [Figure 22B] FIG. 13 is a top view showing a first example of a shape of a cavity of a sample holder according to the third embodiment. [Figure 22C] 22C is an end view of the sample holder according to the third embodiment, in which the vicinity of the cavity of the sample holder in the first shape example is cut along a plane parallel to the xz plane including the cutting line I-II shown in FIG. 22B. [Figure 23A] FIG. 11 is a perspective view showing a second example of the shape of a cavity of a sample holder according to the third embodiment. [Figure 23B] FIG. 13 is a top view showing a second example of a shape of a cavity of a sample holder according to the third embodiment. [Figure 23C]23C is a cross-sectional view of the sample holder in the second example of the shape of the cavity of the sample holder according to the third embodiment, taken along a plane parallel to the xz plane including the cutting line J-JJ shown in FIG. 23B. FIG. [Figure 24] FIG. 13 is an explanatory diagram showing a simulation result of S11 of a system in which a chip is mounted on a sample holder of the third embodiment with bonding wires. [Figure 25A] FIG. 13 is a perspective view of a sample holder according to a modified example of the third embodiment. [Figure 25B] FIG. 13 is a top view of a sample holder according to a modified example of the third embodiment. [Figure 25C] 25C is a cross-sectional view of a sample holder according to a modified example of the third embodiment, taken along a plane parallel to the xz plane including the cutting line K-KK shown in FIG. 25B. [Figure 26A] FIG. 13 is a perspective view showing a first example of a shape of a cavity of a sample holder according to a modified example of the third embodiment. [Figure 26B] FIG. 13 is a top view showing a first example of a shape of a cavity of a sample holder in a modified example of the third embodiment. [Figure 26C] 26B. FIG. 26C is an end view of the vicinity of the cavity of the sample holder in the first shape example of the cavity of the modified example of the third embodiment, cut by a plane parallel to the xz plane including the cutting line L-LL shown in FIG. 26B. [Figure 27A] FIG. 13 is a perspective view showing a second example of a shape of a cavity of a sample holder in a modified example of the third embodiment. [Figure 27B] FIG. 13 is a top view showing a second example of a shape of a cavity of a sample holder in a modified example of the third embodiment. [Figure 27C] 27C is a cross-sectional view of the sample holder in the second example of the shape of the cavity of the sample holder in the modified example of the third embodiment, taken along a plane parallel to the xz plane including the cutting line M-MM shown in FIG. 27B. FIG. [Figure 28] FIG. 13 is an explanatory diagram showing a simulation result of S11 of a system in which a chip is mounted on a sample holder with bonding wires according to a modified example of the third embodiment. [Figure 29A] FIG. 11 is a top view showing the structure of a PCB according to another embodiment. [Figure 29B]This is a cross-sectional view of a PCB according to another embodiment, cut along a plane parallel to the xy plane so that a core wire formed in an area sandwiched between a front surface GND and a back surface GND is visible. [Figure 29C] 29B is an enlarged view of the vicinity of the core wire in a cross section of a PCB according to another embodiment taken along a plane parallel to the xz plane including the cutting line N-NN shown in FIG. 29A. [Figure 29D] FIG. 11 is a bottom view showing the structure of a PCB according to another embodiment. [Figure 29E] FIG. 13 is a perspective view of a PCB according to another embodiment. [Figure 29F] 13 is an enlarged view of the vicinity of a through hole of a PCB according to a modified example of the other embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, with reference to the drawings, an embodiment of a sample holder and a superconducting quantum computer according to the present disclosure will be described in detail. However, the drawings show a schematic configuration of the embodiment of the present disclosure. Furthermore, the embodiment of the present disclosure described below is an example, and can be modified as appropriate within the scope of the same essence. In addition, in the description of the drawings below, the same or similar parts are given the same or similar symbols. In addition, in the drawings below, elements not used in the description are omitted as appropriate. In addition, in the following description, ground may be expressed as GND. For example, a front surface ground is expressed as a front surface GND. For example, a back surface ground is expressed as a back surface GND.

[0014] In order to clarify the effect of the sample holder according to each embodiment, the results of a simulation of a sample holder in which a cavity is formed in the pedestal immediately below the chip are compared with the results of a simulation of a sample holder according to each embodiment. Therefore, before a detailed description of each embodiment, the problem of the chip mode in the superconducting quantum circuit is first described in more detail. Then, the results of a simulation of a sample holder to be compared with the sample holder according to each embodiment are described. The sample holder to be compared has a PCB placed on a metal pedestal. Furthermore, this sample holder has a through hole near the center of the PCB. Furthermore, this sample holder has a part of the metal pedestal immediately below the chip hollowed out to form a cavity immediately below the chip.

[0015] In addition, in order to clarify each direction in each drawing, the description will be given using x-axis, y-axis, and z-axis as a three-dimensional coordinate system.

[0016] FIG. 1A is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. FIG. 1B is a side view of the sample holder 101 shown in FIG. 1A. As shown in FIG. 1A, the sample holder 101 has a configuration in which a PCB 103 is placed on a metal base 102. In FIG. 1A, the base 102 has a rectangular parallelepiped or cubic shape. A through hole 104 penetrating the PCB 103 is provided near the center of the PCB 103.

[0017] An example of PCB 103 is shown in Figures 2A to 2E. Figure 2A is a top view of PCB 103. Figure 2B is a bottom view of PCB 103. Figure 2C is a side view of PCB 103. Figure 2D is a perspective view of PCB 103. Figure 2E is an enlarged view of the vicinity of through-hole 104 of PCB 103.

[0018] As shown in FIG. 2A to FIG. 2E, the PCB 103 has a structure in which, for example, a surface GND 109 and a core 110 of the coplanar waveguide are formed on one surface of a plate-like dielectric 108 extending parallel to the xy plane, and a back GND 111 is formed on the other surface of the dielectric 108. The core 110, the surface GND 109, and the back GND 111 are conductors, for example, metals. Here, the coplanar waveguide is a waveguide structured to be composed of a central conductor (hereinafter abbreviated as the central conductor) and two GND planes arranged on both side surfaces of the central conductor with a gap between the central conductor and the xy plane, and the central conductor and the two GND planes are arranged on approximately the same plane. The two GND planes of the coplanar waveguide shown in FIG. 2A and FIG. 2E are formed by the surface GND 109. In the PCB 103 shown in FIG. 2A to FIG. 2E, the core 110 corresponds to the central conductor. In the PCB 103 shown in FIG. 2A to FIG. 2E, a coplanar waveguide is formed by forming the front GND 109 on both sides of the core 110 with a gap in the xy plane. In the example shown in FIG. 2A to FIG. 2E, eight coplanar waveguides are formed in the PCB 103. As shown in FIG. 2D, the PCB 103 is provided with a plurality of through holes 112. These through holes 112 penetrate the dielectric 108 and electrically connect the front GND 109 and the back GND 111. For example, the through holes 112 are fabricated by forming holes that penetrate the dielectric 108, the front GND 109, and the back GND 111, and then plating the inside of the holes with metal. In FIG. 1A and FIG. 1B, the back GND 111 of the PCB 103 is in contact with the base 102. Therefore, the metal base 102, the back surface GND 111 of the PCB 103, the through hole 112 of the PCB 103, and the front surface GND 109 of the PCB 103 are electrically connected. Also, the through hole 104 provided near the center of the PCB 103 has, for example, the same shape as the chip of the superconducting quantum circuit mounted on the sample holder 101, that is, a rectangular or square shape. Also, the area of ​​the through hole 104 is larger than the area of ​​the chip so that the chip can fit inside the through hole 104.

[0019] Next, the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in Figures 1A and 1B is shown in Figures 3A and 3B. Figure 3A is a perspective view showing the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in Figures 1A and 1B. Figure 3B is an end view of the configuration when the chip 107 of the superconducting quantum circuit is mounted on the sample holder 101 shown in Figures 1A and 1B, cut along a plane parallel to the xz plane including the cutting line A-AA shown in Figure 3A. In Figures 3A and 3B, the PCB 103 shown in Figures 2A to 2E is used. 3A and 3B, chip 107 is inserted inside through hole 104 of PCB 103 and placed on base 102, pads of chip 107 and core wire 110 of PCB 103 are electrically connected by bonding wire 113 such as Al (aluminum), and the GND plane of chip 107 and surface GND 109 of PCB are electrically connected by bonding wire 113 such as Al. Note that the pads of chip 107 here refer to terminals for signal input / output formed on chip 107. In the example shown in FIGS. 3A and 3B, the back surface of chip 107 (the lower surface of chip 107 in FIG. 3B) is in contact with metal base 102.

[0020] When a chip 107 is mounted on the sample holder 101 shown in FIG. 1A and FIG. 1B, resonance occurs when a signal of a specific frequency is input to the chip 107. In order to identify the cause of the resonance of this chip mode, a simulation is performed using electromagnetic field analysis software. Here, the simulation is performed using ANSYS (registered trademark) HFSS made by ANSYS Japan Co., Ltd. The same tool is used for the subsequent simulations.

[0021] The chip is shown in FIG. 4A and FIG. 4B. FIG. 4A is a top view of the chip 107 used in the simulation. FIG. 4B is an enlarged view of the tip of the first coplanar waveguide 71. As shown in FIG. 4A, the chip 107 has a rectangular or square shape, and the lengths of each side of the chip 107 are v and w. In the simulation described below, the shape of the chip 107 is a square, and the length of each side of the chip 107 is v=w=5 [mm] (millimeters). In addition, in the chip 107 used in the simulation, a metal film having a thickness of 200 [nm] (nanometers) is laminated on a silicon substrate having a thickness of 380 [μm] (micrometers), and a circuit pattern is formed by removing a predetermined portion of the metal film. In the chip 107 shown in FIG. 4A and FIG. 4B, a first coplanar waveguide 71 and a second coplanar waveguide 72 are formed. The first coplanar waveguide 71 and the second coplanar waveguide 72 have the same shape. The characteristic impedance of the first coplanar waveguide 71 and the second coplanar waveguide 72 are designed to be 50 [Ω] (ohms), and the length is 1 [mm]. FIG. 4B shows an enlarged view of the vicinity of the tip of the first coplanar waveguide 71. As shown in FIG. 4B, the tip of the first coplanar waveguide 71 is not in contact with the GND plane 73. As shown in FIG. 4A, the first coplanar waveguide 71 and the second coplanar waveguide 72 are not connected. Similarly, the tip of the second coplanar waveguide 72 is not in contact with the GND plane 73. One end of the first core wire 74 is connected to the first pad 76, and one end of the second core wire 75 is connected to the second pad 77.

[0022] 5A and 5B show an example in which the chip 107 shown in FIG. 4A and FIG. 4B is mounted on the sample holder 101 shown in FIG. 1A and FIG. 1B. FIG. 5A is a perspective view showing an example in which the chip 107 shown in FIG. 4A and FIG. 4B is mounted on the sample holder 101 shown in FIG. 1A and FIG. 1B. FIG. 5B is an enlarged view of the vicinity of the chip 107. As shown in FIG. 5A and FIG. 5B, the first pad 76 of the chip 107 is electrically connected to the first core 110a of the PCB 103 by an Al bonding wire 113. Also, the second pad 77 of the chip 107 is electrically connected to the second core 110b of the PCB 103 by an Al bonding wire 113, and the GND plane 73 of the chip 107 is electrically connected to the surface GND 109 of the PCB 103 by an Al bonding wire 113. 5A, the end of the first core wire 110a of the PCB 103 other than the end connected to the first pad 76 of the chip 107 is defined as Port1. Meanwhile, the end of the second core wire 110b of the PCB 103 other than the end connected to the second pad 77 of the chip 107 is defined as Port2. In the simulation, for example, when a high-frequency signal is input from Port1, the reflection to Port1 and the transmission to Port2 are calculated. Here, the reflection to Port1 is defined as S11, and the transmission to Port2 is defined as S21.

[0023] 6A and 6B show the simulation results when a high-frequency signal is input from Port1 shown in FIG. 5A. FIG. 6A is an explanatory diagram showing reflection (S11) to Port1 when a high-frequency signal is input from Port1 shown in FIG. 5A. FIG. 6B is an explanatory diagram showing transmission (S21) to Port2 when a high-frequency signal is input from Port1 shown in FIG. 5A. In FIGS. 6A and 6B, the horizontal axis is frequency (unit: GHz (gigahertz)). S11 and S21 on the vertical axis are displayed in decibels (dB). That is, S11 and S21 on the vertical axis are displayed in logarithm. Note that in the following explanation of the simulation results, the horizontal axis is frequency (unit: GHz), and S11 and S21 on the vertical axis are displayed in decibels (dB).

[0024] As shown in FIG. 6A and FIG. 6B, when signals of some specific frequencies are input, S21 becomes very large and S11 becomes very small. As shown in FIG. 4A and FIG. 4B, the first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are not connected. Therefore, even if a signal is input to Port1, it is expected that the signal will not be transmitted to Port2. However, as shown in the simulation result of FIG. 6B, when signals of some specific frequencies are input from Port1, S21 becomes very large. For example, according to the simulation result of FIG. 6B, when a signal of 8.9 [GHz] is input from Port1, S21 is about -1.9 [dB]. That is, about 65% of the energy of the signal input from Port1 is transmitted to Port2. At such a specific frequency where S21 becomes very large, according to the simulation result shown in FIG. 6A, it can be seen that S11 becomes very small.

[0025] From the above, the simulation results shown in Fig. 6A and Fig. 6B reveal the following. That is, in a system in which a superconducting quantum circuit chip 107 is mounted on a sample holder 101 as shown in Fig. 5A and Fig. 5B, the space between the GND plane 73 on the surface of the chip 107 and the metal base 102, i.e., the silicon substrate, forms a cavity resonator. The first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are coupled to this cavity resonator. Therefore, when a signal having a frequency equal to the resonant frequency of this cavity resonator is input to the chip from, for example, Port1, the resonance of the cavity resonator is excited. Then, a standing wave is generated in the silicon substrate, and the energy of the electromagnetic field is accumulated. Since the second coplanar waveguide 72 of the chip 107 is also coupled to this cavity resonator, a part of the energy of the electromagnetic field accumulated in the silicon substrate is transmitted to Port2 through the second coplanar waveguide 72 of the chip 107.

[0026] Such a phenomenon can occur in the system shown in Figures 3A and 3B regardless of the type of circuit formed on chip 107. This phenomenon can occur not only when coplanar waveguides 71 and 72 as shown in Figures 4A and 4B are formed on chip 107, but also when any superconducting quantum circuit is formed on chip 107. In the mounting system shown in Figure 3, the space between GND plane 73 on the surface of chip 107 and metal base 102, i.e., the silicon substrate, forms a cavity resonator, and this resonance is referred to as chip mode resonance in this specification.

[0027] In the simulation results of FIG. 6A and FIG. 6B, some specific frequencies at which S21 becomes very large and S11 becomes very small are referred to as the resonant frequency of the chip mode hereinafter. When a signal having a frequency equal to or close to the resonant frequency of the chip mode is input to the chip 107, the chip mode resonates. According to the simulation results of FIG. 6A and FIG. 6B, in the system shown in FIG. 5A and FIG. 5B, the lowest resonant frequency of the chip mode is 8.9 [GHz]. In the system shown in FIG. 3A and FIG. 3B in which the chip 107 on which the superconducting quantum circuit is formed is mounted on the sample holder 101 shown in FIG. 1A and FIG. 1B, when the chip mode is coupled with the superconducting quantum circuit formed on the chip 107, it causes decoherence of the superconducting quantum circuit. It is known that in order to reduce the effect of this decoherence, it is necessary to make the resonant frequency of the chip mode as high as possible.

[0028] For this reason, there is a demand for technology to increase the resonance frequency of the tip mode. For example, in the comparative sample holder 101, the influence of the tip mode can be reduced by hollowing out a part of the part of the base 102 directly below the tip 107 to form a cavity directly below the tip 107.

[0029] 7A to 7C are enlarged views of the sample holder 101 having a cavity formed in the pedestal 102 near the through hole 104 of the PCB 103. FIG. 7A is a perspective view of the sample holder 101 having a cavity formed in the pedestal. FIG. 7B is a top view of the sample holder 101 having a cavity formed in the pedestal. FIG. 7C is an end view of the sample holder 101 having a cavity formed in the pedestal cut along a plane parallel to the xz plane including the cutting line B-BB shown in FIG. 7B. As shown in FIGS. 7A to 7C, the pedestal 102 has a cavity 105 formed in a portion directly below the through hole 104 of the PCB 103. In other words, as shown in FIGS. 7A to 7C, the pedestal 102 has a cavity 105 formed in a portion directly below the chip 107 when the chip 107 is mounted on the sample holder 101. 7A to 7C, cavity 105 is in the shape of a square prism having a bottom surface with the same area as chip 107. Base 102 has a structure in which pillars 106 remain at the four corners of cavity 105. Pillars 106 are made of, for example, metal. In FIG. 7C, chip 107 is mounted on sample holder 101 with bonding wires 113.

[0030] In Fig. 7A, Fig. 7B, and Fig. 7C, in order to clearly show the pillars 106, the pillars 106 are shown in a pattern different from that of the base 102. The metal pillars 106 at the four corners are integrated with the base 102 and form a part of the base 102. The upper bottom surface of the two bottom surfaces of the metal pillars 106 at the four corners shown in Figs. 7A to 7C contacts the back surface of the chip 107. In Figs. 7A and 7B, the bottom surface of the metal pillars 106 is a right-angled isosceles triangle. As shown in Fig. 7C, the length of the two equal sides of the bottom surface of the pillars 106 is set to 1 [mm] (millimeter), the height of the cavity 105 is set to 3 [mm], and a simulation is performed for the case where the chip 107 of Figs. 4A and 4B is mounted on the sample holder 101 of Fig. 7.

[0031] FIG. 8 is an explanatory diagram showing a simulation result of reflection (S11) to Port1 when a high-frequency signal is input from Port1 shown in FIG. 5A in the case where the chip 107 shown in FIG. 4A and FIG. 4B is mounted on the sample holder 101 shown in FIG. 7A, FIG. 7B, and FIG. 7C by the bonding wire 113. According to the simulation result of FIG. 8, it can be seen that when the chip 107 shown in FIG. 4A and FIG. 4B is mounted on the sample holder 101 in which the cavity 105 of FIG. 7 is formed on the base 102 by the bonding wire 113, the lowest resonance frequency of the chip mode can be increased to 19.9 [GHz]. In the simulation result (FIG. 6A and FIG. 6B) in the case where the cavity 105 is not formed on the base 102, the lowest resonance frequency of the chip mode is 8.9 [GHz]. From this, it can be seen that the resonance frequency of the chip mode can be significantly increased by using the sample holder 101 in which the cavity 105 of FIG. 7A, FIG. 7B, and FIG. 7C is formed on the base 102.

[0032] The reason why the resonant frequency of the chip mode can be increased by forming the cavity 105 in the base 102 is that when the cavity 105 is formed directly under the chip 107, the inside of the cavity resonator formed by the space between the GND plane 73 on the surface of the chip 107 and the base 102 (the bottom of the cavity 105 in this case) is presumed to be silicon (thickness 380 [μm] in the simulation) and vacuum (thickness 3 [mm] in the simulation). This is presumed to be because the effective dielectric constant of the inside of the cavity resonator is lower than when the cavity 105 is not formed in the base 102 (i.e., when the inside of the cavity resonator is almost only silicon). Note that the relative dielectric constant of vacuum is 1, while the relative dielectric constant of silicon is 11.9, which is very high. In addition, the resonant frequency of the cavity resonator generally has the property that the lower the dielectric constant of the medium filling the inside of the cavity resonator, the higher the resonant frequency becomes.

[0033] In this way, by using the sample holder 101 in which the cavity 105 is formed in the base 102, the resonant frequency of the chip mode can be increased. However, in order to reduce the influence of the chip mode on the superconducting quantum circuit, it is required to increase the resonant frequency of the chip mode as much as possible. In addition, it is predicted that, when the number of quantum bits integrated in the chip 107 increases toward the practical application of quantum computers, the chip 107 with an area larger than 5 [mm] × 5 [mm] will be required. The larger the area of ​​the chip 107, the lower the resonant frequency of the chip mode. This is because, as the area of ​​the chip 107 increases, the dimensions of the bottom surface of the cavity resonator formed by the space sandwiched between the GND plane 73 on the surface of the chip 107 and the base 102 become larger. Therefore, even if the sample holder 101 in which the cavity 105 is formed in the base 102 as shown in Figures 7A to 7C is used, it is predicted that the larger the area of ​​the chip 107, the lower the resonant frequency of the chip mode and the greater the influence on the quantum circuit. In view of the above, there is a need to develop a technique that can make the resonance frequency of the tip mode as high as possible, compared to the case where sample holder 101 having cavity 105 formed in base 102 is used.

[0034] Therefore, various embodiments that can increase the resonant frequency of the chip mode will be described.

[0035] First Embodiment In the first embodiment, the sample holder includes a pedestal and a PCB in contact with the pedestal. In the first embodiment, an example is described in which the PCB has a dielectric, a front GND formed on the front surface of the dielectric, a back GND formed on the back surface of the dielectric, and a through hole penetrating from the front GND to the back GND in which the chip is stored. Furthermore, in the first embodiment, at least a part of the pedestal below the through hole has a cavity, and the cavity has a support structure that supports the surface of the chip and is conductive to the pedestal. Here, the first embodiment is characterized in that at least a part of the part of the support structure that supports the chip is not parallel to the back surface of the chip. In particular, in the first embodiment, an example is described in which a pillar is used as the support structure.

[0036] 9 is an explanatory diagram showing a sample holder according to the first embodiment. As shown in FIG. 9, the sample holder 1 of the first embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2. A through hole 4 penetrating the PCB 3 is provided near the center of the PCB 3. The shape of the pedestal 2 is not particularly limited. For example, the shape of the pedestal 2 may be a rectangular parallelepiped or a cube. The sample holder 1 has a cavity 5 in a portion of the pedestal 2 directly below the through hole 4 of the PCB 3.

[0037] By aligning the height of the circuit surface of the chip and the height of the surface of the PCB3 as much as possible, wire bonding can be easily performed and the bonding wire can be shortened. The shorter the bonding wire, the better the electrical characteristics. Furthermore, by forming a through hole 4 in the PCB3, the resonance frequency of the chip mode can be increased. If a dielectric or conductor is present on the back surface of the chip (the surface opposite to the circuit surface), the resonance frequency of the chip mode will decrease. Therefore, in order to increase the resonance frequency of the chip mode, the back surface of the chip is made to contact vacuum as much as possible. If the through hole 4 is not formed in the PCB3 and the chip is placed on the PCB3, the dielectric or conductor of the PCB3 will come into contact with the back surface of the chip, so that the resonance frequency of the chip mode cannot be increased. Therefore, in the first embodiment, a through hole 4 is formed in the PCB3, the chip is placed in the through hole 4, and a cavity 5 is formed in the pedestal 2 directly below the chip, so that the largest possible area of ​​the back surface of the chip is in contact with vacuum.

[0038] 10A to 10C are enlarged views of the vicinity of the through-hole 4 of the PCB 3 of the sample holder 1 of the first embodiment. FIG. 10A is a perspective view showing the sample holder 1 of the first embodiment. FIG. 10B is a top view of the sample holder 1 of the first embodiment. FIG. 10C is an end view of the sample holder 1 of the first embodiment cut along a plane parallel to the xz plane including the cutting line C-CC shown in FIG. 10B. In FIG. 10C, a chip 7 is mounted on the sample holder 1 of the first embodiment with a bonding wire 13.

[0039] The sample holder 1 has a cavity 5 in at least a part of the base 2 below the through hole 4. In Figs. 10A to 10C, the sample holder 1 has a cavity 5 in a part of the base 2 directly below the through hole 4 of the PCB 3. In other words, in Figs. 10A to 10C, the sample holder 1 has a cavity 5 in a part of the base 2 directly below the chip 7 when the chip 7 is mounted on the sample holder 1 with a bonding wire 13. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be flat or may be other than flat. The side surface of the cavity 5 may be flat or may be other than flat. For example, the side surface or the bottom surface of the cavity 5 may have a depression. In Figs. 10A to 10C, the cavity 5 has a shape of a quadrangular prism. 10A to 10C, the cavity 5 has a rectangular base with sides of lengths a and b, and a shape of a rectangular prism with a height of d. Furthermore, the cavity 5 has a support structure that supports the surface of the chip 7 and is conductive to the base. The material of the support structure is, for example, a metal. Specifically, the material of the support structure may be a mixture containing a metal, such as a resin mixed with metal particles or a filler.

[0040] The shape of the support structure is not particularly limited. For example, in Fig. 10A to Fig. 10C, the support structure may be a pillar 6. Although not shown, the support structure may be, for example, a protrusion extending from the side surface of the cavity 5. Alternatively, although not shown, the support structure may be, for example, three non-linear supports. Alternatively, although not shown, the support structure may be a structure extending from the bottom surface of the cavity 5 like a pin holder.

[0041] Here, the support structure will be described by taking pillars 6 shown in Fig. 10A to Fig. 10C as an example. The number of pillars 6 and the shape of the pillars 6 are not particularly limited. This also applies to the following embodiments. In Fig. 10A to Fig. 10C, a plurality of pillars 6 are provided in a cavity 5. More specifically, the pillars 6, which are conductive materials, are arranged at the four corners of the cavity 5.

[0042] In Fig. 10A to Fig. 10C, the pillars 6 are shown in a different pattern from the base 2 in order to clearly show the pillars 6. The cavity 5 in Fig. 10A to Fig. 10C has the same structure as the cavity 105 shown in Fig. 7A to Fig. 7C. That is, the lower base of the pillars 6 at the four corners is in the shape of a right-angled isosceles triangle. The length of two equal sides (equal sides) of the lower base of the pillars 6 is s. The height of the pillars 6 is d. The conductive pillars 6 at the four corners are in electrical contact with the base 2. The four conductive pillars 6 shown in Fig. 10A to Fig. 10C may be separate from the base 2. Alternatively, the pillars 6 shown in Fig. 10A to Fig. 10C may be made of the same material as the base 2. That is, the base 2 and the pillars 6 may be integrated.

[0043] Here, the effect of using the pillars 6 will be described. If the pillars 6 are not present, there is a concern that the chip 7 will fall into the cavity 5. The chip 7 and the PCB 3 are connected by bonding wires. Therefore, even if the pillars 6 are not present, the chip 7 may not fall into the cavity 5. However, the chip 7 may fall into the cavity 5 due to vibration or the like, or some of the bonding wires may come off, causing the chip 7 to fall into the cavity 5. Therefore, by providing the metal pillars 6, the chip 7 can be prevented from falling into the cavity 5 and the bonding wires can be prevented from coming off. In addition, the metal pillars 6 can strengthen the thermal path between the chip 7 and the base 2. The chip 7 of the superconducting quantum circuit is cooled to about 10 [mK] (millikelvin) by a refrigerator and operated, and the base 2 is generally in thermal contact with the cold stage (the coldest part) of the refrigerator. That is, the base 2 becomes a very low temperature. The stronger the thermal path between the base 2 and the chip 7, in other words, the smaller the thermal resistance between the base 2 and the chip 7, the better the chip 7 cools. If the chip 7 is not cooled well, it is not possible to bring out the best performance of the quantum circuit formed on the chip 7, so it is desirable to cool the chip 7 to the lowest possible temperature. Therefore, it is preferable that the thermal resistance between the base 2 and the chip 7 is as small as possible. The metal pillar 6 can reduce the thermal resistance between the base 2 and the chip 7.

[0044] 7A to 7C is that in this embodiment, at least a part of the upper surface of the pillars 6 at the four corners, i.e., the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, is not parallel to the back surface of the chip 7. In other words, in this embodiment, at least a part of the upper surface of the pillars 6 at the four corners is not parallel to the upper surface of the base 2.

[0045] In FIG. 10C, the column 6 used in the sample holder 1 of this embodiment has a structure in which an upper part 61 and a lower part 62 are connected. The lower part 62 has a columnar shape. The lower part 62 has a prism shape. In FIGS. 10A to 10C, the lower part 62 has a triangular prism shape, and the bottom surface of the lower part 62 has a right-angled isosceles triangle shape. The length of the two equal sides of the bottom surface is s, and the height of the lower part 62 is d1. The upper part 61 has a frustum shape. The bottom surface with the narrower area of ​​the frustum is on the through-hole 4 side. In FIGS. 10A to 10C, the upper part 61 has a triangular pyramid shape, and the bottom surface of the upper part 61 has a right-angled isosceles triangle shape, and the height of the upper part 61 is d2. Here, d1+d2=d. For example, the bottom surface of the upper part 61 and the bottom surface of the lower part 62 have the same shape and dimensions. In this structure, when a chip 7 is mounted on the sample holder 1, at least a portion of each of the pillars 6 at the four corners contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the conductive pillars 6 can be reduced more than in the sample holder 101 shown in Figures 7A to 7C.

[0046] Fig. 11A is a top view of the PCB 3 used in the sample holder 1 of the first embodiment. Fig. 11B is a bottom view of the PCB 3 used in the sample holder 1 of the first embodiment. Fig. 11C is a side view of the PCB 3 used in the sample holder 1 of the first embodiment. Fig. 11D is a perspective view of the PCB 3 used in the sample holder 1 of the first embodiment. Fig. 11E is an enlarged view of the vicinity of the through-hole 4 of the PCB 3 used in the sample holder 1 of the first embodiment.

[0047] As shown in FIG. 11A and FIG. 11E, the PCB 3 has a plate-shaped dielectric 8 extending parallel to the xy plane. The PCB 3 has a structure in which a front GND 9 and a core 10 of a coplanar waveguide are formed on one surface (front surface) of the dielectric 8. The PCB 3 has a structure in which a back GND 11 is formed on the other surface (back surface) of the dielectric 8. The core 10, the front GND 9, and the back GND 11 are conductors, for example, metals. Examples of the metal include Cu (copper) and Cu plated with Au (gold). In FIG. 11A, eight coplanar waveguides are formed in the PCB 3. The coplanar waveguides are as described in FIG. 2A. However, the number of coplanar waveguides formed in the PCB 3 is not particularly limited and may be any number. Note that, as shown in FIG. 11D, the PCB 3 is provided with a plurality of through holes 12. These through holes 12 penetrate the dielectric 8 and electrically connect the front surface GND 9 and the back surface GND 11. The through holes 12 are produced, for example, by forming holes penetrating the dielectric 8, the front surface GND 9, and the back surface GND 11, and then plating the inside of the holes with metal.

[0048] In FIG. 9, the back surface GND 11 of the PCB 3 is in contact with the pedestal 2. Therefore, the metallic pedestal 2, the back surface GND 11 of the PCB 3, the through hole 12 of the PCB 3, and the front surface GND 9 of the PCB 3 are electrically connected. In addition, a through hole 4 is provided near the center of the PCB 3. This through hole 4 may be, for example, the same shape as the chip 7 of the superconducting quantum circuit mounted on the sample holder 1, that is, a rectangular or square shape. In addition, the area of ​​the through hole 4 is larger than the area of ​​the chip 7 so that the chip 7 can fit inside the through hole 4.

[0049] FIG. 12 shows a simulation result of S11 in a system in which a chip 7 is mounted on the sample holder 1 of the first embodiment shown in FIG. 9 with a bonding wire 13. Here, S11 is the reflection to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 11A, as described above. FIG. 12 is an explanatory diagram showing a simulation result of S11 in a case in which a chip 7 is mounted on the sample holder 1 according to the first embodiment with a bonding wire 13. In the simulation in FIG. 12, a=5[mm], b=5[mm], d=3[mm], d1=2[mm], d2=1[mm], and s=1[mm].

[0050] As shown in Fig. 12, the lowest resonance frequency in the chip mode is 21.5 [GHz]. Therefore, as shown in Fig. 12, the lowest resonance frequency in the chip mode can be made higher than the simulation result shown in Fig. 8, which is obtained by simulating using the sample holder 101 shown in Figs. 7A to 7C.

[0051] The reason why the resonant frequency of the chip mode can be increased by using the sample holder 1 of the first embodiment is considered to be as follows. In the example of the sample holder 101 shown in FIG. 7A to FIG. 7C, the electric field of the standing wave generated when the resonance of the chip mode occurs spreads mainly in the silicon substrate and in the cavity 105 (vacuum) provided in the pedestal 2. In the part directly above the pillars 106 at the four corners, the space between the GND plane 73 on the surface of the chip 107 and the pillars 106 is only silicon, and the electric field cannot spread in the vacuum, so the effective dielectric constant is high in the part directly above the pillars 106 at the four corners. In contrast, in the case of the sample holder 1 of the first embodiment, at least a part of the upper surface of the pillars 6 at the four corners is not parallel to the back surface of the chip 7. As a result, in the part directly above the pillars 6 at the four corners, the space between the GND plane 73 on the surface of the chip 7 and the pillars 6 becomes silicon and vacuum, so that the electric field can spread in the vacuum in this part. For this reason, it is considered that the effective dielectric constant in the portion directly above the pillars 6 at the four corners is lower than that of the sample holder 101 shown in FIG. 7A to FIG. 7C. As another example of the first embodiment, FIG. 13A to FIG. 13C show a case where the thickness s of the pillars 6 at the four corners is larger than that of FIG. 10A to FIG. 10C. FIG. 13A is a perspective view of the sample holder 1 according to another example of the first embodiment. FIG. 13B is a top view of the sample holder 1 according to another example of the first embodiment. FIG. 13C is an end view of the sample holder 1 according to another example of the first embodiment cut by a plane parallel to the xz plane including the cutting line D-DD shown in FIG. 13B. In FIG. 13C, a chip 7 is mounted on the sample holder 1 according to another example of the first embodiment.

[0052] FIG. 14 shows the results of a simulation of S11 in which a chip 7 is mounted with bonding wires 13 on a sample holder 1 using a base 2 having a cavity 5 formed therein as shown in FIGS. 13A to 13C. FIG. 14 is an explanatory diagram showing a simulation result of S11 according to another example of the first embodiment. In the simulation, a=5[mm], b=5[mm], d=3[mm], d1=0.5[mm], d2=2.5[mm], and s=2.5[mm]. As shown in FIG. 14, the lowest resonance frequency of the chip mode is 21.5[GHz]. As shown in FIG. 14, the lowest resonance frequency of the chip mode can be made higher than the simulation result shown in FIG. 8, which is obtained by simulating using the sample holder 101 shown in FIG. 7A to FIG. 7C.

[0053] [Modification of the first embodiment] In a modified example of the first embodiment, a portion of the upper surface of the upper portion 61 of the pillars 6 at the four corners of the cavity 5, i.e., the surface that faces the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 with bonding wires 13, is not parallel to the back surface of the chip 7, but a portion of it is parallel to the back surface of the chip 7.

[0054] FIG. 15A is a perspective view of the sample holder 1 according to the modified example of the first embodiment. FIG. 15B is a top view of the sample holder 1 according to the modified example of the first embodiment. FIG. 15C is an end view of the sample holder 1 according to the modified example of the first embodiment cut along a plane parallel to the xz plane including the cutting line E-EE shown in FIG. 15B. In FIGS. 15A to 15C, the upper surfaces of the upper portions 61 of the pillars 6 at the four corners of the cavity 5, that is, the surfaces of the pedestal 2 forming the cavity 5 when the chip 7 is mounted on the sample holder 1 with the bonding wires 13, facing the back surface of the chip 7, are not parallel to the back surface of the chip 7, but are partially parallel to the back surface of the chip 7. In other words, at least a part of the upper surfaces of the upper portions 61 of the pillars 6 at the four corners are not parallel to the upper surface of the pedestal 2, but are partially parallel to the upper surface of the pedestal 2. The lower portion 62 of the pillar 6 has the shape of a triangular prism, as in the cases of Figures 10A to 10C and 13A to 13C, and the base of the lower portion 62 is a right-angled isosceles triangle with the length of two equal sides being s1.

[0055] On the other hand, the upper part 61 of the pillar 6 has a shape of a triangular pyramid, the lower base of the upper part 61 is a right-angled isosceles triangle, and the length of the two equal sides is s1, while the upper base of the upper part 61 is a right-angled isosceles triangle, and the length of the two equal sides is s2. Here, s1>s2. The height of the lower part 62 of the pillar 6 is d1, and the height of the upper part 61 is d2. In this structure, when the chip 7 is mounted on the sample holder 1, at least a part of the pillars 6 at the four corners contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the conductive pillars 6 can be reduced more than that of the sample holder 101 shown in Figures 7A to 7C. However, the sample holder 1 shown in Figures 15A to 15C has a larger contact area between the back surface of the chip 7 and the conductive pillars 6 than those in Figures 10A to 10C and Figures 13A to 13C.

[0056] FIG. 16 is an explanatory diagram showing a simulation result of S11 when the chip 7 is mounted on the sample holder 1 using the pedestal 2 with the cavity 5 formed in FIG. 15A to FIG. 15C. In the simulation, a=5[mm], b=5[mm], d=3[mm], d1=2[mm], d2=1[mm], s1=1[mm], and s2=0.5[mm]. As shown in FIG. 16, the lowest resonance frequency of the chip mode is 21.2[GHz]. As shown in FIG. 16, according to the modification of the first embodiment, the lowest resonance frequency of the chip mode can be made higher than the simulation result shown in FIG. 8 which is simulated using the sample holder 101 shown in FIG. 7A to FIG. 7C. In this way, in the first embodiment, even if a part of the upper surface of the upper part 61 of the pillar 6 at the four corners is parallel to the back surface of the chip 7, the effect of being able to make it higher than the simulation result shown in FIG. 8 which is simulated using the sample holder 101 shown in FIG. 7A to FIG. 7C can be obtained.

[0057] In the first embodiment and its modifications, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape. Let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, in the cavities 5 shown in FIGS. 10A to 10C, FIGS. 13A to 13C, and FIGS. 15A to 15C, it is preferable that a < b, and it is preferable that a is equal to or greater than v and b is equal to or greater than w. If this is not the case, the contact area between the back surface of the chip 7 and the pedestal 2 may increase, and the resonance frequency of the chip mode may decrease. Also, in this case, the through hole 4 of the PCB 3 used in the first embodiment and its modifications is preferably rectangular. When the length of the short side of the through hole 4 of the PCB 3 is x1 and the length of the long side of the through hole 4 is y1, since the chip 7 must enter the inside of the through hole 4, it is necessary that v < x1 and w < y1. And since the resonance frequency of the chip mode can be increased as x1 and y1 are shorter, it is preferable that x1 is equal to or less than 1.2v, and more preferably equal to or less than 1.1v. For the same reason, it is preferable that b is equal to or less than 1.2w, and more preferably equal to or less than 1.1w.

[0058] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, in the cavities 5 shown in FIGS. 10A to 10C, FIGS. 13A to 13C, and FIGS. 15A to 15C, it is preferable that a = b, and it is preferable that a is equal to or greater than v. Also, in this case, the through hole 4 of the PCB 3 used in the first embodiment and its modifications is preferably square. When the length of one side of the through hole 4 of the PCB 3 is x1, since the chip 7 must enter the inside of the through hole 4, it is necessary that v < x1. And since the resonance frequency of the chip mode can be increased as x1 is shorter, it is preferable that x1 is equal to or less than 1.2v, and more preferably equal to or less than 1.1v.

[0059] Also, according to the simulation, the higher the height d of the cavity 5, the higher the resonance frequency of the chip mode. However, when d is increased to a certain extent, further increasing d hardly changes the resonance frequency of the chip mode. Therefore, in the first embodiment, when the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavity 5 shown in FIGS. 10A to 10C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more. Also, in the first embodiment and its modification, if d2 is greater than 0, it has the effect of increasing the resonance frequency of the chip mode. Therefore, d2 is preferably greater than 0 and less than or equal to d. When d2 = d, d1 = 0, and in that case, the column 6 is composed of only the upper part 61. Also, in the first embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, s is preferably 0.1v or more and 0.5v or less. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, s is preferably 0.1v or more and 0.5v or less. Similarly, in the modification of the first embodiment, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, s1 is preferably 0.1v or more and 0.5v or less. Also, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, s1 is preferably 0.1v or more and 0.5v or less. In the modification of the first embodiment, s2 only needs to satisfy s2 < s1. Also, in the first embodiment and its modification, if d2 is greater than 0, it has the effect of increasing the resonance frequency of the chip mode. Therefore, d2 is preferably greater than 0 and less than or equal to d. When d2 = d, d1 = 0, and in that case, the column 6 is composed of only the upper part 61.

[0060] In the first embodiment and its modified examples, the shape of the lower part 62 of the pillar 6 is a triangular prism whose base is a right-angled isosceles triangle, and the shape of the upper part 61 is a triangular pyramid, but the shapes of the lower part 62 and the upper part 61 of the pillar 6 are not particularly limited. As long as at least a part of the upper surface of the upper part 61, i.e., the surface of the upper part 61 facing the back surface of the chip 7, is not parallel to the back surface of the chip 7 or the upper surface of the base 2, the effects described in the first embodiment and its modified examples can be achieved.

[0061] Second Embodiment The second embodiment will be described in detail with reference to the drawings. Below, the description of the second embodiment will be omitted to the extent that the description of the second embodiment is not unclear.

[0062] The sample holder 1 of the second embodiment has a configuration in which the PCB 3 is placed on the metal pedestal 2 as shown in FIG. 9. In the second embodiment, the PCB 3 shown in FIG. 11A to FIG. 11E is used as in the first embodiment. In the second embodiment, the sample holder 1 has a cavity 5 in the portion of the pedestal 2 directly below the through hole 4 of the PCB 3. In other words, the sample holder 1 has a cavity 5 in the portion of the pedestal 2 directly below the chip 7 when the chip 7 is mounted on the sample holder 1. In the second embodiment, the cavity 5 has a shape that combines a pillar and a frustum, and the bottom surface of the frustum with a smaller area and the bottom surface of the upper side of the pillar have the same shape. For example, the bottom surface of the frustum with a larger area is the through hole 4 side. As an example of the frustum of the cavity 5, a pyramid truncated pyramid will be described. As an example of the pillar of the cavity 5, a pillar will be described.

[0063] The sample holder 1 according to the second embodiment is shown in Fig. 17A to Fig. 17C. Fig. 17A is a perspective view of the sample holder 1 according to the second embodiment. Fig. 17B is a top view of the sample holder 1 according to the second embodiment. Fig. 17C is an end view of the sample holder 1 according to the second embodiment cut along a plane parallel to the xz plane including the cutting line F-FF shown in Fig. 17B. In Fig. 17C, a chip 7 is mounted on the sample holder 1 according to the second embodiment with a bonding wire 13.

[0064] As shown in FIGS. 17B and 17C, in the second embodiment, the cavity 5 formed in the pedestal 2 has a structure in which a prism portion 51 that is a prism and a frustum portion 52 that is a frustum of a pyramid are connected. In FIGS. 17B and 17C, the bottom surface of the prism portion 51 and the smaller bottom surface of the frustum portion 52 in terms of area are connected. For this reason, the bottom surface of the prism portion 51 and the smaller bottom surface of the frustum portion 52 in terms of area have the same shape and the same area. Also, the larger bottom surface of the frustum portion 52 is on the side of the through hole 4.

[0065] In FIGS. 17A to 17C, the prism portion 51 has a bottom surface that is a quadrilateral with side lengths a1 and b1 for each side, and has a shape of a quadrangular prism with a height of d1. In FIGS. 17A to 17C, the frustum portion 52 is a frustum of a square pyramid.

[0066] Here, for example, the lengths of the sides of the chip 7 and the prism portion 51 in the case where the chip 7 mounted on the sample holder 1 has a rectangular shape will be described. When the length of the short side of the chip 7 is v and the length of the long side of the chip 7 is w, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0067] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0068] In FIGS. 17A to 17C, the frustum portion 52 has a shape of a quadrilateral with side lengths a1 and b1 for the smaller bottom surface among the two bottom surfaces in terms of area. In FIGS. 17A to 17C, the frustum portion 52 has a shape of a quadrilateral with side lengths a2 and b2 for the larger bottom surface in terms of area.

[0069] Here, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, where the length of the short side of the chip 7 is v and the length of the long side of the chip 7 is w. In such a case, in the frustum of a pyramid portion 52, it is preferable that a2 < b2, and a2 is preferably not less than v and not more than 1.5v, and b2 is preferably not less than w and not more than 1.5w.

[0070] On the other hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, in the frustum of a pyramid portion 52, it is preferable that a2 = b2, and a2 is preferably not less than v and not more than 1.5v. Also, the height of the frustum of a pyramid portion 52 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum of a pyramid portion 52 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum of a pyramid portion 52 are the same surface. Here, the lower bottom surface of the frustum of a pyramid portion 52 is the bottom surface with the smaller area among the two bottom surfaces of the frustum of a pyramid portion 52.

[0071] The feature of the sample holder 1 of the second embodiment is that by providing the frustum of a pyramid portion 52 above the cavity 5, when the chip 7 is mounted on the sample holder 1, at least a part of the surface of the pedestal 2 facing the back surface of the chip 7 is not parallel to the back surface of the chip 7. In FIGS. 17A to 17C, this part is the side surface of the frustum of a pyramid portion 52. As shown in FIG. 17C, let the angle formed by the side surface of the frustum of a pyramid portion 52, that is, the part of the surface facing the back surface of the chip 7 that is not parallel to the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1, and the back surface of the chip 7 be θ. In other words, let the angle formed by the side surface of the frustum of a pyramid portion 52 and the upper surface of the pedestal 2 be θ. θ is, for example, in the range such that a part of the side surface of the frustum of a pyramid portion 52 that is not parallel to the back surface of the chip 7 can be formed. For example, θ is less than 90 degrees. In the structure of the sample holder 1 of the second embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the pedestal 2 contacts the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the pedestal 2 can be reduced compared to the sample holder 101 shown in FIGS. 7A to 7C.

[0072] Fig. 18 is an explanatory diagram showing a simulation result of S11 when a chip 7 is mounted on a sample holder 1 according to the second embodiment with a bonding wire 13. In the simulation in Fig. 18, a1 = 4 [mm], b1 = 4 [mm], d1 = 2.5 [mm], a2 = 5 [mm], b2 = 5 [mm], and d2 = 0.5 [mm]. In this case, θ is 45 degrees. As shown in Fig. 18, the lowest resonance frequency of the chip mode can be increased to 20.8 [GHz].

[0073] Thus, the sample holder 1 of the second embodiment has an effect of being able to make the resonance frequency of the chip mode higher than the simulation result shown in FIG. 8, which was obtained by simulating the sample holder 101 shown in FIG. 7A to FIG. 7C. The reason why the resonance frequency of the chip mode in the second embodiment can be made higher than the simulation result shown in FIG. 8, which was obtained by simulating the sample holder 101 shown in FIG. 7A to FIG. 7C, will be explained. In the case of the sample holder 101 shown in FIG. 7A to FIG. 7C, the electric field of the standing wave generated when the resonance of the chip mode occurs spreads mainly in the silicon substrate and in the cavity 105 (vacuum) provided in the pedestal 102, but in the parts directly above the pillars 106 at the four corners, in other words, in the four corners of the chip 107, the space between the GND plane 73 on the surface of the chip 107 and the pillars 106 is only silicon, and the electric field cannot spread into the vacuum. For this reason, the effective dielectric constant is high in the four corners of the chip 107. In contrast to this, in the case of this embodiment, by providing the truncated pyramidal portion 52 in the cavity 5, the space between the GND plane 73 on the surface of the chip 7 and the base 2 becomes a vacuum with silicon even at the four corners of the chip 7. For this reason, it is believed that the effective dielectric constant at the four corners of the chip 7 becomes lower than that of the sample holder 101 shown in Figures 7A to 7C because the electric field can spread in the vacuum in this portion.

[0074] [Modification of the second embodiment] As a modification of the second embodiment, the sample holder 1 in which the prism portion 51 of the cavity 5 is eliminated and only the pyramid frustum portion 52 is provided is shown in Figs. 19A to 19C. Fig. 19A is a perspective view of the sample holder 1 according to the modification of the second embodiment. Fig. 19B is a top view of the sample holder 1 according to the modification of the second embodiment. Fig. 19C is an end view of the sample holder 1 according to the modification of the second embodiment cut along a plane parallel to the xz plane including the cutting line G-GG shown in Fig. 19B. In Fig. 19C, the chip 7 according to the modification of the second embodiment is mounted with a bonding wire 13. As shown in Figs. 19A to 19C, the cavity 5 does not have the prism portion 51, but has the pyramid frustum portion 52. In Figs. 19A to 19C, the pyramid frustum portion 52 is a quadrangular pyramid frustum. In addition, θ is, for example, in a range in which the side of the pyramid frustum portion 52 is not parallel to the back surface of the chip 7. For example, in the case of a truncated square pyramid, θ is less than 90 degrees.

[0075] FIG. 20 is an explanatory diagram showing a simulation result of S11 when a chip 7 is mounted by a bonding wire 13 on a sample holder 1 using a base 2 having a cavity 5 shown in FIG. 19A to FIG. 19C. In the simulation in FIG. 20, a1=2[mm], b1=2[mm], a2=5[mm], b2=5[mm], d1=0[mm], and d2=5[mm]. In this case, θ is about 73.3 degrees. As shown in FIG. 20, the lowest resonance frequency of the chip mode is 21.4[GHz]. As shown in FIG. 20, the lowest resonance frequency of the chip mode can be made higher than the simulation result of FIG. 8 using the sample holder 101 shown in FIG. 7A to FIG. 7C.

[0076] In the second embodiment and its variations, if the thickness of the chip 7 mounted on the sample holder 1 is t, then the height d1+d2 of the cavity 5 in Figures 17A to 17C and Figures 19A to 19C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0077] In the second embodiment and its modified examples, if d2 is greater than 0, it has the effect of increasing the resonant frequency of the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or greater. When d1=0, the cavity 5 is composed of only the truncated pyramidal portion 52.

[0078] In the second embodiment and its modified examples, the cavity 5 has a structure in which the prism portion 51 and the pyramid frustum portion 52 are connected, or a structure consisting of only the pyramid frustum portion 52. However, the pyramid frustum portion 52 does not have to have a pyramid frustum shape. For example, the side surface of the pyramid frustum portion 52 may be a curved surface instead of a flat surface. In other words, the effect described in the second embodiment and its modified examples can be achieved as long as at least a part of the surface of the base 2 forming the cavity 5 that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7 or the upper surface of the base 2. In addition, instead of the pyramid frustum shape of the pyramid frustum portion 52, a pyramid shape may be used. Therefore, the cavity 5 may have a structure in which the prism portion 51 and the pyramid portion are connected, or a structure consisting of only the pyramid portion.

[0079] Third embodiment The third embodiment will be described in detail with reference to the drawings. Below, the description of the third embodiment will be omitted to the extent that the description will not be unclear.

[0080] The sample holder 1 of the third embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2 as shown in FIG. 9. In the third embodiment, the PCB 3 having the structure shown in FIGS. 11A to 11E, which is the same as that of the first embodiment, is used. And in the third embodiment, the sample holder 1 has a cavity 5 in a portion of the pedestal 2 that corresponds directly below the through hole 4 of the PCB 3, in other words, in a portion that corresponds directly below the chip 7 when the chip 7 is mounted on the sample holder 1. The cavity 5 has a shape that combines a prism and a frustum of a pyramid, similar to the second embodiment, and is a shape in which the smaller bottom surface of the frustum of the pyramid and the upper bottom surface of the prism are connected. Further, in the third embodiment, unlike the second embodiment, the frustum of the pyramid may be deformed. Thereby, in the third embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the surface of the pedestal 2 that forms the cavity 5 and faces the back surface of the chip 7 is not parallel to the back surface of the chip 7.

[0081] FIG. 21A is a perspective view of the sample holder of the third embodiment. FIG. 21B is a top view of the sample holder of the third embodiment. FIG. 21C is a cross-sectional view of the sample holder 1 of the third embodiment cut along a plane parallel to the xz plane including the cutting line H-HH shown in FIG. 21B. In FIG. 21C, the chip 7 is mounted on the sample holder 1 according to the third embodiment with bonding wires 13. As shown in FIGS. 21A to 21C, the cavity 5 formed in the pedestal 2 in the third embodiment has a structure connecting a prism portion 51 and a frustum of a pyramid deformed portion 53.

[0082] The prism portion 51 has a bottom surface in the shape of a quadrilateral with side lengths a1 and b1 for each side, and has the shape of a quadrangular prism with a height of d1.

[0083] Here, for example, the chip 7 mounted on the sample holder 1 has a rectangular shape, and let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a1 < b1 in the prism portion 51, and it is preferable that a1 is smaller than v and b1 is smaller than w.

[0084] On the one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a1 = b1 in the prism portion 51, and it is preferable that a1 is smaller than v.

[0085] The frustum pyramid deformation part 53 has a shape of a quadrangle with the shorter bottom surface of the two bottom surfaces having side lengths of a1 and b1, and the larger bottom surface has a shape of an octagon with the four corners of the quadrangle with side lengths of a2 and b2 cut diagonally.

[0086] Here, for example, when the chip 7 mounted on the sample holder 1 has a rectangular shape, let the length of the short side of the chip 7 be v and the length of the long side of the chip 7 be w. In such a case, it is preferable that a2 < b2 in the frustum pyramid deformation part 53, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v, and b2 is equal to or greater than w and equal to or less than 1.5w.

[0087] On the one hand, when the chip 7 mounted on the sample holder 1 has a square shape and the length of one side of the chip 7 is v, it is preferable that a2 = b2 in the frustum pyramid deformation part 53, and it is preferable that a2 is equal to or greater than v and equal to or less than 1.5v.

[0088] Also, the height of the frustum pyramid deformation part 53 is d2. The cavity 5 formed in the pedestal 2 of the sample holder 1 of the present embodiment has a structure in which the frustum pyramid deformation part 53 is connected on the prism portion 51, and the upper bottom surface of the prism portion 51 and the lower bottom surface of the frustum pyramid deformation part 53 are the same plane. Here, the lower bottom surface of the frustum pyramid deformation part 53 is the smaller bottom surface of the two bottom surfaces of the frustum pyramid deformation part 53. To more accurately explain the shape of the cavity 5 in FIGS. 21A to 21C of the present embodiment, FIGS. 22A to 22C and FIGS. 23A to 23C will be used for explanation.

[0089] Fig. 22A is a perspective view showing a first shape example of the cavity 5 of the sample holder 1 of the third embodiment. Fig. 22B is a top view showing a first shape example of the cavity 5 of the sample holder 1 of the third embodiment. Fig. 22C is an end view of the cavity 5 of the sample holder 1 in the first shape example of the cavity 5 of the sample holder 1 of the third embodiment, cut along a plane parallel to the xz plane including the cutting line I-II shown in Fig. 22B. In Fig. 22C, a chip 7 is mounted on the sample holder 1 according to the second embodiment with a bonding wire 13.

[0090] Fig. 23A is a perspective view showing a second shape example of the cavity 5 of the sample holder 1 of the third embodiment. Fig. 23B is a top view showing a second shape example of the cavity 5 of the sample holder 1 of the third embodiment. Fig. 23C is a cross-sectional view of the sample holder 1 in the second shape example of the cavity 5 of the sample holder 1 of the third embodiment, cut along a plane parallel to the xz plane including the cutting line J-JJ shown in Fig. 23B. In Fig. 23C, a chip 7 is mounted on the sample holder 1 according to the third embodiment with a bonding wire 13.

[0091] The cavity 5 shown in Figs. 22A to 22C has the same structure as the cavity 5 shown in Figs. 17A to 17C of the second embodiment. That is, the cavity 5 shown in Figs. 22A to 22C has a configuration in which a prism portion 51 and a truncated pyramid portion 52 are connected. In the third embodiment, four conductive pillars 6 shown in Figs. 23A to 23C are added to the four corners of the cavity 5 shown in Figs. 22A to 22C similar to the second embodiment. Thereby, the cavity 5 having the structure shown in Figs. 21A to 21C can be formed in the base 2. As shown in Figs. 23A to 23C, in this embodiment, the conductive pillars 6 at the four corners are triangular pillars, and the base of the triangular pillar has a shape of a right-angled isosceles triangle, the length of the two equal sides of the base is s, and the height of the triangular pillar is d1+d2. The conductive pillars 6 at the four corners are in electrical contact with the base 2. The four conductive pillars 6 shown in Figures 23A to 23C may be separate from the base 2, or may be made of the same material as the base 2, that is, the base 2 and the four pillars 6 may be integrated.

[0092] The feature of the sample holder 1 of the third embodiment is that, by providing the truncated pyramid deformation portion 53 on the upper side of the cavity 5, at least a part of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 with the bonding wire 13 is not parallel to the back surface of the chip 7. As shown in FIG. 21C, the angle between the side surface of the truncated pyramid deformation portion 53, that is, the part of the surface facing the back surface of the chip 7 when the chip 7 is mounted on the sample holder 1 that is not parallel to the back surface of the chip 7, and the back surface of the chip 7 is θ. In other words, the angle between the side surface of the truncated pyramid deformation portion 53 and the upper surface of the pedestal 2 is θ. θ is, for example, a range in which the side surface of the truncated pyramid deformation portion 53 is not parallel to the back surface of the chip 7. For example, when the truncated pyramid deformation portion 53 is created based on the truncated pyramid portion 52, which is a quadrangular pyramid, θ is less than 90 degrees. In the structure of the sample holder 1 of the third embodiment, when the chip 7 is mounted on the sample holder 1, at least a part of the base 2 comes into contact with the back surface of the chip 7.

[0093] FIG. 24 shows a simulation result of S11 in the case where the chip 7 is mounted by the bonding wire 13 on the sample holder 1 using the base 2 with the cavity 5 formed in FIG. 21A to FIG. 21C. FIG. 24 is an explanatory diagram showing a simulation result of S11 in the system where the chip 7 is mounted by the bonding wire 13 on the sample holder 1 of the third embodiment. In the simulation in FIG. 24, a1=3[mm], b1=3[mm], a2=5[mm], b2=5[mm], d1=1[mm], d2=2[mm], and s=0.5[mm]. In this case, θ is about 63.4 degrees. As shown in FIG. 24, the lowest resonance frequency of the chip mode is 21.0[GHz]. As shown in FIG. 24, the lowest resonance frequency of the chip mode can be made higher than the simulation result shown in FIG. 8, which is simulated using the sample holder 101 shown in FIG. 7A to FIG. 7C.

[0094] In this way, the sample holder 1 of the third embodiment has the effect of being able to increase the resonance frequency of the tip mode compared to the sample holder 101 shown in FIGS. 7A to 7C.

[0095] [Modification of the third embodiment] As a modification of the third embodiment, a sample holder in which the prism portion 51 of the cavity 5 is eliminated and only the truncated pyramidal deformation portion 53 is provided is shown in Figs. 25A to 25C. Fig. 25A is a perspective view of the sample holder 1 of the modification of the third embodiment. Fig. 25B is a top view of the sample holder 1 of the modification of the third embodiment. Fig. 25C is a cross-sectional view of the sample holder 1 of the modification of the third embodiment cut along a plane parallel to the xz plane including the cutting line K-KK shown in Fig. 25B. In Fig. 25C, a chip 7 is mounted on the sample holder 1 according to the third embodiment with a bonding wire 13. Furthermore, in order to explain the shape of the cavity 5 of the modification of the third embodiment shown in Figs. 25A, 25B, and 25C in more detail, a description will be given using Figs. 26A to 26C and Figs. 27A to 27C.

[0096] Fig. 26A is a perspective view showing a first shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment. Fig. 26B is a top view showing a first shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment. Fig. 26C is an end view of the vicinity of the cavity 5 of the sample holder 1 in the first shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment, cut along a plane parallel to the xz plane including the cutting line L-LL shown in Fig. 26B. In Fig. 26C, a chip 7 is mounted on the sample holder 1 according to the modified example of the third embodiment with a bonding wire 13.

[0097] Fig. 27A is a perspective view showing a second shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment. Fig. 27B is a top view showing a second shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment. Fig. 27C is a cross-sectional view of the sample holder 1 in the second shape example of the cavity 5 of the sample holder 1 of the modified example of the third embodiment, cut along a plane parallel to the xz plane including the cutting line M-MM shown in Fig. 27B. In Fig. 27C, a chip 7 is mounted on the sample holder 1 according to the modified example of the third embodiment with a bonding wire 13.

[0098] The cavity 5 shown in Figs. 26A to 26C has the same structure as the cavity 5 shown in Figs. 19A to 19C of the modified example of the second embodiment. That is, the cavity 5 shown in Figs. 26A to 26B is composed of only the truncated pyramid portion 52. In the modified example of the third embodiment, four conductive pillars 6 shown in Fig. 27 are further added to the four corners of the cavity 5 shown in Fig. 26 similar to the modified example of the second embodiment. This allows the cavity 5 shown in Figs. 25A to 25C to be formed in the base 2. θ is, for example, in a range in which a portion that is not parallel to the back surface of the chip 7 is formed on the side of the cavity 5 (frustum of pyramid portion 52) shown in Figs. 26A to 26C. For example, when the cavity 5 shown in Figs. 26A to 26C is a truncated pyramid, θ is less than 90 degrees.

[0099] FIG. 28 shows a simulation result of S11 in the case where the chip 7 is mounted by the bonding wire 13 on the sample holder 1 using the base 2 having the cavity 5 shown in FIG. 25A to FIG. 25C. FIG. 28 is an explanatory diagram showing a simulation result of S11 in the system where the chip 7 is mounted by the bonding wire 13 on the sample holder 1 of the modified example of the third embodiment. In FIG. 28, in the simulation, a1=2[mm], b1=2[mm], a2=5[mm], b2=5[mm], d2=5[mm], and s=0.5[mm]. In this case, θ is about 73.3 degrees. As shown in FIG. 28, the lowest resonance frequency of the chip mode is 21.1[GHz]. As shown in FIG. 28, the lowest resonance frequency of the chip mode can be made higher than the simulation result shown in FIG. 8, which is simulated using the sample holder 101 shown in FIG. 7A to FIG. 7C.

[0100] In the third embodiment and its variations, if the thickness of the chip 7 mounted on the sample holder 1 is t, the sum d1+d2 of the height d1 of the prismatic portion 51 of the cavity 5 in Figures 21A to 21C and Figures 25A to 25C and the height d2 of the truncated pyramidal portion 53 is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0101] In the third embodiment and its modified examples, if d2 is greater than 0, it has the effect of increasing the resonant frequency of the chip mode. Therefore, it is preferable that d2 is greater than 0. On the other hand, since d1 may be 0, it is preferable that d2 is 0 or greater. When d1=0, the cavity 5 is composed of only the truncated pyramidal deformation portion 53.

[0102] In the third embodiment and its modified examples, the smaller the base area of ​​the pillars 6 at the four corners in Figs. 23A to 23C and Figs. 27A to 27C, the more the contact area between the back surface of the chip 7 and the base 2 can be reduced, and the higher the resonance frequency of the chip mode can be. Therefore, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, s needs to be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less. On the other hand, when the chip 7 mounted on the sample holder 1 is square and the length of one side of the chip 7 is v, s needs to be 0.5v or less, preferably 0.3v or less, and more preferably 0.2v or less.

[0103] In the third embodiment and its modified examples, the cavity 5 has a structure in which a prism portion and a truncated pyramidal deformation portion are connected, or a structure consisting of only the truncated pyramidal deformation portion, but the shape of the cavity 5 may be other shapes, for example, the side surface of the truncated pyramidal deformation portion may be curved instead of flat. In other words, the effects described in the third embodiment and its modified examples can be achieved as long as at least a part of the surface of the base 2 forming the cavity 5 that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7 or the upper surface of the base 2.

[0104] [Other embodiments] In the first to third embodiments and their modifications, the PCB 3 shown in FIG. 11A to FIG. 11D is used as the PCB 3. The PCB 3 shown in FIG. 11A to FIG. 11D has two metal layers. Specifically, the PCB 3 has two metal layers in total, a metal layer on which the front GND 9 and the core wire 10 are formed, and a metal layer on which the back GND 11 is formed. However, in the first to third embodiments and their modifications, even if a PCB 3 having three or more metal layers is used instead of the PCB 3 having two metal layers as shown in FIG. 11A to FIG. 11D, the effects described in the first to third embodiments and their modifications can be obtained. As an example of the PCB 3 having three or more metal layers, FIG. 29A to FIG. 29F show a configuration example of a PCB 3 having three metal layers.

[0105] FIG. 29A is a top view showing the structure of PCB3 according to another embodiment. FIG. 29B is a cross-sectional view of PCB3 according to another embodiment cut along a plane parallel to the xy plane so that the core wire formed in the region between the front GND9 and the back GND11 can be seen. FIG. 29C is an enlarged view of the vicinity of the core wire 10 in the cross section of PCB3 according to another embodiment cut along a plane parallel to the xz plane including the cutting line N-NN shown in FIG. 29A. Note that the cross-sectional view shown in FIG. 29B is a view of PCB3 cut along a plane parallel to the xy plane including the cutting line O-OO shown in FIG. 29C. FIG. 29D is a bottom view showing the structure of PCB3 according to another embodiment. FIG. 29E is a perspective view of PCB3 according to another embodiment. FIG. 29F is an enlarged view of the vicinity of the through hole 4 of PCB3 according to a modified example of another embodiment.

[0106] As shown in FIG. 29C, the PCB 3 has a structure in which a surface GND 9 is formed on one surface of a plate-shaped dielectric 8 extending parallel to the xy plane. The PCB 3 also has a structure in which a back surface GND 11 is formed on the other surface of the dielectric 8. Furthermore, the PCB 3 has a structure in which a core wire 10 is formed inside the dielectric 8, that is, in the area sandwiched between the surface GND 9 and the back surface GND 11. A line having such a structure is generally called a strip line. As shown in FIG. 29A, the surface GND 9, an input / output pad 15, and a bonding pad 16 are formed on the upper surface of the PCB 3. The input / output pad 15 is a pad for connecting the core wire 10 of the PCB 3 to an external measuring instrument or the like and for inputting and outputting signals. The bonding pad 16 is a pad for connecting the core wire 10 of the PCB 3 to a pad of the chip 7 by a bonding wire 13 or the like. The input / output pads 15 and bonding pads 16 formed on the upper surface of the PCB 3 are electrically connected to the core wire 10 formed in the area between the front GND 9 and the back GND 11. In the top view of FIG. 29A, the core wire 10 is hidden by the front GND 9 and is not visible. FIG. 29B shows a cross-sectional view cut along a plane parallel to the xy plane near the core wire 10. In FIG. 29A to FIG. 29F, four strip lines are formed on the PCB 3. However, the number of strip lines formed on the PCB 3 is not particularly limited and may be any number. As shown in FIG. 29B, FIG. 29C, and FIG. 29E, the PCB 3 is provided with a plurality of through holes 12. These through holes 12 penetrate the dielectric 8 and electrically connect the front GND 9 and the back GND 11. In addition, a through hole 4 is provided near the center of the PCB 3.

[0107] In the first to third embodiments and their modified examples, even if a PCB 3 having three or more metal layers as shown in FIGS. 29A to 29F is used, the same effects as those of the first to third embodiments and their modified examples are achieved.

[0108] In the first to third embodiments and their modified examples, the method of mounting the superconducting quantum circuit chip 7 is described as placing the chip 7 directly on the metal base 2, but the mounting method is not limited to this. Even in the case of a mounting form in which a resin material such as varnish is applied onto the metal base 2 and then the chip 7 is placed on the resin material such as varnish, the effect of each embodiment, that is, the effect of being able to increase the resonant frequency of the chip mode, can be obtained.

[0109] In the first to third embodiments and their modified examples, the sample holder 1 is configured to have the PCB 3 placed directly on the metal pedestal 2. The effect of each embodiment can be obtained even with a sample holder 1 configured to have a metal sheet such as In (indium) placed on the metal pedestal 2 and the PCB 3 placed on the metal sheet such as In. By sandwiching a soft metal sheet such as In between the pedestal 2 and the PCB 3, it is possible to prevent a gap from occurring between the back surface GND 11 of the PCB 3 and the pedestal 2. This may improve the high frequency characteristics of the sample holder 1. Specifically, if there is a gap between the PCB 3 and the pedestal 2, the gap may form a new cavity resonator, which may cause resonance when a signal of a specific frequency is input to the chip 7. For this reason, it is preferable to prevent a gap from occurring between the back surface GND 11 of the PCB 3 and the pedestal 2.

[0110] In the first to third embodiments and their modified examples, the sample holder 1 is configured such that the PCB 3 is placed on the metal pedestal 2. A metal lid may be placed on the PCB 3. Even when the lid is placed, the effects of each embodiment can be obtained. In such a sample holder 1, the metal lid is in electrical contact with the surface GND 9 of the PCB 3. However, the lid is not in contact with the core wire 10 of the PCB 3 or the chip 7. This is to prevent the core wire 10 of the PCB 3 and the circuit and wiring of the chip 7 from contacting the GND. For the same reason as above, it is preferable that there is no gap between the lid and the surface GND 9 of the PCB 3, so a sheet such as In may be sandwiched between the lid and the surface GND 9 of the PCB 3.

[0111] In the first to third embodiments and their modified examples, the pedestal 2 is shown to have a rectangular parallelepiped or cubic shape as the shape of the sample holder 1, but the effects of the present invention can be obtained even if the shape of the pedestal 2 is another shape, such as a cylinder. Similarly, the effects of each embodiment can be obtained even if the shape of the PCB 3 is a shape other than a rectangle or square, such as a circle.

[0112] (Fourth embodiment) In the fourth embodiment, a basic configuration of the contents described in the first to third embodiments will be described. Here, the fourth embodiment will be described with reference to FIG. 10A used in the first embodiment.

[0113] As shown in FIG. 10A, the sample holder 1 includes a base 2 and a PCB 3 in contact with the base 2. The PCB 3 has a through hole 4. The PCB 3 has a cavity 5 in at least a portion below the through hole 4 of the base 2. The shape of the cavity 5 is not particularly limited. For example, the bottom surface of the cavity 5 may be flat or non-flat. The side surface of the cavity 5 may be flat or non-flat.

[0114] The cavity 5 has a support structure that supports the surface of the chip 7 and is conductive to the base 2. At least a part of the part of the support structure that supports the chip 7 is not parallel to the surface of the chip. The surface of the chip here is the back surface of the chip opposite to the circuit surface of the chip. The support structure is not particularly limited. In FIG. 10A, the support structure is a conductive pillar 6 arranged at the four corners of the cavity 5. At least a part of the upper surface of the pillar 6 is not parallel to the upper surface of the base 2. Note that, when the support structure is a pillar 6, it is not limited to the shape of FIG. 10A. As shown in FIG. 13A and FIG. 13C used in the description of another example of the first embodiment, the upper part 61 of the pillar 6 may be in the shape of a triangular pyramid so that the upper part 61 is not parallel to the back surface of the chip 7. For example, as shown in FIG. 15A used in the description of the modified example of the first embodiment, at least a part of the upper surface of the pillar 6 is not parallel to the back surface of the chip 7, and at least a part of the upper surface of the pillar 6 may be parallel to the back surface of the chip 7.

[0115] The support structure may be realized by the shape of the cavity 5. Specifically, as described in the second and third embodiments, the shape of the cavity 5 may be a shape that includes a part of a frustum. This makes it possible that, when the chip 7 is mounted on the sample holder 1, among the surfaces of the base 2 that form the cavity 5, at least a part of the surface that faces the back surface of the chip 7 is not parallel to the back surface of the chip 7.

[0116] In the fourth embodiment, the sample holder 1 has a cavity 5 in the base 2, and the cavity 5 has a support structure for supporting the back surface of the chip, and at least a part of the portion of the support structure that supports the chip 7 is not parallel to the surface of the chip. This makes it possible to increase the resonance frequency of the chip mode.

[0117] This completes the description of the sample holder 1 according to each embodiment. The superconducting quantum computer according to each embodiment includes the sample holder 1 according to each embodiment, and a chip on which a superconducting quantum circuit is formed and is stored in the sample holder 1.

[0118] Although the present disclosure has been described above with reference to each embodiment, the present disclosure is not limited to the above embodiment. The configuration and details of each disclosure may include embodiments to which various modifications that a person skilled in the art can understand within the scope of the present disclosure are applied. The present disclosure may include embodiments in which the matters described in this specification are appropriately combined or replaced as necessary. For example, matters described using a specific embodiment may also be applied to other embodiments to the extent that no contradiction occurs.

[0119] A part or all of the above-described embodiments can be described as follows: However, a part or all of the above-described embodiments is not limited to the following.

[0120] (Appendix 1) With a pedestal, a PCB in contact with the base; Equipped with The PCB has a through hole, The base has a cavity in at least a portion below the through hole, a support structure in the cavity that supports a face of the chip and is in electrical communication with the pedestal; At least a part of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Sample holder.

[0121] (Appendix 2) The support structure is a conductive pillar. A sample holder as described in Appendix 1.

[0122] (Appendix 3) The pillar has a shape combining a frustum and a rectangular pillar, The bottom surface of the frustum having a smaller area is on the through hole side, The bottom surface of the larger area of ​​the frustum and the top bottom surface of the prism have the same shape and are connected. A sample holder as described in Appendix 2.

[0123] (Appendix 4) The support structure is a plurality of pillars disposed in the cavity. 4. A sample holder as described in appendix 2 or 3.

[0124] (Appendix 5) The plurality of pillars are provided at four corners of the cavity. A sample holder as described in Appendix 4.

[0125] (Appendix 6) the cavity is in the shape of a frustum; The bottom surface of the frustum having a larger area is the through hole side. A sample holder as described in Appendix 1.

[0126] (Appendix 7) The cavity has a shape that is a combination of the frustum and a pillar, The base surface of the smaller area of ​​the frustum and the base surface of the upper side of the pillar have the same shape and are connected. A sample holder as described in Appendix 6.

[0127] (Appendix 8) The prism is a quadrangular prism. The frustum is a square pyramid. A sample holder as described in Appendix 7.

[0128] (Appendix 9) The cavity further includes a conductive prism, The bottom surface of the upper side of the rectangular pillar of the conductor is parallel to the upper surface of the base. 9. A sample holder according to any one of claims 6 to 8.

[0129] (Appendix 10) The rectangular pillars are provided at the four corners of the cavity. A sample holder as described in Appendix 8.

[0130] (Appendix 11) the cavity is pyramidal in shape; The bottom surface of the pyramid is on the through hole side. A sample holder as described in Appendix 1.

[0131] (Appendix 12) The support structure is made of a metal or a composite that includes a metal. 12. A sample holder according to any one of claims 1 to 11.

[0132] (Appendix 13) The base is made of metal. 13. A sample holder according to any one of claims 1 to 12.

[0133] (Appendix 14) The tip is stored in the through hole. 14. A sample holder according to any one of claims 1 to 13.

[0134] (Appendix 15) The PCB includes a dielectric, a front ground formed on a front surface of the dielectric, and a back ground formed on a back surface of the dielectric. 15. A sample holder according to any one of claims 1 to 14.

[0135] (Appendix 16) The PCB has a core of a coplanar waveguide on the surface of the dielectric. 16. A sample holder according to any one of claims 1 to 15.

[0136] (Appendix 17) The PCB further includes a core wire in a region of the dielectric that is sandwiched between the front surface ground and the back surface ground. 16. A sample holder according to any one of claims 1 to 15.

[0137] (Appendix 18) A sample holder; A chip on which a superconducting quantum circuit is formed, the chip being stored in the sample holder; Equipped with The sample holder comprises: With a pedestal, a PCB in contact with the base; Equipped with The PCB has a through hole, The base has a cavity in at least a portion below the through hole, a support structure in the cavity that supports a face of the chip and is in electrical communication with the pedestal; At least a part of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Superconducting quantum computer. [Explanation of symbols]

[0138] 1 Sample holder 2 Pedestal 3 PCB 4 Through holes 5 hollow 6 Pillars 7. Chip 8 Dielectrics 9 Surface GND 10 core wire 11 Backside GND 12 through holes 13 Bonding Wire 14 Conductors 15 Input / Output Pad 16 Bonding Pads 51 Square column 52 truncated pyramid part 53 Pyramid deformation part 61 Top 62 Lower 71 First Coplanar Waveguide 72 Second Coplanar Waveguide 73 GND Plane 74 First core wire 75 Second core wire 76 First Pad 77 Second Pad 101 Sample Holder 102 Pedestal 103 PCB 104 Through hole 105 Cavity 106 Pillars 107 Chips 108 Dielectric 109 Surface GND 110 core wire 110a First core 110b Second core wire 111 Backside GND 112 through hole 113 Bonding Wire

Claims

1. With a pedestal, A PCB (Printed Circuit Board) in contact with the base; Equipped with The PCB has a through hole, The base has a cavity in at least a portion below the through hole, a support structure in the cavity that supports a face of the chip and is in electrical communication with the pedestal; At least a part of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Sample holder.

2. The support structure is a conductive pillar. The sample holder of claim 1 .

3. The pillar has a shape combining a frustum and a rectangular pillar, The bottom surface of the frustum having a smaller area is on the through hole side, The bottom surface of the larger area of ​​the frustum and the top bottom surface of the prism have the same shape and are connected. The sample holder of claim 2 .

4. The pillars are a plurality of pillars provided in the cavity. A sample holder according to claim 2 or 3.

5. The plurality of pillars are provided at four corners of the cavity.

5. The sample holder of claim 4.

6. the cavity is in the shape of a frustum; The bottom surface of the frustum having a larger area is the through hole side. The sample holder of claim 1 .

7. The cavity has a shape combining the frustum and a prism, The base surface of the frustum having a smaller area and the base surface of the upper side of the prism have the same shape and are connected to each other. The sample holder of claim 6.

8. The prism is a quadrangular prism. The frustum is a square pyramid. The sample holder of claim 7.

9. The cavity further includes a conductive prism, The bottom surface of the upper side of the rectangular pillar of the conductor is parallel to the upper surface of the base. A sample holder according to any one of claims 6 to 8.

10. A sample holder; A chip on which a superconducting quantum circuit is formed, the chip being stored in the sample holder; Equipped with The sample holder comprises: With a pedestal, a PCB in contact with the base; Equipped with The PCB has a through hole, The base has a cavity in at least a portion below the through hole, a support structure in the cavity that supports a face of the chip and is in electrical communication with the pedestal; At least a part of the portion of the support structure that supports the chip is not parallel to the surface of the chip. Superconducting quantum computer.

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