Flexible circuit board and chip package including same

Abstract

To provide a flexible circuit board for an all-in-one COF to which a plurality of chips are mounted onto one substrate, a chip package including the same, and an electron device including the same.SOLUTION: A flexible circuit board 100 according to an embodiment of the present invention, includes: a substrate 110; a first wiring pattern layer 121 arranged onto a first surface of the substrate 110; a second wiring pattern layer 122 that is arranged onto a second surface opposite to the first surface of the substrate 110; a first dummy pattern part DP1 that is arranged onto the second surface of the substrate 110 where the second wiring pattern layer 122 is not arranged; and a protection layer 140 that is formed by a first protection layer arranged onto the first wiring pattern layer 121 and a second protection layer arranged onto the second wiring pattern layer 122 and the first dummy pattern part DP1. At least a part of the first dummy pattern part DP1 is overlapped in a vertical direction of the first wiring pattern layer 121.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a flexible circuit board for all-in-one COF and a chip package including the same. This is related to the page.

[0002] Specifically, the present invention provides a flexible substrate that can mount different types of chips on a single substrate. and a chip package including the same. [Background technology]

[0003] Recently, various electronic products have become thinner, smaller, and lighter. Various researches are being conducted to mount semiconductor chips at high density in a small area.

[0004] Among them, the COF (Chip On Film) method uses a flexible substrate, so it is It can be applied to both flat panel displays and flexible displays. That is, the COF method is attracting attention because it can be applied to a variety of wearable electronic devices. In addition, the COF method can realize fine peaches, which makes it possible to achieve high resolution due to the increased number of pixels. It can be used to realize a QHD display.

[0005] COF (Chip On Film) is a technology that mounts semiconductor chips on a thin film-type flexible circuit board. For example, semiconductor chips are integrated circuit (IC) chips. It may consist of a chip or a large scale integrated circuit (LSI) chip. can.

[0006] On the other hand, in order to respond to the recent trend of miniaturization, thinning and lightening of electronic products, high density semiconductors As a mounting technology for conductor chips, various COF packaging technologies using flexible substrates are available. It has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0007] This invention is an all-in-one COF flexible board that can mount multiple chips on one board. and a chip package including the same, and an electronic device including the same. Let's say.

[0008] The present invention is an all-in-one solder mask that can remove pinholes that occur during solder resist printing. Flexible circuit board for COF, chip package including the same, and electronic device including the same Trying to provide the device.

[0009] This invention is an all-in-one design system that allows for product design taking into account the solder resist printing process. Flexible circuit board for one-in-one COF and chip package including the same, We aim to provide electronic devices that

[0010] The technical problem to be achieved by the proposed embodiment is limited to the technical problem mentioned above. Other technical problems not mentioned, including but not limited to, the implementation proposed in the following description, This should be clearly understood by those skilled in the art to which the embodiments pertain. [Means for solving the problem]

[0011] The flexible circuit board according to the embodiment of the present invention includes a substrate and a first surface of the substrate. a first wiring pattern layer disposed on a second surface of the substrate opposite to the first surface; a second wiring pattern layer on the substrate where the second wiring pattern layer is not disposed; a first dummy pattern portion disposed on the second surface; and a second dummy pattern portion disposed on the first wiring pattern layer. a first protective layer disposed on the second wiring pattern layer and the first dummy pattern portion; and a second protective layer formed by the first dummy pattern portion. It overlaps the pattern layer vertically.

[0012] Also, a wiring pattern layer is disposed on the first surface of the substrate on which the first wiring pattern layer is not disposed. a second dummy pattern portion at least part of which overlaps with the second wiring pattern layer in the vertical direction; Further includes:

[0013] The first dummy pattern portion has the same width as the first wiring pattern layer, and one end is The first wiring pattern layer is disposed on the same vertical line as one end of the first wiring pattern layer.

[0014] The first dummy pattern portion has a width greater than that of the first wiring pattern layer, and one end is closer to the edge of the substrate than one end of the first wiring pattern layer.

[0015] Moreover, the first surface is an upper surface of the substrate, and the second surface is a lower surface of the substrate, The first dummy pattern portion is a first dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. It is placed to the left of the wiring pattern layer.

[0016] The second dummy pattern portion is disposed on the rightmost side of the second wiring pattern layer. The second wiring pattern layer is disposed to the right of the first wiring pattern layer.

[0017] Also, a first plating layer containing tin (Sn) disposed on the first wiring pattern layer; and a second plating layer including tin (Sn) disposed on the second wiring pattern layer. The dummy pattern portion includes a first dummy pattern layer corresponding to the second wiring pattern layer, and a second dummy pattern layer corresponding to the second plating layer, wherein the second dummy pattern portion comprises: a third dummy pattern layer corresponding to the first wiring pattern layer and a third dummy pattern layer corresponding to the first plating layer; and a fourth dummy pattern layer.

[0018] On the other hand, the package according to the embodiment is an all-in-one COF flexible circuit board, A substrate, a conductive pattern portion disposed on the substrate, and a dummy pattern portion disposed on the substrate. a pattern portion, a region on the conductive pattern portion, and a region on the dummy pattern portion; a protective portion disposed on the first surface of the substrate, and the conductive pattern portion is disposed on the first surface of the substrate. a first wiring pattern layer formed on the first wiring pattern layer; and a first plating layer disposed on the first wiring pattern layer; a second wiring pattern layer disposed on a second surface of the substrate opposite to the first surface; a second plating layer disposed on the second wiring pattern layer, The tin (Sn) content of the plating layer in the second open region of the protective layer is A first chip disposed in the first open area has a tin (Sn) content greater than that of the plating layer. and a second chip disposed in the second open area, wherein the dummy pattern portion comprises: The second wiring pattern layer is disposed on the second surface of the substrate where the second wiring pattern layer is not disposed, and a first dummy pattern portion at least partly overlapping with the first wiring pattern layer in a vertical direction; a first wiring pattern layer disposed on the first surface of the substrate on which the first wiring pattern layer is not disposed; The second wiring pattern layer also includes a second dummy pattern portion, a part of which overlaps the second wiring pattern layer in the vertical direction.

[0019] Moreover, the first surface is an upper surface of the substrate, and the second surface is a lower surface of the substrate, The first dummy pattern portion is a first dummy pattern portion arranged at the leftmost side of the first wiring pattern layer. The second dummy pattern portion is disposed on the left side of the wiring pattern layer. It is arranged to the right of the second wiring pattern layer, which is arranged at the rightmost side of the layer.

[0020] The first chip is a drive IC chip, and the second chip is , Diode chip, Power supply IC chip, Touch sensor IC chip, MLCC chip, B All-in-one capacitors including at least one of GA chip and chip capacitors Includes flexible circuit boards for OF.

[0021] On the other hand, an electronic device according to an embodiment of the present invention includes a substrate and a conductive layer disposed on the substrate. a conductive pattern portion, a dummy pattern portion disposed on the substrate, and the conductive pattern portion a protective portion partially disposed in a region on the substrate, a first wiring pattern layer disposed on the first surface of the plate; and a wiring pattern layer disposed on the first wiring pattern layer. a first plating layer disposed on a second surface of the substrate opposite the first surface; a wiring pattern layer and a second plating layer disposed on the second wiring pattern layer, The tin (Sn) content of the plating layer in the first open region of the protective layer is 2. All-in-one plating containing a tin (Sn) content greater than that of the plating layer in the open area a flexible circuit board for COF, and one end of the all-in-one flexible circuit board a display panel to be connected to the one end of the all-in-one flexible circuit board; and a main board connected to the other end opposite to the dummy pattern part. The second wiring pattern layer is disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed, and at least a first dummy pattern portion, the first dummy pattern portion being partially overlapped with the first wiring pattern layer in the vertical direction; a wiring pattern layer disposed on the first surface of the substrate on which the wiring pattern layer is not disposed, The second wiring pattern layer includes a second dummy pattern portion that partially overlaps the second wiring pattern layer in the vertical direction.

[0022] In addition, a first connection portion and a second connection portion are formed on the one region and the other region of the conductive pattern portion, respectively. A second connection portion is disposed, a first chip is disposed on the first connection portion, and A second chip is placed on top.

[0023] The display panel and the main board are arranged to face each other. The all-in-one flexible circuit board includes the display panel and the main board. The plate is folded and placed between the plates. [Effects of the Invention]

[0024] According to an embodiment of the present invention, a first chip and a second chip of different types are integrated into one frame. All-in-one CO that can be mounted on a flexible circuit board for improved reliability Flexible circuit board chip packages for F can be provided.

[0025] Furthermore, according to an embodiment of the present invention, one all-in-one flexible circuit for COF is provided. The display panel and main board are directly connected by a circuit board, and the The size and thickness of the flexible circuit board that transmits the signals to the main board are reduced. This allows for more space for other components and / or battery space. It is possible.

[0026] Furthermore, according to an embodiment of the present invention, a plurality of PCBs (printed circuit boards) can be connected. Since no additional wiring is required, the convenience of the process and the reliability of the electrical connection are improved. All-in-one COF flexible cable suitable for electronic devices with high resolution display A flexible circuit board can be provided.

[0027] Furthermore, according to the embodiment of the present invention, a circuit pattern corresponding to the circuit pattern arranged on the first surface of the substrate is formed. A dummy pattern is arranged on the second surface of the substrate so as to By disposing a dummy pattern on the first surface of the substrate so as to correspond to the wiring pattern, Solder resist generated when printing the solder resist on the first or second surface of the board This can solve the problems of not applying the paste and pinholes. [Brief explanation of the drawings]

[0028] [Figure 1a] 1 is a cross-sectional view of an electronic device having a display unit including a conventional PCB. [Figure 1b] 1b is a cross-sectional view of the PCB according to FIG. 1a in a bent configuration; [Figure 1c] FIG. 1b is a plan view of the PCB according to FIG. 1a in a folded configuration; [Figure 2a] FIG. 1 is a cross-sectional view of an electronic device having a display unit including a flexible circuit board for all-in-one COF according to an embodiment. [Figure 2b]2b is a cross-sectional view of the flexible circuit board for all-in-one COF shown in FIG. 2a in a bent state. [Figure 2c] 2b is a plan view of the all-in-one COF flexible circuit board of FIG. 2a in a folded state. FIG. [Figure 3a] 1 is a cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 3b] FIG. 10 is another cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 4a] FIG. 10 is a cross-sectional view of a flexible circuit board not including a dummy pattern portion according to a comparative example. [Figure 4b] 1 is a cross-sectional view of a flexible circuit board including a lower dummy pattern portion DP1 according to an embodiment of the present invention. [Figure 5a] 4A and 4B are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4B. [Figure 5b] 4A and 4B are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4B. [Figure 5c] 4A and 4B are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4B. [Figure 5d] 4A and 4B are diagrams showing various modified examples of the lower dummy pattern portion DP1 shown in FIG. 4B. [Figure 6] 10 is a view showing an upper dummy pattern part DP2 according to an embodiment of the present invention. [Figure 7a] FIG. 2 is another cross-sectional view of the double-sided all-in-one COF flexible circuit board according to the embodiment. [Figure 7b] 7b is a cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to FIG. 7a. [Figure 8] FIG. 2 is another cross-sectional view of a chip package including a double-sided all-in-one COF flexible circuit board according to an embodiment. [Figure 9]FIG. 2 is an enlarged cross-sectional view of one area of ​​the double-sided all-in-one COF flexible circuit board according to the embodiment. [Figure 10] 7b is a plan view of the flexible circuit board for double-sided all-in-one COF according to FIG. 7a. FIG. [Figure 11] 7b is a bottom view of the flexible circuit board for double-sided all-in-one COF according to FIG. 7a. FIG. [Figure 12a] 7b is a schematic plan view of a chip package including a flexible circuit board for double-sided all-in-one COF according to FIG. [Figure 12b] 7b is a schematic plan view of a chip package including a flexible circuit board for double-sided all-in-one COF according to FIG. [Figure 13a] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 13b] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 14a] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 14b] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 15a] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 15b] 7B is a diagram showing a process of manufacturing the flexible circuit board for double-sided all-in-one COF shown in FIG. 7A into a chip package including the flexible circuit board for double-sided all-in-one COF shown in FIG. 7B. [Figure 16] 16 is a cross-sectional view of a chip package including the double-sided all-in-one COF flexible circuit board according to FIG. 15. FIG. [Figure 17] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 18] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19a] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19b] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 19c] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 20] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. [Figure 21] 1 is a diagram of various electronic devices including flexible circuit boards for all-in-one COF. DETAILED DESCRIPTION OF THE INVENTION

[0029] In the description of the embodiments, each layer, region, pattern or structure is a substrate, each layer, region, pattern or structure is a A statement that a code or pattern is formed "on" or "under" the code or pattern is directly This includes layers formed directly or through other layers. The description will be made with reference to the drawings.

[0030] Also, when a part is "connected" to another part, this is "directly connected" This does not only apply to cases where the parts are indirectly connected by placing other parts between them. In addition, when a part is described as "comprising" a certain component, this does not mean that it is specifically opposed. Unless otherwise specified, the invention may further include other components, rather than excluding other components. It means that it is possible.

[0031] In the drawings, the thickness and size of each layer, region, pattern or structure may be varied for clarity of description and The dimensions may be distorted for convenience and convenience, and do not reflect the actual size.

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] A PCB (printed circuit board) according to a comparative example will be described with reference to FIGS. 1a to 1c. .

[0034] An electronic device having a display unit transmits the signal from the display panel to the main board. At least two PCBs are required to transmit the signal.

[0035] The electronic device including the display unit according to the comparative example has at least two PCBs. It can be done.

[0036] The electronic device including the display unit according to the comparative example has a first PCB 10 and a second PCB 2 May contain 0.

[0037] The first PCB 10 can be made of a flexible printed circuit board (FPCB). Specifically, the first PCB 10 is a FPCB for COF (Chip On Film). The first PCB 10 is a FPCB for COF on which the first chip C1 is mounted. More specifically, the first PCB 10 includes a drive IC chip ) can be comprised of an FPCB for COF placement.

[0038] The second PCB 20 may be a FPCB. 0 is a part of the FPCB for arranging a second chip C2 of a different type from the first chip C1. Here, the second chip C2 may be a drive IC chip or Other than the drive IC chip, other chips, semiconductor elements, and software It refers to various chips that are placed on the FPCB for electrical connection, such as sockets. The second PCB 20 is made of an FPCB for arranging a plurality of second chips C2. For example, the second PCB 20 can be provided with a plurality of second chips C of different types. 2a, C2b.

[0039] The first PCB 10 and the second PCB 20 may have different thicknesses. The thickness of the second PCB 20 is smaller than the thickness of the first PCB 10. For example, the first PCB 10 may have a thickness of about 20 μm to 100 μm. The second PCB 20 may have a thickness of about 100 μm to 200 μm. For example, the sum t1 of the thicknesses of the first PCB 10 and the second PCB is 200 μm to 2 It may have a thickness of 50 μm.

[0040] The electronic device having a display unit according to the comparative example has a display panel and a main button. Since a first and second PCB are required between the boards, the overall thickness of the electronic device increases. Specifically, the electronic device having the display unit according to the comparative example has a top and bottom The overall thickness of the electronic device is increased because stacked first and second PCBs are required. This will be the case.

[0041] The first PCB 10 and the second PCB 20 are formed in different processes. For example, the first PCB 10 may be manufactured by a roll-to-roll process. The second PCB 20 may be manufactured in a sheet format.

[0042] The first PCB 10 and the second PCB 20 are provided with different types of chips. The pitch of the conductive pattern to connect each chip is For example, the conductive pattern portion disposed on the second PCB 20 may be different from the conductive pattern portion. The pitch is smaller than the pitch of the conductive pattern portion disposed on the first PCB 10. For example, the conductive layer 24 may have a larger spacing than the conductive layer 24 disposed on the second PCB 20. The pitch of the functional pattern portion is 100 μm or more, and the The pitch of the conductive pattern portions may be less than 100 μm.

[0043] Specifically, the first P has conductive pattern portions arranged at fine intervals. CB10 is manufactured through a roll-to-roll process, which makes the process efficient and reduces process costs. On the other hand, a conductive pattern portion arranged at intervals of 100 μm or more can be The second PCB 20 is difficult to handle in a roll-to-roll process, so it is made by using a sheet process. It was common for

[0044] The first and second PCBs according to the comparative example are formed in different processes, so the process efficiency is Decreases.

[0045] In addition, the chip packages including the flexible circuit boards according to the comparative examples are of different types. Since it is difficult to arrange the chips on one substrate, the first and second PCs are separately B is required.

[0046] In addition, the chip packages including the flexible circuit boards according to the comparative examples are of different types. However, there is a problem in that it is difficult to connect these chips on a single substrate.

[0047] In addition, the flexible circuit board according to the comparative example has an upper circuit pattern and a lower circuit pattern. , and are designed taking into consideration only the signal transmission characteristics of each. Flexible circuit boards are made of a protective layer (e.g., solder resist) that is placed on the outermost layer of the board. The upper and lower circuit patterns are printed without considering the reliability of the printing process. Therefore, in the flexible circuit board according to the comparative example, the protective layer is Pinholes due to positional differences between the upper and lower circuit patterns during the printing process There is a problem that occurs.

[0048] On the other hand, the first and second PCBs are placed between the conventional display panel and the main board. will be done.

[0049] To control, process or transmit the R, G, B signals generated by the display panel 30 Then, the first PCB 10 is connected to the display panel 30, and the first PCB 10 is again connected to the second The second PCB 20 is connected to the main board 40 .

[0050] One end of the first PCB 10 is connected to the display panel 30. The panel 30 is connected to the first PCB 10 by an adhesive layer 50 .

[0051] The other end of the first PCB 10 opposite to the one end is connected to the second PCB 20. The first PCB 10 is connected to the second PCB 20 by the adhesive layer 50 .

[0052] One end of the second PCB 20 is connected to the first PCB 10. The other end opposite to the one end is connected to the main board 40. The second PCB 20 is The adhesive layer 50 connects the main board 40 .

[0053] The electronic device having a display unit according to the comparative example has the display panel 30 and Between the first PCB 10, between the first PCB 10 and the second PCB 20, A separate adhesive layer 50 is required between the B20 and the main board 40. The electronic device having a display unit according to the comparative example requires a large number of adhesive layers. The reliability of electronic devices is reduced due to poor connection of the adhesive layer. The adhesive layer disposed between the first PCB 10 and the second PCB 20 is Increasing the thickness of the device.

[0054] 1b and 1c, a first P that serves as a housing in an electronic device according to a comparative example is shown. The CB 10, the second PCB 20, the display panel 30, and the main board 40 are described. .

[0055] FIG. 1b is a cross-sectional view of the PCB according to FIG. 1a in a bent configuration, and FIG. 1c is a cross-sectional view of the PCB according to FIG. 1b , a plan view of the underside of FIG.

[0056] The display panel 30 and the main board 40 are disposed facing each other. The display panel 30 and the main board 40 are arranged in a folded state. A first PCB 10 including a bending region is placed.

[0057] The first PCB 10 has one area that is bent and one area that is not bent that contains the first chip. Group C1 is placed.

[0058] The second PCB 20 is disposed opposite the display panel 30. The second chip C2 is disposed in the unbendable area of ​​the second PCB20.

[0059] Referring to FIG. 1c, the comparative example requires multiple substrates, so the length L 1 is the sum of the lengths of the first PCB 10 and the second PCB 20. The length L1 of the first PCB 10 and the second PCB 20 in one direction is The length of the short side of the first PCB 20 is the sum of the length of the short side of the second PCB 20. The length L1 of the CB10 and the second PCB20 in one direction is 30 mm to 40 mm. However, depending on the type of chip and electronic device to be mounted, The length L1 of the first PCB 10 and the second PCB 20 in one direction may vary. It can have.

[0060] The electronic device according to the comparative example requires multiple PCBs, so that other components can be mounted on the PCBs. The space for mounting the battery 60 or the space for placing the battery 60 is reduced.

[0061] Recently, electronic devices such as smartphones have become more and more popular for their convenience or security. In order to enhance the functionality of smartphones, various functional components have been added. Electronic devices such as smartwatches often have multiple camera modules (dual cameras) It is equipped with various functions such as iris recognition and VR (Virtual Reality) Therefore, it is important to secure space to mount the added components. be.

[0062] In addition, various electronic devices, including wearable devices, are becoming more convenient for users. To improve this, an increase in battery space is required.

[0063] Therefore, it is possible to replace multiple PCBs used in existing electronic devices with one PCB. To secure space for mounting new components or to increase the size of the battery The importance of securing space is becoming more apparent.

[0064] The electronic device according to the comparative example has a first chip and a second chip of different types. The first PCB 10 and the second PCB 30 are separately arranged. The thickness of the adhesive layer 50 between the two PCBs 30 and the thickness of the second PCB 30 are There was a problem with increasing the thickness.

[0065] In addition, the size of the second PCB 30 is sufficient to accommodate a battery space or other components. There was a problem of reducing the space.

[0066] In addition, poor bonding between the first and second PCBs can reduce the reliability of electronic devices. there were.

[0067] In order to solve this problem, the embodiment is a device that can mount multiple chips on one substrate. A new structure of all-in-one COF flexible circuit board and a chip package including the same A cage and an electronic device including the cage can be provided. The surface symbols represent the same components, and explanations that overlap with the comparative example described above will be omitted.

[0068] 2a to 2c, an all-in-one COF flexible circuit board according to an embodiment is shown. An electronic device including the board is described.

[0069] The electronic device according to the embodiment transmits a signal from a display panel to a main board. One PCB can be used for the electronic device including the display unit according to the embodiment. The PCB included in the device can be one FPCB. The flexible circuit board 100 for all-in-one COF (all-in-one chip on film) is The display is bent between the opposing display section and the main board. The main board and the main board can be connected.

[0070] Specifically, the flexible film for all-in-one COF (all-in-one chip on film) according to the embodiment The block circuit board 100 is a single substrate for mounting multiple chips of different types. It can be.

[0071] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The board 100 is a substrate for arranging first and second chips C1 and C2 of different types. It can consist of:

[0072] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The thickness t2 of the plate 100 can be 20 μm to 100 μm. The thickness of the flexible circuit board 100 for all-in-one COF (all-in-one chip on film) The thickness t2 can be 30 μm to 80 μm. The thickness t2 of the flexible circuit board 100 for COF (All in one chip on film) is 50 μm. However, depending on the type of chip to be mounted and the electronic device, Depending on the type of device, the all-in-one COF (All in one chip on film) film according to the embodiment may be used. The thickness of the flexible circuit board 100 can be designed to have various sizes.

[0073] Here, when the thickness t2 of the flexible circuit board 100 is less than 20 μm, When the cable circuit board 100 is bent, it may break. There is a possibility that damage may occur due to heat generated in the mounted chip. There is.

[0074] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The thickness t2 of the plate 100 is 1 / 5 to 1 / 2 the thickness t1 of the plurality of first and second PCBs according to the comparative example. That is, the all-in-one COF (All i The thickness t2 of the flexible circuit board 100 for (n one chip on film) is The thickness of the first and second PCBs may be 20% to 50% of the thickness t1. For example, the flexible circuit for all-in-one COF (all in one chip on film) according to the embodiment The thickness t2 of the printed circuit board 100 is 25% of the thickness t1 of the first and second PCBs according to the comparative example. For example, the all-in-one CO according to the embodiment can have a thickness of about 40%. The thickness t2 of the flexible circuit board 100 for F (All in one chip on film) is The thickness of the first and second PCBs may be about 25% to 35% of the thickness t1 of the first and second PCBs. Cut.

[0075] The electronic device having a display unit according to the embodiment includes a display panel and a main button. Only one all-in-one COF (All in one chip on film) flexible Because the circuit board 100 is required, the overall thickness of the electronic device can be reduced. Specifically, the electronic device having a display unit according to the embodiment requires a single-layer PCB. This reduces the overall thickness of the electronic device.

[0076] In addition, the embodiment omits the adhesive layer 50 between the first PCB and the second PCB included in the comparative example. It can be used for all-in-one COF chip packaging including flexible circuit boards. The overall thickness of the electronic device containing the same can be reduced.

[0077] In addition, the embodiment can omit the adhesive layer 50 between the first PCB and the second PCB, and the adhesive layer 50 can be easily attached. This can eliminate problems caused by poor connection, thereby improving the reliability of electronic devices. This can be done.

[0078] In addition, the process of bonding multiple PCBs can be omitted, increasing process efficiency and reducing process costs. is reduced.

[0079] In addition, by replacing substrates that were previously managed in separate processes with one process, process efficiency and product The yield can be improved.

[0080] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The plate 100 can include a folded region and a non-folded region. The flexible circuit board 100 for COF (All in one chip on film) includes a bending region. Thus, the display panel 30 and the main board 40, which are arranged opposite to each other, are connected. It is possible.

[0081] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The non-bending area of ​​the plate 100 is positioned opposite the display panel 30. All-in-one COF (All-in-one chip on film) flexible circuit board according to the embodiment The first chip C1 and the second chip C2 are disposed on the non-bending region of the plate 100. , an all-in-one COF (all-in-one chip on film) flexible circuit board according to an embodiment The board 100 allows the first chip C1 and the second chip C2 to be stably mounted.

[0082] FIG. 2c is a plan view of the underside of FIG. 2b.

[0083] Referring to FIG. 2c, an embodiment requires only one substrate, so the length in one direction, L 2 is the length of one substrate. The length L2 in one direction of the flexible circuit board 100 for the optical fiber cable (for the optical fiber cable) is The length of the short side of the flexible circuit board 100 for all-in-one COF (all-in-one chip on film) As an example, an all-in-one COF (all in one chip on film) according to an embodiment The length L2 of the flexible circuit board 100 in one direction is set to 10 mm to 50 mm. For example, the all-in-one COF (All in one chip on film) according to the embodiment can be The length L2 of the flexible circuit board 100 in one direction is 10 mm to 30 mm. For example, the all-in-one COF (all-in-one chip on film) frame according to the embodiment can be used. The length L2 of the flexible circuit board 100 in one direction may be 15 mm to 25 mm. However, the embodiment is not limited to this, and the type of chip to be placed may be changed. And / or the number and size can be designed depending on the type of electronic device. As in the example, by mounting multiple chips on one substrate, flexible The length of the circuit board can be reduced to 50mm or less. The length of the flexible circuit board can be reduced to 10mm or less. If the spacing is less than mm, the design freedom of the many chips mounted will decrease, and the spacing between chips will The narrowness of the gap can affect the mutual electrical characteristics.

[0084] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The length L2 of the board 100 in one direction is the same as that of the first and second PCBs in the comparative example. For example, in the embodiment, the length can be about 50% to 70% of the length L1 in the The flexible circuit board 100 for all-in-one COF (all-in-one chip on film) The length L2 in one direction is the length in one direction of the plurality of first and second PCBs according to the comparative example. The length of the all-in-one device according to the embodiment can be about 55% to 70% of the length L1. Length in one direction of the flexible circuit board 100 for COF (All in one chip on film) L2 is 60% to 70% of the length L1 in one direction of the plurality of first and second PCBs according to the comparative example. It can have a length of about 0%.

[0085] Thus, embodiments may include an all-in-one chip on film (COF) in an electronic device. ) the size of the chip package including the flexible circuit board 100 for the battery is reduced, The space for placing the all-in-one COF (All i The chip package including the flexible circuit board 100 for one chip on film has a surface area of This reduces the weight, making it possible to secure space for mounting other components.

[0086] Hereinafter, an all-in-one COF (All in one chip on film) according to an embodiment will be described with reference to the drawings. A flexible circuit board 100 for lm) and a chip package thereof will now be described.

[0087] FIG. 3a is a cross-sectional view of a flexible circuit board according to a first embodiment of the present invention, and FIG. 3b is a cross-sectional view of a flexible circuit board according to a first embodiment of the present invention. 3a is a modified example of the flexible circuit board, and FIG. 4a is a dummy pattern portion according to a comparative example. 4a is a cross-sectional view of a flexible circuit board without a lower dummy according to an embodiment of the present invention; FIG. 5a to 5d are cross-sectional views of a flexible circuit board including a pattern portion DP1. 6 shows various modifications of the lower dummy pattern portion DP1 shown in FIG. 7A and 7B are diagrams showing an upper dummy pattern part DP2 according to an embodiment of the present invention. 7b is another cross-sectional view of the double-sided all-in-one COF flexible circuit board; 7a of the chip package including the double-sided all-in-one COF flexible circuit board 8 is a cross-sectional view of a double-sided all-in-one COF flexible circuit board according to an embodiment of the present invention. 1 is another cross-sectional view of a chip package including

[0088] Figure 3a, Figure 3b, Figure 4a, Figure 4b, Figure 5a, Figure 5b, Figure 5c, Figure 5d, Figure 6, Figure 7a, 7b and 8, an all-in-one COF (All in one chip on film) according to an embodiment is shown. The flexible circuit board 100 for lm is a double-sided all-in-one board having electrode pattern portions on both sides. The flexible circuit board for the NX COF can be made of:

[0089] Flexible circuit board for all-in-one COF (all in one chip on film) according to an embodiment The plate 100 comprises a substrate 110, a wiring pattern layer 120 disposed on the substrate 110, a plating layer 120, and a wiring pattern layer 120. the protective layer 130, the upper dummy pattern portion DP2, the lower dummy pattern portion DP1, and the protective layer 14 May contain 0.

[0090] On one surface of the substrate 110 according to the embodiment, a wiring pattern layer 120, a plating layer 130, an upper da After disposing the Mie pattern part DP2 and the protective layer 140, The wiring pattern layer 120, the plating layer 130, the lower dummy pattern portion DP1, and the protective layer 140 can be placed.

[0091] That is, an upper wiring pattern layer, an upper plating layer, an upper The dummy pattern portion DP2 and the upper protective layer are disposed on the other surface opposite to the one surface. A lower wiring pattern layer, a lower plating layer, a lower dummy pattern part DP1 and a lower protective layer are arranged. can be.

[0092] The upper wiring pattern layer may include a metal material corresponding to the lower wiring pattern layer. Therefore, the process efficiency is improved. However, the embodiment is not limited to this, and other Of course, it may contain conductive materials.

[0093] The thickness of the upper wiring pattern layer may correspond to the thickness of the lower wiring pattern layer. Improved process efficiency.

[0094] The upper plating layer may include a metal material corresponding to the lower plating layer. However, the embodiment is not limited to this, and other conductive materials may be used. Of course, it can include.

[0095] The thickness of the upper plating layer may correspond to the thickness of the lower plating layer, thereby improving process efficiency. To rise.

[0096] The upper dummy pattern portion DP2 is formed on the lower surface of the substrate 110. The lower wiring pattern layer is arranged at a position corresponding to the lower wiring pattern layer, and the lower dummy pattern part DP1 corresponds to the upper wiring pattern layer disposed on the upper surface of the substrate 110 among the lower surfaces of the substrate. Therefore, in the present invention, in the printing process of the upper protective layer or the lower protective layer, , the problem of pinholes occurring due to the difference in height between the upper and lower parts of the substrate 110 can be solved. This can improve the reliability of the PCB.

[0097] The substrate 110 supports the wiring pattern layer 120, the plating layer 130, and the protective layer 140. The substrate may comprise a support substrate.

[0098] The substrate 110 may include a bent region and a region other than the bent region. The substrate 110 may include a bent region that is bent and a non-bent region other than the bent region. do.

[0099] The substrate 110 may be a flexible substrate. That is, the substrate 110 is made of flexible plastic. For example, the substrate 110 may be a polyimide substrate. However, the examples are not limited to this, and polyethylene terephthalate may be used. phthalate (polyethylene terephthalate), polyethylene naphthalate (polyethylene na The substrate may be made of a polymer material such as phthalate. The flexible circuit board including the board 110 can be used to mount various electrical components including a curved display device. For example, a flexible circuit board including the substrate 110 can be used in a child device. has excellent flexibility, making it suitable for mounting semiconductor chips in wearable electronic devices. In particular, embodiments are suitable for electronic devices that include curved displays. do.

[0100] The substrate 110 may be an insulating substrate. It may consist of an insulating substrate that supports the wiring pattern.

[0101] The substrate 110 may have a thickness of 20 μm to 100 μm. The plate 110 may have a thickness of 25 μm to 50 μm. For example, the substrate 100 may be The thickness of the substrate 100 may be 30 μm to 40 μm. If it exceeds this, the thickness of the overall flexible circuit board will increase. When the thickness of 100 is less than 20 μm, the first chip C1 and the second chip C2 are simultaneously If the thickness of the substrate 110 is less than 20 μm, it becomes difficult to arrange a large number of chips. In the process of mounting chips, the substrate 110 is vulnerable to heat / pressure, etc., and it is difficult to mount multiple chips at the same time. Wiring is disposed on the substrate 110. For example, the plurality of wirings may be arranged on the substrate 110. That is, a wiring pattern layer 120 is disposed on one surface of the substrate 110. It will be placed.

[0102] The area of ​​the substrate 110 is larger than the area of ​​the wiring pattern layer 120. Specifically, the planar area of ​​the substrate 110 is equal to the planar area of ​​the wiring pattern layer 120. That is, the wiring pattern on the substrate 110 can have a larger plane area. For example, the lower surface of the wiring pattern layer 120 is The wiring panel is in contact with the substrate 110, and the substrate 110 is exposed between the wirings. The turning layer 120 may include a conductive material.

[0103] The substrate 110 may include a plurality of through holes. The through-holes of the substrate 110 can be formed by a mechanical process or a chemical process. For example, the plurality of through holes in the substrate 110 may be formed individually or simultaneously by a conventional process. The through holes are formed by a drilling process or an etching process. The through holes in the plate are formed through a laser punching and desmearing process. The desmearing step is a step of removing polyimide smears adhering to the inner surfaces of the through holes. The desmearing process may form a line or similar on the inner surface of the polyimide substrate. The slanted surface may be similar.

[0104] On the substrate 110, a wiring pattern layer 120, a plating layer 130, and a dummy pattern portion D P1, DP2 and a protective layer 140 are disposed on both sides of the substrate 110. The wiring pattern layer 120, the plating layer 130, the dummy pattern portions DP1 and DP2, and the protective layer 1 At this time, the dummy pattern portions DP1 and DP2 are arranged in the same order. The height corresponds to the wiring pattern layer 120 and the plating layer 130. Preferably, The dummy pattern portions DP1 and DP2 in the first embodiment of the present invention are The wiring pattern layer 120 is made of the same metal material as the wiring pattern layer 120 and has a thickness greater than that of the wiring pattern layer 120. Preferably, the dummy pattern portions DP1 and DP2 are formed on the wiring pattern. The thickness of the coating layer 120 and the thickness of the plating layer 130 may be the sum of these.

[0105] The wiring pattern layer 120 is formed by evaporation, plating, sputtering, etc. The pores are formed by at least one of the following methods:

[0106] For example, the wiring layer for forming the circuit is formed by electrolytic plating after sputtering. For example, the wiring layer for forming the circuit is formed by electroless plating. Alternatively, the wiring layer may be formed by electroless plating and electrolytic plating. The copper plating layer may be formed by plating.

[0107] Next, a light film is laminated on the wiring layer, and then exposed, developed, and etched. Through the bonding process, patterned arrangements are formed on both sides of the flexible circuit board, i.e., the top and bottom surfaces. Therefore, the wiring pattern layer 120 can be formed. do.

[0108] For example, the wiring pattern layer 120 may include a metal material having excellent electrical conductivity. More specifically, the wiring pattern layer 120 may include copper (Cu). Examples include, but are not limited to, copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), and the like. At least one of nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti) and their alloys Of course, both can contain one metal.

[0109] The wiring pattern layer 120 is disposed with a thickness of 1 μm to 15 μm. The pattern layer 120 is disposed with a thickness of 1 μm to 10 μm. For example, 120 is disposed with a thickness of 2 μm to 10 μm.

[0110] When the thickness of the wiring pattern layer 120 is less than 1 μm, When the thickness of the wiring pattern layer 120 exceeds 10 μm, the resistance increases. This makes it difficult to realize the desired effect.

[0111] The via holes V1, V2, and V3 penetrating the substrate 110 are filled with a conductive material. The conductive material filled in the via hole corresponds to the wiring pattern layer 120. For example, the via hole may be filled with the same material or a different conductive material. The conductive materials used are copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), Contains at least one metal selected from the group consisting of molybdenum (Mo), gold (Au), titanium (Ti) and alloys thereof. The electrical signal of the conductive pattern portion CP on the upper surface of the substrate 110 can be transmitted to the The conductive pattern portion CP on the bottom surface of the substrate 110 is formed through the conductive material filled in the holes. is transmitted to.

[0112] Next, a plating layer 130 is formed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132 .

[0113] A first plating layer 131 is disposed on the wiring pattern layer 120. The second plating layer 132 is disposed on the first plating layer 131. The second plating layer 132 is formed to prevent the formation of whiskers (whisker-kr00000374075b1). 120. Therefore, the wiring pattern layer 1 In addition, the wiring pattern layer 120 can prevent short circuits between the patterns. Two plating layers are placed on top, improving the bonding characteristics with the chip. When the wiring pattern layer contains copper (Cu), the wiring pattern layer is directly bonded to the first chip C1. It is not possible to bond the wiring, and a separate process for bonding is required. When the plating layer disposed on the pattern layer contains tin (Sn), the surface of the plating layer Since the first chip C1 is a pure tin layer, it can be easily bonded to the first chip C1. The wire that connects to the chip C1 is simply connected to the pure tin layer using heat and pressure, This improves the accuracy of wire bonding and the convenience of the manufacturing process.

[0114] The area where the first plating layer 131 is disposed is the area where the second plating layer 132 is disposed. That is, the area where the first plating layer 131 is disposed may correspond to the area where the second plating layer 131 is disposed. This may correspond to the area where the layer 132 is disposed.

[0115] The plating layer 130 may include tin (Sn). For example, the first plating layer 131 The second plating layer 132 may include tin (Sn).

[0116] For example, the wiring pattern layer 120 is formed of copper (Cu), and the first plating layer 131 and The second plating layer 132 may be formed of tin (Sn). When the wiring pattern layer 120 contains tin (Sn), the corrosion resistance of the tin (Sn) is excellent, so that the wiring pattern layer 120 can be prevented from being oxidized. It is possible.

[0117] Meanwhile, the material of the plating layer 130 has lower electrical conductivity than the material of the wiring electrode layer 120. The plating layer 130 can be electrically connected to the wiring electrode layer 120.

[0118] The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), or formed in a separate process.

[0119] When the manufacturing process of the flexible circuit board according to the embodiment includes a heat treatment process such as heat curing diffusion of copper (Cu) in the wiring pattern layer 120 or tin (Sn) in the plating layer 130 occurs. Specifically, through the curing of the protective layer 140, diffusion of copper (Cu) in the wiring pattern layer 12 0 or tin (Sn) in the plating layer 130 occurs. As a result, in the first plating layer 131, the diffusion concentration of copper (Cu) decreases as it goes towards the surface of the second plating layer 132, so that the copper (Cu) content continuously decreases. On the other hand

[0120] in the first plating layer 131, the tin (Sn) content continuously increases as it goes towards the surface of the second plating layer 132. Therefore, the uppermost part of the plating layer 130 can contain pure tin. That is, due to the chemical action at the lamination interface between the wiring pattern layer 120 and the plating layer 130, at least a part of the plating layer 130 can consist of an alloy of tin and copper. The thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120 is smaller than the thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130. The alloy of tin and copper contained in at least a part of the plating layer 130 has the chemical formula of Cu Sn y and 0 < x + y < 12. For example, in the chemical formula, the sum of x and y is 4 ≤ x

[0121] That is, due to the chemical action at the lamination interface, at least a part of the plating layer 130 can consist of an alloy of tin and copper. The thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130 increases compared to the thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120. The alloy of tin and copper formed on the wiring pattern layer 120 After forming the plating layer 130 on the wiring pattern layer 120, the thickness of the alloy of tin and copper is smaller than the thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130. increases.

[0122] The alloy of tin and copper contained in at least a part of the plating layer 130 has the chemical formula of Cu , Sn y and 0 < x + y < 12. For example, in the chemical formula, the sum of x and y is 4 ≤ x + y ≤ 10. +y≦11. For example, the alloy of tin and copper contained in the plating layer 130 is Cu3S Specifically, the first plating may include at least one of Cu6Sn5 and Cu6Sn5. The layer 131 may be made of an alloy layer of tin and copper.

[0123] The first plating layer 131 and the second plating layer 132 have the same tin and copper content. The first plating layer 131 that is in direct contact with the copper wiring pattern layer may be different from the first plating layer 131. The copper content is greater than that of the second plating layer 132 .

[0124] The second plating layer 132 has a higher tin content than the first plating layer 131. The second plating layer 132 can contain pure tin. Here, pure tin means a material containing tin (Sn). The content is 50 atomic % or more, 70 atomic % or more, or 90 atomic % or more. In this case, the element other than tin can be copper. For example, The second plating layer 132 may have a tin (Sn) content of 50 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 70 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 90 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 95 atomic % or more. The second plating layer 132 may have a tin (Sn) content of 98 atomic % or more.

[0125] The plating layer according to the embodiment is electrochemically migrated due to the diffusion development of Cu / Sn. Prevents electrochemical migration resistance (EMR) and prevents short circuits caused by metal growth It is possible.

[0126] However, the embodiment is not limited to this, and the plating layer 130 may be Ni / A u alloy, gold (Au), electroless nickel immersion gold (ENIG) , Ni / Pd alloy, organic compound plating (Organic Solderability Preservative, OSP) Of course, it can contain either one.

[0127] The first plating layer 131 and the second plating layer 132 may have corresponding or different thicknesses. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0. The first plating layer 131 and the second plating layer 132 may have a thickness of 0.3 μm to 1 μm. The total thickness of the first plating layer 132 may be 0.3 μm to 0.7 μm. The total thickness of the second plating layer 132 and the second plating layer 31 may be 0.3 μm to 0.5 μm. Either the first plating layer 131 or the second plating layer 132 can be For example, the first plating may have a thickness of 0.05 μm to 0.15 μm. The thickness of either the layer 131 or the second plating layer 132 is 0.07 μm to 0.1 It may have a thickness of 3 μm or less.

[0128] Thereafter, the protective portion PP can be screen-printed on the conductive pattern portion CP. do.

[0129] The protective layer 140 is partially disposed on the wiring pattern layer 120. For example, The protective layer 140 is disposed on the plating layer 130 on the wiring pattern layer 120. The protective layer 140 may cover the plating layer 130, and the wiring pattern layer 120 and the plating layer 130 can be prevented from being damaged or peeled off due to oxidation.

[0130] The protective layer 140 is formed by removing the wiring pattern layer 120 and / or the plating layer 130 from the The display panel 30, the main board 40, the first chip C1 or the second chip C2 and the electrical The image is partially arranged in an area excluding the area for efficient connection.

[0131] As a result, the protective layer 140 can protect the wiring pattern layer 120 and / or the plating. It may partially overlap with the layer 130.

[0132] The area of ​​the protective layer 140 may be smaller than the area of ​​the substrate 110 . The protective layer 140 is disposed in an area other than the end of the substrate and includes a plurality of open areas. This can be done.

[0133] The protective layer 140 may include a first open area OA1 shaped like a hole. The first open area OA1 is formed by the wiring pattern layer 120 and / or the plating The layer 130 is electrically connected to the first chip C1 in the non-placement area of ​​the protective layer 140. It's okay to have it.

[0134] The protective layer 140 may include a second open area OA2 shaped like a hole. The second open area OA2 is formed by the wiring pattern layer 120 and / or the plating In the non-placement area of ​​the protective layer 140, the layer 130 is electrically connected to the second chip C2. Therefore, in the second open area OA2, the plating layer 130 may be formed on the outer surface. exposed to the parts.

[0135] In the second open area OA2, the copper content of the plating layer 130 is 50 atomic percent. For example, the copper content in the plating layer 130 may be 60 atomic % or more. For example, the copper content in the plating layer 130 may be 60 atomic % to 80 atomic %. Specifically, the first open area OA2 measured in the second open area OA2 may be expressed in atomic percent. The copper content of the plating layer 131 may be 60 atomic % to 80 atomic %.

[0136] The protective layer 140 is electrically connected to the main board 40 or the display panel 30. The conductive pattern portion may not be disposed on the conductive pattern portion for effectively connecting the conductive pattern portion. A conductive panel for electrically connecting to the inboard 40 or the display panel 30 a third open area OA3, which is a non-placement area of ​​the protective layer 140 on the turn portion; Therefore, the plating layer 130 is exposed to the outside in the third open area OA3. can be.

[0137] In the third open area OA3, the copper content of the plating layer 130 is 50 atomic percent. % or more. Alternatively, in the third open area OA3, the plating layer 1 The copper content of the third open area OA3 may be less than 50 atomic %. The first open area OA1 may be located at the outer edge of the substrate. The open area OA3 may be located closer to the outer edge of the substrate than the second open area OA2. do.

[0138] The first open area OA1 and the second open area OA2 are Area OA3 can be located in a more central area of ​​the substrate.

[0139] The protective layer 140 is disposed in the folding area. Therefore, the all-in-one device according to the embodiment can disperse stress that may occur when the device is moved. The reliability of COF flexible circuit boards can be improved.

[0140] The protective layer 140 may include an insulating material. It may contain a variety of substances that are applied and then heated to harden to protect the surface of the turn. The protective layer 140 may be a resist layer. For example, The protective layer 140 may be a solder resist layer containing an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate resin. Specifically, the protective layer 140 may contain a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, etc. The examples may include, but are not limited to, the following. The protective layer 140 is not a photo solder resist layer, a cover layer, or the like. ay) and polymeric substances.

[0141] The protective layer 140 may have a thickness of 1 μm to 20 μm. The thickness of the protective layer 140 may be 1 μm to 15 μm. When the thickness of the protective layer 140 exceeds 20 μm, the thickness of the protective layer 140 may be in the range of 1 μm to 20 μm. In this case, the thickness of the flexible circuit board for all-in-one COF will increase. When the thickness of the protective layer 140 is less than 1 μm, the flexible protective layer 140 for all-in-one COF is The reliability of the conductive pattern portion included in the circuit board is reduced.

[0142] That is, the single-sided all-in-one COF flexible circuit board 100 according to the embodiment is a board 110, a conductive pattern portion CP and a dummy pattern portion DP1 arranged on one surface of the substrate; DP2 and the dummy pattern portions DP1, DP2 and one portion above the conductive pattern portion CP. A protective portion PP may be included, which is formed by disposing a protective layer 140 in a portion of the region.

[0143] The conductive pattern portion CP includes the wiring pattern layer 120 and the plating layer 130. It can be done.

[0144] The protective portion PP is disposed on one region and another region of the conductive pattern portion CP. It's not necessary.

[0145] The protective portion PP is disposed on the dummy pattern portions DP1 and DP2. do.

[0146] As a result, the conductive pattern portion CP has a conductive layer on one area and a conductive layer on the other area. The pattern portion CP and the substrate 110 between the spaced apart conductive pattern portions CP are exposed. A first connecting portion 70 and a second connecting portion 71 are formed on one area and another area of ​​the conductive pattern portion CP. Specifically, the conductive pattern 80 on which the protective portion PP is not disposed is A first connecting portion 70 and a second connecting portion 80 are disposed on the upper surface of the connecting portion CP.

[0147] The first connecting portion 70 and the second connecting portion 80 may have different shapes. For example, the first connection portion 70 may have a hexahedral shape. The cross section of the first connection part 70 may include a rectangular shape. The cross section of the second connecting portion 8 may include a rectangular or square shape. The cross section of the second connection portion 80 may include a spherical shape. Alternatively, the second connection portion 80 may include a partially or entirely rounded shape. For example, the cross-sectional shape of the second connection part 80 may be flat on one side and flat on the front. The other side opposite to the one side may be curved.

[0148] The first connecting portion 70 and the second connecting portion 80 may have different sizes. The first connecting portion 70 may have a smaller size than the second connecting portion 80. .

[0149] The first connection portion 70 and the second connection portion 80 may have different widths. For example, the width D1 between both side surfaces of one first connection portion 70 is It may have a width smaller than the width D2 between the sides.

[0150] The first chip C1 is disposed on the first connection portion 70. The first connection part 70 may include a conductive material. 0 and the first chip C1 disposed on the lower surface of the first connecting portion 70. The conductive pattern portions CP can be electrically connected.

[0151] The second chip C2 is disposed on the second connection portion 80. The second connection portion 80 The second connection part 80 may include a conductive material. 0 and the second chip C2 disposed on the lower surface of the second connecting portion 80. The conductive pattern portions CP can be electrically connected.

[0152] On the same side of the single-sided all-in-one COF flexible circuit board 100 according to the embodiment In the embodiment, a first chip C1 and a second chip C2 of different types are arranged. On the same side of the single-sided all-in-one COF flexible circuit board 100 according to the embodiment, In this case, one first chip C1 and multiple second chips C2 may be arranged. This can improve the efficiency of the chip packaging process.

[0153] The first chip C1 may include a drive IC chip.

[0154] The second chip C2 means a chip other than the drive IC chip. The second chip C2 can be a socket or a chip other than a drive IC chip. For example, the second chip C2 may refer to a Diode chips, power supply IC chips, touch sensor IC chips, MLCC chips, BGA The capacitor may include at least one of a chip and a chip capacitor.

[0155] A plurality of second chips are arranged on the flexible circuit board 100 for all-in-one COF. C2 consists of a diode chip, a power IC chip, a touch sensor IC chip, and an MLCC chip. This means that at least one of the following is placed multiple times: chip, BGA chip, or chip capacitor. As an example, the all-in-one COF flexible circuit board 100 On top of this, multiple MLCC chips are placed.

[0156] The second chip C2 includes a diode chip, a power IC chip, a touch sensor IC, and a C chip, MLCC chip, BGA chip, chip capacitor That is, on the flexible circuit board 100 for all-in-one COF, A plurality of second chips C2a and C2b of different types are arranged. On the flexible circuit board 100 for COF, a diode chip, a power IC chip, Touch sensor IC chip, MLCC chip, BGA chip, chip capacitor Any one of the second chips C2a, diode chip, power IC chip, and touch sensor Any one of IC chips, MLCC chips, BGA chips, and chip capacitors and a second chip C2b different from the first chip C1.

[0157] Specifically, a diode is mounted on the flexible circuit board 100 for all-in-one COF. Chip, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, A plurality of second chips C2a of any one of the chip capacitors are arranged, and the diode chips chips, power IC chips, touch sensor IC chips, MLCC chips, BGA chips, chips A plurality of second chips C2b are arranged, each of which is different from any one of the chip capacitors. For example, a flexible circuit board for all-in-one COF is included. On the top of 100, a plurality of MLCC chips C2a and a plurality of power supply IC chips C2b are included. As an example, on the flexible circuit board 100 for all-in-one COF, , may include a plurality of MLCC chips C2a and a plurality of diode chips C2b. As an example, the all-in-one COF flexible circuit board 100 may have a plurality of ML It may include a CC chip C2a and multiple BGA chips C2b.

[0158] In the embodiment, the number of types of the second chips is not limited to two, and the number of types of the driving IC chips is not limited to two. Of course, all of the various chips except the chip can be included in the second chip.

[0159] One end of the all-in-one COF flexible circuit board 100 is connected to a display panel. One end of the all-in-one COF flexible circuit board 100 is connected to the cable 30. , and is connected to the display panel 30 by an adhesive layer 50. Specifically, the adhesive layer 50 The display panel 30 is disposed on the upper surface of the adhesive layer 50, and the The flexible circuit board 100 for all-in-one COF is arranged. The play panel 30 and the all-in-one COF flexible circuit board 100 are The upper and lower parts are joined together with an adhesive layer 50 sandwiched therebetween.

[0160] The other end opposite to the one end of the all-in-one COF flexible circuit board 100 is connected to the main board 40. The flexible circuit board for all-in-one COF The other end of the 100 opposite to the one end is connected to the main board 40 by an adhesive layer 50. Specifically, the main board 40 is disposed on the upper surface of the adhesive layer 50. The all-in-one COF flexible circuit board 100 is disposed on the bottom surface of the The main board 40 and the all-in-one COF flexible circuit board 100 are bonded together from above and below with the adhesive layer 50 sandwiched therebetween.

[0161] The adhesive layer 50 may include a conductive material. The adhesive layer 50 may include conductive particles. For example, the adhesive layer 50 may be an anisotropic conductive film. The film can be made of ACF.

[0162] As a result, the adhesive layer 50 can be easily attached to the display panel 30, the all-in-one The flexible circuit board 100 for F transmits electrical signals between the main board 40. At the same time, it is possible to stably connect other components.

[0163] On the other hand, the above-mentioned dummy pattern portions DP1 and DP2 are arranged on the substrate 110. That is, the upper dummy pattern portion DP2 is disposed on the upper surface of the substrate 110. The lower dummy pattern portion DP1 is disposed on the lower surface of the substrate 110.

[0164] The upper dummy pattern portion DP2 is formed on the upper surface of the substrate 110 adjacent to the upper wiring pattern. The upper dummy pattern portion DP2 is preferably disposed in a region where no insulating layer is disposed. , a lower wiring pattern layer disposed on the lower surface of the substrate 110 and a top surface of the substrate vertically overlapping the lower wiring pattern layer. It is disposed on an area of ​​the surface where the upper wiring pattern layer is not disposed.

[0165] The lower dummy pattern portion DP1 is formed on the lower surface of the substrate 110 adjacent to the lower wiring pattern. The lower dummy pattern portion DP1 is preferably disposed in a region where no insulating layer is disposed. , an upper wiring pattern layer disposed on the upper surface of the substrate 110 and a lower wiring pattern layer disposed on the upper surface of the substrate 110. It is disposed on an area of ​​the surface where the upper wiring pattern layer is not disposed.

[0166] That is, the upper wiring pattern layer and the lower wiring pattern layer disposed on the substrate 110 The positions of the dots do not correspond to each other, but are determined according to the functions and the number of signal wiring lines. are designed and placed on each surface of the substrate 110.

[0167] Therefore, the upper wiring pattern layer and the upper plating layer are vertically overlapped with each other. The lower wiring pattern layer and the lower plating layer are disposed on the lower surface of the substrate 110. Furthermore, a region where the lower wiring pattern layer and the lower plating layer are disposed may be formed vertically. The upper surface of the substrate 110 is provided with the upper wiring pattern layer and the upper plating layer. It does not have to be placed.

[0168] At this time, the protective layer 140 is disposed on the substrate 110 by a printing process. The protective layer 140 is preferentially printed on one side of the substrate 110, and the printing on the one side After the printing process is completed, the other side of the substrate 110 is printed.

[0169] Here, the surface on which the protective layer 140 is printed first is On the other hand, there is an area where no wiring pattern layer / plating layer is arranged, and on the other hand, there is an area where no wiring pattern layer / plating layer is arranged. The coexistence of areas where plating layers are arranged results in the occurrence of steps. If the step exists on the surface opposite to the surface on which the protective layer 140 is printed, the protective layer 1 In the printing process of 40, problems such as the protective layer 140 not being positioned or pinholes may occur. This has a significant impact on the reliability of the PCB.

[0170] Therefore, in order to solve the above problem, the present invention provides a method for eliminating the step. On the surface opposite to the surface on which the protective layer 140 is printed, the dummy pattern portion DP1 as described above is formed. , forming DP2.

[0171] At this time, the protective layer 140 is printed preferentially on the upper surface of the substrate 110. When the process is performed, the dummy pattern portions DP1 and DP2 are formed as lower dummy pattern portions D That is, the protective layer 140 may be printed on the upper surface of the substrate 110. In this case, the lower dummy pattern portion DP1 disposed on the lower surface of the substrate 110 The unevenness of the step is eliminated, and thus the upper surface of the substrate 110 has a uniform height. Layer 140 is placed.

[0172] After the printing process of the protective layer 140 on the upper surface of the substrate 110 is completed, When the printing process of the protective layer 140 on the lower surface of the substrate 110 is performed, the upper surface of the substrate 110 The protective layer 140 formed on the surface of the upper wiring pattern layer / upper plating layer is As a result, a uniform protective layer 140 is formed on the lower surface of the substrate 110. do.

[0173] However, the surface on which the protective layer 140 is printed first is The above-mentioned changes depending on the manufacturing environment of the PCB. Considering the manufacturing environment of the PCB, the lower wiring pattern is formed on the upper surface of the substrate 110. and forming an upper dummy pattern portion DP2 at a position corresponding to the lower plating layer, The lower surface of 110 is provided with a lower datum at a position corresponding to the upper wiring pattern layer and the upper plating layer. The corresponding position is formed on one surface of the substrate 110. This refers to the position on the other surface of the substrate that is vertically overlapped with the wiring pattern layer and plating layer arranged on the .

[0174] The dummy pattern portions DP1 and DP2 may be made of a single layer. The dummy pattern portions DP1 and DP2 may include only a dummy pattern layer. The dummy pattern layer may include the same metal material as the wiring pattern layer, provided that: The present invention is not limited to this, and the dummy pattern layer may be formed by the wiring pattern. For example, the dummy pattern layer may be made of a non-metallic material. It can include.

[0175] In contrast, as shown in FIG. 3b, the dummy pattern portions DP1 and DP2 The first dummy pattern layer 151, the second dummy pattern layer 152 and the third dummy pattern Layer 153 may be included.

[0176] The first dummy pattern layer 151 corresponds to the wiring pattern layer 120. The dummy pattern layer 151 includes the same metal material as the wiring pattern layer 120. The dummy pattern layer 151 may be a part of the wiring pattern layer 120. The surface of the substrate 110 is provided with a wiring pattern for electrically connecting to the chip and transmitting signals. At this time, the first dummy pattern layer 120 is disposed together with the wiring pattern layer 120. A turn layer 151 can be formed on the substrate 110. That is, a pattern layer can be formed on the substrate 110. This is formed by the wiring pattern layer 120 for transmitting the electrical signals and the first dummy The first dummy pattern layer 151 includes the wiring pattern. Unlike the turn layer 120, it does not transmit electrical signals, and therefore the wiring pattern layer 1 That is, the first dummy pattern layer 151 is not electrically connected to the substrate 11. The wiring pattern layer 120 is formed on the surface of the substrate 100 in an area where the wiring pattern layer 120 is not formed. The insulating layer 120 is disposed independently without being connected to the insulating layer 120.

[0177] The second dummy pattern layer 152 is disposed on the first dummy pattern layer 151. The second dummy pattern layer 152 may be a part of the first plating layer 131. The third dummy pattern layer 152 is disposed on the second dummy pattern layer 152. The third dummy pattern layer 153 may be a part of the second plating layer 132. .

[0178] That is, the dummy pattern portions DP1 and DP2 in the present invention are the conductive pattern portions CP The dummy pattern portion may be formed of a single layer, unlike the layer structure of the dummy pattern portion. DP1 and DP2 have a three-layer structure similar to the layer structure of the conductive pattern portion CP. It is possible.

[0179] On the other hand, the protective layer 140 is disposed on the dummy pattern portions DP1 and DP2. That is, the protective layer 140 is formed on the surface of a part of the conductive pattern portion CP to be opened. The dummy pattern portions DP1 and DP2 are not exposed to the outside. As a result, the protective layer 14 is formed on the dummy pattern portions DP1 and DP2. 0 is placed.

[0180] Meanwhile, referring to FIG. 3a, the area of ​​the wiring pattern layer 120 is The area of ​​the first plating layer 131 may correspond to the area of ​​the second plating layer 132. It may be possible to respond.

[0181] Referring to FIG. 7, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. The area of ​​the wiring pattern layer 120 may correspond to the area of ​​the first plating layer 131. The area of ​​the first plating layer 131 may be different from the area of ​​the second plating layer 132. For example, the area of ​​the first plating layer 131 may be larger than the area of ​​the second plating layer 132. It can have a large area.

[0182] Referring to FIG. 8, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. That's fine.

[0183] Referring to FIG. 9, on one surface of the substrate 110, the area of ​​the wiring pattern layer 120 Unlike the plating layer 130, the wiring pattern layer 130 is formed on the other surface of the substrate 110. The area of ​​120 may correspond to the plating layer 130 .

[0184] The protective layer 140 is disposed on the substrate 110 in direct contact with the wiring pattern. The first plating layer 131 is disposed on the first plating layer 120 in direct contact therewith, or on the first plating layer 131 in direct contact therewith. or is placed on the second plating layer 132 in direct contact therewith. The protective layer 140 is disposed in direct contact with the dummy pattern portions DP1 and DP2.

[0185] Referring to FIGS. 3a and 3b, the first plating layer 110 is formed on the wiring pattern layer 120. 31 is disposed, and the second plating layer 132 is formed on the first plating layer 131. The protective layer 140 is partially disposed on the second plating layer 132. The protective layer 140 is disposed over the entire pattern portions DP1 and DP2.

[0186] Referring to FIGS. 7a and 7b, the first plating layer 13 is formed on the wiring pattern layer 120. 1 is disposed on the first plating layer 131, and the protective layer 140 is disposed partially on the first plating layer 131. The second plating layer 132 is formed on the area where the protective layer 140 is disposed on the plating layer 131. It is placed in an area other than the

[0187] The first plating layer 131, which is in contact with the lower surface of the protective layer 140, is made of an alloy layer of copper and tin. The second plating layer 132 in contact with the side surface of the protective layer 140 may be pure. Therefore, the protective layer 140 and the first plating layer 131 can be formed in a common layer. This can prevent the protective layer from peeling off due to the formation of this portion, and can prevent the formation of whiskers, Therefore, the embodiment can include two plating layers. This makes it possible to provide a highly reliable electronic device.

[0188] Also, only a single layer of tin plating layer 131 is disposed on the wiring pattern layer 120, When the protective layer 140 is disposed on the two tin-plated layers 131, the protective layer 140 is hardened by heat. When the tin-plated layer 131 is heated, copper is diffused into the tin-plated layer 131. Therefore, the tin-plated layer 131 becomes an alloy layer of tin and copper, and the first Therefore, the plating layer 130 according to the embodiment is formed by removing the plating layer 130 from the substrate. The first plating layer 131 and the second plating layer 132 are required in which the tin concentration increases continuously with increasing distance. It is required.

[0189] As shown in FIG. 7a, the dummy pattern portions DP1 and DP2 are formed on the wiring pattern. The first plating layer 131 may include a single dummy pattern layer corresponding to the first plating layer 120 and the first plating layer 131. can.

[0190] As shown in FIG. 7b, the dummy pattern portions DP1 and DP2 are formed on the wiring pattern a first dummy pattern layer 151 corresponding to the layer 120; a second dummy pattern layer 152 corresponding to the first plating layer 131; 2 dummy pattern layer 152, and a third dummy pattern corresponding to the second plating layer 132. The insulating layer 153 may include a conductive layer 153 .

[0191] Referring to FIG. 8, the first plating layer 131 is disposed on the wiring pattern layer 120. The protective layer 140 is partially disposed on the first plating layer 131. The plating layer 132 is formed on the area other than the area where the protective layer 140 is disposed on the plating layer 131. are placed in the area.

[0192] At this time, the wiring pattern layer 120 is made up of a first wiring pattern layer 121 and a second wiring pattern layer 122. The substrate may include a wiring pattern layer 122. That is, a plurality of wiring pattern layers are disposed on the substrate. will be done.

[0193] Although not shown, there is a gap between the substrate 110 and the first wiring pattern layer 121. a metal seed layer for improving the adhesion between the substrate 110 and the first wiring pattern layer 121; In this case, the metal seed layer is formed by sputtering. The metal seed layer may include copper.

[0194] The first wiring pattern layer 121 and the second wiring pattern layer 122 are formed by a process corresponding to each other. The layers may be formed in the same step or in different steps.

[0195] The first wiring pattern layer 121 is formed by sputtering copper to a thickness of 0.1 μm to 0.5 μm. The first wiring pattern layer 121 is formed by connecting the upper and lower portions of the substrate and the through-holes. At this time, since the thickness of the first wiring pattern layer 121 is thin, The inner surfaces of the holes are spaced apart from each other.

[0196] Next, the second wiring pattern layer 122 is disposed on the first wiring pattern layer 121. In addition, the second wiring pattern layer 122 is entirely formed inside the through-hole by plating. is fulfilled.

[0197] The first wiring pattern layer 121 is formed by sputtering, so that the substrate 110 or the metal seed layer has the advantage of excellent adhesion, but the manufacturing cost is high. Then, the second wiring pattern layer 121 is formed on the first wiring pattern layer 121 by plating. By forming the through hole 22, the manufacturing cost can be reduced. The second wiring pattern layer 121 is formed on the first wiring pattern layer 121 without filling the holes with a conductive material. Since copper is filled into the via holes at the same time as the line pattern layer 122 is disposed, the process efficiency is improved. Furthermore, it is possible to prevent voids from being formed in the via holes, resulting in a highly reliable overcoat. A flexible circuit board for one-in-one COF and an electronic device including the same are provided. can.

[0198] The dummy pattern portions DP1 and DP2 correspond to the first wiring pattern layer 121. a first dummy pattern layer 151 corresponding to the second wiring pattern layer 122; a pattern layer 152, and a third dummy pattern layer 153 corresponding to the first plating layer 131; , a fourth dummy pattern layer 154 corresponding to the second plating layer 132 may be included.

[0199] Referring to Figure 9, a plurality of protective layers 140 are disposed on one side of the substrate. The layers can include a first protective layer 141 and a second protective layer 142 .

[0200] For example, a first protective layer 141 is partially disposed on one surface of the substrate, and the first protective layer 14 The wiring pattern layer 120 is disposed on the area other than the area where the wiring pattern layer 1 is disposed.

[0201] The second protective layer 142 is disposed on the protective layer 141. 2 covers the first protective layer 141 and the wiring pattern layer 120, and It is placed in an area greater than 1.

[0202] The protective layer 142 faces the first protective layer 141 while covering the upper surface of the first protective layer 141. The second protective layer 142 is disposed on the corresponding area. The width of the second protective layer 142 is larger than that of the protective layer 141. Therefore, the lower surface of the second protective layer 142 may be formed on the wiring pattern layer 141. 120 and the first protective layer 141. Therefore, the second protective layer 14 2 is that stress is concentrated at the interface between the first protective layer 141 and the wiring pattern layer 120. Therefore, the all-in-one COF flexible circuit according to the embodiment can be This can reduce the occurrence of peeling or cracks that may occur when the substrate is bent.

[0203] The plating layer 130 is disposed in the area other than the area where the second protective layer 142 is disposed. Specifically, the wiring pattern is formed in the area other than the area where the second protective layer 142 is disposed. The first plating layer 131 is disposed on the insulating layer 120, and a front plated layer 132 is disposed on the first plating layer 131. The second plating layer 132 is then disposed.

[0204] A wiring pattern layer 120 is disposed on the other surface of the substrate opposite to the one surface. The plating layer 130 is disposed on the line pattern layer 120. A protective layer 140 is disposed partially on top.

[0205] The width of the protective layer disposed on one side of the substrate and the width of the protective layer disposed on the other side of the substrate are They may correspond or differ from each other.

[0206] In the drawings, a plurality of protective layers are arranged on only one side of the substrate. Without being limited thereto, the substrate may include a plurality of protective layers on both sides thereof. In addition, multiple or one protective layer may be placed on only one side of the substrate. Of course, that is also good.

[0207] The structure of one or both surfaces of the substrate is shown in Figs. 3a, 3b, 7a, 7b, 8, The conductive pattern part and the protective part according to at least one of FIG. 9 may be combined and arranged in various ways. Of course, this is the case.

[0208] 4a and 4b, the flexible circuit board according to the comparative example has a substrate 110. An upper conductive pattern portion CP is disposed on the upper surface of the substrate 110, and a lower conductive pattern portion CP is disposed on the lower surface of the substrate 110. At this time, the upper conductive pattern portion CP and the lower conductive pattern portion CP are disposed. The core part CP is designed without taking into consideration the printing process of the protective layer 140. The upper conductive pattern portion CP is present on the upper surface of the substrate 110. The lower surface of the conductive pattern portion CP may include an area where the lower conductive pattern portion CP does not exist. The lower surface of the substrate 110 perpendicularly overlapping the surface on which the upper conductive pattern portion CP is disposed is provided with: There is a region where the lower conductive pattern portion CP is not disposed.

[0209] At this time, the flexible circuit board according to the comparative example has a lowermost surface formed of the lower conductive pattern. In the region where the lower conductive pattern portion CP exists, the lower conductive pattern portion CP is formed on the lower surface of the lower conductive pattern portion CP. The area where the conductive pattern portion CP does not exist becomes the lower surface of the substrate 110.

[0210] Then, a protective layer 140 is printed on the upper surface of the substrate 110, and the lower conductive pattern is In the area where the core part CP is not arranged and where the area overlaps vertically, the lowermost surface is The lower surface of the film 10 is the same as the lower surface of the film 10, so that pinholes do not occur. In a state where the protective layer 140 is printed on an area where the conductive pattern portion CP does not exist, When the lower conductive pattern portion CP suddenly appears, the edge of the lower conductive pattern portion CP and the vertical A sudden step occurs in the upper region of the substrate 110 overlapping the substrate 110, causing a jumping phenomenon. Therefore, in the conventional method, the lower dummy pattern portion DP1 is first arranged at the end portion. The splashing phenomenon occurs in the area where the protective layer 140 is located. This will result in pinhole problems that are not fixed.

[0211] Meanwhile, as shown in FIG. 4b, in the present invention, the upper conductive pattern portion CP is disposed The lower dummy pattern portion DP1 is formed on the lower surface of the substrate 110, which is vertically overlapped with the region where the lower dummy pattern portion DP1 is formed. By disposing the protective layer 140, the generation of the step is eliminated, and a uniform protective layer 140 is formed. can be done.

[0212] The lower dummy pattern portion DP1 is formed by connecting the upper conductive pattern portion CP to the lower dummy pattern portion DP2. That is, as shown in FIG. 4b, the lower conductive pattern portion CP On the upper surface of the substrate 110, which overlaps vertically with the region where no conductive pads are disposed, three upper conductive pads are disposed. It can be seen that the turn portion CP is disposed. The lower surface is provided with first lower conductive pattern portions CP, each corresponding to one of the three upper conductive pattern portions CP. Dummy pattern portion DP1, second lower dummy pattern portion DP1 and third lower dummy pattern The parts DP1 are arranged in the respective positions.

[0213] On the other hand, the pinhole development in the protective layer 140 as described above occurs when the substrate on which the protective layer 140 is printed is The position where the first upper conductive pattern portion CP starts on the upper surface of 110 and the position where the first upper conductive pattern portion CP starts on the lower surface of the substrate This is because the positions at which the first lower conductive pattern portion CP starts are different from each other. , the lower conductive pattern portion CP is formed from the position where the first upper conductive pattern portion CP starts, based on the left end of the substrate. This is because the starting position of the conductive pattern portion CP is far away.

[0214] Therefore, the pinhole development occurs at the position where the first upper conductive pattern portion CP starts and the This can also be solved by making the starting positions of the lower conductive pattern portions CP the same.

[0215] That is, as shown in FIG. 5a, when the area A in FIG. 3a is enlarged, the upper surface of the substrate 110 Make sure that the four upper conductive pattern parts CP are arranged around the left edge. The bottom surface of the substrate 110 has two lower conductive pads, one at the left end and the other at the right end. It can be seen that the turn part CP is arranged. That is, the four upper conductive The lower conductive pattern portion CP is formed at the position of the third upper conductive pattern portion CP. It can be seen that the conductive pattern portion CP starts first.

[0216] Therefore, in the present invention, the first upper conductive pattern portion on the lower surface of the substrate 110 The lower dummy pattern part DP1 is arranged in the region vertically overlapping with the CP. The left end of the upper conductive pattern portion DP1 and the left end of the lower dummy pattern portion DP1 are That is, on the upper and lower surfaces of the substrate 110, The starting position of the first upper conductive pattern portion CP and the lower dummy pattern portion DP1 The starting position is the same. And the area that vertically overlaps with the second upper conductive pattern portion CP The lower conductive pattern portion CP and the lower dummy pattern portion DP1 are not disposed above the upper conductive pattern portion CP. It's okay.

[0217] That is, the lower portion of the substrate 110 overlapping the starting position of the first upper conductive pattern portion CP If no lower conductive pattern portion CP is disposed on the surface, the first upper conductive pattern portion CP is The lower dummy pattern is formed only on the lower surface of the substrate 110, which overlaps with the start position of the turn portion CP. The pinhole phenomenon can be solved by providing a pinhole part DP1.

[0218] However, the pinhole development is completed by using the one lower dummy pattern portion DP1. In order to solve this problem, the width of the lower dummy pattern portion DP1 is set to be equal to that of the first upper conductive pattern portion DP2. It is preferable that the width of the hole portion CP is larger than that of the hole portion CP.

[0219] In contrast, as shown in FIG. 5b, the first upper conductive layer on the lower surface of the substrate 110 A lower dummy pattern portion DP1 is disposed in the region vertically overlapping with the pattern portion CP. At this time, the left end of the first upper conductive pattern portion and the lower dummy pattern portion DP1 The left ends are not aligned on the same vertical line. , the starting position of the first upper conductive pattern portion CP and the lower dummy pattern portion DP1 The starting positions of the pinhole development are not the same. To solve this problem, the protective layer 140 is first placed on the surface to be printed. From the start position of the printing pattern section CP and the dummy pattern sections DP1 and DP2 The starting position of the pattern placed first on the surface opposite to the surface to be printed must be early.

[0220] Therefore, in the present invention, the substrate is formed from the starting position of the first upper conductive pattern portion CP. In order to make the start position of the lower dummy pattern portion DP1 arranged on the lower surface of 110 earlier, The first upper conductive pattern portion CP is formed on the lower surface of the substrate 110, the lower surface of the substrate 110 being vertically overlapped with the first upper conductive pattern portion CP. A lower dummy pattern portion DP1 is formed.

[0221] That is, the distance from the left end of the substrate 110 to the left end of the lower dummy pattern portion DP1 is The distance from the left end of the substrate 110 to the left end of the first upper conductive pattern portion CP is Make it closer than the distance.

[0222] In conclusion, the lower dummy pattern CP is formed from the left end of the first upper conductive pattern portion CP. The first upper conductive layer DP1 has a first gap a. The width of the lower dummy pattern portion DP1 is a first width b. The second width c is wider than the first width b.

[0223] According to this, in the present invention, by forming a minimum number of dummy pattern parts, the pinhole This can solve the problem of roll development.

[0224] Also, as shown in FIG. 5c, the lower dummy pattern portion DP1 may have a third width d. In this case, the third width d is the width of the first upper conductive pattern portion CP, the width of the second upper conductive pattern portion CP, and the width of the first upper conductive pattern portion CP The width corresponds to the total width of the gaps between the second upper conductive pattern portions CP.

[0225] That is, in FIG. 4b, the first upper conductive pattern portion CP is provided below the first upper conductive pattern portion CP. A first lower dummy pattern portion DP1 having the same width as the upper conductive pattern portion CP is formed. The second upper conductive pattern portion CP is provided at the bottom of the second upper conductive pattern portion CP. A second lower dummy pattern portion DP1 having the same width as the first lower dummy pattern portion DP1 was formed.

[0226] In contrast, as shown in FIG. 5c, the first upper conductive pattern portion CP 1 to the bottom surface of the substrate 110 corresponding to the end position of the second upper conductive pattern portion CP. Only one conductive pattern portion CP can be formed.

[0227] On the other hand, the dummy pattern portions DP1 and DP2 in the present invention have various shapes. That is, the dummy pattern portions DP1 and DP2 can be formed by printing the protective layer 140. It is placed to eliminate the step at the bottom of the printing surface, so the thickness of the pattern part is made conductive. It is only necessary to maintain the thickness of the dummy pattern portion CP the same as that of the pattern portion CP. DP1 and DP2 can have a horizontally extending bar shape as shown in Fig. 5d(a). It can have a vertically extending bar shape as in (b), or a circular shape as in (c). It may have a circular shape (ring shape) with an open center as shown in (d). , (e) can have a square shape (ladder shape) with an open center. The shapes of the dummy pattern portions DP1 and DP2 in the present invention are not limited to these. The shape can be changed into various shapes such as an ellipse, a sector, a polygon, or a triangle.

[0228] 6, when the area B in FIG. 3a is enlarged, an upper dummy electrode is formed on the upper surface of the substrate 110. The upper dummy pattern portion DP2 is disposed in the upper dummy pattern portion DP2. The conditions are the same as those for forming the lower dummy pattern portion DP1. The right end of the plate 110 is positioned in front of the starting position of the first lower conductive pattern portion CP. When the starting position of the upper conductive pattern portion CP is delayed, the lower conductive pattern portion CP is An upper dummy pattern portion DP2 is formed on the upper surface of the substrate 110, which is perpendicular to the start of the turn portion CP. At this time, the upper dummy pattern portion DP2 is formed on the lower conductive pattern portion DP1. The lower conductive pattern is placed first. One may be formed to correspond to the loop portion CP.

[0229] 3a, 3b, 7a, 7b, 8, 10 and 11, according to an embodiment. A first chip C mounted on the double-sided all-in-one COF flexible circuit board 100 1. The connection relationship between the display panel 30 and the main board 40 will be explained.

[0230] The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has through-holes. and a wiring board disposed on each side of the substrate including the through-hole. a turn layer 120, a first plating layer 131 disposed on the wiring pattern layer 120; A second plating layer 132 disposed on the first plating layer 131 and a second plating layer 132 disposed on the wiring pattern layer It may include a protective layer 140 partially disposed thereon.

[0231] The region where the protective layer 140 is formed is the protective portion PP. In the region other than the protective portion PP where the protective layer is not formed, the conductive pattern portion The CP is exposed to the outside, i.e., it is protected on the open area or conductive pattern of the protective layer. In the region where the protection portion is not arranged, the conductive pattern portion CP is The display panel 30 and the main board 40 are electrically connected.

[0232] The lead pattern portion and the lead of the flexible circuit board for all-in-one COF according to the embodiment The lead pattern portion does not have to overlap with the protective portion. The test pattern portion is a conductive pattern located in an open area not covered by a protective layer. It can be divided into a lead pattern part and a test pattern part according to the function. It can be distinguished.

[0233] The lead pattern portion is connected to the first chip, the second chip, and the display panel. Alternatively, it may refer to a conductive pattern portion for connection to the main board.

[0234] The test pattern section is a flexible circuit board for all-in-one COF according to an embodiment. Conductive pattern part for checking whether there is any defect in the chip package product including this can mean:

[0235] The lead pattern portion is divided into an inner lead pattern portion and an outer lead pattern portion according to the position. It can be distinguished from the turn part. It is placed relatively close to the first tip C1 and The area of ​​the conductive pattern that is not overlapped by the protective layer is referred to as the inner lead pattern. The first chip C1 is placed relatively far away from the first chip C2 and is covered by a protective layer. The area of ​​the conductive pattern portion that should not be exposed can be expressed as an outer lead pattern portion. do.

[0236] Referring to FIGS. 3a, 3b, 7a, 7b, 8, 10 and 11, the embodiment The all-in-one COF flexible circuit board 100 has a first inner lead pattern portion I1, a second inner lead pattern portion I2, a third inner lead pattern portion I3, and It may include four inner lead pattern portions I4.

[0237] The all-in-one COF flexible circuit board 100 according to the embodiment has a first outer liner. outer lead pattern portion O1, second outer lead pattern portion O2, third outer lead pattern The fourth outer lead pattern portion O3 and the fourth outer lead pattern portion O4 may be included.

[0238] The all-in-one COF flexible circuit board 100 according to the embodiment is a first test pattern. The test pattern portion T1 may include a first test pattern portion T2.

[0239] On one surface of the all-in-one COF flexible circuit board 100 according to the embodiment, The first inner lead pattern portion I1, the second inner lead pattern portion I2, and the 3 inner lead pattern portion I3, the first outer lead pattern portion O1, and the The outer lead pattern portion O2 is disposed.

[0240] The opposite side of the flexible circuit board 100 for all-in-one COF according to the embodiment On the other surface, the fourth inner lead pattern portion I4 and the third outer lead pattern the turn portion O3, the fourth outer lead pattern portion O4, and the first test pattern portion T1 and the second test pattern portion T2.

[0241] The flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface thereof. The first chip C1 is connected to the first inner lead pattern portion through the first connection portion 70. I1, the second inner lead pattern portion I2 or the third inner lead pattern portion It is connected to I3.

[0242] The first connection part 70 is divided into a first sub-second connection part 71, a second sub-second connection part 72, and a third sub-second connection part 73 according to the position and / or function. The first sub-connection portion 72 and the third sub-first connection portion 73 may be included.

[0243] The flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface thereof. The first chip C1 is connected to the first inner lead through the first sub-first connection portion 71. The conductive pattern portion I1 is electrically connected to the conductive pattern portion I2.

[0244] The first inner lead pattern portion I1 is formed along the upper surface of the substrate 110 by a second via hole. The first outer lead pattern portion O1 adjacent to the first outer lead pattern portion V2 can transmit an electrical signal. The second via hole V2 and the first outer lead pattern portion O1 are electrically That is, the first inner lead pattern portion I1 and the first outer lead The conductive pattern portion O1 may be one end and the other end of a conductive pattern portion extending in one direction. stomach.

[0245] For example, the main board 40 is connected to the first outer lead pattern portion O1. Therefore, the signal transmitted from the first chip is transmitted to the first chip. The inner lead pattern portion I1 and the first outer lead pattern portion O1 are connected to the main It is transmitted to the inboard 40.

[0246] The first inner lead pattern portion I1 is formed along the upper surface of the substrate 110. A conductive material electrically connected to the second via hole V2 and filled in the second via hole V2. A third outer via hole V2 is formed along the lower surface of the substrate 110 through the third outer via hole V1. The second via hole V2 can transmit an electrical signal to the lead pattern portion O3. is electrically connected to the third outer lead pattern part O3. However, the main board 40 is attached to the third outer lead pattern portion O3 by an adhesive layer. Of course, they can be electrically connected through 50.

[0247] The flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface thereof. The first chip C1 is connected to the second inner lead through the second sub-first connection portion 72. The conductive pattern portion I2 is electrically connected to the conductive pattern portion I3.

[0248] The second inner lead pattern portion I2 disposed on the upper surface of the substrate 110 is 2. Conductive material filled in the first via hole V1 located under the inner lead pattern portion I2. A fourth via hole V1 is formed along the bottom surface of the substrate 110 through a conductive material. The inner lead pattern portion I4 and the first test pattern portion T1 are electrically connected to the inner lead pattern portion I4. The first via hole V1, the first test pattern portion T1, and the fourth via hole V2 can be formed by The inner lead pattern portion I4 is electrically connected to the lower surface of the substrate.

[0249] The fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 are A display panel 30 is attached.

[0250] The first test pattern portion T1 is electrically connected through the first via hole V1. For example, the first test pattern section T1 can be used to check for signal defects. The accuracy of the signal transmitted to the fourth inner lead pattern portion I4 can be confirmed. Specifically, the voltage or current is measured in the first test pattern area T1. A short circuit or short circuit in the conductive pattern portion located between the first chip and the display panel It is possible to check whether or not a defect has occurred and where it has occurred, thereby improving the reliability of the product.

[0251] The flexible circuit board 100 for all-in-one COF according to the embodiment is arranged on one surface thereof. The first chip C1 is connected to the third inner lead through the third sub-first connection part 73. The wiring pattern portion I3 is electrically connected to the wiring pattern portion I4.

[0252] The third inner lead pattern portion I3 is formed by a third via hole along the upper surface of the substrate 110. The second outer lead pattern O2 adjacent to the terminal V3 can transmit an electrical signal. The third via hole V3 and the second outer lead pattern portion O2 are electrically That is, the third inner lead pattern portion I3 and the second outer lead The conductive pattern portion O2 may be one end and the other end of a conductive pattern portion extending in one direction. stomach.

[0253] The third inner lead pattern portion I3 is formed along the upper surface of the substrate 110. The conductive material is electrically connected to the third via hole V3 and is filled in the third via hole V3. A fourth outer via hole V3 is formed along the lower surface of the substrate 110 through the fourth outer via hole V4. Electrical signals can be transmitted to the lead pattern portion O4 and the second test pattern portion T2. can.

[0254] The second via hole V2, the fourth outer lead pattern portion O4, and the second test The pattern portion T2 is electrically connected to the lower surface of the substrate.

[0255] As described above, the fourth inner lead pattern portion I4 and the fourth outer lead pattern The display panel 30 is attached onto the bottom portion O4 via an adhesive layer 50.

[0256] The second test pattern portion T2 is electrically connected through the third via hole V3. For example, the second test pattern section T2 can be used to check for signal defects. The accuracy of the signal transmitted to the fourth outer lead pattern portion O4 can be confirmed. Specifically, the voltage or current is measured in the second test pattern area T2. A short circuit or short circuit in the conductive pattern portion located between the first chip and the display panel It is possible to check whether or not a defect has occurred and where it has occurred, thereby improving the reliability of the product.

[0257] In the all-in-one COF flexible circuit board according to the embodiment, the first chip C1 is The display panel 30 can be disposed on the other side opposite to the one side on which it is disposed, allowing for greater freedom of design. In addition, the surface opposite to the surface on which multiple chips are mounted can be By disposing the display panel, it is possible to effectively dissipate heat. This improves the reliability of the all-in-one COF flexible circuit board.

[0258] FIG. 10 is a plan view of FIG. 7a, and FIG. 11 is a bottom view of FIG. 7a.

[0259] 10 and 11, the flexible circuit board for all-in-one COF according to the embodiment is The plate 100 has sprocket holes on both sides of the plate 100 in the longitudinal direction for the convenience of manufacturing or processing. Therefore, the all-in-one COF flexible circuit board 100 The roll is wound or unwound by the sprocket holes in the roll to roll method. Or it is done.

[0260] The all-in-one COF flexible circuit board 100 is cut along the dotted line. can be defined as an inner region IR and an outer region OR.

[0261] The inner region IR of the all-in-one COF flexible circuit board 100 includes a first chip. , a conductive pad for connecting the second chip, the display panel and the main board, respectively The turn portion is disposed.

[0262] Sprocket holes are formed on the flexible circuit board 100 for all-in-one COF. By cutting the part that has been cut off and placing the chip on the substrate, an all-in-one COF flexible substrate is created. The flexible circuit board 100 is processed into a chip package and an electronic device including the same. It is possible.

[0263] Referring to FIG. 11, the upper surface of the flexible circuit board 100 for all-in-one COF is Then, a region of the conductive pattern portion CP is exposed through the first open region OA1 of the protective layer 140. The first inner lead pattern portion I1 and the second inner lead pattern portion I The second and third inner lead pattern portions I2 and I3 are exposed to the outside.

[0264] In addition, on the upper surface of the all-in-one COF flexible circuit board 100, the protective The conductive pattern portion CP is formed through the third open area OA3 of the layer 140. The first outer lead pattern portion O1 is exposed to the outside.

[0265] The first inner lead pattern portion I1 and the third inner lead pattern portion I3 are , may be a conductive pattern portion for connection to a chip through a first connection portion.

[0266] The end of the first inner lead pattern portion I1 and the third inner lead pattern portion The ends of I3 are arranged in a line. The first inner lead pattern portions I1 are spaced apart from each other, and the first inner lead pattern portions I For example, the ends of the third electrodes are arranged in a line in the horizontal direction (x-axis direction) of the substrate. The inner lead pattern portions I3 are spaced apart from each other, and the third inner lead pattern portion I3 The ends of the first inner lead pattern portion I1 and the third inner lead pattern portion I2 are arranged in a line. The inner lead pattern portion I3 has excellent bonding with the first connecting portion and the first chip.

[0267] The second via holes V2 are spaced apart from each other and arranged in a row in the horizontal direction (x-axis direction) of the substrate. The third via holes V3 are spaced apart from each other in the horizontal direction (x-axis direction) of the substrate. and arranged in a row.

[0268] The end of the first inner lead pattern portion I1 is connected to the second inner lead pattern portion It is spaced apart from the end of I2.

[0269] The second inner lead pattern portion I2 is a conductive portion that is not bonded to the first chip. The second inner lead pattern portion I2 may be a pattern. At least one end may not be aligned.

[0270] For example, the second inner lead pattern I 2 may be spaced apart from each other. At least one end of the first inner ring is closer to the lateral direction (x-axis direction) of the substrate. The distance between the second inner lead pattern portion I1 and the end of the second inner lead pattern portion I2 is reduced. At least one of the ends of I2 is The distance from the end of the first inner lead pattern portion I1 increases.

[0271] The first via holes V1 are spaced apart from each other in the horizontal direction (x-axis direction) of the substrate. are arranged in rows.

[0272] The length between one end and the other end of the second inner lead pattern portion I2 is The first set portion of the second inner lead pattern portion I2 gradually decreases in the x-axis direction. Specifically, one end and the other end of the second inner lead pattern portion I2 The length between the first and second lengths gradually decreases in the horizontal direction (x-axis direction) of the board. The first inner lead pattern portion I2 may include a first set portion. The first length may be greater than the second length. Thus, on the substrate 110, a first set of The second inner lead pattern portion I2 may include a portion having a length that gradually decreases from the second inner lead pattern portion I2. The second inner lead pattern portion I2 has a length and the second inner lead pattern adjacent to the second inner lead pattern portion I3 has a length. The loop portion I2 can again have a first length. The second inner lead pattern portion I gradually decreases in length from the first length to the second length. 2, and the second inner lead whose length gradually decreases from a first length to a second length. The first set of pattern portions I2 is repeatedly arranged.

[0273] At least one of the ends of the second inner lead pattern portion I2 is The closer to the lateral direction (x-axis direction) of the substrate, the closer to the end of the first inner lead pattern portion I1 The separation distance decreases.

[0274] The first inner lead pattern portions I1 are spaced apart at a first interval. The second inner lead pattern I1 is formed in the region between two adjacent first inner lead pattern portions I1. One end of the lead pattern portion I2 may be located thereon.

[0275] In the lateral direction of the substrate, the end of the first inner lead pattern portion I1 and the end of the second inner lead pattern portion I2 are The ends of the inner lead pattern portions I2 are arranged alternately.

[0276] Referring to FIG. 11, the bottom surface of the flexible circuit board 100 for all-in-one COF is Then, a region of the conductive pattern portion CP is exposed through the third open area OA3 of the protective layer 140. The fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 are is exposed to the outside.

[0277] 7b and 12 to 16, the double-sided all-in-one COF flexible board according to the embodiment is A chip package including a first chip C1 and a second chip C2 on a flexible circuit board 100. will be explained in detail.

[0278] FIG. 12 shows a flexible circuit board 100 for double-sided all-in-one COF according to an embodiment. FIG. 2 is a schematic plan view of a chip package including the same.

[0279] Referring to Figs. 12a and 12b, a flexible circuit for a double-sided all-in-one COF according to an embodiment is shown. The circuit board 100 has a first chip C1 and a second chip C2 arranged on the same surface. It can include.

[0280] The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has a lateral direction (x The length in the vertical direction (y-axis direction) may be greater than the length in the vertical direction (y-axis direction). The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has two lateral It can have a long side and two short sides running lengthwise.

[0281] The first chip C1 and the second chip C2 each have a length in the horizontal direction (x-axis direction) of That is, the first chip C1 may have a length greater than the length in the y-axis direction. The second chip C2 may have two long sides in the horizontal direction and two short sides in the vertical direction. Cut.

[0282] The long side of the double-sided all-in-one COF flexible circuit board 100 according to the embodiment is The long sides of the first chip C1 and the long sides of the second chip C2 are arranged parallel to each other, Multiple chips can be mounted effectively on one double-sided all-in-one COF flexible circuit board 100. can be efficiently arranged.

[0283] The horizontal length (long side) of the first chip C1 is equal to the horizontal length (long side) of the second chip C2. The length (short side) of the first chip C1 in the vertical direction may be longer than the length (short side). The length of the second chip C2 may be shorter than the length (short side) of the second chip C2. Referring to FIG. 3a, the second chip C2 is disposed below the first chip C1. The long sides of the first chip C1 and the long sides of the second chip C2 may overlap each other.

[0284] Referring to FIG. 13b, the second chip C2 is disposed on the side of the first chip C1. The long sides of the first chip C1 and the long sides of the second chip C2 do not need to overlap vertically. .

[0285] The first chip C1 is a driving IC chip, and the second chip C2 is a diode chip. chips, power IC chips, touch sensor IC chips, MLCC chips, BGA chips, chips The second chip C2a of one of the chip capacitors and the diode chip, the power supply IC Chips, touch sensor IC chips, MLCC chips, BGA chips, chip capacitors , and a second chip C2b different from any one of the above.

[0286] 13 to 16, a flexible circuit for double-sided all-in-one COF according to an embodiment is shown. The steps in manufacturing a chip package including a circuit board will now be described.

[0287] FIG. 13 is a plan view of a double-sided all-in-one COF flexible circuit board 100 according to an embodiment. FIG.

[0288] 13a and 13b, a double-sided all-in-one COF flexible board according to an embodiment of the present invention is shown. The protective layer 140 located on one side of the flexible circuit board 100 may include a plurality of holes. That is, the protective layer 140 may include a plurality of open areas.

[0289] The first open area OA1 of the protective layer is exposed to be connected to the first connection part 70. The conductive pattern portion exposed in the first open area OA1 of the protective layer may be a conductive pattern portion exposed in the first open area OA1 of the protective layer. The CP may include a pure plating on the surface facing the first connection portion. The tin of the second plating layer included in the conductive pattern portion CP in the first open area OA1 The content may be 50 atomic % or more.

[0290] The second open area OA2 of the protective layer is exposed to be connected to the second connection part 80. The conductive pattern portion exposed in the second open area OA2 of the protective layer may be a conductive pattern portion exposed in the second open area OA2 of the protective layer. The CP may include a copper and tin alloy layer on the surface facing the second connection portion. The second plating included in the conductive pattern portion CP in the second open area OA2 of the protective layer The layer may have a tin content of less than 50 atomic percent.

[0291] The first open area OA1 may be an area for connecting a first chip. The third open area OA3 is provided with a first outer lead pattern portion O1 extending therefrom. The first inner lead pattern portion I1 facing the inside of the first open area OA1 is The widths may correspond to each other or may be different. For example, the first outer lead pattern The width W1 of the first inner lead pattern portion O1 may correspond to the width W2 of the first inner lead pattern portion I1. For example, the width W1 of the first outer lead pattern portion O1 is The width of the first outer layer may be greater than the width W2 of the pattern portion I1. The width W1 of the lead pattern portion O1 is equal to the width W2 of the first inner lead pattern portion I1. The difference may be within 20%.

[0292] The first inner lead pattern extends toward the inside of the first open area OA1. The lead pattern portion I1 and the third inner lead pattern portion I3 have widths corresponding to each other. can be done.

[0293] The first outer lining extends from the first open area OA1 toward the outer edge of the substrate. The outer lead pattern portion O1 and the second outer lead pattern portion O2 have widths corresponding to each other. Therefore, it is possible to manufacture a first chip having a fine line width and requiring a large number of first connecting portions. The first chip has a larger line width and requires fewer secondary connections, all in one. All components can be mounted on the flexible circuit board 100 for one COF. At this time, the fine line width is , the first outer lead pattern portion O1 and the second outer lead pattern portion O2 The line width of either one of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6 is It can mean that the line width of any one of the sections O6 is smaller than that of the other section O6. The width is either the outer lead pattern portion O5 or the sixth outer lead pattern portion O6. One line width is the width of the first outer lead pattern portion O1 and the second outer lead pattern portion O2. The line width of either one of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O2 is It can mean that the line width is relatively larger than any one of the line widths of the code pattern portion O6. do.

[0294] The all-in-one COF flexible circuit board 100 of the embodiment is A plurality of second open areas OA2 are provided for connecting two chips C2a and C2b. It can include.

[0295] The second open area OA2 is an area for connecting one second chip C2a. A fifth inner lead pattern located in the second open area OA2 may be The fifth outer lead pattern portion O5 extending from the portion I5 toward the outer edge of the substrate is For example, the width W of the fifth inner lead pattern portion I5 may be different from the width W of the fifth inner lead pattern portion I6. The fifth outer lead pattern portion O3 may have a width greater than the width W4 of the fifth outer lead pattern portion O5. Specifically, the width W3 of the fifth inner lead pattern portion I5 is It may be 1.5 times or more larger than the width W4 of the code pattern portion O5.

[0296] The other second open area OA2 is used to connect the other second chip C2b. The sixth inner lead located in the second open area OA2 may be an area for A sixth outer lead pattern portion O6 extending from the pattern portion I6 toward the outer edge of the substrate. For example, the sixth inner lead pattern portion I The width W5 of the sixth outer lead pattern portion O6 is greater than the width W6 of the sixth outer lead pattern portion O6. Specifically, the width W5 of the sixth inner lead pattern portion I6 is It may be 1.5 times or more larger than the width W6 of the outer lead pattern portion O6.

[0297] The width W3 and width W4 of the fifth inner lead pattern portion I5 exposed through the second open area are and the width W5 of the sixth inner lead pattern portion I6 is equal to or smaller than the width W1 of the first inner lead pattern portion I1. The width of the first inner lead pattern portion I1 exposed through the opening region is greater than the width W2 of the first inner lead pattern portion I1. Therefore, it is possible to provide leads that correspond to the first and second connection parts of various sizes and shapes. Since a patterned portion can be formed, the degree of freedom in design can be improved. For example, various sizes of inner leads are fitted to different types of first and second tips. It can include various shapes of inner lead pattern parts, so it can be used for optimal Chip packaging is possible.

[0298] The shape of the inner lead pattern located under the first chip is the same as that under the second chip. The shape of the inner lead pattern portion may be different from that of the inner lead pattern portion located on the substrate. The first and second chips can have excellent adhesion properties with each other. The inner lead pattern portion may have different shapes. The flexible circuit board for Luinwan COF is suitable for bonding the first and second chips. Excellent characteristics.

[0299] That is, the inner lead pattern portions having different shapes are arranged on one substrate. The first and second chips of the same type are mounted on the optimal pattern to ensure a certain bonding strength. It is a design.

[0300] The first inner lead pattern portion I1 has a rectangular stripe shape in plan view. Specifically, on the plane of the first inner lead pattern portion I1, The shape of the stripe pattern was a square stripe pattern with a uniform width extending in one direction. As an example, the width of one end and the other end of the first inner lead pattern portion I1 may be They may be the same.

[0301] For example, the fifth inner lead pattern portion I5 or the sixth inner lead pattern The shape of the plane of the section I6 is polygonal, circular, elliptical, hammer-shaped, T-shaped, random shape. In particular, the fifth inner lead pad may have a protruding pattern of various shapes. The shape of the turn portion I5 or the sixth inner lead pattern portion I6 in a plane varies. and a polygon, a circle, an ellipse, a hammer-shaped, a T shape having a width that is equal to the width of the first direction and extending in a direction different from the first direction. The fifth inner periphery may have a protruding pattern such as a letter shape, a random shape, or the like. At least one of the lead pattern portion I5 and the sixth inner lead pattern portion I6 The inner lead pattern portion may have a width different at one end from that at the other end. The sixth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 are provided at their ends close to the protective layer. The width at the other end far from the protective layer may be larger than the width at the other end. However, the fifth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 may be formed on the same substrate. The width of the inner lead pattern I6 at one end closest to the protective layer is Of course, the width of the other end, which is the portion, may be smaller.

[0302] For example, when the second chip is an MLCC chip, the inner lead pattern portion is , the fifth inner lead pattern portion I5 of FIG. 13b may have a T-shape.

[0303] For example, when the second chip is a BGA chip, the inner lead pattern portion is It may have a circular shape like the sixth inner lead pattern portion I6 in FIG. 13a. When the first chip is a BGA chip, the inner lead pattern portion is A shape with a semicircular shape or a rounded end like the sixth inner lead pattern I6 It can have a shape.

[0304] The first inner lead pattern portion and the first connecting portion may have the same shape. For example, the top view of the first inner lead pattern portion and the first connection portion is , the first inner lead pattern portion and the The fact that the shapes of the first connection parts are the same means that the planar shapes are the same polygons. , may include ones of different sizes.

[0305] The fifth inner lead pattern portion and the second connecting portion have shapes that are the same as or different from each other. The sixth inner lead pattern portion and the second connecting portion may have the same shape or may have the same shape. may be different.

[0306] Referring to FIGS. 13a and 14a, the plane shape of the fifth inner lead pattern portion I5 is The shape of the first connecting portion may be a polygonal shape, and the planar shape of the second connecting portion may be a circular shape. The sixth inner lead pattern portion I6 has a circular planar shape, and the second connecting portion , may have a circular shape.

[0307] Referring to FIGS. 13b and 14b, the plane shape of the fifth inner lead pattern portion I5 is The shape is a polygonal shape, and the second connection part is a square shape or an ellipse shape with rounded corners. The sixth inner lead pattern portion I6 may have a planar shape of a long semicircle. The second connection portion may have a circular shape.

[0308] The planar shape of the first connection part 70 has a width and a length (aspect ratio) that correspond to each other or are different from each other. For example, the planar shape of the first connection portion 70 may be such that the horizontal length and vertical length (aspect ratio) are They have corresponding square shapes or rectangular shapes with different horizontal and vertical lengths (aspect ratios). It is possible.

[0309] The second connection part 80 has a planar shape in which the horizontal length and the vertical length (aspect ratio) correspond to each other or are different from each other. For example, the planar shape of the second connection portion 80 may be such that the horizontal length and vertical length (aspect ratio) are It can have corresponding circular or elliptical shapes with different horizontal and vertical lengths (aspect ratio). can.

[0310] The pitch between adjacent first outer lead pattern portions O1 is The fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6 adjacent to each other The second pitch (O6) is the pitch between at least one outer lead pattern portion. In this case, the first and second intervals may be smaller than the distance between two adjacent conductive patterns. It can refer to the average separation between the loop portions.

[0311] The first interval P1 may be less than 100 μm. For example, the first interval P1 may be 30 μm. For example, the first interval may be 1 μm to 25 μm.

[0312] The second interval P2 may be 100 μm or more. For example, the second interval P2 may be 100 μm or more. For example, the second interval may be 100 μm to 300 μm. It can have:

[0313] Therefore, the conductive pattern portions connected to the first chip and the second chip are Signal interference can be prevented and signal accuracy can be improved.

[0314] In the first open area OA1, the plane of the first inner lead pattern portion I1 The product may correspond to or differ from the first connecting portion 70 .

[0315] The width of the first inner lead pattern portion I1 and the width of the first connection portion 70 are the same. The difference may be within 20%. The first inner portion I1 and the first connecting portion 70 can be stably mounted. The adhesion between the lead pattern portion I1 and the first connecting portion 70 is improved.

[0316] In the second open area OA2, the fifth inner lead pattern portion I5 and the front The plane of any one of the sixth inner lead pattern portions I6 The product may correspond to or differ from the second connection 80 .

[0317] For example, the width of the second connection portion 80 is equal to or larger than the width of the fifth inner lead pattern portion I5 and The width of any one of the sixth inner lead pattern portions I6 Therefore, the width of the second connection portion 80 may be 1.5 times or more larger than the width of the fifth inner connection portion 80. - Either one of the lead pattern portion I5 and the sixth inner lead pattern portion I6 and the front The second connecting portion 80 has improved adhesion characteristics.

[0318] 14a and 14b, the flexible circuit board 10 for all-in-one COF of the embodiment The step of placing the first connecting portion 70 and the second connecting portion 80 on the substrate 10 will now be described.

[0319] The first inner lead pattern portion I1 exposed through the first open area OA1 and the third inner lead pattern portion I3, a first connecting portion 70 is disposed thereon. For example, the first connection portion 70 is formed by connecting the first inner lead pattern portion I1 and the The upper surface of the third inner lead pattern portion I3 can be entirely or partially covered.

[0320] The first inner lead pattern portions I1 and I2 are spaced apart from each other. The total number of the third inner lead pattern portions I3 arranged in the first connection portion 7 is It may correspond to the number of 0s.

[0321] For example, referring to FIGS. 15a and 15b, a plurality of the first The number of inner lead pattern portions I1 is nine, and the plurality of The number of the inner lead pattern portions I3 is nine, and the number of the first connecting portions 70 is The number of the inner lead pattern portions I1 is nine, and the number of the third inner lead patterns I1 is nine. The total number of the lead pattern portions I1 and I2 is 18, which is the sum of the number of lead pattern portions I2 and I3, which is 9.

[0322] The fifth inner lead pattern portion I5 exposed through the second open area OA2 and the sixth inner lead pattern portion I6, a second connecting portion 80 is disposed thereon. For example, the second connection portion 80 is formed by connecting the fifth inner lead pattern portion I5 and the The upper surface of the sixth inner lead pattern portion I6 can be entirely or partially covered.

[0323] The number of the plurality of fifth inner lead pattern portions I5 arranged at a distance from each other is 5. The number of the second connecting portions 80 arranged on the inner lead pattern portion I5 may also correspond to the number of the second connecting portions 80. good.

[0324] For example, referring to FIGS. 15a and 15b, a plurality of the fifth The number of inner lead pattern portions I5 is two, and the fifth inner lead pattern portion I The number of the second connection portions 80 arranged on the first connection portion 5 is two.

[0325] The number of the sixth inner lead pattern portions I6 arranged at a distance from each other is The number of the second connection portions 80 arranged on the inner lead pattern portion I6 may also correspond to the number of the second connection portions 80. good.

[0326] For example, referring to FIGS. 15a and 15b, a plurality of the sixth ink jet heads are spaced apart from one another. The number of the inner lead pattern portions I6 is three, and the sixth inner lead pattern portion I6 The number of the second connection portions 80 arranged thereon is three.

[0327] The second connection portion 80 may be larger than the first connection portion 70. The fifth inner lead pattern portion I5 or the sixth inner lead pattern I6 exposed through the The width of the turn portion I6 is equal to or larger than the width of the first inner lead pad exposed through the first open region. Since the width of the second connecting portion 80 is larger than that of the first connecting portion 70, stomach.

[0328] 15a and 15b, the flexible circuit board for all-in-one COF of the embodiment is The step of placing the first chip C1 and the second chips C2a and C2b on the plate 100 will be described.

[0329] A first chip C1 is disposed on the first connection portion 70.

[0330] On the second connection part 80, the first chip C2 is disposed.

[0331] The first chip C1 and the second chip C2 are designed to prevent signal interference, wire breakage, and other defects, and to prevent heat In order to prevent problems such as defects due to the above, they are spaced apart at a certain distance.

[0332] FIG. 16 shows the double-sided all-in-one COF flexible circuit board according to FIGS. 15a and 15b. 1 is a cross-sectional view of a chip package including a plate.

[0333] The first chip C1 and the second chip C2 are arranged on the same surface with different sizes. For example, the second chip C2 is larger than the first chip C1.

[0334] Via holes are disposed under the first chip C1 and the second chip C2. , the substrate 1 in the area corresponding to the first open area OA1 and the second open area OA2 10 may include a via hole.

[0335] The electrical signals of the second chip C2 are transmitted through the conductive material disposed in the fourth via hole V4. Therefore, the embodiment can be realized by forming a plurality of conductive patterns on one surface of the substrate. The semiconductor device may be comprised on one substrate.

[0336] The all-in-one COF flexible circuit board 100 according to the embodiment has fine pins on both sides. The conductive pattern portion of the display can be realized, and the display can be made into an electronic device having a high resolution. Fits the device.

[0337] In addition, the all-in-one COF flexible circuit board 100 according to the embodiment is a flexible Its small size and thin thickness make it suitable for use in a variety of electronic devices. do.

[0338] For example, referring to FIG. 17, an all-in-one COF flexible circuit according to an embodiment of the present invention is shown. The substrate 100 can be used in edge displays, as it may reduce the bezel. Cut.

[0339] For example, referring to FIG. 18, an all-in-one COF flexible circuit according to an embodiment of the present invention is shown. The substrate 100 can be included in a flexible electronic device. Therefore, a touch device including this can be a flexible touch device. Therefore, users can bend and twist it by hand. The touch window can be applied to wearable touch and the like.

[0340] For example, referring to FIG. 19, an all-in-one COF flexible circuit according to an embodiment of the present invention is shown. The substrate 100 is applicable to various electronic devices to which a foldable display device is applied. Referring to Figures 19a to 19c, the foldable display device The foldable cover window can be folded. The device can be included in various portable electronic products. Ray devices are included in mobile terminals (cell phones), notebooks (portable computers), etc. This allows the display area of ​​portable electronic products to be enlarged while still being easy to store and use. When moving, the size of the device can be reduced, and portability can be improved. It is possible to improve the convenience of users of portable electronic products, but the embodiment is not limited thereto. The foldable display device can be used in a variety of electronic products. Of course, this is the case.

[0341] Referring to FIG. 19a, the foldable display device has one fold in the screen area. For example, a foldable display device may include a folded area. That is, the foldable display device may have a C-shape at one end and at the front. The one end and the other end opposite to each other can be overlapped. At this time, the one end and the other end are close to each other. For example, the one end and the other end are arranged to face each other.

[0342] Referring to FIG. 19b, the foldable display device has two folds in the screen area. For example, a foldable display device may include a folded display area. That is, the foldable display device may have a G shape. The opposite ends of the sheets are folded in the corresponding directions so that they overlap each other. At this time, the one end and the other end are spaced apart from each other. For example, the one end and the other end are They are arranged parallel to each other.

[0343] Referring to FIG. 19c, the foldable display device has two folds in the screen area. For example, a foldable display device may include a folded area. That is, the foldable display device may have an S-shape at one end and at the front. The other end opposite to the one end is bent in a different direction. The ends are spaced apart from each other, for example, the one end and the other end are parallel to each other.

[0344] Although not shown, the all-in-one COF flexible circuit board according to the embodiment Of course, the board 100 can be applied to a rollable display.

[0345] Referring to FIG. 20, a flexible circuit board 10 for all-in-one COF according to an embodiment of the present invention is shown. 0 can be included in a variety of wearable touch devices, including curved displays. Therefore, the electric device including the all-in-one COF flexible circuit board 100 according to the embodiment The child device may be slimmer, smaller or lighter.

[0346] Referring to FIG. 21, a flexible circuit board 10 for all-in-one COF according to an embodiment of the present invention is shown. 0 is a variety of electronic devices with display parts such as TVs, monitors, and notebooks. It can be used for chairs.

[0347] It should be noted that the examples are not limited to these, and the all-in-one COF according to the examples The flexible circuit board 100 can be used for various display devices having flat or curved display portions. It goes without saying that the present invention can be used in various electronic devices.

[0348] According to an embodiment of the present invention, a first chip and a second chip of different types are integrated into one frame. All-in-one CO that can be mounted on a flexible circuit board for improved reliability Flexible circuit board chip packages for F can be provided.

[0349] Furthermore, according to an embodiment of the present invention, one all-in-one flexible circuit for COF is provided. The display panel and main board are directly connected by a circuit board, and the The size and thickness of the flexible circuit board that transmits the signals to the main board are reduced. This allows for more space for other components and / or battery space. It is possible.

[0350] Furthermore, according to the embodiment of the present invention, since it is not necessary to connect multiple PCBs, the process is simplified. Convenience and reliability of electrical connection are improved, enabling high-resolution display units. To provide an all-in-one COF flexible circuit board suitable for electronic devices. This can be done.

[0351] Furthermore, according to the embodiment of the present invention, a circuit pattern corresponding to the circuit pattern arranged on the first surface of the substrate is formed. A dummy pattern is arranged on the second surface of the substrate so as to By disposing a dummy pattern on the first surface of the substrate so as to correspond to the wiring pattern, Solder resist generated when printing the solder resist on the first or second surface of the board This can solve the problems of not applying the paste and pinholes.

[0352] The features, structures, advantages, etc. described in the above-described embodiments are included in at least one implementation of the present invention. The examples are included in the examples and are not necessarily limited to one embodiment. The features, structures, effects, etc., may be easily understood by a person having ordinary skill in the art to which the embodiments pertain. The embodiments can be combined or modified in various ways. Such content should be construed as being included within the scope of the present invention.

[0353] Although the above description has focused on the examples, these are merely examples and do not limit the present invention. It is understood that those skilled in the art will be able to understand the essence of the present invention. Various modifications and applications not exemplified above are possible within the scope of the basic characteristics. For example, each component specifically presented in the embodiments can be modified and implemented. The differences relating to such modifications and applications are the subject of the present invention as defined in the appended claims. should be interpreted as being within the scope of

Claims

1. A substrate; a plurality of first conductive pattern portions disposed on a first surface of the substrate; a plurality of second conductive pattern portions disposed under a second surface of the substrate opposite the first surface of the substrate; at least one first dummy pattern portion disposed in an area under the second surface of the substrate where the second conductive pattern portion is not disposed, and overlapping the first conductive pattern portion in a thickness direction of the substrate; at least one second dummy pattern portion disposed in an area on the first surface of the substrate where the first conductive pattern portion is not disposed, and overlapping the second conductive pattern portion in the thickness direction; a first protective layer disposed on the first conductive pattern portion and the second dummy pattern portion; a second protective layer disposed under the second conductive pattern portion and the first dummy pattern portion.

2. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, 2. The flexible circuit board of claim 1, wherein the first dummy pattern portion overlaps in the thickness direction at least one of a first conductive pattern portion arranged closest to the first side and a first conductive pattern portion arranged closest to the second side among the plurality of first conductive pattern portions.

3. 3. The flexible circuit board of claim 2, wherein the second dummy pattern portion overlaps in the thickness direction at least one of the second conductive pattern portion arranged closest to the first side and the second conductive pattern portion arranged closest to the second side among the plurality of second conductive pattern portions.

4. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, 2 . The flexible circuit board of claim 1 , wherein the first dummy pattern portion overlaps in the thickness direction with a first conductive pattern portion arranged closest to the first side and a first conductive pattern portion arranged closest to the second side among the plurality of first conductive pattern portions.

5. 5. The flexible circuit board of claim 4, wherein the second dummy pattern portion overlaps in the thickness direction with each of the second conductive pattern portions that is closest to the first side and the second conductive pattern portion that is closest to the second side among the plurality of second conductive pattern portions.

6. the first surface of the substrate includes first and second edges that are opposite to each other along a width direction of the first conductive pattern portion, 2 . The flexible circuit board of claim 1 , wherein the first dummy pattern portion overlaps in the thickness direction at least one of a first conductive pattern portion arranged closest to the first edge and a first conductive pattern portion arranged closest to the second edge among the plurality of first conductive pattern portions.

7. the second surface of the substrate includes third and fourth edges that are opposite to each other along a width direction of the second conductive pattern portion, 7. The flexible circuit board of claim 6, wherein the second dummy pattern portion overlaps in the thickness direction at least one of the second conductive pattern portion arranged closest to the third edge and the second conductive pattern portion arranged closest to the fourth edge among the plurality of second conductive pattern portions.

8. the first surface of the substrate includes first and second edges that are opposite to each other along a width direction of the first conductive pattern portion, 2 . The flexible circuit board of claim 1 , wherein the first dummy pattern portion overlaps, in the thickness direction, a first conductive pattern portion arranged closest to the first edge and a first conductive pattern portion arranged closest to the second edge among the plurality of first conductive pattern portions.

9. the second surface of the substrate includes third and fourth edges that are opposite to each other along a width direction of the second conductive pattern portion, 9. The flexible circuit board of claim 8, wherein the second dummy pattern portion overlaps, in the thickness direction, each of the second conductive pattern portions that is closest to the third edge and the second conductive pattern portion that is closest to the fourth edge among the plurality of second conductive pattern portions.

10. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, The flexible circuit board according to claim 1 , wherein the first dummy pattern portion is located closer to at least one of the first side and the second side of the substrate than the second conductive pattern portion.

11. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, The flexible circuit board according to claim 1 , wherein the second dummy pattern portion is located closer to at least one of the first side and the second side than the first conductive pattern portion.

12. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, 12. The flexible circuit board according to claim 1, wherein a distance from the first side to an initial start position of a first conductive pattern portion arranged closest to the first side is greater than a distance from the first side to an initial start position of a first dummy pattern portion arranged closest to the first side.

13. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, 13. The flexible circuit board according to claim 1, wherein a distance from the second side to an initial start position of a second conductive pattern portion arranged closest to the second side is greater than a distance from the second side to an initial start position of a first dummy pattern portion arranged closest to the first side.

14. the substrate includes a first side and a second side that are opposite to each other along a width direction of the substrate, 10. The flexible circuit board according to claim 1, wherein a distance from the first side to an initial start position of a first conductive pattern portion arranged closest to the first side is the same as a distance from the first side to an initial start position of a first dummy pattern portion arranged closest to the first side.

15. 15. The flexible circuit board of claim 14, wherein a distance from the second side to an initial start position of a second conductive pattern portion arranged closest to the second side is the same as a distance from the second side to an initial start position of a second dummy pattern portion arranged closest to the second side.

16. 15. The flexible circuit board of claim 14, wherein a distance from the first side to an initial start position of a second conductive pattern portion arranged closest to the first side is the same as a distance from the first side to an initial start position of a second dummy pattern portion arranged closest to the first side.

17. A flexible circuit board is included. The flexible circuit board is a substrate including a first surface and a second surface that are opposite to each other in a thickness direction and a first side and a second side that are opposite to each other in a width direction; a plurality of first conductive pattern portions disposed on the first surface of the substrate; a plurality of second conductive pattern portions disposed beneath the second surface of the substrate; At least one first dummy pattern unit is disposed under the second surface of the substrate, disposed in an area where the second conductive pattern unit is not disposed, and overlaps the first conductive pattern unit in the thickness direction; At least one second dummy pattern unit is disposed on the first surface of the substrate, is disposed in an area where the first conductive pattern unit is not disposed, and overlaps the second conductive pattern unit in the thickness direction; a first protective layer disposed on the first conductive pattern portion and the second dummy pattern portion; a second protective layer disposed under the second conductive pattern portion and the first dummy pattern portion, a chip disposed on the first conductive pattern portion; the first dummy pattern unit overlaps in the thickness direction with at least one of a first conductive pattern unit arranged closest to a first side of the substrate and a first conductive pattern unit arranged closest to a second side of the substrate, among the plurality of first conductive pattern units; A chip package, wherein the second dummy pattern portion overlaps in a thickness direction with at least one of the second conductive pattern portions that is closest to a first side of the substrate and the second conductive pattern portion that is closest to a second side of the substrate among the plurality of second conductive pattern portions.

18. the first dummy pattern unit overlaps with a first conductive pattern unit disposed closest to a first side of the substrate and a first conductive pattern unit disposed closest to a second side of the substrate in the thickness direction; 20. The chip package of claim 17, wherein the second dummy pattern portion overlaps in the thickness direction with each of a second conductive pattern portion arranged closest to a first side of the substrate and a second conductive pattern portion arranged closest to a second side of the substrate.

19. 20. The chip package of claim 17, wherein a distance from the first side to an initial start position of a first conductive pattern portion arranged closest to the first side is the same as a distance from the first side to an initial start position of a first dummy pattern portion arranged closest to the first side.

20. 20. The chip package of claim 17, wherein a distance from the second side to an initial start position of a second conductive pattern portion arranged closest to the second side is the same as a distance from the second side to an initial start position of a second dummy pattern portion arranged closest to the second side.

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