Row hammer refresh address calculation method, calculation circuit, and semiconductor storage device incorporating the same

Abstract

A row hammer refresh address (RHA) calculation method and calculation circuit capable of calculating an RHA at high speed with a small circuit scale, and a semiconductor memory device including the same are provided. [Solution] When the seed address is updated, the control unit of the RHA calculation circuit performs order control of the calculation unit so that, among the adjacent RHAs on both sides based on the updated seed address, the address obtained by an operation with a small amount of calculation (only the least significant bit is inverted) is preferentially calculated as the adjacent RHA, or, among the next adjacent RHAs on both sides based on the updated seed address, the address obtained by an operation with a small amount of calculation (only the second least significant bit is inverted) is preferentially calculated as the next adjacent RHA. Meanwhile, the calculation unit of the RHA calculation circuit finds the possibility that the physical arrangement of the word lines and the row addresses assigned thereto will eventually be trained to a predetermined logic, and based on that, finds the calculation logic of the adjacent RHAs and next adjacent RHAs with the minimum amount of calculation, and implements an arithmetic circuit that is optimized for the order control of calculations.

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device that additionally performs row hammer refresh in order to retain data in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) that requires a refresh operation, as well as a row hammer refresh address calculation method and calculation circuit. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device, is a volatile memory that stores information by storing electric charge in a capacitor, which is a memory cell, and loses the stored information when power is cut off. Since the electric charge stored in the capacitor is discharged after a certain period of time, DRAM requires a data retention operation called refresh, in which the electric charge is periodically charged (for example, Patent Documents 1 and 2).

[0003] In addition, a frequently accessed row address is called an RHA, and it has been known for some time that cell leakage increases in memory cells of row addresses adjacent to the RHA due to memory array noise that occurs with the access operation, minority carriers, or rare device defects. In addition, with the progress of miniaturization of semiconductor devices, this cell leakage has increased significantly, and after the 20 nm process generation, it has become difficult to retain data with only conventional refresh operations (e.g., Patent Documents 1 and 2).

[0004] For this reason, a frequently accessed row address may be captured as a seed address, and additional refresh may be performed not only on the two row addresses adjacent to the seed address on either side, but also on the two adjacent row addresses on either side of the seed address (e.g., Patent Document 3).

[0005] This additionally performed refresh is called Row-Hammer Refresh (RHR), and the row address assigned to the target of the word line Row-Hammer Refresh is called an RHA (Row-Hammer Refresh Address).

[0006] The memory cells connected to the word line (WL) assigned to the refresh address are subject to the data retention operation. In other words, the memory cells connected to the word line assigned to the row hammer refresh address (RHA) are subject to additional data retention.

[0007] On the other hand, based on a single seed address captured before performing row hammer refresh, it is necessary to complete the calculation of four row hammer refresh addresses (RHA), including the adjacent addresses on both sides and the addresses adjacent to each other.In the past, this calculation was complex, took a long time, and required a large circuit size. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2019 / 026197 [Patent Document 2] US Patent Application Publication No. 2017 / 0287547 [Patent Document 3] US Patent Application Publication No. 2019 / 0385667 Summary of the Invention [Problem to be solved by the invention]

[0009] The present invention has been made in consideration of the above problems, and aims to provide a row hammer refresh address (RHA) calculation method and calculation circuit that can calculate the row hammer refresh address (RHA) quickly and with a small circuit scale, and a semiconductor memory device equipped with the same. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention provides An RHA calculation circuit for calculating an RHA, comprising: In a memory array including a plurality of memory cells arranged in a matrix, a calculation unit, based on a seed address captured by some means (e.g., random sampling, etc.), calculates an RHA adjacent to the upper side and an RHA adjacent to the lower side in a complementary manner by a first calculation or a second calculation having a larger amount of calculation than the first calculation, based on the seed address, calculates an RHA adjacent to the upper side and an RHA adjacent to the lower side in a complementary manner by a third calculation or a fourth calculation having a larger amount of calculation than the third calculation; A control unit controls the operation of the calculation unit so that, when the seed address is updated, the address obtained by the first calculation among the upper adjacent RHA and the lower adjacent RHA corresponding to the updated seed address is calculated preferentially by the first calculation as a priority adjacent RHA, and the address obtained by the third calculation among the upper adjacent RHA and the lower adjacent RHA corresponding to the updated seed address is calculated preferentially by the third calculation as a priority adjacent RHA. An RHA calculation circuit is provided (Invention 1).

[0011] In the above invention (Invention 1), The control unit supplies to the calculation unit a first identification signal for identifying whether the current unit period is an A type period in which the higher-side adjacent RHA or the lower-side adjacent RHA is calculated based on an A type seed address, or a B type period in which the higher-side adjacent RHA or the lower-side adjacent RHA is calculated based on a B type seed address, and a second identification signal for identifying whether the current period in each unit period belongs to a priority period in which a priority RHA is generated starting from the start of the unit period, or a non-priority period in which a non-priority RHA is generated starting from the middle of the unit period; The calculation unit may calculate the priority adjacent RHA by the first calculation based on the A type seed address during a period that is the A type period and the priority period based on the first and second type identification signals, and may calculate the priority adjacent RHA by the third calculation based on the B type seed address during a period that is the B type period and the priority period (Invention 2).

[0012] In the above invention (Invention 2), the calculation unit may calculate a non-priority adjacent RHA by the second calculation based on the seed address of the A type during a period that is both the A type period and the non-priority period (Invention 3).

[0013] In the above invention (Invention 2 or 3), the calculation unit may calculate a non-priority adjacent RHA by the fourth calculation based on the seed address of the B type during a period that is also the B type period and the non-priority period (Invention 4).

[0014] In the above invention (Invention 2), if the type A seed address is updated during a period that is the type A period and the non-priority period, the control unit may continue an additional type A period after the current type A period ends, and the calculation unit may calculate the preferred adjacent RHA by the first calculation based on the type A seed address updated during the period that is the current type A period and the non-priority period during the additional type A period and the priority period (Invention 5).

[0015] In the above invention (Invention 2), if the type A seed address has not been updated during a period that is the type A period and the non-priority period, the control unit may continue the type B period after the current type A period ends, and the calculation unit may calculate the priority adjacent RHA by the third calculation based on the type B seed address during the updated period that is the type B period and the priority period (Invention 6).

[0016] In the above invention (Invention 2), if the priority period is changed to the non-priority period during the B type period, the calculation unit may calculate the non-priority adjacent RHA by the fourth calculation based on the B type seed address used when calculating the priority adjacent RHA output before the change (Invention 7).

[0017] In the above invention (Invention 2), if the type B seed address is updated during a period that is the type B period and the non-priority period, the control unit may continue an additional type B period after the current type B period ends, and the calculation unit may calculate the priority adjacent RHA by the third calculation based on the type B seed address updated during the period that is the type B period and the non-priority period after the continuation and is the type B period and the priority period (Invention 8).

[0018] In the above invention (Invention 2), if the type B seed address is not updated during a period that is the type B period and the non-priority period, the control unit may continue the type A period after the current type B period ends, and the calculation unit may calculate the priority adjacent RHA by the first calculation based on the type A seed address during the updated type A period and the priority period (Invention 9).

[0019] In the above invention (Invention 2), the type A seed address may be obtained by sampling a row address used in accessing the memory array with a first sampling signal generated at random timing, and the type B seed address may be obtained by sampling the row address used in accessing the memory array with a second sampling signal generated at random timing and independent of the first sampling signal (Invention 10).

[0020] In the above invention (Invention 1), the calculation unit may include a forward address conversion unit that converts the seed address in the logical address space into a physical address according to the physical arrangement of a specified memory cell or the physical arrangement information of a word line, a physical address shift unit that calculates one of the first to fourth physical RHAs by adding or subtracting ±1 or ±2 based on the seed address converted into a physical address, and a reverse address conversion unit that reverse converts the first to fourth physical RHAs into logical addresses according to the physical arrangement of the specified memory cell or the physical arrangement information of the word line, to determine one of the upper adjacent RHA, the lower adjacent RHA, the upper adjacent adjacent RHA, and the lower adjacent adjacent RHA in the logical address space (Invention 11).

[0021] In the above invention (Invention 2), the calculation unit includes a first part which receives the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address, as well as the first identification signal and the second identification signal, and outputs a signal that maintains the logic levels of the least significant bit and the second least significant bit of the seed address when the first identification signal indicates that the current unit time is the A type period, and outputs a signal obtained by passing the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address, as well as the first identification signal and the second identification signal through a first combinational circuit included in its first part when the first identification signal indicates that the current unit time is the B type period; and a second part which passes the signal input from the first part, the third least significant bit and the fourth least significant bit of the seed address, and the second identification signal through a second combinational circuit included in its second part. and a second part that outputs the lower four bits of the RHA obtained by passing the signal input from the third part, the third least significant bit and the fourth least significant bit of the seed address, and the second identification signal through the second combination circuit included in the second part, and in a calculation circuit corresponding to the own RHA calculation circuit, the calculation part and the part related to the adjacent RHA of the control unit are configured (Invention 12).

[0022] In order to solve the above problems, the present invention provides a memory array including a plurality of memory cells arranged in rows and columns; The RHA calculation circuit of the above invention (Inventions 1 to 12), Preparation, A plurality of memory cells connected to a word line having the RHA calculated by the RHA calculation circuit as a row address are refreshed. A semiconductor memory device is provided (Invention 13).

[0023] In order to solve the above problems, the present invention provides A method for calculating the RHA, comprising: a calculation step of calculating an upper adjacent RHA corresponding to a word line adjacent to an upper side of a word line to which a seed address is assigned and a lower adjacent RHA corresponding to a word line adjacent to a lower side of the word line to which the seed address is assigned, in a memory array including a plurality of memory cells arranged in a matrix, by a first calculation or a second calculation having a larger amount of calculation than the first calculation, and calculating an upper adjacent RHA corresponding to a word line adjacent to the upper side of the word line to which the seed address is assigned and a lower adjacent RHA corresponding to a word line adjacent to the lower side of the word line to which the seed address is assigned, by a third calculation or a fourth calculation having a larger amount of calculation than the third calculation; A control step of controlling the calculation step so that, when the seed address is updated, among the higher-side adjacent RHA and the lower-side adjacent RHA corresponding to the updated seed address, an address obtained by the first calculation is calculated preferentially as a priority adjacent RHA by the first calculation, and, when the seed address is updated, among the higher-side adjacent RHA and the lower-side adjacent RHA corresponding to the updated seed address, an address obtained by a third calculation is calculated preferentially as a priority adjacent RHA by the third calculation. A method for calculating RHA is provided (Invention 14). Effect of the Invention

[0024] According to the present invention, the row hammer refresh address can be calculated at high speed with a small circuit scale. [Brief description of the drawings]

[0025] [Figure 1] 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention; [Diagram 2] 2 is a block diagram showing a configuration of an i-th memory block 101-i (i=1 to N) shown in FIG. [Diagram 3] 3 is a block diagram showing a configuration of a row hammer refresh address calculation unit shown in FIG. 2. [Figure 4] 3 is a timing diagram of signals associated with the row hammer refresh address calculation unit shown in FIG. 2. [Diagram 5] FIG. 2 is a diagram showing an arrangement pattern of a portion corresponding to 16 row lines in a memory array of a semiconductor memory device according to an embodiment of the present invention. [Figure 6] FIG. 13 is a diagram showing the correspondence between seed addresses and row hammer refresh addresses. [Figure 7] 4 is a circuit diagram showing a configuration example of a calculation unit shown in FIG. 3. [Figure 8] 1A is a table showing the correspondence between seed addresses and adjacent hammer refresh addresses in an embodiment of the present invention; FIG. 1B is a table showing the correspondence between seed addresses and adjacent hammer refresh addresses in an embodiment of the present invention; and FIG. 1C is a table showing the correspondence between physical addresses and logical addresses in an embodiment of the present invention. [Figure 9] 13 is a table showing signals and data required for switching between a prioritized adjacent row hammer refresh address, a non-prioritized adjacent row hammer refresh address, a prioritized adjacent row hammer refresh address, and a non-prioritized adjacent row hammer refresh address, and their combinations. [Figure 10] 8 is a circuit diagram showing an example of the configuration of the modified 4-bit adder shown in FIG. 7. [Figure 11] 13 is a logical expression showing, by condition, a logical operation performed in a row hammer refresh address calculation unit according to the second embodiment of the present invention. [Figure 12]FIG. 11 is a circuit diagram showing a configuration of a row hammer refresh address calculation unit according to a second embodiment of the present invention. [Figure 13] FIG. 13 is a circuit diagram showing a configuration of a row hammer refresh address calculation unit according to a third embodiment of the present invention. [Figure 14] FIG. 13 is a circuit diagram showing a configuration of a row hammer refresh address calculation unit in a first connection state according to a fourth embodiment of the present invention. [Figure 15] FIG. 13 is a circuit diagram showing a configuration of a row hammer refresh address calculation unit in a second connection state according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, a row hammer refresh address calculation circuit, a semiconductor memory device, and a row hammer refresh address calculation method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is an example, and the present invention is not limited thereto.

[0027] [First embodiment] 1 is a block diagram showing a semiconductor memory device 100 according to a first embodiment of the present invention. In this embodiment, the semiconductor memory device 100 is a DRAM, but the semiconductor memory device 100 may be, for example, a pseudo-static random access memory (pSRAM) configured to internally control a refresh operation.

[0028] Referring to FIG. 1, a semiconductor memory device 100 includes a first memory block 101-1 to an Nth memory block 101-N (N is an integer equal to or greater than 2), an address input buffer 103, an address decoder 105, a column address counter & latch 107, a block address control logic 109, a command input buffer 111, a command decoder 113, a clock input buffer 115, an internal clock generating unit 117, a mode register & fuse ROM unit 119, a global input / output gate 121, a DQ input / output buffer 123, a temperature sensor 125, and an internal power supply generating unit 127.

[0029] Data DQ input from the outside is supplied to the global input / output gate 121 via the DQ input / output buffer 123, and data supplied from the global input / output gate 121 to the DQ input / output buffer 123 is output to the outside as data DQ.

[0030] The global input / output gate 121 demultiplexes the data input from the DQ input / output buffer 123 and supplies the demultiplexed data to the first memory block 101-1 to the N-th memory block 101-N. The global input / output gate 121 also multiplexes the data supplied from the first memory block 101-1 to the N-th memory block 101-N and supplies the multiplexed data to the DQ input / output buffer 123.

[0031] Each of the first memory block 101-1 to the Nth memory block 101-N includes a plurality of memory cells arranged in a matrix. Each memory cell is specified by a row address and a column address. Data input from the outside via the global input / output gate 121 and the DQ input / output buffer 123 is written in accordance with a write signal WT to a memory cell specified by the row address and the column address of the memory block 101-i (i=1 to N) whose own block is specified by the block selection signal BS_i (i=1 to N). Data written in a memory cell specified by the row address and the column address of the memory block 101-i (i=1 to N) whose own block is specified by the block selection signal BS_i (i=1 to N) is read in accordance with a read signal RD via the global input / output gate 121 and the DQ input / output buffer 123.

[0032] An address input from the outside via the address input buffer 103 is supplied to an address decoder 105 , a command decoder 113 and a mode register & fuse ROM unit 119 .

[0033] The address decoder 105 decodes the input address and outputs the decoded results as a block address BA, a row address XADD, and a column address YADD.

[0034] The column address counter & latch 107 mainly latches the column address YADD, and supplies it as a column address YADD1 to the first memory block 101-1 to the N-th memory block 101-N.

[0035] The block address control logic 109 decodes the block address BA, and supplies the decoded block selection signals BS_1 to BS_N to the first memory block 101-1 to the N-th memory block 101-N, respectively.

[0036] A command COM input from the outside via a command input buffer 111 is supplied to a command decoder 113 .

[0037] The command decoder 113 decodes the command and calculates the signals ACT, PREC, RFIP_1 to RFIP_N, the read signal RD, the write signal WT, and the signal MRS based on the decoded result and the address. The signals ACT, PREC, RFIP_1 to RFIP_N, the read signal RD, and the write signal WT are supplied to the first memory block 101-1 to the Nth memory block 101-N.

[0038] Complementary clocks CK and CKB input from the outside are converted into a clock ICLK by a clock input buffer 115 and supplied to a command decoder 113 , an address decoder 105 and an internal clock generator 117 .

[0039] The internal clock generation unit 117 generates an internal clock LCLK based on the signal CKE and the clock ICLK supplied from the command input buffer 111. The internal clock LCLK is supplied to a DQ input / output buffer 123.

[0040] The mode register & fuse ROM unit 119 calculates the signals TMRHR and TMRS based on the signal MRS and the address. The signals TMRHR and TMRS are supplied to the first memory block 101-1 to the N-th memory block 101-N.

[0041] The temperature sensor 125 measures the temperature of the semiconductor memory device 100 and outputs temperature data TS indicating the measurement result. The temperature data TS is supplied to the first memory block 101-1 to the N-th memory block 101-N and is used to control the refresh rate.

[0042] The internal power supply generating unit 127 generates internal power supplies VPP, VBB, VBLH, VOD, VINT, etc., which are supplied to each unit of the semiconductor memory device 100, based on the power supplies VDD and VSS input from the outside.

[0043] FIG. 2 is a block diagram showing a configuration of the i-th memory block 101-i (i=1 to N) shown in FIG.

[0044] The i-th memory block 101-i includes a refresh control unit 201, a row hammer refresh address calculation unit 203, a row address multiplexer 205, a row decoder & bank logic unit 207, a logic inversion gate 209, logic AND gates 211, 213, 215, a logic OR gate 217, a column address decoder 221, an I / O gate & DM logic 223, a memory array 225, a word driver 227, and a sense amplifier 229. The row hammer refresh address calculation unit 203 corresponds to the "row hammer refresh address calculation circuit" of the present invention.

[0045] The refresh control unit 201 receives the signals TMRS, TMRHR, ACT, PREC, temperature data TS, and clock RFIP_i, and calculates the normal refresh address RFA, the signal CBRSLOT, and the signal RHRSLOT based on these.

[0046] The row hammer refresh address calculation unit 203 basically calculates the row hammer refresh address RHA based on the row address XADD2. Hereinafter, the "row hammer refresh address" may be referred to as "RHA." The row address XADD2 is supplied by the row address multiplexer 205 to the row decoder & bank logic unit 207 for access (write, read or refresh) to the memory array 225.

[0047] However, if a cell in the X-redundancy area is used instead of a cell in the row specified by row address XADD2, signal XREDMatch is activated. In this case, row address XRED of the X-redundancy area is used instead of row address XADD2 as the reference address for RHA calculation. Here, row address XRED is the row address of the memory cell actually accessed, and is input to row hammer refresh address calculation unit 203 from row decoder & bank logic unit 207.

[0048] Furthermore, the row hammer refresh address calculation unit 203 also uses the signals ACT, PREC, and RHR when calculating the RHA.

[0049] The row address multiplexer 205 selects, as the row address XADD2, one of the row address XADD1, the normal refresh address RFA, and the row hammer refresh address RHA based on the signals CBR and RHR. The row address XADD2 is supplied to a row decoder and bank logic unit 207.

[0050] The signal CBR has the logical level of the logical inversion signal of the signal RHRSLOT and the logical AND operation result of the signal CBRSLOT and the clock RFIP_i, and is obtained by passing these signals through a logical inversion gate 209 and a logical AND gate 211 .

[0051] The signal RHR has a logic level which is a result of a logical AND operation of the signal RHRSLOT and the clock RFIP_i, and is calculated by passing the signal RHRSLOT and the clock RFIP_i through a logical AND gate 213 .

[0052] The signal RFEXE has a logic level which is the result of an AND operation between the signal CBRSLOT and the signal RHRSLOT and the clock RFIP_i, and is calculated by passing the signal CBRSLOT, the signal RHRSLOT and the clock RFIP_i through an OR gate 217 and an AND gate 215 .

[0053] When the memory block 101-i is selected by the block selection signal BS_i, the row decoder & bank logic unit 207 decodes the row address XADD2 and selects a word line WL to be driven by the word drive unit 227 from among the word lines WL provided for each row of the memory array 225.

[0054] When the memory block 101-i is selected by the block selection signal BS_i, the column address decoder 221 decodes the column address YADD1 and selects a sense amplifier 229 corresponding to the bit line BL to be sensed from among the sense amplifiers 229 provided corresponding to each bit line BL of the memory array 225. The selected sense amplifier 229 senses the corresponding bit line BL at a timing according to the signal SAEn.

[0055] The I / O gate & DM logic 223 is interposed between the memory I / O bus MIO and the column I / O bus LIO, and controls the direction of data input / output based on the write signal WT and the read signal RD.

[0056] Fig. 3 is a block diagram showing a configuration of row hammer refresh address calculation unit 203 shown in Fig. 2. Also, Fig. 4 is a timing diagram of signals related to row hammer refresh address calculation unit 203.

[0057] 3, the row hammer refresh address calculation unit 203 includes a random number generation unit 231, AND gates 233 and 235, latches 237, 239 and 241, multiplexers 243 and 245, a control unit 247 and a calculation unit 249.

[0058] A first sampling signal Sample is calculated at random timing as shown in Fig. 4 by ANDing a signal EN generated at random timing by the random number generator 231 with a signal PREC by the AND gate 233. A second sampling signal Sample2 is calculated at random timing as shown in Fig. 4 by ANDing a signal EN2 generated at random timing independent of the signal EN by the random number generator 231 with a signal PREC by the AND gate 235.

[0059] The multiplexer 243 is supplied with a row address XADD2 from the row address multiplexer 205 via the row decoder & bank logic unit 207. In addition, the multiplexer 243 is supplied with a row address XRED and a signal XREDMatch from the row decoder & bank logic unit 207.

[0060] The multiplexer 243 selects either the row address XADD2 or the row address XRED as the row address XADDS in accordance with the signal XREDMatch.

[0061] The latch 237 outputs a signal obtained by randomly sampling the address XADDS using the first sampling signal Sample as the A-type seed address S1.

[0062] The latch 239 outputs a signal obtained by randomly sampling the address XADDS using the second sampling signal Sample2 as a type B seed address S2.

[0063] Here, the type A seed address S1 and the type B seed address S2 have in common that they can be obtained by randomly sampling the address XADDS. “Type A” and “Type B” are not classifications used to distinguish the physical properties of the seed addresses.

[0064] The control unit 247 calculates a distance switching signal PM2 and a priority / non-priority switching signal RHR2nd based on the RHR signal. Here, the distance switching signal PM2 is an example of a "first identification signal" of the present invention, and the priority / non-priority switching signal RHR2nd is an example of a "second identification signal" of the present invention.

[0065] Now, referring to FIG. 4, the pulses of the clock RFIP continue periodically. The signal RHRSLOT has a period corresponding to the refresh rate. In each period, the logic level of the signal RHRSLOT becomes HIGH for a period corresponding to two periods of the clock RFIP. The signal RHR is obtained by ANDing the clock RFIP and the signal RHRSLOT. Thus, two successive pulses of the signal RHR are generated in each period of the signal RHRSLOT.

[0066] The first of the two successive pulses of the signal RHR changes the logic level of the priority / non-priority switching signal RHR2nd from LOW to HIGH, and the second pulse changes the logic level of the priority / non-priority switching signal RHR2nd from HIGH to LOW.

[0067] In addition, the logic level of the distance switching signal PM2 is basically inverted by the second pulse of two consecutive pulses of the signal RHR, but it may not be inverted. This will be described later.

[0068] One unit period is from one falling edge of the priority / non-priority switching signal RHR2nd to the next falling edge. At the same time as the start of this period, a period in which the priority / non-priority switching signal RHR2nd is LOW begins, and when a pulse of the signal RHR occurs thereafter, the priority / non-priority switching signal RHR2nd becomes HIGH. When a pulse of the signal RHR occurs thereafter, the unit period ends and the priority / non-priority switching signal RHR2nd becomes LOW again.

[0069] The distance switching signal PM2 does not change during the unit period. The distance switching signal PM2 basically inverts every unit period, but there are times when it does not invert.

[0070] When the logic level of the distance switching signal PM2 is LOW, it specifies that two addresses respectively assigned to two adjacent word lines on both sides of a word line to which a seed address of type A is assigned in the arrangement of word lines in the memory array are calculated as the upper adjacent RHA and the lower adjacent RHA. When the logic level of the distance switching signal PM2 is HIGH, it specifies that two addresses respectively assigned to two adjacent word lines on both sides of a word line to which a seed address of type B is assigned in the arrangement of word lines in the memory array are calculated as the upper adjacent RHA and the upper adjacent RHA. Here, "upper" and "lower" refer to the permutation of the arrangement of word lines in the memory array.

[0071] When the priority / non-priority switching signal RHR2nd is at a LOW logic level, it specifies that of two RHAs calculated based on the same seed address (the same seed address of type A or the same seed address of type B), the RHA that precedes the other in time (i.e., the priority RHA) is to be calculated. On the other hand, when the logic level is at a HIGH logic level, it specifies that the RHA that follows the other in time (i.e., the non-priority RHA) is to be calculated.

[0072] Therefore, when the distance switching signal PM2 is LOW and the priority / non-priority switching signal RHR2nd is LOW, the priority adjacent RHA is designated as the RHA, when the distance switching signal PM2 is LOW and the priority / non-priority switching signal RHR2nd is HIGH, the non-priority adjacent RHA is designated as the RHA, when the distance switching signal PM2 is HIGH and the priority / non-priority switching signal RHR2nd is LOW, the priority adjacent RHA is designated as the RHA, and when the distance switching signal PM2 is HIGH and the priority / non-priority switching signal RHR2nd is HIGH, the non-priority adjacent RHA is designated as the RHA.

[0073] When the logical level of the distance switching signal PM2 is LOW, the multiplexer 245 selects the A-type seed address S1 as the seed address, and when the logical level of the distance switching signal PM2 is HIGH, the multiplexer 245 selects the B-type seed address S2 as the seed address.

[0074] When the logical level of the priority / non-priority switching signal RHR2nd is LOW, the latch 241 outputs the seed address supplied from the multiplexer 245 as the seed address Seed as is, and when the logical level of the priority / non-priority switching signal RHR2nd is HIGH, the latch 241 continues to output the seed address Seed that was present immediately before it became HIGH.

[0075] The calculation unit 249 calculates and outputs four types of RHA based on the seed address Seed in accordance with a combination of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd.

[0076] Furthermore, the A type seed address S1 randomly sampled by the latch 237 and the B type seed address S2 randomly sampled by the latch 239 are combined as one seed address Seed by the multiplexer 245. In practice, when the logical level of the distance switching signal PM2 is LOW, the A type seed address is selected as the seed address Seed, whereas when the logical level of the distance switching signal PM2 is HIGH, the B type seed address is selected as the seed address Seed.

[0077] Therefore, when the logical levels of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd are LOW, LOW, the calculation unit 249 calculates the priority adjacent RHA selected from the higher-side adjacent RHA and the lower-side adjacent RHA by a first calculation based on the seed address Seed of type A. Also, when the logical levels of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd are LOW, HIGH, the calculation unit 249 calculates the non-priority adjacent RHA selected from the higher-side adjacent RHA and the lower-side adjacent RHA by a second calculation based on the seed address Seed of type A.

[0078] Furthermore, when the logical levels of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd are HIGH and LOW, a priority neighbor RHA selected from the higher-side neighbor RHA and the lower-side neighbor RHA is calculated by a third calculation based on the seed address Seed of type B. Also, when the logical levels of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd are HIGH and HIGH, a non-priority neighbor RHA selected from the higher-side neighbor RHA and the lower-side neighbor RHA is calculated by a fourth calculation based on the seed address Seed of type B.

[0079] Here, the amount of calculation for the second calculation is greater than the amount of calculation for the first calculation, and the amount of calculation for the fourth calculation is greater than the amount of calculation for the third calculation.

[0080] The latch 237 and the latch 239 are an example of the "sampling unit" of the present invention.

[0081] 4, as already described, the signal RHRSLOT has a logic level of HIGH periodically for a period including two clocks. Note that the signal RHRSLOT is calculated by the refresh control unit 201, and in particular, the period of the signal RHRSLOT depends on the temperature indicated by the temperature data TS.

[0082] The signal RHR is generated at the same timing as the clock RFIP (AREF) during the period when the logic level of the signal RHRSLOT is HIGH. More specifically, the signal RHR is generated as two consecutive pulses in synchronization with the clock RFIP during the period when the logic level of the signal RHRSLOT is HIGH.

[0083] Before time tck5, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are LOW, LOW.

[0084] In the period from time tck5 to time tck6, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are HIGH and LOW.

[0085] In the period from time tck6 to time tck15, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are LOW and HIGH.

[0086] In the period from time tck15 to time tck16, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are HIGH, HIGH.

[0087] Similarly, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are essentially repeated between (LOW, LOW), (HIGH, LOW), (LOW, HIGH), and (HIGH, HIGH).

[0088] However, for example, at time tck16, the logic level of the distance switching signal PM2 does not change from LOW to HIGH. In such a case, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are repeated from (LOW, LOW), (HIGH, LOW) to (LOW, LOW), (HIGH, LOW). Similarly, although not shown, the logic level of the distance switching signal PM2 may not change from HIGH to LOW even at the timing when the logic level of the distance switching signal PM2 would normally change from HIGH to LOW. In such a case, the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are repeated from (LOW, HIGH), (HIGH, HIGH), (LOW, HIGH), (HIGH, HIGH). These will be described later.

[0089] The first sampling signal Sample is generated at times ts11, ts12, . . . , ts16, and the type A seed address S1 is updated at these times.

[0090] The second sampling signal Sample2 is generated at times ts21 and ts23, and the B-type seed address S2 is updated at these times.

[0091] As shown in FIG. 4, the type A seed addresses S1 corresponding to updates at times ts11, ts12, . . . , ts16 are assumed to be S1(1), S1(2), . . . , S1(6).

[0092] As shown in FIG. 4, the B type seed addresses S2 corresponding to the updates at times ts21 and ts22 are S2(2) and S2(3), and the B type seed address S2 before time ts21 is S2(1).

[0093] Next, the operation according to the flow of time will be described.

[0094] At time ts11, the A-type seed address S1 is updated to S1(1) by the first sampling signal Sample. Since the logical level of the distance switching signal PM2 is LOW, the A-type seed address S1(1) is selected as the seed address Seed. Furthermore, since the logical level of the distance switching signal PM2 is LOW and the logical level of the priority / non-priority switching signal RHR2nd is LOW, the priority adjacent RHA S1(1)±1 1st is calculated by the first calculation based on the A-type seed address S1(1). This continues until time tck5.

[0095] At time tck5, the logic level of the priority / non-priority switching signal RHR2nd changes from LOW to HIGH, and is maintained at this level until time tck6. Therefore, the A-type seed address S1(1) immediately before time tck5 is maintained as the seed address Seed until time tck6. In FIG. 4, the A-type seed address S1(1) is not updated between time tck5 and time tck6, but even if the A-type seed address S1(1) is updated between time tck5 and time tck6, the A-type seed address S1(1) immediately before time tck5 is maintained as the seed address Seed until time tck6.

[0096] From time tck5, the non-priority adjacent RHA S1(1)±1 2nd is calculated by the second calculation based on the A-type seed address S1(1) as the RHA. This continues until time tck6. Therefore, based on the same A-type seed address S1(1), the priority adjacent RHA S1(1)±1 1st is calculated by the first calculation, and then the non-priority adjacent RHA S1(1)±1 2nd is calculated by the second calculation.

[0097] Here, the second calculation involves more calculations than the first calculation, so a certain delay is required until all bits of the non-priority adjacent RHA S1(1)±1 2nd are determined. However, the non-priority adjacent RHA S1(1)±1 2nd can be calculated in synchronization with the corresponding pulse of the signal RHR.

[0098] At time tck6, the logic level of the distance switching signal PM2 changes from LOW to HIGH, and the logic level of the priority / non-priority switching signal RHR2nd changes from HIGH to LOW. Therefore, the B type seed address S2(1) is selected as the seed address Seed. Also, the priority adjacent RHA S2(1)±21st is calculated by the third calculation based on the B type seed address S2(1). This continues until time ts21. Note that the B type seed address S2(1) has already been determined before time tck1.

[0099] At time ts21, the logical level of the distance switching signal PM2 remains HIGH, and the logical level of the priority / non-priority switching signal RHR2nd remains LOW. However, the second sampling signal Sample2 updates the B-type seed address S2(1) to the B-type seed address S2(2). Therefore, the priority adjacent RHA S2(1)±21st calculated as the RHA by the third calculation based on the B-type seed address S2(1) is updated to the priority adjacent RHA S2(2)±21st calculated by the third calculation based on the B-type seed address S2(2).

[0100] At time tck15, the logic level of the priority / non-priority switching signal RHR2nd changes from LOW to HIGH, and is maintained at this level until time tck16. Therefore, the B type seed address S2(2) immediately before time tck15 is maintained as the seed address Seed until time tck16. In FIG. 4, the B type seed address S2(2) is not updated between time tck15 and time tck16, but even if the B type seed address S2(2) is updated between time tck15 and time tck16, the B type seed address S2(2) immediately before time tck15 is similarly maintained as the seed address Seed until time tck16.

[0101] From time tck15, the non-priority adjacent RHA S2(2)±2 2nd is calculated as the RHA by a fourth calculation based on the seed address S2(2) of type B. This continues until time tck16.

[0102] Here, the fourth calculation requires a larger amount of calculation than the third calculation, so a certain delay period is required until all bits of the non-priority adjacent RHA S2(2)±2 2nd are determined. However, the non-priority adjacent RHA S2(2)±2 2nd can be calculated in synchronization with the corresponding pulse of the signal RHR.

[0103] At time tck16, the logic level of the distance switching signal PM2 changes from HIGH to LOW, and the logic level of the priority / non-priority switching signal RHR2nd changes from HIGH to LOW. Therefore, the A-type seed address S1(2) is selected as the seed address Seed. Also, the priority adjacent RHA S1(2)±1 1st is calculated by the first calculation based on the A-type seed address S1(2). This continues until time ts13. Note that the A-type seed address S1(2) has already been determined at time ts12.

[0104] At time ts13, the logical level of the distance switching signal PM2 remains LOW, and the logical level of the priority / non-priority switching signal RHR2nd remains LOW. However, the A-type seed address S1(2) is updated to the A-type seed address S1(3) by the first sampling signal. Therefore, the priority adjacent RHA S1(2)±1 1st calculated as the RHA by the first calculation based on the A-type seed address S1(2) is updated to the priority adjacent RHA S1(3)±1 1st calculated by the first calculation based on the A-type seed address S1(3).

[0105] At time ts14, similarly to time ts13, the logical level of the distance switching signal PM2 is maintained at LOW, and the logical level of the priority / non-priority switching signal RHR2nd is maintained at LOW. However, the A-type seed address S1(3) is updated to the A-type seed address S1(4) by the first sampling signal. Therefore, the priority adjacent RHA S1(3)±1 1st calculated as the RHA by the first calculation based on the A-type seed address S1(3) is updated to the priority adjacent RHA S1(4)±1 1st calculated by the first calculation based on the A-type seed address S1(4).

[0106] At time ts15, similarly to times ts13 and ts14, the logical level of the distance switching signal PM2 is still maintained at LOW, and the logical level of the priority / non-priority switching signal RHR2nd is still maintained at LOW. However, the A-type seed address S1(4) is updated to the A-type seed address S1(5) by the first sampling signal. Therefore, the priority adjacent RHA S1(4)±1 1st calculated as the RHA by the first calculation based on the A-type seed address S1(4) is updated to the priority adjacent RHA S1(5)±1 1st calculated by the first calculation based on the A-type seed address S1(5).

[0107] At time tck25, the logic level of the priority / non-priority switching signal RHR2nd changes from LOW to HIGH, and this is maintained until time tck26. Therefore, the A-type seed address S1(5) immediately before time tck25 is maintained as the seed address Seed until time tck26. In Fig. 4, the A-type seed address S1(5) is updated to S1(6) between time tck25 and time tck26, but the A-type seed address S1(5) immediately before time tck25 is maintained as the seed address Seed until time tck6.

[0108] From time tck25, the non-priority adjacent RHA S1(5)±1 2nd is calculated by the fourth calculation based on the A-type seed address S1(5) as the RHA. This continues until time tck26 when the logic level of the priority / non-priority switching signal RHR2nd changes from HIGH to LOW.

[0109] Here, to avoid duplication, the first sampling signal Sample is generated at time ts16, which belongs to the period during which the logic level of the priority / non-priority switching signal RHR2nd is HIGH from time tck25 to time t26. As a result, the first sampling signal S1(5) is updated to the first sampling signal S1(6).

[0110] However, the update from the non-priority adjacent RHA S1(5)±1 2nd to the priority adjacent RHA S1(6)±1 1st corresponding to the first sampling signal S1(6) is not performed at time ts16, but is performed at time tck26 when the logical level of the priority / non-priority switching signal RHR2nd changes from HIGH to LOW.

[0111] Normally, at time tck26, the logical level of the distance switching signal PM2 changes from LOW to HIGH. However, since the first sampling signal Sample was generated at time ts16, which belongs to the period from time tck25 to time t26 when the logical level of the priority / non-priority switching signal RHR2nd is HIGH, the logical level of the distance switching signal PM2 is maintained at LOW.

[0112] Incidentally, although not shown, there is also an operation example in which the adjacent RHA and the adjacent adjacent RHA are swapped with respect to the example shown in Fig. 4. In this case, the second sample signal is generated at the timing when the first sample signal is generated, and the first sample signal is generated at the timing when the second sample signal is generated. Therefore, the timing of the A type seed address S1 and the B type seed address S2 are swapped. Also, the polarity of the distance switching signal PM2 is inverted.

[0113] The timing of adjacent RHA S1(i)±1 is replaced with the timing of the next adjacent RHA S2(i)±2, and the timing of the next adjacent RHA S2(j)±2 is replaced with the timing of adjacent RHA S1(j)±1.

[0114] 5 shows the layout pattern of a portion corresponding to 16 row lines in memory array 225. In memory array 225, this layout pattern is repeated.

[0115] Referring to FIG. 5, the memory array 225 is wired with eight select lines FXL corresponding to the decoded results of the lower three bits of the row address, and multiple select lines MWL corresponding to the decoded results of the higher bits of the row address.

[0116] The sub-word driver 305 selected by both the activated selection line MWL and the activated selection line FXL is activated, and the row line SWL connected thereto is activated.

[0117] The sub-word drivers 305 arranged below the row lines are arranged every two row lines, and the sub-word drivers 305 arranged above the lines are also arranged every two row lines. These are arranged alternately with respect to the row lines.

[0118] Four of the eight selection lines FXL correspond to the sub-word driver 305 arranged below, and are arranged below the sub-word driver 305 .

[0119] The remaining four selection lines FXL of the eight selection lines FXL correspond to the sub-word driver 305 arranged above, and are arranged above the sub-word driver 305 .

[0120] The four select lines FXL on the lower side are arranged in the order of 000, 010, 100, and 110 from the bottom in terms of the last four digits of the logical row address. Also, the four select lines FXL on the upper side are arranged in the order of 001, 011, 101, and 111 from the bottom in terms of the last four digits of the logical row address. Therefore, the four select lines FXL corresponding to even-numbered logical row addresses are arranged on the lower side, and the four select lines FXL corresponding to odd-numbered logical row addresses are arranged on the upper side.

[0121] Focusing on the four selection lines FXL on the lower side, the selection lines FXL and the wiring 309 are arranged so that the intersections 311 of the wiring 309 connecting each selection line FXL and each sub-word driver 305 are in a zigzag pattern at a period of eight sub-word drivers 305.

[0122] Similarly, looking at the four upper selection lines FXL and the wiring 309, the selection lines FXL and the wiring 309 are arranged so that the intersections 311 of the wiring 309 connecting each selection line FXL and each sub-word driver 305 are in a zigzag pattern at a period of eight sub-word drivers 305.

[0123] Intersections 311-0 to 311-f, which correspond to the last four digits 0 to f of the row address expressed in binary, respectively, are placed at the positions shown in FIG.

[0124] Sub-word drivers 305-0 to 305-f, which correspond to the last four digits 0 to f of the row address expressed in binary, respectively, are arranged at the positions shown in Fig. 5. Each sub-word driver 305 is connected to a selection line FXL via a cross point 311 and a wiring 309.

[0125] Therefore, when the remainder when a row address is divided by 16 is expressed in hexadecimal from zero to f, the word lines assigned with row addresses with a remainder of zero to the word lines assigned with row addresses with a remainder of f are arranged as shown in Figure 5. In other words, when expressed as the remainder when the row address assigned to the word lines is divided by 16 (expressed as a hexadecimal number corresponding to the lower 4 bits of the row address), the word lines in memory array 225 are arranged as follows: 0, 1, 2, 3, 4, 5, 6, 7, e, f, c, d, a, b, 8, 9 Line up in the order of:

[0126] Therefore, if the order assigned to the word lines in accordance with the order of the word lines in the arrangement in the memory array 225 is called the physical row address, and the row address XADD2 input to the row decoder & bank logic unit 207, which was simply called the row address above, is called the logical row address, then the correspondence between the lower 4 bits of the physical row address and the lower 4 bits of the logical row address is as follows, as shown in FIG. Physical row address Logical row address (0) 0 (1) 1 (twenty two (3) 3 (4) 4 (5) 5 (6) 6 (7) 7 (8) e (9) f (a) c (b) d (c) a (d) b (e) 8 (f) 9 It turns out to be.

[0127] As described above, the row lines SWL are arranged in the order of physical row addresses in the memory array 225. Therefore, any two arbitrarily selected row lines SWL are spaced apart from each other by a distance corresponding to the difference between the two physical row addresses corresponding to them.

[0128] Further, referring to FIG. The word line assigned logical row address 0 is assigned physical address (0). The word line assigned logical row address 1 is assigned physical address (1). The word line assigned logical row address 2 is assigned physical address (2). The word line assigned logical row address 3 is assigned physical address (3). The word line assigned logical row address 4 is assigned physical address (4). The word line assigned logical row address 5 is assigned physical address (5). The word line assigned logical row address 6 is assigned a physical address (6). The word line assigned logical row address 7 is assigned a physical address (7). The word line assigned logical row address 8 is assigned physical address (e). The word line to which logical row address 9 is assigned is assigned a physical address (f). A physical address (c) is assigned to the word line to which the logical row address a is assigned. The word line to which logical row address b is assigned is assigned a physical address (d). The word line to which logical row address c is assigned is assigned physical address (a). A word line to which logical row address d is assigned is assigned a physical address (b). The word line to which the logical row address e is assigned is assigned a physical address (8). The word line to which the logical row address f is assigned is assigned a physical address (9).

[0129] Also, looking backwards, The word line assigned physical address (0) is assigned logical row address 0. The word line assigned physical address (1) is assigned logical row address 1. The word line assigned physical address (2) is assigned logical row address 2. The word line assigned physical address (3) is assigned logical row address 3. The word line assigned physical address (4) is assigned logical row address 4. The word line assigned physical address (5) is assigned logical row address 5. The word line assigned physical address (6) is assigned logical row address 6. The word line assigned physical address (7) is assigned logical row address 7. The word line to which the physical address (8) is assigned is assigned the logical row address e. The word line to which the physical address (9) is assigned is assigned the logical row address f. A word line assigned physical address (a) is assigned logical row address c. A word line assigned with a physical address (b) is assigned a logical row address (d). A word line to which a physical address (c) is assigned is assigned a logical row address a. The word line to which the physical address (d) is assigned is assigned the logical row address b. The word line to which the physical address (e) is assigned is assigned the logical row address 8. The word line to which the physical address (f) is assigned is assigned the logical row address 9.

[0130] Therefore, for example, if logical row address 2 is selected as the A-type seed address (A-type logical seed address), the corresponding physical address (physical seed address) is (2). Then, the physical addresses (physical RHAs) corresponding to the adjacent RHAs (logical adjacent RHAs) are (1) and (3) adjacent to (2), and the adjacent RHAs (logical adjacent RHAs) are 1 and 3. Also, for example, if logical row address 7 is selected as the A-type seed address (A-type logical seed address), the corresponding physical address (physical seed address) is (7). Then, the physical addresses (physical RHAs) corresponding to the adjacent RHAs (logical adjacent RHAs) are (6) and (8) adjacent to (7), and the adjacent RHAs (logical adjacent RHAs) are 6 and e. Furthermore, for example, if logical row address b is selected as the A-type seed address (A-type logical seed address), the corresponding physical address (physical seed address) is (d). Then, the physical addresses (physical RHAs) corresponding to the adjacent RHAs (logical adjacent RHAs) are (c) and (e) adjacent to (d), and the adjacent RHAs (logical adjacent RHAs) are a and 8.

[0131] Furthermore, for example, if logical row address 2 is selected as a type B seed address (type B logical seed address), the corresponding physical address (physical seed address) is (2). Then, the physical addresses (physical RHAs) corresponding to the next-neighbor RHAs (logical next-neighbor RHAs) are (0) and (4) adjacent to (2), and the next-neighbor RHAs (logical next-neighbor RHAs) are 0 and 4. Furthermore, for example, if logical row address e is selected as a type B seed address (type B logical seed address), the corresponding physical address (physical seed address) is (8). Then, the physical addresses (physical RHAs) corresponding to the next-neighbor RHAs (logical next-neighbor RHAs) are (6) and (a) adjacent to (8), and the next-neighbor RHAs (logical next-neighbor RHAs) are 6 and c. Furthermore, for example, if logical row address b is selected as a type B seed address (type B logical seed address), the corresponding physical address (physical seed address) is (d). Then, the physical addresses (physical RHAs) corresponding to the next-neighbor RHAs (logical next-neighbor RHAs) are (b) and (f) adjacent to (d), and the next-neighbor RHAs (logical next-neighbor RHAs) are d and 9.

[0132] 6 is a diagram showing the correspondence between seed addresses and row hammer refresh addresses. The left side shows the correspondence between A-type seed addresses and adjacent RHAs, and the right side shows the correspondence between B-type seed addresses and the adjacent RHAs. Note that only the lower 4 bits are shown in FIG. 6.

[0133] 6, it can be seen that the logical adjacent RHA 3 can be calculated simply by inverting the least significant bit of the A type logical seed address 2 from 0 to 1. It can also be seen that the logical adjacent RHA 6 can be calculated simply by inverting the least significant bit of the A type logical seed address 7 from 1 to 0. Furthermore, it can be seen that the logical adjacent RHA a can be calculated simply by inverting the least significant bit of the A type logical seed address b from 1 to 0. This operation corresponds to the first operation.

[0134] However, the logical adjacent RHA 8 cannot be calculated by simply inverting the least significant bit of the A type logical seed address b. In order to calculate the adjacent RHA 8 from the A type logical seed address b, in addition to inverting the least significant bit from 1 to 0, it is necessary to invert the second least significant bit from 1 to 0. This requires a somewhat complicated calculation such as carry processing. This calculation corresponds to the second calculation.

[0135] Therefore, the preferred neighboring RHA corresponding to the logical seed address b of type A is a, and the non-preferred neighboring RHA is 8.

[0136] 6, it can be seen that the logical neighbor RHA 0 can be calculated simply by inverting the second least significant bit of the B type logical seed address 2 from 1 to 0. It can also be seen that the logical neighbor RHA c can be calculated simply by inverting the second least significant bit of the B type logical seed address e from 1 to 0. Furthermore, it can be seen that the logical neighbor RHA 9 can be calculated simply by inverting the second least significant bit of the B type logical seed address b from 1 to 0. This operation corresponds to the third operation.

[0137] However, the adjacent RHA d cannot be calculated from the seed address b by simply inverting the second least significant bit of the B type logical seed address b. In order to calculate the adjacent RHA d from the B type logical seed address b, it is necessary to invert the third least significant bit from 0 to 1 in addition to inverting the second least significant bit from 1 to 0. This requires a somewhat complicated calculation such as carry processing. This calculation corresponds to the fourth calculation.

[0138] Therefore, the preferred adjacent RHA corresponding to the logical seed address b of type B is 9, and the non-preferred adjacent RHA is d.

[0139] In addition, the physical RHA corresponding to the logical RHA of type A can be obtained by adding or subtracting 1 to the physical seed address corresponding to the logical seed address of type A. Therefore, in order to obtain a logical adjacent address from the logical seed address of type A, for example, (SA1) A physical seed address is obtained from the A type logical seed address (perform forward translation). (SA2) A physical adjacent RHA is obtained by adding or subtracting 1 from the physical seed address (shifting the physical address). (SA3) A logically adjacent RHA is obtained from the physically adjacent RHA (performing a reverse transformation). The method involves three steps:

[0140] Similarly, the physical RHA corresponding to the logical RHA of type B can be obtained by adding or subtracting 2 to or from the physical seed address corresponding to the logical seed address of type B. Therefore, in order to obtain the logical adjacent address from the logical seed address of type B, for example, (SB1) A physical seed address is obtained from the B type logical seed address (perform forward conversion). (SB2) The physical seed address is added or subtracted by 2 to obtain the physical adjacent RHA (the physical address is shifted). (SB3) A logical adjacent RHA is obtained from the physical adjacent RHA (performing a reverse transformation). The method involves three steps:

[0141] Here, to obtain the physical seed address from the logical seed address by forward conversion, a table showing the correspondence between the two may be referenced, but for example, the following bit operation may be executed. Logical seed address: (Ain<n:3+1> , Ain <3> ,Ain <2> ,Ain <1> ,Ain <0> ) Physical Seed Address: (APin<n:3+1> , APin <3> ,APin <2> ,APin <1> ,APin <0> ) Calculations: APin <0> = Ain <0> APin <1> = Ain <1> ^ Ain <3> APin <2> = Ain <2> ^ Ain <3> APin <3> = Ain <3> APin<n:3+1> = Ain<n:3+1> The operator ^ denotes the logical exclusive-or operation.

[0142] Similarly, to obtain the logically adjacent RHA from the physically adjacent RHA by reverse conversion, a table showing the correspondence between the two may be referenced, but for example, the following bit operations may be executed. Physical RHA: (APout<n:3+1> , APout <3> ,Aout <2> ,Aout <1> ,Aout <0> ) Logical RHA: (Aout<n:3+1> , Aout <3> ,Aout <2> ,Aout <1> ,Aout <0> ) Calculations Aout <0> = APout <0> Aout <1> = APout <1> ^ <apout3> August <2> = APout <2> ^ <apout3> Aout <3> = APout <3> Aout<n:3+1> = APout<n:3+1> The operator ^ denotes the logical exclusive-or operation. The logical adjacent RHA may be similarly obtained from the physical adjacent RHA.

[0143] FIG. 7 is a circuit diagram showing a configuration of the calculation unit 249 shown in FIG.

[0144] As already described, the calculation unit 249 calculates and outputs four types of RHA based on the seed address Seed in accordance with the combination of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd.

[0145] The calculation unit 249 calculates the lower 4 bits Aout<3:0> of the RHA and the carry C based on the lower 4 bits Ain<3:0> of the seed address, the distance switching signal PM2, and the priority / non-priority switching signal RHR2nd. <3> The calculation unit 249 also includes a modified 4-bit adder 4 for calculating the positive / negative switching signal SWPM. <n-1:4>, Carrie C <3> And the part Aout higher than the lower 4 bits of RHA based on the plus / minus switching signal SWPM <n:4>Here, m is n-4, where n is the number of bits constituting the RHA.

[0146] More specifically, the modified 4-bit adder 401 calculates the lower 4 bits Aout<3:0> of the logical RHA (that is, RHA) corresponding to the lower 4 bits Ain<3:0> of the logical seed address Seed, the carry-out C <3> and calculates the plus / minus switching signal SWPM. The configuration of the modified 4-bit adding section 401 will be described later.

[0147] As already explained, the distance switching signal PM2 is a signal for specifying whether to calculate adjacent RHA or adjacent RHA. Also, the priority / non-priority switching signal RHR2nd is a signal for specifying whether to calculate a priority RHA (priority adjacent RHA or priority adjacent RHA) or a non-priority RHA (non-priority adjacent RHA or non-priority adjacent RHA) for the same seed address. The plus / minus switching signal SWPM is a signal for specifying whether to calculate a higher-order RHA or a lower-order RHA in the order of physical addresses for the same seed address.

[0148] The half adder 411 includes exclusive OR gates 412 and 413 and an AND gate 414. The half adder 411 is also provided for each bit in the modified 4-bit addition unit 401 (see FIG. 10).

[0149] The exclusive OR gate 412 included in the half adder 411 calculates the corresponding bit Ain (where i=4 to n-1) and the carry-in C from the lower bit <i-1>and store the result in the output address Aout The output is as follows:

[0150] In addition, the exclusive OR gate 413 included in the half adder 411 outputs the corresponding bit Ain (where i=4 to n-1) and the plus / minus switching signal SWPM are exclusive-ORed.

[0151] Furthermore, the logical product gate 414 included in the half adder 411 receives the carry-in C <i-1>and the result of the exclusive OR operation by the exclusive OR gate 412 is carried out as a carry-out C The output is as follows:

[0152] The plus / minus switching signal SWPM is calculated within the modified 4-bit adder 401 as will be described next.

[0153] That is, as shown in FIG. 9, when the distance switching signal PM2 is LOW and the adjacent RHA is designated, the logic level of the priority / non-priority switching signal RHR2nd and the bit Ain included in the seed address <0> The logic level of the plus / minus switching signal SWPM is determined by the combination of the logic levels of the bits Ain and Aind. <0> When the priority / non-priority switching signal RHR2nd is HIGH and the non-priority RHA is specified, the logic level of the bit Ain <0> The inverted logic level of the positive / negative switching signal SWPM is the logic level of the positive / negative switching signal SWPM.

[0154] Therefore, as shown in FIG. 9, when the distance switching signal PM2 is LOW, which designates the adjacent RHA, and the priority / non-priority switching signal RHR2nd is LOW, which designates the priority RHA, the least significant bit Ain <0> If Ain is LOW, the operation +1 is specified and the least significant bit Ain of the seed address is <0> If is HIGH, a -1 operation is specified.

[0155] When the distance switching signal PM2 is LOW, thereby designating the adjacent RHA, and the priority / non-priority switching signal RHR2nd is HIGH, thereby designating the non-priority RHA, the least significant bit Ain of the seed address <0> If Ain is LOW, the operation -1 is specified and the least significant bit Ain of the seed address is <0> If is HIGH, a +1 operation is specified.

[0156] Here, the "-1 operation" is an operation for calculating the RHA (upper adjacent RHA) assigned to the wiring that is one step away from the wiring to which the A type seed address is assigned in the order of physical addresses. Also, the "+1 operation" is an operation for calculating the RHA (lower adjacent RHA) assigned to the wiring that is one step away from the wiring to which the A type seed address is assigned in the order of physical addresses.

[0157] Also, as shown in FIG. 9, when the distance switching signal PM2 is HIGH and the adjacent RHA is designated, the priority / non-priority switching signal RHR2nd and the bit Ain included in the seed address <1> And Ain <3> The plus / minus switching signal SWPM is determined by the combination of the results of the exclusive OR operation of the above. When the priority / non-priority switching signal RHR2nd is LOW and the priority RHA is specified, the bit Ain <1> And Ain <3> The logic level of the result of the exclusive OR operation of these becomes the logic level of the plus / minus switching signal SWPM as it is. When the priority / non-priority switching signal RHR2nd is HIGH and the non-priority RHA is specified, the bit Ain <1> And Ain <3> The logic level of the result of the exclusive OR operation is inverted to become the logic level of the plus / minus switching signal SWPM.

[0158] As already explained, the seed address bit Ain <1> And Ain <3> The result of the exclusive OR operation of the bit APin of the physical seed address. <1> Corresponds to.

[0159] Therefore, as shown in FIG. 9, when the distance switching signal PM2 is HIGH, the adjacent RHA is designated, and the priority / non-priority switching signal RHR2nd is LOW, the priority RHA is designated, the bit Ain <1> And Ain <3> If the result of the exclusive OR operation of is LOW, the +2 operation is specified and the seed address bit Ain <1> And Ain <3> If the result of the exclusive OR operation on these two is HIGH, then an operation of -2 is specified.

[0160] When the distance switching signal PM2 is LOW, adjacent RHA is designated, and the priority / non-priority switching signal RHR2nd is HIGH, non-priority RHA is designated, the bit Ain <1> And Ain <3> If the result of the exclusive OR operation of is LOW, the -2 operation is specified and the Ain bit of the seed address is <1> And Ain <3> If the result of the exclusive OR operation of is HIGH, a +2 operation is specified.

[0161] Here, the "-2 operation" is an operation for calculating the RHA (next-upper adjacent RHA) assigned to the wiring that is 2 away from the wiring to which the B type seed address is assigned in the order of physical addresses. Also, the "+2 operation" is an operation for calculating the RHA (next-lower adjacent RHA) assigned to the wiring that is 2 away from the wiring to which the B type seed address is assigned in the order of physical addresses.

[0162] Here, the A type seed address, the upper adjacent RHA, the lower adjacent RHA, the priority adjacent RHA, and the non-priority adjacent RHA are grouped together as shown in Figure 8(a). Also, the B type seed address, the upper adjacent RHA, the lower adjacent RHA, the priority adjacent RHA, and the non-priority adjacent RHA are grouped together as shown in Figure 8(b). The correspondence between physical addresses and logical addresses is shown in Figure 8(c). Here, all the addresses shown in the tables of Figures 8(a) and 8(b) are logical addresses, but the corresponding physical addresses can be found by referring to Figure 8(c).

[0163] In order to obtain the upper adjacent RHA corresponding to the A type seed address, the physical A type seed address is obtained from the A type seed address by referring to the table in Fig. 8(c), and a physical address that is one less than the physical A type seed address is obtained as the physical upper adjacent RHA. The logical address that corresponds to the physical upper adjacent RHA is the upper adjacent RHA.

[0164] To obtain the lower adjacent RHA corresponding to the A type seed address, the physical A type seed address is obtained from the A type seed address by referring to the table in Fig. 8(c), and a physical address that is 1 greater than the physical A type seed address is obtained as the physical lower adjacent RHA. The logical address that corresponds to the physical lower adjacent RHA is the lower adjacent RHA.

[0165] To obtain the upper adjacent RHA corresponding to the B type seed address, the physical B type seed address is obtained from the B type seed address by referring to the table in Fig. 8(c), and a physical address that is 2 less than the physical B type seed address is obtained as the physical upper adjacent RHA. The logical address corresponding to the physical upper adjacent RHA is the upper adjacent RHA.

[0166] To obtain the lower adjacent RHA corresponding to the seed address of type B, the physical seed address of type B is obtained from the seed address of type B with reference to the table in Fig. 8(c), and a physical address that is two greater than the physical seed address of type B is obtained as the physical lower adjacent RHA. The logical address that corresponds to the physical lower adjacent RHA is the lower adjacent RHA.

[0167] FIG. 10 is a circuit diagram showing an example of the configuration of the modified 4-bit adding unit 401 shown in FIG.

[0168] As already explained, the modified 4-bit addition unit 401 includes four half adders 411 each corresponding to each bit of Ain<3:0> of the RHA to be calculated.

[0169] In addition, the modified 4-bit adder 401 converts the seed address Seed into a physical seed address by subtracting the bit Ain <1> , the bit Ain of the seed address Seed <2> The circuit 430 includes an exclusive OR gate 433 corresponding to:

[0170] Exclusive OR gate 432 receives the seed address bit Ain <1> And a bit <3> The result of the exclusive OR operation of the physical seed address bit APin <1> Similarly, the exclusive OR gate 433 outputs the seed address bit Ain <2> And a bit <3> The result of the exclusive OR operation of the physical seed address bit APin <2> The output is as follows:

[0171] Also, the bit APin of the physical seed address <n-1:3>and APin <0> is the seed address bit Ain <n-1:3>and Ain <0> is equivalent to.

[0172] Therefore, the exclusive OR gates 432 and 433 constitute the main part of a conversion section from a seed address Seed to a physical seed address (corresponding to the "forward address conversion section" of the present invention).

[0173] Furthermore, the modified 4-bit adder 401 converts the physical RHA back to the RHA by subtracting the bit Aout <1> The exclusive OR gate 482 corresponds to the bit Aout of RHA. <2> The circuit 480 includes an exclusive OR gate 483 corresponding to:

[0174] The exclusive OR gate 482 outputs the bit APout of the physical RHA. <1> and Bit APout <3> The result of the exclusive OR operation is stored in the Aout bit of RHA. <1> Similarly, an exclusive-OR gate 483 outputs the bit APout of the physical RHA as <2> and Bit APout <3> The result of the exclusive OR operation is stored in the Aout bit of RHA. <2> The output is as follows:

[0175] Also, the RHA bit Aout <n-1:3>and Aout <0> is the physical RHA bit APout <n-1:3>and APout <0> is equivalent to.

[0176] Therefore, the exclusive OR gates 482 and 483 constitute the main part of a physical RHA to RHA conversion section (corresponding to the "reverse address conversion section" of the present invention).

[0177] Furthermore, the modified 4-bit adding unit 401 includes a logic inversion gate 431 that calculates a signal EN1 that is an inverted logical level of the distance switching signal PM2.

[0178] Further, the modified 4-bit adder unit 401 includes a multiplexer 434 and an exclusive-OR gate 435. The exclusive-OR gates 432, 435 and the multiplexer 434 are used to calculate the plus-minus switching signal SWPM by a combination of signals as described with reference to FIG.

[0179] Furthermore, the modified 4-bit adder 401 includes a multiplexer 481. The multiplexer 481 receives, as the signal EN2, a signal at logic level HIGH or the carry-out C from the half adder 411 corresponding to the least significant bit, under the control of the distance switching signal PM2. <0> Output.

[0180] Here, the least significant bit <0> The half adder 411 corresponding to the most significant bit <n-1>The half adder 411 and the multiplexer 481 correspond to the "physical address shift unit" of the present invention.

[0181] Next, the operation will be described. When the logical level of the distance switching signal PM2 is LOW, which designates that the adjacent RHA is to be calculated based on the A-type seed address, a signal EN1 with a logical level of HIGH is input to the carry-in terminal (the input terminal common to the exclusive OR gate 412 and the logical AND gate 414) of the half adder 411 corresponding to the least significant bit. Therefore, the bit Ain of the first type seed address <0> The opposite logic level of the RHA bit is Aout <0> The logic level is:

[0182] In addition, when the logical level of the distance switching signal PM2 is LOW, which specifies that the adjacent RHA is calculated based on the A type seed address, and the logical level of the priority / non-priority switching signal RHR2nd is LOW, which specifies that the priority adjacent RHA is calculated from the two adjacent RHAs, the multiplexer 434 and the exclusive OR gate 435 select the plus / minus switching signal SWPM as Ain <0> Therefore, in this case, RHA is calculated as follows:

[0183] Bit Ain of seed address of type A <0> If the bit Ain of the seed address of type A is LOW, the plus / minus switching signal SWPM becomes LOW, and the lower adjacent (+1) RHA of the two adjacent RHAs is calculated as the priority adjacent RHA. <0> If Ain is HIGH, the plus / minus switching signal SWPM becomes HIGH, and the higher (-1) adjacent RHA of the two adjacent RHAs is calculated as the priority adjacent RHA. In these cases, the necessary calculation is <0> The only operation is to invert the bit line . No carry processing is required in any of the half adders 411 included in the calculation unit 249. However, the operations in the exclusive OR gates 432, 433, 482, and 483 are executed.

[0184] In addition, when the logical level of the distance switching signal PM2 is LOW, which specifies that the adjacent RHA is calculated based on the A type seed address, and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, which specifies that the non-priority adjacent RHA of the two adjacent RHAs is calculated, the multiplexer 434 and the exclusive OR gate 435 select the plus / minus switching signal SWPM as Ain <0> Therefore, in this case, RHA is calculated as follows:

[0185] Bit Ain of seed address of type A <0> If the bit Ain of the seed address of type A is LOW, the plus / minus switching signal SWPM becomes HIGH, and the higher adjacent (-1) RHA of the two adjacent RHAs is calculated as the non-priority adjacent RHA. <0> If is HIGH, the plus / minus switching signal SWPM becomes LOW, and the lower adjacent (+1) RHA of the two adjacent RHAs is calculated as the non-priority adjacent RHA. In these cases, the necessary calculation is the least significant bit Ain <0> In addition, the calculation is not limited to the calculation of inverting the arithmetic operation. A process including carry processing is also required in at least a part of the half adder 411 included in the calculation unit 249. The calculations in the exclusive OR gates 432, 433, 482, and 483 are also performed.

[0186] In addition, when the logical level of the distance switching signal PM2 is HIGH, which specifies that the adjacent RHA is calculated based on the seed address of type B, and the logical level of the priority / non-priority switching signal RHR2nd is LOW, which specifies that the priority adjacent RHA is calculated from the two adjacent RHAs, the multiplexer 434 and the exclusive OR gate 435 select the plus / minus switching signal SWPM as Ain <1> And Ain <3> The logic level of the exclusive OR of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> Therefore, in this case, RHA is calculated as follows:

[0187] Bit Ain of seed address of type B <1> And Ain <3> The result of the exclusive OR operation of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> ) is LOW, the plus / minus switching signal SWPM becomes LOW, and the lower adjacent adjacent RHA (+2) of the two adjacent adjacent RHAs is calculated as the priority adjacent RHA. On the other hand, if the bit Ain <1> And Ain <3> The result of the exclusive OR operation of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> ) is HIGH, the plus / minus switching signal SWPM is HIGH, and the higher-order adjacent neighbor (-2) RHA of the two adjacent neighbor RHAs is calculated as the priority adjacent neighbor RHA. In these cases, the necessary calculation is the second least significant bit APin of the seed address of type B. <1> The only operation is to invert the bit line . No carry processing is required in any of the half adders 411 included in the calculation unit 249. However, the operations in the exclusive OR gates 432, 433, 482, and 483 are executed.

[0188] In addition, when the logical level of the distance switching signal PM2 is HIGH, which specifies that the adjacent RHA is calculated based on the seed address of type B, and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, which specifies that the non-priority adjacent RHA of the two adjacent RHAs is calculated, the multiplexer 434 and the exclusive OR gate 435 select the plus / minus switching signal SWPM as Ain <1> And Ain <3> The logic level of the inverted exclusive OR of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> Therefore, in this case, the physical RHA is calculated as follows:

[0189] Bit Ain of seed address of type B <0> And Ain <3> The result of the exclusive OR operation of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> ) is LOW, the plus / minus switching signal SWPM becomes HIGH, and the higher-order adjacent RHA (-2) of the two adjacent RHAs is calculated as the non-priority adjacent RHA. On the other hand, if the Ain <1> And Ain <3> The result of the exclusive OR operation of the second least significant bit APin of the physical address corresponding to the seed address of type B <1> ) is HIGH, the plus / minus switching signal SWPM is LOW, and the lower adjacent adjacent RHA (+2) of the two adjacent adjacent RHAs is calculated as the priority adjacent RHA. In these cases, the necessary calculation is <1> In addition, the calculation is not limited to the calculation of inverting the arithmetic operation. A process including carry processing is also required in at least a part of the half adder 411 included in the calculation unit 249. The calculations in the exclusive OR gates 432, 433, 482, and 483 are also performed.

[0190] Here, although the explanation is partially repeated, referring to Fig. 4, during the period when the logic levels of the priority / non-priority switching signal RHR2nd and the distance switching signal PM2 are LOW, the A-type adjacent RHA can be updated by simply inverting the least significant bit of the seed address S1 immediately after the A-type seed address S1 is updated by the first sampling signal Sample. This is because one of the two adjacent RHAs (the upper adjacent RHA and the lower adjacent RHA) is selected as the priority adjacent RHA by the above logic.

[0191] Also, if the logic level of the priority / non-priority switching signal RHR2nd changes from LOW to HIGH while the logic level of the distance switching signal PM2 is maintained at LOW, the priority adjacent RHA is switched to the non-priority adjacent RHA in synchronization with this. In other words, if the higher-order adjacent address is selected as the priority adjacent RHA, it is switched to the lower-order adjacent address as the non-priority adjacent RHA. Conversely, if the lower-order adjacent address is selected as the priority adjacent RHA, it is switched to the higher-order adjacent address as the non-priority adjacent RHA.

[0192] Furthermore, during a period when the logical level of the distance switching signal PM2 is LOW and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, even if the type A seed address S1 is updated by the first sampling signal Sample, the seed address Seed supplied to the calculation unit 249 is held by the latch 241 controlled by the priority / non-priority switching signal RHR2nd, so that it is possible to avoid updating the RHA during this period. In other words, during a period when the logical level of the distance switching signal PM2 is LOW and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, it is possible to avoid updating the RHA by processing including the carry processing based on the new seed address.

[0193] Similarly, in a period in which the logic level of the priority / non-priority switching signal RHR2nd is LOW and the logic level of the distance switching signal PM2 is HIGH, immediately after the seed address S2 of type B is updated by the second sampling signal Sample2, the physical address corresponding to the RHA can be updated by simply inverting the second least significant bit of the physical address corresponding to the seed address S2 of type B for the group of half adders 411. This is because one of the two adjacent RHAs (the upper adjacent RHA and the lower adjacent RHA) is selected as the priority adjacent RHA by the above logic.

[0194] Also, if the logic level of the priority / non-priority switching signal RHR2nd changes from LOW to HIGH while the logic level of the distance switching signal PM2 is maintained at HIGH, the priority adjacent RHA is switched to the non-priority adjacent RHA in synchronization with this. In other words, if the higher-side adjacent address is selected as the priority adjacent RHA, it is switched to the lower-side adjacent address. Conversely, if the lower-side adjacent address is selected as the priority adjacent RHA, it is switched to the higher-side adjacent address.

[0195] Furthermore, during a period when the logical level of the distance switching signal PM2 is HIGH and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, even if the B-type seed address S2 is updated by the second sampling signal Sample2, the seed address Seed supplied to the calculation unit 249 is held by the latch 241 controlled by the priority / non-priority switching signal RHR2nd, so that it is possible to avoid updating the RHA during this period. In other words, during a period when the logical level of the distance switching signal PM2 is HIGH and the logical level of the priority / non-priority switching signal RHR2nd is HIGH, it is possible to avoid updating the RHA by processing including the carry processing based on the new seed address.

[0196] [Second embodiment] The basic configuration of the second embodiment is similar to that of the first embodiment, so duplicated description will be omitted. The second embodiment differs from the first embodiment in the configuration of the modified 4-bit adder 401 included in the calculation unit 249. In the second embodiment, the modified 4-bit adder 401 performs calculations based on the truth table shown in FIG.

[0197] Although the notation overlaps with that in the truth table shown in FIG. 11, if the lowest four bits of the seed address (logical seed address) are represented by A<3:0>, the lowest four bits of the RHA (logical RHA) are represented by B<3:0>, and the carry-out from the third least significant bit inside calculation unit 249 is represented by C3, then each of the bits B3 to B0 included in the lowest four bits B<3:0> of the RHA and the carry-out C3 can be calculated based on each of the bits A3 to A0 included in the lowest four bits A<3:0> of the seed address by operations 1 to 4 having the following logical formulas.

[0198] (Calculation 1) Adjacent priority RHA (PM2=LOW, RHR2nd=LOW) B0 = !A0 B1 = A1 B2 = A2 B3 = A3 C3 = 0 (Operation 2) Adjacent non-priority RHA (PM2=LOW, RHR2nd=HIGH) B0 = !A0 B1 = A1^ {(A0^A1^A3)| (A1^A2)} B2 = A2^!{(A0^A1^A3)|!(A1^A2)} B3 = A3^!{(A0^A1^A3)| (A1^A2)} C3 = (!A0^A3)&(A1|A2) (Calculation 3) Adjacent priority RHA (PM2=HIGH, RHR2nd=LOW) B0 = A0 B1 = !A1 B2 = A2 B3 = A3 C3 = 0 (Operation 4) Adjacent non-priority RHA (PM2=HIGH, RHR2nd=HIGH) B0 = A0 B1 = A2 B2 = A1 B3 = A3^!(A1^A2) C3 = !(A1|A2) Where: !:NOT |:OR &:AND ^:OR It is.

[0199] Here, by replacing A0 included in the calculation formula corresponding to the adjacent non-prioritized RHA with A1^A3, except for the calculation formula for bit B0, it is possible to obtain a calculation formula corresponding to the second adjacent non-prioritized RHA.

[0200] To perform the above calculations, for example, modified 4-bit adding unit 401 may have a configuration as shown in Fig. 12. Modified 4-bit adding unit 401 shown in Fig. 12 includes a calculation unit 501 corresponding to the above calculation (1), a calculation unit 502 corresponding to the above calculation (2), a calculation unit 503 corresponding to the above calculation (3), a calculation unit 504 corresponding to the above calculation (4), and a selection circuit 505 that switches and selects one of the outputs from calculation units 501, 502, 503, and 504 in response to distance switching signals PM2 and RHR2nd.

[0201] According to the second embodiment, unlike the first embodiment, conversion from a seed address to a physical seed address and conversion from a physical RHA to an RHA are not necessary.

[0202] [Third embodiment] The basic configuration of the third embodiment is similar to that of the first embodiment, and therefore a duplicated description will be omitted. The third embodiment differs from the first embodiment in the configuration of a modified 4-bit addition unit 401 included in a calculation unit 249.

[0203] Like the second embodiment, the third embodiment differs from the first embodiment in that it has a configuration that eliminates the need for conversion from a seed address to a physical seed address and conversion from a physical RHA to an RHA.

[0204] In the second embodiment, the selection circuit 505 is treated as a functional block. In contrast, in the third embodiment, the internal logic circuit of the selection circuit 505 is specified, and the logic circuits for each bit B0 to B3 of the RHA and the carry C0 are integrated into one. That is, in the third embodiment, the logic circuits included in the arithmetic units 501 to 504 and the selection circuit 505 are integrated into one logic circuit.

[0205] The circuit shown in FIG. 13 also calculates and outputs the priority adjacent RHA, non-priority adjacent RHA, priority next-neighbor RHA or non-priority next-neighbor RHA corresponding to the seed address for the lower 4 bits according to the combination of the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd.

[0206] Note that an operation including an operation corresponding to the above operation i (i=1 to 4) and an operation corresponding to the selection may be regarded as operation i.

[0207] [Fourth embodiment] The basic configuration of the fourth embodiment is similar to that of the first embodiment, and therefore a duplicated description will be omitted. The fourth embodiment differs from the first embodiment in the configuration of a modified 4-bit addition unit 401 included in a calculation unit 249.

[0208] Like the second and third embodiments, the fourth embodiment differs from the first embodiment in that it has a configuration that eliminates the need for conversion from a seed address to a physical seed address and conversion from a physical RHA to an RHA.

[0209] In the second embodiment, the selection circuit 505 is treated as a functional block. In contrast, in the fourth embodiment, the internal logic circuit of the selection circuit 505 is specified, and the logic circuits for each bit B0 to B3 of the RHA and the carry C0 are integrated into one. That is, in the fourth embodiment, as shown in FIG. 14, the logic circuits included in the arithmetic units 501 to 504 and the selection circuit 505 are integrated into one logic circuit. In this respect, the modified 4-bit addition unit 401 according to the fourth embodiment is common to the modified 4-bit addition unit 401 according to the third embodiment.

[0210] Unlike the modified 4-bit adding unit 401 according to the third embodiment, the modified 4-bit adding unit 401 according to the fourth embodiment has compatibility as will be described below.

[0211] As shown in Fig. 14, the logic circuit according to the fourth embodiment has a form in which a first portion 511 is coupled to a second portion 513. Here, as shown in Fig. 15, it is possible to replace the first portion 511 in Fig. 14 with a third portion 515 and couple the third portion 515 to the second portion 513. Note that while the first portion 511 and the second portion 513 include combinational circuits, the third portion 515 does not include a combinational circuit and is composed of only wiring.

[0212] When the modified 4-bit adder 401 is configured by combining the first part 511 and the second part 513 as shown in Fig. 14, the modified 4-bit adder 401 outputs adjacent RHA and adjacent RHA. On the other hand, when the modified 4-bit adder 401 is configured by combining the third part 515 and the second part 513 as shown in Fig. 15, the modified 4-bit adder 401 outputs adjacent RHA but does not output adjacent RHA.

[0213] More specifically, the first portion 511 is the least significant bit Ain of the seed address. <0> , second least significant bit Ain <1> and the fourth least significant bit Ain <3> Also, when the distance switching signal PM2 indicates that the current unit period is an A-type period, the first portion 511 inputs the least significant bit Ain of the seed address. <0> and the second least significant bit Ain <1> Furthermore, when the distance switching signal PM2 indicates that the current unit time is a type B period, the first portion 511 outputs a signal that maintains the logic level of the least significant bit Ain <0> , second least significant bit Ain <1> and the fourth least significant bit Ain <3> In addition, the first portion 511 outputs a signal obtained by passing the distance switching signal PM2 and the priority / non-priority switching signal RHR2nd through a first combination circuit included in the first portion 511.

[0214] In other words, when the distance switching signal PM2 indicates that the current unit period is an A-type period, the signals A0p and A0d output from the first portion 511 are the least significant bit Ain of the seed address. <0> The signal A1p output by the first portion 511 has the same logic level as the second least significant bit Ain <1> It has the same logic level as

[0215] When the distance switching signal PM2 indicates that the current unit period is a type B period, the logic level of the signal A0p output by the first portion 511 is the least significant bit Ain of the seed address. <0> The logic level of the signal A0d is the inverted level of the least significant bit Ain of the seed address. <0> and the fourth least significant bit Ain <3> It has a logic level of the exclusive OR of the above.

[0216] When the distance switching signal PM2 indicates that the current unit period is a type B period and the priority / non-priority switching signal RHR2nd indicates that the current unit period is a priority period, the signal A1p is set to the second least significant bit Ain <1> On the other hand, when the distance switching signal PM2 indicates that the current unit period is a type B period and the priority / non-priority switching signal RHR2nd indicates that the current unit period is a non-priority period, the signal A1p has a logic level that is the inverted logic level of the second least significant bit Ain <1> It has the same logic level as

[0217] In the second portion 513, the signal A0p is <0> The signal A0d is input to an exclusive-OR gate 521 associated with the bits Aout<3:0> of the RHA and the signal SWPM, and to an inverting gate 529. The signal A1p is input to an exclusive-OR gate 527 associated with the second least significant bit Aout<3:0> of the RHA and the signal SWPM. <1> is input to an exclusive OR gate 523 corresponding to

[0218] Referring to FIG. 15, in the third portion 515, the seed address bits Ain <0> becomes the signals A0p and A0d as is, and the seed address bit Ain <1> This becomes signal A1p as is.

[0219] This configuration can ensure compatibility. That is, when it is required to calculate only the adjacent RHA, the third part 515 and the second part 513 are combined to form the modified 4-bit addition unit 401. When it is required to calculate the adjacent RHA and the adjacent adjacent RHA, the first part 511 and the second part 513 are combined to form the modified 4-bit addition unit 401.

[0220] If there is no need to exchange the first portion 511 and the third portion 515 for compatibility, the first portion 511 may always be coupled to the second portion 513 in the circuit of Figure 14. Similarly, the third portion 515 may always be coupled to the second portion 513 in the circuit of Figure 15.

[0221] As described above, according to the RHA calculation circuit of this embodiment, the row hammer refresh address can be calculated with a small circuit scale.

[0222] The above-described embodiments are described for the purpose of facilitating understanding of the present invention, and are not described for the purpose of limiting the present invention. Therefore, the elements disclosed in the above embodiments are intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0223] For example, in each of the above-mentioned embodiments, the correspondence between the logical address and the physical address according to the arrangement of the wiring and the sub-word driver shown in FIG. 5 is assumed, but other arrangements and correspondences may be assumed. For example, if at least one of the two adjacent RHAs corresponding to each seed address can be calculated by a simplified circuit, that one RHA can be set as the priority RHA. Similarly, if at least one of the two adjacent RHAs corresponding to each seed address can be calculated by a simplified circuit, that one RHA can be set as the priority RHA.

[0224] In particular, in each of the above-described embodiments, 16 word lines are arranged in a repeating pattern, but this may be modified to have another number of word lines arranged in a repeating pattern. [Explanation of symbols]

[0225] 100...Semiconductor memory device 101-1 to 101-N: 1st memory block to Nth memory block 201…Refresh control section 203... Row hammer refresh address calculation unit 205...Row address multiplexer 221…Random number generator 225…Memory array 247…Control unit 249...Calculation section

Claims

1. A row hammer refresh address calculation circuit for calculating a row hammer refresh address, a calculation unit that, in a memory array including a plurality of memory cells arranged in a matrix, calculates, in a complementary manner, an upper adjacent row hammer refresh address corresponding to a word line adjacent on an upper side to a word line to which a seed address is assigned and a lower adjacent row hammer refresh address corresponding to a word line adjacent on a lower side to the word line to which the seed address is assigned, by a first calculation or a second calculation having a larger amount of calculation than the first calculation, and calculates, in a complementary manner, an upper adjacent row hammer refresh address corresponding to a word line adjacent on the upper side to the word line to which the seed address is assigned and a lower adjacent adjacent row hammer refresh address corresponding to a word line adjacent on the lower side to the word line to which the seed address is assigned, by a third calculation or a fourth calculation having a larger amount of calculation than the third calculation; a control unit that controls an operation of the calculation unit so that, when the seed address is updated, an address obtained by the first calculation among the upper adjacent row hammer refresh address and the lower adjacent row hammer refresh address corresponding to the updated seed address is calculated as a priority adjacent row hammer refresh address by the first calculation, and when the seed address is updated, an address obtained by the third calculation among the upper adjacent row hammer refresh address and the lower adjacent row hammer refresh address corresponding to the updated seed address is calculated as a priority adjacent row hammer refresh address by the third calculation. Rowhammer refresh address calculation circuit.

2. The control unit supplies to the calculation unit a first identification signal for identifying whether the current unit period is an A type period in which the upper adjacent row hammer refresh address or the lower adjacent row hammer refresh address is calculated based on an A type seed address, or a B type period in which the upper adjacent row hammer refresh address or the lower adjacent row hammer refresh address is calculated based on a B type seed address, and a second identification signal for identifying whether the current period in each unit period belongs to a priority period in which a priority row hammer refresh address is generated starting from the start of the unit period, or a non-priority period in which a non-priority row hammer refresh address is generated starting from the middle of the unit period; the calculation unit calculates the prioritized adjacent row hammer refresh address by the first calculation based on the A type seed address during a period that is the A type period and the priority period, based on the first identification signal and the second identification signal, and calculates the prioritized adjacent row hammer refresh address by the third calculation based on the B type seed address during a period that is the B type period and the priority period.

2. The row hammer refresh address calculation circuit of claim 1.

3. the calculation unit calculates a non-priority adjacent row hammer refresh address by the second calculation based on the A-type seed address during a period that is the A-type period and the non-priority period; 3. The row hammer refresh address calculation circuit of claim 2.

4. the calculation unit calculates a non-priority adjacent row hammer refresh address by the fourth calculation based on the B-type seed address during a period that is the B-type period and the non-priority period; 4. The row hammer refresh address calculation circuit of claim 3.

5. The control unit is If the seed address of the type A is updated during a period that is the type A period and the non-preferential period, an additional type A period is continued after the current type A period ends; The calculation unit is In a period that is the A-type period and the priority period after the continuation, the first calculation is performed based on the A-type seed address updated in the A-type period and the non-priority period.

3. The row hammer refresh address calculation circuit of claim 2.

6. The control unit is If the type A seed address is not updated during a period that is the type A period and the non-priority period, the type B period is continued after the current type A period ends; The calculation unit is calculating the priority adjacent row hammer refresh address by the third calculation based on the B type seed address during a period that is the B type period and the priority period after updating; 3. The row hammer refresh address calculation circuit of claim 2.

7. if the priority period is changed to the non-priority period during the B type period, the calculation unit calculates a non-priority adjacent row hammer refresh address by the fourth calculation based on the B type seed address used when calculating the priority adjacent row hammer refresh address output before the change; 3. The row hammer refresh address calculation circuit of claim 2.

8. The control unit is If the seed address of the type B is updated during a period that is the type B period and the non-priority period, an additional type B period is continued after the current type B period ends; The calculation unit is in a period that is the B type period and the priority period after the continuation, calculating the priority adjacent row hammer refresh address by the third calculation based on the B type seed address updated in the period that is the B type period and the non-priority period; 3. The row hammer refresh address calculation circuit of claim 2.

9. The control unit is If the type B seed address is not updated during a period that is the type B period and the non-priority period, the type A period is continued after the current type B period ends; The calculation unit is calculating the prioritized adjacent row hammer refresh address by the first calculation based on the type A seed address during a period that is the type A period and the priority period after updating; 3. The row hammer refresh address calculation circuit of claim 2.

10. the type A seed address is obtained by sampling a row address used in accessing the memory array with a first sampling signal generated at random timing, the type B seed address is obtained by sampling the row address used in accessing the memory array with a second sampling signal which is generated at random timing and is independent of the first sampling signal; 3. The row hammer refresh address calculation circuit of claim 2.

11. The calculation unit is a forward address conversion unit that converts the seed address in a logical address space into a physical address in accordance with information on a physical layout of a predetermined memory cell or a physical layout of a word line; a physical address shift unit that calculates one of first to fourth physical row hammer refresh addresses by addition or subtraction of ±1 or ±2 based on the seed address converted into a physical address; a reverse address conversion unit that converts the first to fourth physical row hammer refresh addresses into logical addresses in accordance with information on the physical arrangement of the predetermined memory cells or physical arrangement of word lines, and obtains the addresses as any one of the upper adjacent row hammer refresh address, the lower adjacent row hammer refresh address, the second adjacent upper row hammer refresh address, and the second adjacent lower row hammer refresh address in a logical address space; 2. The row hammer refresh address calculation circuit of claim 1.

12. The calculation unit is a first portion which receives the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address, as well as the first identification signal and the second identification signal, and outputs a signal which maintains the logic levels of the least significant bit and the second least significant bit of the seed address when the first identification signal indicates that the current unit time is the type A period, and outputs a signal obtained by passing the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address, as well as the first identification signal and the second identification signal through a first combinational circuit included in the first portion, when the first identification signal indicates that the current unit time is the type B period; a second part that outputs the lower four bits of the row hammer refresh address obtained by passing the signal input from the first part, the third least significant bit and the fourth least significant bit of the seed address, and the second identification signal through a second combinational circuit included in the second part; Equipped with When the first portion is connected to the second portion, in the row hammer refresh address calculation circuit, both the portion relating to the adjacent row hammer refresh address and the portion relating to the adjacent row hammer refresh address of the calculation unit and the control unit are configured, When a third section is connected to the second section, the third section receives the least significant bit and the second least significant bit of the seed address and outputs a signal that maintains the logic levels of the least significant bit and the second least significant bit of the seed address, the second section outputs the lower four bits of the row hammer refresh address obtained by passing the signal received from the third section, the third least significant bit and the fourth least significant bit of the seed address, and the second identification signal through the second combination circuit included in the second section itself, and in a calculation circuit corresponding to the row hammer refresh address calculation circuit itself, the calculation section and a section of the control section related to the adjacent row hammer refresh address are configured.

3. The row hammer refresh address calculation circuit of claim 2.

13. the memory array including a plurality of memory cells arranged in rows and columns; A row hammer refresh address calculation circuit according to any one of claims 1 to 12; Equipped with A plurality of memory cells corresponding to a word line having the row hammer refresh address calculated by the row hammer refresh address calculation circuit as a row address are refreshed. Semiconductor memory device.

14. A row hammer refresh address calculation method for calculating a row hammer refresh address, comprising: a calculation step of calculating an upper adjacent row hammer refresh address corresponding to a word line adjacent on an upper side to a word line to which a seed address is assigned and a lower adjacent row hammer refresh address corresponding to a word line adjacent on a lower side to the word line to which the seed address is assigned, in a memory array including a plurality of memory cells arranged in a matrix, by a first calculation or a second calculation having a larger amount of calculation than the first calculation, and calculating an upper adjacent row hammer refresh address corresponding to a word line adjacent on the upper side to the word line to which the seed address is assigned and a lower adjacent row hammer refresh address corresponding to a word line adjacent on the lower side to the word line to which the seed address is assigned, by a third calculation or a fourth calculation having a larger amount of calculation than the third calculation; a control step of controlling the calculation step such that, when the seed address is updated, an address obtained by the first calculation among the upper adjacent row hammer refresh address and the lower adjacent row hammer refresh address corresponding to the updated seed address is calculated as a priority adjacent row hammer refresh address by the first calculation, and when the seed address is updated, an address obtained by a third calculation among the upper adjacent row hammer refresh address and the lower adjacent row hammer refresh address corresponding to the updated seed address is calculated as a priority adjacent row hammer refresh address by the third calculation. Rowhammer refresh address calculation method.

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