Ceramic electronic components and their manufacturing method

Abstract

To provide a ceramic electronic component that can achieve a high continuing rate of an internal electrode layer, and a manufacturing method for the same.SOLUTION: In a ceramic electronic component, a plurality of dielectric layers mainly containing ceramic and a plurality of internal electrode layers are stacked. The internal electrode layers include a multilayer chip formed so as to expose to at least one of opposite two end surfaces. In the internal electrode layer, along a cross section formed in the direction where the two end surfaces face each other and in the direction where the internal electrode layers are stacked, a plurality of spaces that are closed in the internal electrode layer are provided so as to be arranged at intervals along the direction where the two end surfaces face each other.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Ceramic electronic components such as multilayer ceramic capacitors have been developed (see, for example, Patent Documents 1 and 2). As electronic devices become smaller, ceramic electronic components mounted in electronic devices are also required to be further smaller. The capacitance value, which is a basic characteristic of ceramic electronic components, is determined by the thickness, area, and number of laminated dielectric layers when a dielectric material with the same dielectric constant is used. Ceramic electronic components are provided with approximately the same number of internal electrode layers as the dielectric layers, and the proportion of the internal electrode layers in the volume is large. In order to obtain a larger capacitance from a limited volume, it is desired to make the internal electrode layers thinner and increase the number of laminated internal electrode layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-078267 [Patent Document 2] JP 2001-122660 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the internal electrode layers are made thin, there is a risk that the continuity ratio of the internal electrode layers will decrease.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a ceramic electronic component capable of achieving a high continuity rate of internal electrode layers, and a manufacturing method thereof. [Means for solving the problem]

[0006] The ceramic electronic component of the present invention comprises a laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are laminated, and the plurality of internal electrode layers are formed so as to be exposed on at least one of two opposing end faces, and the internal electrode layers are characterized in that in a cross section formed in the direction in which the two end faces oppose each other and in the direction in which the plurality of internal electrode layers are stacked, a plurality of voids are provided in the internal electrode layers so as to be closed within the internal electrode layers and to be arranged at intervals along the direction in which the two end faces oppose each other.

[0007] In the ceramic electronic component, a total length of the gaps in the direction in which the two end faces face each other may be 3% or more and 90% or less of a length of the internal electrode layers in the direction in which the two end faces face each other.

[0008] In the ceramic electronic component, the sum of the length of the gaps in the direction in which the two end faces face each other may be 15% or more and 80% or less of the length of the internal electrode layers in the direction in which the two end faces face each other.

[0009] In the ceramic electronic component, a total length of the gaps in the direction in which the two end faces face each other may be 30% or more and 65% or less of a length of the internal electrode layers in the direction in which the two end faces face each other.

[0010] In the ceramic electronic component, the shortest distance between the gap and the dielectric layer may be greater than the length of the gap in the stacking direction.

[0011] In the ceramic electronic component, the length of the void in the stacking direction may be not less than 0.03 μm and not more than 0.8 μm.

[0012] In the ceramic electronic component, the length of the gap in the direction in which the two end faces face each other may be 0.03 μm or more and 5.0 μm or less.

[0013] The method for manufacturing a ceramic electronic component according to the present invention includes the steps of forming a laminate unit by forming an internal electrode pattern on a dielectric green sheet by a vacuum film formation process, forming a laminate by stacking the laminate units so that the dielectric green sheets are bonded opposite to each other and the internal electrode patterns are bonded opposite to each other, cutting the laminate into a substantially rectangular parallelepiped shape and exposing the internal electrode pattern on at least one of two opposing end faces, and firing the laminate, and is characterized in that the conditions of the firing step are adjusted so that in an internal electrode layer obtained from the internal electrode pattern, a plurality of voids closed in the internal electrode layer are arranged at intervals along the direction in which the two end faces face each other. Effect of the Invention

[0014] According to the present invention, it is possible to provide a ceramic electronic component capable of realizing a high continuity rate of internal electrode layers, and a manufacturing method thereof. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 2 is a cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a diagram showing the continuity rate of internal electrode layers. [Diagram 5] 1A is an enlarged view of an internal electrode layer 12 in a cross section of the XZ plane defined by the X-axis and Z-axis, and FIG. 1B is a diagram for explaining the sizes related to the gap. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and (b) are diagrams illustrating the lamination process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment will be described with reference to the drawings.

[0017] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the lamination direction are referred to as side faces. The external electrodes 20a, 20b extend on the upper, lower and two side faces in the lamination direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other. In FIG. 1, the X-axis direction (first direction) is the length direction of the laminated chip 10, the direction in which the two end faces of the laminated chip 10 face each other, and the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction (second direction) is the width direction of the internal electrode layers. The Z-axis direction is the stacking direction, and the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0018] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edges of the internal electrode layers 12 are alternately exposed to the end face on which the external electrode 20a of the laminated chip 10 is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layers 11 and the ceramic material.

[0019] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0020] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12. The average thickness of the internal electrode layers 12 is, for example, 1 μm or less. The dielectric layers 11 are mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. The perovskite structure is an ABO that deviates from the stoichiometric composition. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (strontium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used. The thickness of each dielectric layer 11 is, for example, 0.01 μm or more and 5.0 μm or less, or 0.1 μm or more and 3.0 μm or less, or 0.2 μm or more and 1.0 μm or less.

[0021] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3 as a main phase. 3-αIn this embodiment, BaTiO3 (barium titanate) is used as the ceramic material. The dielectric layer 11 is obtained by firing a dielectric material including a ceramic raw material powder mainly composed of a ceramic material having a perovskite structure, for example.

[0022] 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, the region that generates capacitance is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0023] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is referred to as the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin 15. In other words, the end margin 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin 15 is a region that does not generate capacitance.

[0024] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. That is, the side margins 16 are regions provided to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure that extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0025] As electronic devices become smaller, further miniaturization is also required for the multilayer ceramic capacitors 100 mounted on the electronic devices. The capacitance value, which is a basic characteristic of the multilayer ceramic capacitor 100, is determined by the thickness, area, and number of laminations of the dielectric layers 11 when a dielectric material with the same dielectric constant is used. In the multilayer ceramic capacitor 100, the number of internal electrode layers 12 is approximately the same as the number of dielectric layers 11, and the proportion of the internal electrode layers 12 in the volume is large. In order to obtain a larger capacity from a limited volume, it is desired to make the internal electrode layers 12 thinner and increase the number of laminations of the internal electrode layers 12.

[0026] However, when the internal electrode layer 12 is thinned, the continuity rate of the internal electrode layer 12 may decrease. Fig. 4 is a diagram showing the continuity rate. As illustrated in Fig. 4, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2,...,Ln of the metal parts are measured and summed up, and the ratio of the metal parts, ΣLn / L0, can be defined as the continuity rate of the layer.

[0027] The multilayer ceramic capacitor 100 according to this embodiment has a configuration that can achieve a high continuity rate of the internal electrode layers 12. The details will be described below.

[0028] FIG. 5(a) is an enlarged view of the internal electrode layer 12 in the cross section of the XZ plane formed by the X-axis and the Z-axis. As illustrated in FIG. 5(a), the internal electrode layer 12 is provided with a plurality of voids 17 that are closed within the internal electrode layer 12 so as to be spaced apart along the X-axis direction. For example, the center positions of the voids 17 in the Z-axis direction are aligned along the X-axis direction. For example, the center positions of the voids 17 may be within the central 1 / 5 region when the internal electrode layer 12 is divided into 5 equal parts in the Z-axis direction. The voids 17 have the effect of relieving stress by plastic deformation of the free surface. In particular, the stress caused by the difference in thermal contraction between the dielectric layer 11 and the internal electrode layer 12 when the laminated chip 10 is fired can be relieved. By providing a plurality of voids 17 along the X-axis direction, the stress can be relieved over a wide range in the X-axis direction. As a result, the discontinuity of the internal electrode layer 12 is suppressed, and a high continuity rate of the internal electrode layer 12 can be achieved.

[0029] Since the voids 17 are closed within the internal electrode layers 12, the voids 17 are not exposed to the dielectric layers 11. Since the voids 17 are not exposed to the dielectric layers 11, a decrease in capacitance value can be suppressed. Furthermore, since the voids 17 and the ceramic of the dielectric layers 11 are not in contact with each other, stress is not concentrated in the ceramic, and delamination, cracks, and the like are suppressed, improving the reliability of the dielectric layers 11.

[0030] For example, the multiple voids 17 are aligned along the X-axis direction in a range of 20% to 80% of the center in the thickness direction of the internal electrode layer 12. Alternatively, the multiple voids 17 are aligned along the X-axis direction in a range of 30% to 70% of the center in the thickness direction of the internal electrode layer 12. Alternatively, the multiple voids 17 are aligned along the X-axis direction in a range of 40% to 60% of the center in the thickness direction of the internal electrode layer 12.

[0031] Fig. 5(b) is a diagram for explaining each size related to the void 17. As illustrated in Fig. 5(b), the thickness of the internal electrode layer 12 is dimension 1. The shortest distance between the void 17 and the dielectric layer 11 is dimension 2. The length of the void 17 in the X-axis direction is dimension 3. The length of the void 17 in the Z-axis direction is dimension 4. The distance between adjacent voids 17 in the X-axis direction is dimension 5.

[0032] Dimensions 1 to 5 can be measured using SEM photographs of the cross section of the internal electrode layer 12. As dimensions 1 to 5, the maximum lengths along the X-axis direction, Y-axis direction, and Z-axis direction according to the respective defined directions are adopted. Image analysis software such as ImageJ may be used as necessary.

[0033] In the internal electrode layer 12, if the total length of each void 17 in the X-axis direction (the sum of the dimensions 3 of each void 17) is too small, there is a risk that stress will not be sufficiently alleviated. Therefore, in this embodiment, it is preferable to set a lower limit on the ratio (abundance rate) of the total length of each void 17 in the X-axis direction to the length of the internal electrode layer 12 in the X-axis direction. For example, the abundance rate is preferably 3% or more, more preferably 15% or more, and even more preferably 30% or more. On the other hand, if the abundance rate is too large, there is a risk of problems such as the internal electrode layer 12 peeling off within the layer. Therefore, it is preferable to set an upper limit on the abundance rate. For example, the abundance rate is preferably 90% or less, more preferably 80% or less, and even more preferably 65% ​​or less.

[0034] It is preferable that the gap 17 is located approximately at the center in the Z-axis direction in the internal electrode layer 12. In this case, the relationship of dimension 2>dimension 4 can be realized. By realizing this relationship, a gap for stress relaxation can be formed with a minimum electrode thickness while maintaining the electrode thickness for contact with the dielectric layer 11, so that the number of layers can be increased to increase the capacitance value.

[0035] The dimension 1 is, for example, 0.01 μm or more and 5.0 μm or less, 0.05 μm or more and 3.0 μm or less, or 0.1 μm or more and 1.0 μm or less. Even if the internal electrode layer 12 is thinned in this manner, a high continuity ratio can be achieved by providing the gap 17.

[0036] If dimension 4 is too small, the dimension in the Z-axis direction of the voids that contribute to stress relaxation becomes short, which may cause problems such as cracks occurring due to internal stress. Therefore, it is preferable to set a lower limit for dimension 4. For example, dimension 4 is preferably 0.03 μm or more, more preferably 0.05 μm or more, and even more preferably 0.06 μm or more. On the other hand, if dimension 4 is too large, the number of internal electrode layers and the number of dielectric layers in the laminate are reduced, which may make it difficult to ensure the capacitance value. Therefore, it is preferable to set an upper limit for dimension 4. For example, dimension 4 is preferably 0.8 μm or less, more preferably 0.5 μm or less, and even more preferably 0.4 μm or less.

[0037] If dimension 3 is too small, the dimension in the X-axis direction of the gap that contributes to stress relaxation becomes short, and there is a risk of problems such as cracks occurring due to internal stress. Therefore, it is preferable to set a lower limit for dimension 3. For example, dimension 4 is preferably 0.03 μm or more, more preferably 0.05 μm or more, and even more preferably 0.08 μm or more. On the other hand, if dimension 3 is too large, there is a risk of problems such as peeling off of the internal electrode layer within the layer. Therefore, it is preferable to set an upper limit for dimension 3. For example, dimension 3 is preferably 5.0 μm or less, more preferably 3.0 μm or less, and even more preferably 2.0 μm or less.

[0038] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG 6 is a diagram illustrating a flow of the method for manufacturing the multilayer ceramic capacitor 100.

[0039] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0040] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. The additive compound may be an oxide of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or an oxide containing cobalt (Co), nickel, lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or a glass containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0041] For example, a compound containing an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

[0042] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 having a thickness of, for example, 0.5 μm to 1.0 μm on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0043] Next, as illustrated in Fig. 7(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52 by a vacuum film formation process. In Fig. 7(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The vacuum film formation method is not particularly limited, but for example, sputtering, vapor deposition, etc. can be used. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is regarded as a lamination unit.

[0044] Next, the laminate units are laminated while peeling off the dielectric green sheet 52 from the base material 51. As illustrated in Fig. 7(b), the laminate units are laminated so that the dielectric green sheets 52 are bonded to each other so as to face each other and so that the internal electrode patterns 53 are bonded to each other so as to face each other.

[0045] Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are laminated on the top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut into a predetermined chip size (e.g., 1.0 mm x 0.5 mm). In the example of Fig. 7(b), cutting is performed along the dotted lines. The cover sheet may have the same components as the dielectric green sheet 52, or may have a different additive compound.

[0046] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in a N2 atmosphere, after which a metal paste that would become the undercoat layers of the external electrodes 20a and 20b was applied thereto by a dipping method, and the ceramic laminate was then subjected to a dipping treatment in a nitrogen atmosphere under an oxygen partial pressure of 10 -5 ~10 -8The laminate is fired in a reducing atmosphere of 1 atm at 1100 to 1300°C for 10 minutes to 2 hours. In this manner, a multilayer ceramic capacitor 100 is obtained. One dielectric layer 11 is obtained from two dielectric green sheets 52. One internal electrode layer 12 is obtained from two internal electrode patterns 53.

[0047] (Reoxidation treatment process) After that, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0048] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating.

[0049] According to the manufacturing method of this embodiment, the internal electrode pattern 53 is formed on the dielectric green sheet 52 by a vacuum film formation process, so that the adhesion between the dielectric green sheet 52 and the internal electrode pattern 53 can be improved. For example, the adhesion can be improved compared to the case where metal powder is printed on the dielectric green sheet 52. As a result, delamination is suppressed, the spheroidization of the internal electrode layer 12 is suppressed, and a high continuity rate of the internal electrode layer 12 can be realized. The delamination here means that peeling occurs along the interface between the dielectric green sheet 52 and the internal electrode pattern 53 when the two layers are simultaneously fired. In addition, since the two layers of the internal electrode pattern 53 are bonded together, a plurality of voids 17 are arranged at intervals along the X-axis direction at approximately the center in the Z-axis direction of the internal electrode layer 12, as illustrated in FIG. 5(a). This makes it possible to alleviate the stress caused by the difference in thermal contraction between the dielectric layer 11 and the internal electrode layer 12 when firing the laminated chip 10. As a result, discontinuity of the internal electrode layer 12 is suppressed, and a high continuity rate of the internal electrode layer 12 can be realized.

[0050] In addition, since one internal electrode layer 12 is formed from two internal electrode patterns 53, the thickness of the internal electrode pattern 53 can be approximately half the thickness of the internal electrode layer 12. In this case, the time required to form one internal electrode pattern 53 is shortened, and the time during which the dielectric green sheet 52 is exposed to a low-pressure, high-temperature atmosphere in a vacuum process is shortened. This makes it possible to suppress the amount of evaporation of organic solvents such as binders from the dielectric green sheet 52.

[0051] In addition, since one side of the dielectric green sheet 52 is covered with a PET film and the other side is not covered with a PET film, differences occur in the amount of solvent volatilized between the two sides, density, etc., resulting in different surface conditions. According to the manufacturing method of this embodiment, the internal electrode pattern 53 is not formed on both sides of the dielectric green sheet 52 after lamination, but is formed only on the top surface, so that the firing temperature profile can be adjusted to match this adhesion condition so that delamination does not occur, and the temperature condition range is wide. Furthermore, the multilayer ceramic capacitor manufactured in this manner can be a highly reliable product that is less likely to delaminate.

[0052] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0053] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0054] Example 1 Additives were added to the barium titanate powder, and the mixture was thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene and ethyl alcohol were added to the dielectric material as a solvent, and a dielectric green sheet was applied onto a PET substrate by the doctor blade method. The thickness of the dielectric green sheet was 0.6 μm.

[0055] Next, an internal electrode pattern was formed on the dielectric green sheet by sputtering. A Ni target was used as the cathode.

[0056] Next, the laminated units were laminated while peeling off the dielectric green sheet from the substrate. The laminated units were laminated so that the dielectric green sheets faced each other and the internal electrode patterns faced each other. After the laminated units were laminated, they were pressed under atmospheric pressure. Then, they were cut to the specified chip dimensions (1.5 mm x 0.75 mm x 0.3 mm).

[0057] The ceramic laminate thus obtained was subjected to a binder removal treatment in an N2 atmosphere, after which a metal paste that would become the underlayer of the external electrodes was applied thereto, and sintered in a reducing atmosphere.

[0058] An SEM photograph of the cross section of the obtained multilayer ceramic capacitor was taken. In the embodiment, a plurality of voids were confirmed in the direction in which the external electrodes faced each other, approximately at the center of the lamination direction of the internal electrode layers. In the SEM photograph, dimensions 1 to 5 of the voids were measured. Dimensions 1 to 5 were measured for 20 pieces selected at random. In addition, the presence rate (the ratio of the total length of each void in the X-axis direction to the length of the internal electrode layers in the X-axis direction) was measured. Furthermore, the continuity rate of the internal electrode layers was measured. The results are shown in Table 1.

[0059] Example 2 After lamination of the laminate units in Example 1, the laminate was pressed under reduced pressure of 700 hPa instead of atmospheric pressure, and the other conditions were the same as those in Example 1. The results are shown in Table 1.

[0060] (Comparative Example) In the comparative example, after forming the internal electrode layers, lamination was performed in the same direction as in the conventional manufacturing method. The internal electrode layers were not bonded to face each other as in the example. The other conditions were the same as in the example. An SEM photograph of the cross section of the obtained multilayer ceramic capacitor was taken. In the comparative example, no voids were confirmed in the approximate center of the lamination direction of the internal electrode layers, aligned along the direction in which the external electrodes face each other. [Table 1]

[0061] As shown in Table 1, in the comparative example, the continuity rate of the internal electrode layer was low. In contrast, in Examples 1 and 2, the continuity rate of the internal electrode layer was high. This is thought to be because stress was alleviated by forming a plurality of voids in the approximately central portion of the lamination direction of the internal electrode layer so as to be aligned in the direction in which the external electrodes face each other. Comparing Example 1 and Example 2, the voids were reduced in Example 2 in which the laminate was pressed under reduced pressure. It was confirmed that the presence rate of voids can be reduced by reducing the pressure when pressing the laminate compared to pressing under atmospheric pressure.

[0062] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0063] 10 Stacked Chip 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 17 void 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. A laminated chip in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are laminated, and the plurality of internal electrode layers are formed so as to be exposed on at least one of two opposing end faces, In the internal electrode layer, in a cross section formed in a direction in which the two end faces face each other and in a direction in which the plurality of internal electrode layers are stacked, a plurality of voids, each having a size in a stacking direction that is closed within the internal electrode layer and has a lower limit of 0.03 μm or more, are arranged at intervals along the direction in which the two end faces face each other, A ceramic electronic component, characterized in that for all of the voids present in the internal electrode layers, the shortest distance between the void and the dielectric layer in the stacking direction is greater than the length of the void in the stacking direction.

2. A laminated chip comprising a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers laminated together, the plurality of internal electrode layers being formed so as to be exposed on at least one of two opposing end faces; In the internal electrode layer, in a cross section formed in a direction in which the two end faces face each other and in a direction in which the plurality of internal electrode layers are stacked, a plurality of voids, each having a size in a stacking direction that is closed within the internal electrode layer and has a lower limit of 0.03 μm or more, are arranged at intervals along the direction in which the two end faces face each other, a shortest distance between the gap and the dielectric layer in a stacking direction is greater than a length of the gap in the stacking direction; a central position of the plurality of voids is within a central ⅕ region when the internal electrode layers are divided into 5 equal parts in the lamination direction, A ceramic electronic component, characterized in that the central positions of the plurality of voids do not exist outside the 1 / 5 region.

3. 3. The ceramic electronic component according to claim 1, wherein the sum of the length of the gaps in the direction in which the two end faces face each other is 30% or more and 65% or less of the length of the internal electrode layers in the direction in which the two end faces face each other.

4. 4. The ceramic electronic component according to claim 1, wherein the thickness of the plurality of internal electrode layers is 0.05 μm or more and 3.0 μm or less.

5. 5. The ceramic electronic component according to claim 1, wherein the length of the void in the stacking direction is 0.03 μm or more and 0.8 μm or less.

6. 6. The ceramic electronic component according to claim 1, wherein a length of the gap in the direction in which the two end faces face each other is 0.03 μm or more and 5.0 μm or less.

7. 7. The ceramic electronic component according to claim 1, wherein the shortest distance between the gap and the dielectric layer in the stacking direction is 0.03 μm or more and 0.8 μm or less.

8. 8. The ceramic electronic component according to claim 1, wherein the spacing between the plurality of voids in the direction in which the two end faces face each other is not less than 0.10 μm and not more than 2.06 μm.

9. forming an internal electrode pattern on a dielectric green sheet by a vacuum deposition process to form a laminate unit; forming a laminate by laminating the lamination units so that the dielectric green sheets are bonded to each other while facing each other and the internal electrode patterns are bonded to each other while facing each other; cutting the laminate into a substantially rectangular parallelepiped shape and exposing the internal electrode pattern on at least one of two opposing end faces; and firing the laminate. a first end face that faces the first electrode and a second end face that faces the second electrode; a second end face that faces the first electrode and a third end face that faces the second electrode;

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