Nitride Semiconductor Devices

Abstract

A nitride semiconductor device (10) is provided with: a substrate (12); a drift layer (14), a high-resistance layer (16) and a first underlayer (18) disposed in that order on the substrate (12); a gate open part (22) that passes through the first underlayer (18) and the high-resistance layer (16) and reaches the drift layer (14); an electron transit layer (24) and an electron supply layer (26) disposed such as to cover the upper part of the first underlayer (18) and the gate open part (22); a gate electrode (38) disposed above the electron supply layer (26); source electrodes (32) that are in contact with the electron supply layer (26); an electrode open part (34) that passes through the electron supply layer (26) and the electron transit layer (24) and reaches the first underlayer (18); fixed potential electrodes (36) that are in contact with the first underlayer (18) at the base (34a) of the electrode open part (34); and a drain electrode (40) disposed below the substrate (12).

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductors, such as GaN (gallium nitride), are wide-gap semiconductors with a large band gap, and have the characteristics of a large dielectric breakdown field and a high electron saturation drift velocity compared to compound semiconductors such as GaAs (gallium arsenide) or Si (silicon) semiconductors. For example, the band gaps of GaN and AlN (aluminum nitride) are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development is being conducted on power transistors using nitride semiconductors, which are advantageous for achieving high output and high voltage resistance. For example, Patent Document 1 discloses a vertical FET (Field Effect Transistor) having a GaN-based semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4737471 Summary of the Invention [Problem to be solved by the invention]

[0004] When a vertical FET is used in a power conversion circuit, the drain potential may become lower than the source potential when the vertical FET is off, causing a large current to flow from the source to the drain, a phenomenon known as reverse conduction. Conventional vertical FETs have a problem in that the breakdown voltage decreases after this reverse conduction.

[0005] Therefore, the present disclosure provides a nitride semiconductor device capable of suppressing a decrease in breakdown voltage caused by reverse conduction. [Means for solving the problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first high-resistance layer provided above the first nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first p-type nitride semiconductor layer provided above the first high-resistance layer, a first opening penetrating the first p-type nitride semiconductor layer and the first high-resistance layer to reach the first nitride semiconductor layer, and an upper portion of the first p-type nitride semiconductor layer and the first opening. the first p-type nitride semiconductor layer; a gate electrode provided above the electron supply layer so as to cover the first opening; a source electrode provided away from the gate electrode and in contact with the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer and reaching the first p-type nitride semiconductor layer; a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening; and a drain electrode provided below the substrate.

[0007] a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a first opening penetrating the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from the substrate side to cover an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a source electrode provided apart from the gate electrode and in contact with the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer and reaching the first p-type nitride semiconductor layer;

[0008] A nitride semiconductor device according to another aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer, a first opening penetrating the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer, an electron transit layer and an electron supply layer provided in this order from the substrate side so as to cover an upper portion of the first p-type nitride semiconductor layer and the first opening, a gate electrode provided above the electron supply layer so as to cover the first opening, and a second gate electrode spaced from the gate electrode. a source electrode in contact with the electron supply layer, a second opening penetrating the electron supply layer and the electron transit layer and reaching the first p-type nitride semiconductor layer, a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening, and a drain electrode provided below the substrate, wherein a layer thickness of a contact portion of the first p-type nitride semiconductor layer in contact with the potential fixed electrode is 50% or more of a layer thickness of a non-contact portion of the first p-type nitride semiconductor layer not in contact with the potential fixed electrode, and the layer thickness of the non-contact portion is 400 nm or more. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a nitride semiconductor device capable of suppressing a decrease in breakdown voltage caused by reverse conduction operation. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram of a typical power conversion circuit. [Diagram 2] FIG. 2 is a circuit diagram showing an equivalent circuit of a vertical FET. [Diagram 3] FIG. 3 is a cross-sectional view of the nitride semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a partially enlarged cross-sectional view showing an enlarged vicinity of a potential fixing electrode of the nitride semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to the second modification of the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a partially enlarged cross-sectional view showing an enlarged vicinity of a potential fixing electrode of a nitride semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a nitride semiconductor device according to a modification of the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a nitride semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a partially enlarged cross-sectional view showing the vicinity of a potential fixing electrode of a nitride semiconductor device according to the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a nitride semiconductor device according to a modification of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Findings on which this disclosure is based) The present inventors have found that the conventional vertical FET described in the "Background Art" section has the following problems.

[0012] Fig. 1 is a circuit diagram of a typical power conversion circuit. The power conversion circuit 1 shown in Fig. 1 is a boost circuit. The power conversion circuit 1 boosts a power supply voltage Vin of 100V generated by a power supply 3 to generate an output voltage Vout of 400V, for example, and supplies the generated output voltage Vout to a load 2.

[0013] The power conversion circuit 1 includes a capacitor 4, an inductor 5, a gate drive circuit 6, a capacitor 7, and two FETs 8a and 8b. The source of the FET 8a and the drain of the FET 8b are connected. A power source 3 is connected to the connection point between the two FETs 8a and 8b via the inductor 5. The two FETs 8a and 8b are switched on and off exclusively by the gate drive circuit 6. For example, the gate drive circuit 6 supplies complementary PWM (Pulse Width Modulation) signals to the gates of the FETs 8a and 8b.

[0014] By turning off FET 8a and turning on FET 8b, power is stored in the inductor 5. By turning on FET 8a and turning off FET 8b, the power stored in the inductor 5 is released and an output voltage Vout higher than the power supply voltage Vin is supplied to the load 2.

[0015] When switching between on and off, the FETs 8a and 8b may momentarily be turned on or off simultaneously. In this case, reverse conduction occurs in each of the FETs 8a and 8b. In other words, the drain side potential becomes lower than the source side potential, causing a large current to flow from the source to the drain.

[0016] The inventors' research has revealed that in a vertical FET, the breakdown voltage of the vertical FET decreases after a large current flows during reverse conduction. This decrease in breakdown voltage is a problem specific to the vertical FET, but does not occur in a lateral FET, whose current path is only the surface layer of the device.

[0017] Fig. 2 is a circuit diagram showing an equivalent circuit of a vertical FET. As shown in Fig. 2, the vertical FET has a parasitic diode between the source and drain. The parasitic diode is a parasitic pn diode formed by a parasitic pn junction that the vertical FET has.

[0018] As a result of extensive investigations, the inventors of the present application have found that a decrease in breakdown voltage occurs when a large current flows through the parasitic pn diode of a vertical FET. Therefore, in order to suppress the decrease in breakdown voltage, it has become clear that suppressing current flow through the parasitic pn diode or the process technology used when contacting the source electrode with the p-type GaN layer is important.

[0019] In view of the above, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first high-resistance layer provided above the first nitride semiconductor layer and having a higher resistance than the first nitride semiconductor layer, a first p-type nitride semiconductor layer provided above the first high-resistance layer, a first opening that penetrates the first p-type nitride semiconductor layer and the first high-resistance layer and reaches the first nitride semiconductor layer, and a second opening that extends between an upper portion of the first p-type nitride semiconductor layer and the first opening. the first p-type nitride semiconductor layer; a gate electrode provided above the electron supply layer so as to cover the first opening; a source electrode provided away from the gate electrode and in contact with the electron supply layer; a second opening that penetrates the electron supply layer and the electron travel layer and reaches the first p-type nitride semiconductor layer; a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening; and a drain electrode provided below the substrate.

[0020] In this way, the first high resistance layer is provided between the first nitride semiconductor layer and the first p-type nitride semiconductor layer. The first nitride semiconductor layer is usually formed using an n-type nitride semiconductor. This allows the first high resistance layer to block the current path through the parasitic pn diode generated between the first nitride semiconductor layer and the first p-type nitride semiconductor layer. Therefore, it is possible to suppress a large current from flowing through the parasitic pn diode during reverse conduction, and therefore it is possible to suppress a decrease in breakdown voltage caused by reverse conduction.

[0021] Furthermore, for example, the first high-resistance layer may be a GaN layer containing carbon, or, for example, the first high-resistance layer may be an undoped GaN layer.

[0022] This allows the first high-resistance layer to be continuously formed by epitaxial growth, similar to the first nitride semiconductor layer and the first p-type nitride semiconductor layer. Impurities are less likely to be mixed into the interfaces between the first nitride semiconductor layer, the first high-resistance layer, and the first p-type nitride semiconductor layer, so that deterioration of the characteristics of the nitride semiconductor device can be suppressed. By including carbon in GaN, it is possible to realize a higher resistance than undoped GaN.

[0023] Furthermore, for example, the potential fixed electrode may be formed using a material that forms a Schottky contact with the first p-type nitride semiconductor layer.

[0024] This allows a Schottky barrier diode to be formed by the source electrode and the first p-type nitride semiconductor layer. The reverse characteristics of the Schottky barrier diode make the turn-on voltage of the parasitic pn diode higher than when the source electrode and the first p-type nitride semiconductor layer are in ohmic contact. The turn-on voltage of the parasitic pn diode is the voltage between the source and drain when a current starts to flow through the parasitic pn diode. This makes it possible to suppress the flow of current through the parasitic pn diode, and to suppress a decrease in the breakdown voltage.

[0025] Furthermore, for example, the layer thickness of a contact portion of the first p-type nitride semiconductor layer in contact with the potential fixed electrode may be 50% or more of the layer thickness of a non-contact portion of the first p-type nitride semiconductor layer not in contact with the potential fixed electrode, and the layer thickness of the non-contact portion may be 400 nm or more.

[0026] This makes it possible to keep the damage layer formed when forming the second opening that reaches the first p-type nitride semiconductor layer away from the parasitic pn junction, thereby suppressing a decrease in breakdown voltage caused by the damage layer.

[0027] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may further include a second p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer.

[0028] This allows the second p-type nitride semiconductor layer to reduce the carrier concentration directly below the gate electrode, shifting the threshold voltage of the FET to the positive side, and thus allowing the nitride semiconductor device to operate as a normally-off FET.

[0029] Also, for example, the nitride semiconductor device according to one embodiment of the present disclosure may further include a second high-resistance layer provided above the first p-type nitride semiconductor layer and having a higher resistance than the first p-type nitride semiconductor layer, the first opening further penetrates the second high-resistance layer, and the electron transit layer and the electron supply layer cover an upper portion of the second high-resistance layer.

[0030] This makes it possible to prevent the second high-resistance layer from forming a parasitic bipolar transistor having a parasitic npn structure by the electron transit layer, the first p-type nitride semiconductor layer, and the second nitride semiconductor layer.

[0031] Furthermore, for example, the potential fixing electrode may be electrically connected to the source electrode.

[0032] This makes it possible to stabilize the potential of the first p-type nitride semiconductor layer, thereby ensuring the breakdown voltage.

[0033] Hereinafter, the embodiment will be specifically described with reference to the drawings.

[0034] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims are described as optional components.

[0035] In addition, each figure is a schematic diagram and is not necessarily illustrated precisely. Therefore, for example, the scales in each figure do not necessarily match. In addition, in each figure, substantially the same configurations are given the same reference numerals, and duplicated explanations are omitted or simplified.

[0036] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as trapezoid or rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

[0037] In this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upward) and lower direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. The terms "upper" and "lower" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0038] In this specification, AlGaN refers to ternary mixed crystal Al x Ga 1-x N (x is a certain value, where 0≦x≦1). Hereinafter, multi-element alloys will be abbreviated by the arrangement of the constituent element symbols, such as AlInN, GaInN, etc. For example, the nitride semiconductor Al x Ga 1-x-y In yN (x, y are some values, where 0≦x≦1, 0≦y≦1) is abbreviated as AlGaInN.

[0039] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0040] (Embodiment 1) First, the configuration of the nitride semiconductor device according to the first embodiment will be described with reference to FIGS.

[0041] Fig. 3 is a cross-sectional view of the nitride semiconductor device 10 according to the present embodiment. Fig. 4 is a partially enlarged cross-sectional view showing an enlarged vicinity of the potential fixing electrode 36 of the nitride semiconductor device 10 according to the present embodiment.

[0042] The nitride semiconductor device 10 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 10 has a heterostructure of an AlGaN film (electron supply layer 26) and a GaN film (electron transit layer 24).

[0043] In addition, in the heterostructure of an AlGaN film and a GaN film, a high concentration of two-dimensional electron gas (2DEG) is generated at the heterointerface due to spontaneous polarization and piezoelectric polarization on the (0001) surface. Therefore, even when undoped, a high concentration of 1×10 13 cm -2 The sheet carrier concentration can be increased by 100%.

[0044] The nitride semiconductor device 10 is a field effect transistor (FET) that utilizes, as a channel, a two-dimensional electron gas 25 generated in an electron transit layer 24. Specifically, the nitride semiconductor device 10 is a so-called vertical FET.

[0045] As shown in FIG. 3 , the nitride semiconductor device 10 includes a substrate 12, a drift layer 14, a high-resistance layer 16, a first underlayer 18, a second underlayer 20, a gate opening 22, an electron transit layer 24, an electron supply layer 26, a source opening 30, a source electrode 32, an electrode opening 34, a potential fixing electrode 36, a gate electrode 38, and a drain electrode 40.

[0046] The substrate 12 is a substrate made of a nitride semiconductor. The substrate 12 has a thickness of, for example, 300 μm and a donor concentration of 1×10 18 cm -3 The substrate 12 is made of n+ type GaN, that is, the upper surface of the substrate 12 almost coincides with the (0001) plane (c-plane) of GaN.

[0047] Note that n-type, n+ type, and n- type, as well as p-type, p+ type, and p- type, indicate the conductivity type of a semiconductor. N-type, n+ type, and n- type are examples of a first conductivity type of a nitride semiconductor. P-type, p+ type, and p- type are examples of a second conductivity type that has a polarity different from that of the first conductivity type.

[0048] The drift layer 14 is an example of a first nitride semiconductor layer provided above the substrate 12. The drift layer 14 is, for example, a film made of n-type GaN with a thickness of 8 μm. The drift layer 14 is provided in contact with the upper surface of the substrate 12. The donor concentration of the drift layer 14 is lower than the donor concentration of the substrate 12, for example, 1×10 15 cm -3 More than 1×10 17 cm -3 The drift layer 14 may also contain carbon (C). The carbon concentration of the drift layer 14 is lower than the carbon concentration of the high resistance layer 16, for example, 1×10 15 cm -3 More than 2×10 17 cm -3 The following is the result.

[0049] The high resistance layer 16 is an example of a first high resistance layer provided above the drift layer 14. The resistance of the high resistance layer 16 is higher than the resistance of the drift layer 14. The thickness of the high resistance layer 16 is, for example, 200 nm. The high resistance layer 16 is provided in contact with the upper surface of the drift layer 14.

[0050] The high resistance layer 16 may be made of any material as long as it is an insulating layer, a semi-insulating layer, or a semiconductor layer with low impurities. The high resistance layer 16 is, for example, a GaN layer containing carbon. The carbon concentration is, for example, 3×10 17 cm -3 More preferably, 1×10 18 cm -3 The high resistance layer 16 may be formed by implanting ions of magnesium (Mg), iron (Fe), boron (B), or the like into GaN. As for the ion species used for the ion implantation, ion species other than those mentioned above can be used to obtain the same effect as long as they are ion species that can increase the resistance.

[0051] The high-resistance layer 16 may be an undoped GaN layer. The term "undoped" means that the GaN layer is not substantially doped with dopants such as Si, O (oxygen), or Mg that change the polarity of the GaN layer to n-type or p-type. For example, the oxygen concentration and silicon concentration of the high-resistance layer 16 are lower than the carbon concentration, and may be, for example, 5×10 16 cm -3 ≦2×10 16 cm -3 It may be the following.

[0052] The first underlayer 18 is an example of a first p-type nitride semiconductor layer provided above the high resistance layer 16. The first underlayer 18 is, for example, a film made of p-type GaN with a thickness of 400 nm. The first underlayer 18 functions as a block layer that suppresses leakage current that flows from the drain electrode 40 to the source electrode 32 without passing through a channel. The first underlayer 18 is connected to a potential fixed electrode 36 and is fixed at a predetermined potential.

[0053] The second underlayer 20 is an example of an n-type nitride semiconductor layer provided above the high resistance layer 16. The second underlayer 20 is a film made of n+ type GaN. The thickness of the second underlayer 20 is, for example, 300 nm, and the donor concentration is 1×10 17 cm -3 More than 3×10 18 cm -3 The following is the result.

[0054] The gate opening 22 is an example of a first opening that penetrates the second underlayer 20, the first underlayer 18, and the high resistance layer 16 and reaches the drift layer 14. As shown in FIG. 3, the gate opening 22 has a bottom 22a and a sidewall 22b. The bottom 22a is the upper surface of the drift layer 14 and is located below the interface between the high resistance layer 16 and the drift layer 14. The sidewall 22b is each of the end faces of the second underlayer 20, the first underlayer 18, and the high resistance layer 16, and a part of the upper surface of the drift layer 14. The sidewall 22b of the gate opening 22 is inclined obliquely with respect to the main surface of the substrate 12. For example, the cross-sectional shape of the gate opening 22 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. The cross-sectional shape of the gate opening 22 may be rectangular.

[0055] The electron travel layer 24 is provided so as to cover the upper portion of the first underlayer 18 and the gate opening 22. Specifically, the electron travel layer 24 is provided so as to be in contact with the upper surface of the second underlayer 20 and with the sidewall portion 22b and the bottom portion 22a of the gate opening 22. The electron travel layer 24 is a first regrown layer formed by regrowth of a nitride semiconductor after the gate opening 22 is formed. The electron travel layer 24 has a substantially uniform thickness and is curved along the shape of the gate opening 22. The electron travel layer 24 is, for example, a film made of undoped GaN having a thickness of 100 nm. The electron travel layer 24 may be doped with Si or the like to be n-type.

[0056] In addition, an AlN layer having a thickness of about 1 nm may be provided as a second regrown layer between the electron transit layer 24 and the electron supply layer 26. The AlN layer can suppress alloy scattering and improve channel mobility. The AlN layer does not have to be provided, and the electron transit layer 24 and the electron supply layer 26 may be in direct contact with each other. At the interface between the AlN layer and the electron transit layer 24, a two-dimensional electron gas 25 that serves as a channel is generated.

[0057] The electron supply layer 26 is provided above the electron transit layer 24. Specifically, the electron supply layer 26 is provided along the upper surface of the electron transit layer 24. The electron supply layer 26 is a third regrowth layer formed by regrowth of a nitride semiconductor after the gate opening 22 is formed. The electron supply layer 26 has a substantially uniform thickness and is curved along the curved shape of the upper surface of the electron transit layer 24. The electron supply layer 26 is, for example, a film made of AlGaN and having a thickness of 50 nm.

[0058] The source opening 30 is an example of a third opening that penetrates at least the electron supply layer 26 at a position away from the gate electrode 38 and exposes at least a part of the end face of the electron transit layer 24. Specifically, the source opening 30 penetrates the electron supply layer 26, the electron transit layer 24, and the second underlayer 20, and reaches the first underlayer 18.

[0059] As shown in FIG. 3 and FIG. 4, the source opening 30 has a bottom 30a and a sidewall 30b. The bottom 30a is the upper surface of the first underlayer 18 and is located below the interface between the first underlayer 18 and the second underlayer 20. The sidewall 30b is each end surface of the electron supply layer 26, the electron transit layer 24, and the second underlayer 20, and a part of the upper surface of the first underlayer 18. The sidewall 30b of the source opening 30 is approximately perpendicular to the main surface of the substrate 12. For example, the cross-sectional shape of the source opening 30 is rectangular, but may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid, similar to the gate opening 22.

[0060] The source electrode 32 is provided away from the gate electrode 38 and in contact with the electron supply layer 26 and the electron transit layer 24. The source electrode 32 is provided so as to cover the bottom 30a and the sidewall 30b of the source opening 30. The source electrode 32 is in direct contact with the two-dimensional electron gas 25 at the sidewall 30b of the source opening 30.

[0061] The source electrode 32 is formed using a conductive material such as a metal. The material of the source electrode 32 may be a material that makes ohmic contact with an n-type semiconductor, such as titanium (Ti). The source electrode 32 may have a laminated structure of a Ti film and an Al film. In this specification, the laminated structure has the Al film below the Ti film, and is represented as Ti / Al.

[0062] The electrode opening 34 is an example of a second opening that penetrates the electron supply layer 26, the electron transit layer 24, and the second underlayer 20 and reaches the first underlayer 18. As shown in FIG. 3 and FIG. 4, the electrode opening 34 has a bottom 34a and a sidewall 34b. The bottom 34a is the upper surface of the first underlayer 18 and is located below the interface between the first underlayer 18 and the second underlayer 20. The sidewall 34b is each of the end surfaces of the electron supply layer 26, the electron transit layer 24, and the second underlayer 20, and a part of the upper surface of the first underlayer 18. The sidewall 34b of the electrode opening 34 is approximately perpendicular to the main surface of the substrate 12. For example, the cross-sectional shape of the electrode opening 34 is rectangular, but may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid, like the gate opening 22.

[0063] The potential fixed electrode 36 is in contact with the first underlayer 18 at the bottom 34a of the electrode opening 34. In this embodiment, the potential fixed electrode 36 is electrically connected to the source electrode 32. In FIG. 4, the electrical connection between the potential fixed electrode 36 and the source electrode 32 is shown by a thick broken line. The electrical connection method is not particularly limited, but for example, the source electrode 32 and the potential fixed electrode 36 are electrically connected to each other by a source pad (not shown) provided above the source electrode 32.

[0064] The potential fixed electrode 36 is formed using a conductive material such as a metal. The potential fixed electrode 36 may be formed using a material that makes ohmic contact with the first underlayer 18, such as palladium (Pd), nickel (Ni), gold (Au), or tungsten silicide (WSi). In other words, in this embodiment, the potential fixed electrode 36 and the source electrode 32 are formed using different materials.

[0065] The gate electrode 38 is provided above the electron supply layer 26 so as to cover the gate opening 22. The gate electrode 38 is formed in a shape that conforms to the upper surface of the electron supply layer 26, in contact with the upper surface of the electron supply layer 26, and with a substantially uniform thickness.

[0066] The gate electrode 38 is formed using a conductive material such as a metal. For example, the gate electrode 38 is formed using Pd. Note that, as the material of the gate electrode 38, a material that makes Schottky contact with an n-type semiconductor can be used, and for example, Ni-based material, WSi, Au, etc. can be used. Note that the gate electrode 38 and the potential fixed electrode 36 can be formed using the same material. Therefore, the gate electrode 38 and the potential fixed electrode 36 can be formed in the same process.

[0067] The drain electrode 40 is provided below the substrate 12. Specifically, the drain electrode 40 is provided in contact with the lower surface of the substrate 12 (the surface opposite to the crystal growth surface). The drain electrode 40 is formed using a conductive material such as a metal. For example, the drain electrode 40 can be made of a material that is in ohmic contact with an n-type semiconductor, like the material of the source electrode 32.

[0068] Each nitride semiconductor layer can be formed by epitaxial growth such as MOVPE (Metal Organic Vapor Phase Epitaxy) or MBE (Molecular Beam Epitaxy). Specifically, the drift layer 14, the high resistance layer 16, the first underlayer 18, the second underlayer 20, the electron transit layer 24, and the electron supply layer 26 can be formed by sequentially depositing the layers using an MOVPE apparatus. The drift layer 14, the high resistance layer 16, the first underlayer 18, and the second underlayer 20 are formed continuously. Thereafter, the gate opening 22 is formed, and then the electron transit layer 24 and the electron supply layer 26 are formed continuously.

[0069] The gate opening 22, the source opening 30, and the electrode opening 34 are formed by photolithography and etching. The etching is, for example, dry etching. The electrode opening 34 can be formed simultaneously with the source opening 30. As a result, the bottom 34a of the electrode opening 34 and the bottom 30a of the source opening 30 are at the same distance to the substrate 12.

[0070] The source electrode 32, the potential fixed electrode 36, the gate electrode 38, and the drain electrode 40 are each formed by forming a metal film by a deposition method, a sputtering method, or the like, and patterning it into a predetermined shape. The patterning can be performed by photolithography and etching. The drain electrode 40 may not be patterned and may be provided on the entire lower surface of the substrate 12.

[0071] [Characteristic composition and effects] Next, a characteristic configuration of the above-mentioned nitride semiconductor device 10 will be described.

[0072] In the nitride semiconductor device 10, a high-resistance layer 16 is inserted between the drift layer 14 and the first underlayer 18. That is, by inserting the high-resistance layer 16 into the parasitic pn junction of the parasitic pn diode that was composed of n-type GaN (drift layer 14) and p-type GaN (first underlayer 18), it becomes difficult for a current to flow between the first underlayer 18 and the drift layer 14. That is, the current path of the parasitic pn junction diode can be blocked.

[0073] 1, even if the drain side potential becomes lower than the source side potential, it is possible to suppress a large current from flowing from the source electrode 32 to the drain electrode 40. Since a large current is unlikely to flow through the parasitic pn diode in reverse conducting operation, it is possible to suppress a decrease in the breakdown voltage caused by reverse conducting operation.

[0074] Moreover, this embodiment is characterized by the thickness of the first underlayer 18. Specifically, as shown in Fig. 4, the first underlayer 18 has a contact portion 18a that contacts the potential fixed electrode 36 and a non-contact portion 18b that does not contact the potential fixed electrode 36. The first underlayer 18 also has a contact portion 18c that contacts the source electrode 32.

[0075] The contact portion 18a is a part of the first underlayer 18, and is a portion whose planar shape coincides with the bottom 34a of the electrode opening 34. The layer thickness t2 of the contact portion 18a is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high-resistance layer 16) to the bottom 34a.

[0076] The contact portion 18c is a part of the first underlayer 18, and is a portion whose planar shape coincides with the bottom 30a of the source opening 30. The layer thickness t3 of the contact portion 18c is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high-resistance layer 16) to the bottom 30a.

[0077] The non-contact portion 18b is a part of the first underlayer 18 excluding the contact portions 18a and 18c. For example, the non-contact portion 18b is a portion whose shape in plan view matches the contact surface between the first underlayer 18 and the second underlayer 20. The layer thickness t1 of the non-contact portion 18b is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high-resistance layer 16) to the upper surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the second underlayer 20).

[0078] In this embodiment, the layer thickness t2 is 50% or more of the layer thickness t1. Moreover, the layer thickness t1 is 400 nm or more. As a result, the layer thickness t2 is 200 nm or more. The layer thickness t3 is 50% or more of the layer thickness t1. In this embodiment, the layer thickness t3 is equal to the layer thickness t2. At least one of the layer thicknesses t2 and t3 may be 70% or more of the layer thickness t1, 80% or more, or 90% or more. The layer thicknesses t1, t2, and t3 may be equal to each other.

[0079] The bottom 34a of the electrode opening 34 and the bottom 30a of the source opening 30 are each damaged by dry etching during the formation of the openings. That is, a damaged layer caused by dry etching is formed on the surface layer of each of the contact portions 18a and 18c of the first underlayer 18. The damaged layer contains crystal defects and the like, which are a cause of leakage current.

[0080] In this embodiment, the thickness t2 of the contact portion 18a and the thickness t3 of the contact portion 18c are both ensured to be 200 nm or more. This allows the damaged layer formed on the surface layer of the contact portions 18a and 18c to be kept away from the parasitic pn junction (in this embodiment, the high resistance layer 16 is included therebetween). This allows the reduction in breakdown voltage caused by the damaged layer to be suppressed.

[0081] [Variation 1] Next, a first modification of the first embodiment will be described.

[0082] Fig. 5 is a cross-sectional view of a nitride semiconductor device 10A according to this modification. As shown in Fig. 5, the nitride semiconductor device 10A differs from the nitride semiconductor device 10 according to the first embodiment in that it includes a potential fixed electrode 36A instead of the potential fixed electrode 36.

[0083] 5, the potential fixed electrode 36A is formed using a material different from that of the potential fixed electrode 36. Specifically, the potential fixed electrode 36A is formed using a material that makes Schottky contact with the first underlayer 18. In other words, for example, Ti / Al can be used as a material that makes Schottky contact with a p-type semiconductor.

[0084] As a result, a Schottky barrier diode is formed by the potential fixed electrode 36A and the first underlayer 18. The Schottky barrier diode is connected in series and in the reverse direction to the parasitic pn diode (i.e., the anodes are connected to each other). Therefore, the reverse characteristics of the Schottky barrier diode make the start-up voltage of the parasitic pn diode higher than when the potential fixed electrode 36 and the first underlayer 18 are in ohmic contact. This makes it possible to suppress current flowing through the parasitic pn diode and suppress a decrease in breakdown voltage.

[0085] [Variation 2] Next, a second modification of the first embodiment will be described.

[0086] Fig. 6 is a cross-sectional view of a nitride semiconductor device 10B according to this modification. As shown in Fig. 6, the nitride semiconductor device 10B differs from the nitride semiconductor device 10A according to the first modification in that it additionally includes a threshold adjustment layer 28.

[0087] 6, the threshold adjustment layer 28 is an example of a second p-type nitride semiconductor layer provided between the gate electrode 38 and the electron supply layer 26. The threshold adjustment layer 28 is in contact with an upper surface of the electron supply layer 26 and a lower surface of the gate electrode 38.

[0088] The threshold adjustment layer 28 has a thickness of, for example, 100 nm and a carrier concentration of 1×10 17 cm -3 The threshold adjustment layer 28 is a nitride semiconductor layer made of p-type AlGaN, which is a p-type nitride semiconductor layer having a p-type conductivity. The threshold adjustment layer 28 is formed by depositing the electron supply layer 26 by MOVPE method, and then patterning the deposited layer.

[0089] According to this modification, the potential of the conduction band edge of the channel portion is raised by the threshold adjustment layer 28. This makes it possible to increase the threshold voltage of the nitride semiconductor device 10B. In other words, the nitride semiconductor device 10B can be operated as a normally-off type FET.

[0090] The threshold adjustment layer 28 does not have to be a p-type nitride semiconductor. For example, the threshold adjustment layer 28 may be formed using an insulating material such as silicon nitride (SiN) or silicon oxide (SiO2). In other words, there is no particular limitation as long as the material has the effect of increasing the potential of the channel.

[0091] The nitride semiconductor device 10 shown in FIG.

[0092] (Embodiment 2) Next, a second embodiment will be described.

[0093] The nitride semiconductor device according to the second embodiment differs from the first embodiment mainly in that a second high-resistance layer is provided above the first p-type nitride semiconductor layer. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0094] Fig. 7 is a cross-sectional view of the nitride semiconductor device 100 according to the present embodiment. Fig. 8 is a partially enlarged cross-sectional view showing an enlarged vicinity of the potential fixing electrode 36 of the nitride semiconductor device 100 according to the present embodiment.

[0095] As shown in FIG. 7, the nitride semiconductor device 100 differs from the nitride semiconductor device 10 according to the first embodiment in that a high-resistance layer 116 is newly provided. The high-resistance layer 116 is an example of a second high-resistance layer provided above the first underlayer 18. The resistance of the high-resistance layer 116 is higher than the resistance of the first underlayer 18. The resistance of the high-resistance layer 116 is also higher than the resistance of the second underlayer 20. The high-resistance layer 116 is provided in contact with both the upper surface of the first underlayer 18 and the lower surface of the second underlayer 20. The high-resistance layer 116 has a thickness of, for example, 200 nm.

[0096] The high-resistance layer 116 is a GaN layer containing carbon or an undoped GaN layer, similar to the high-resistance layer 16. The carbon concentration of the high-resistance layer 116 is the same as that of the high-resistance layer 16, but may be different. The method for forming the high-resistance layer 116 is the same as the method for forming the high-resistance layer 16.

[0097] In this embodiment, since the high resistance layer 116 is provided, the gate opening 22 penetrates the second underlayer 20, the high resistance layer 116, the first underlayer 18, and the high resistance layer 16, and reaches the drift layer 14. The end face of the high resistance layer 116 is a part of the side wall 22b of the gate opening 22. The source opening 30 and the electrode opening 34 penetrate the electron supply layer 26, the electron transit layer 24, the second underlayer 20, and the high resistance layer 116, respectively, and reach the first underlayer 18. The end face of the high resistance layer 116 is a part of each of the side wall 30b of the source opening 30 and the side wall 34b of the electrode opening 34.

[0098] If the high-resistance layers 16 and 116 are not provided, a parasitic bipolar transistor having a parasitic npn structure is formed by the n-type second underlayer 20, the p-type first underlayer 18, and the n-type drift layer 14. When the nitride semiconductor device 100 is in an off state, if a current flows through the first underlayer 18, the parasitic bipolar transistor may be turned on, lowering the breakdown voltage of the nitride semiconductor device 100. In this case, the nitride semiconductor device 100 is likely to malfunction.

[0099] The formation of this parasitic npn structure can be suppressed by providing the high-resistance layer 116, thereby suppressing a decrease in the breakdown voltage of the nitride semiconductor device 100.

[0100] In this embodiment, as shown in FIG. 8, the first underlayer 18 has contact portions 18a and 18c and a non-contact portion 18b. The layer thickness t1 of the non-contact portion 18b, the layer thickness t2 of the contact portion 18a, and the layer thickness t3 of the contact portion 18c have the same relationship as in the first embodiment. In this case, the non-contact portion 18b is a portion whose planar shape coincides with the contact surface between the first underlayer 18 and the high resistance layer 116. The layer thickness t1 of the non-contact portion 18b is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high resistance layer 16) to the upper surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high resistance layer 116).

[0101] [Variations] Next, a modification of the second embodiment will be described.

[0102] 9 is a cross-sectional view of a nitride semiconductor device 100A according to this modification. As shown in Fig. 9, the nitride semiconductor device 100A differs from the nitride semiconductor device 100 according to the second embodiment in that it additionally includes a threshold adjustment layer 28 and a potential fixed electrode 36A instead of the potential fixed electrode 36.

[0103] The threshold adjustment layer 28 is the same as that in Modification 2 of Embodiment 1. By providing the nitride semiconductor device 100A with the threshold adjustment layer 28, the nitride semiconductor device 100A can be operated as a normally-off type FET.

[0104] The potential fixed electrode 36A is the same as that in Modification 1 of Embodiment 1. A Schottky barrier diode is formed by the potential fixed electrode 36A and the first underlayer 18, so that it is possible to suppress a current flowing through a parasitic pn diode and to suppress a decrease in the breakdown voltage.

[0105] It is to be noted that the nitride semiconductor device 100A does not necessarily have to include the threshold adjustment layer 28. Alternatively, the nitride semiconductor device 100A may include a potential fixed electrode 36 instead of the potential fixed electrode 36A.

[0106] (Embodiment 3) Next, a third embodiment will be described.

[0107] The nitride semiconductor device according to the third embodiment differs from the second embodiment mainly in that it does not include the first high-resistance layer. The following description will focus on the differences from the second embodiment, and description of the commonalities will be omitted or simplified.

[0108] Fig. 10 is a cross-sectional view of the nitride semiconductor device 200 according to the present embodiment. Fig. 11 is a partially enlarged cross-sectional view showing an enlarged vicinity of the potential fixing electrode 36 of the nitride semiconductor device 200 according to the present embodiment.

[0109] As shown in Fig. 10, the nitride semiconductor device 200 does not include the high resistance layer 16 shown in Fig. 7. In this embodiment, as in the first and second embodiments, as shown in Fig. 11, the first underlayer 18 has contact portions 18a and 18c and a non-contact portion 18b. The layer thickness t1 of the non-contact portion 18b, the layer thickness t2 of the contact portion 18a, and the layer thickness t3 of the contact portion 18c have the same relationship as in the first and second embodiments. That is, the layer thickness t1 is 400 nm or more, and the layer thicknesses t2 and t3 are each 50% or more of the layer thickness t1.

[0110] At this time, the layer thickness t1 of the non-contact portion 18b is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the drift layer 14) to the upper surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the high-resistance layer 116). The layer thickness t2 of the contact portion 18a is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the drift layer 14) to the bottom 34a. The layer thickness t3 of the contact portion 18c is the distance from the lower surface of the first underlayer 18 (specifically, the interface between the first underlayer 18 and the drift layer 14) to the bottom 30a.

[0111] This allows the damaged layer formed on the surface layer of the contact portions 18a and 18c to be located away from the parasitic pn junction, thereby suppressing a decrease in breakdown voltage caused by the damaged layer.

[0112] [Variations] Next, a modification of the third embodiment will be described.

[0113] Fig. 12 is a cross-sectional view of a nitride semiconductor device 200A according to this modification. As shown in Fig. 12, the nitride semiconductor device 200A differs from the nitride semiconductor device 200 according to the third embodiment in that it additionally includes a threshold adjustment layer 28 and a potential fixed electrode 36A instead of the potential fixed electrode 36.

[0114] The threshold adjustment layer 28 is the same as that in Modification 2 of Embodiment 1. By providing the nitride semiconductor device 200A with the threshold adjustment layer 28, the nitride semiconductor device 200A can be operated as a normally-off type FET.

[0115] The potential fixed electrode 36A is the same as that in Modification 1 of Embodiment 1. A Schottky barrier diode is formed by the potential fixed electrode 36A and the first underlayer 18, so that it is possible to suppress a current flowing through a parasitic pn diode and to suppress a decrease in the breakdown voltage.

[0116] It is to be noted that the nitride semiconductor device 200A does not necessarily have to include the threshold adjustment layer 28. Alternatively, the nitride semiconductor device 200A may include a potential fixing electrode 36 instead of the potential fixing electrode 36A.

[0117] (Other embodiments) Although the nitride semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments are also included within the scope of the present disclosure.

[0118] For example, when the nitride semiconductor device includes the potential fixing electrode 36A, it does not need to include the high resistance layer 16. Also, the layer thickness t1 of the non-contact portion 18b of the first underlayer 18 may be less than 400 nm. Alternatively, the layer thickness t2 of the contact portion 18a may be less than 50% of the layer thickness t1.

[0119] Furthermore, for example, when the nitride semiconductor device includes the high-resistance layer 16, the thickness t1 of the non-contact portion 18b of the first underlayer 18 may be less than 400 nm. Alternatively, the thickness t2 of the contact portion 18a may be less than 50% of the thickness t1.

[0120] Furthermore, for example, the substrate 12 does not have to be a nitride semiconductor substrate, but may be, for example, a Si substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0121] For example, the first underlayer 18 may be formed by implanting Mg ions into i-GaN instead of by crystal growth. In the nitride semiconductor device 200 or 200A not including the high-resistance layer 16, the first underlayer 18 may be an insulating layer formed by implanting Fe ions instead of a p-type semiconductor layer.

[0122] Furthermore, for example, the nitride semiconductor devices according to each of the embodiments and modifications do not necessarily need to include the second underlayer 20.

[0123] Furthermore, for example, the nitride semiconductor devices according to each of the embodiments and modifications do not need to include the source opening 30. However, by providing the source opening 30, the source electrode 32 and the two-dimensional electron gas 25 can be brought into direct contact with each other, and therefore the ohmic contact resistance between the source electrode 32 and the channel can be reduced.

[0124] Also, for example, the source opening 30 and the electrode opening 34 may be integrated into one opening. In other words, the bottom 30a of the source opening 30 and the bottom 34a of the electrode opening 34 may be connected and flush with each other. The source electrode 32 may be provided so as to cover the sidewall of the one opening, and the potential fixing electrode 36 may be provided so as to cover at least a part of the bottom of the one opening. The source electrode 32 and the potential fixing electrode 36 may be in contact with each other. This allows the potential of the potential fixing electrode 36 to be easily fixed to the source potential.

[0125] The potential fixed electrode 36 may be fixed to a potential different from the source potential.

[0126] Furthermore, for example, the donor concentration does not have to be uniform in the drift layer 14. For example, the donor concentration may be low in the surface portion of the drift layer 14, that is, near the interface with the high-resistance layer 16 or the first underlayer 18.

[0127] In addition, the present disclosure also includes forms obtained by applying various modifications to each embodiment that a person skilled in the art may conceive, and forms realized by arbitrarily combining the components and functions of each embodiment within the scope that does not deviate from the spirit of the present disclosure. [Industrial Applicability]

[0128] The present disclosure can be used as a nitride semiconductor device that can suppress a decrease in breakdown voltage caused by reverse conduction, and can be used, for example, as a power device used in the power supply circuits of consumer devices. [Explanation of symbols]

[0129] 1 Power Conversion Circuit 2. Load 3 Power supply 4, 7 Capacitor 5. Inductors 6 Gate drive circuit 8a, 8b FETs 10, 10A, 10B, 100, 100A, 200, 200A Nitride Semiconductor Devices 12 Substrate 14 Drift Layer 16, 116 high resistance layer 18 First Undercoat Layer 18a, 18c contact part 18b Non-contact part 20 Second Undercoat Layer 22 Gate opening 22a, 30a, 34a bottom 22b, 30b, 34b side wall 24 Electron transport layer 25 Two-dimensional electron gas 26 Electron supply layer 28 Threshold adjustment layer 30 Source opening 32 Source electrode 34 Electrode opening 36, 36A potential fixed electrode 38 Gate electrode 40 Drain electrode

Claims

1. A substrate; a first nitride semiconductor layer provided above the substrate; a first high-resistance layer provided above the first nitride semiconductor layer and having a resistance higher than that of the first nitride semiconductor layer; a first p-type nitride semiconductor layer provided above the first high resistance layer; a first opening that penetrates the first p-type nitride semiconductor layer and the first high-resistance layer and reaches the first nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from the substrate side so as to cover an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode provided above the electron supply layer so as to cover the first opening; a source electrode provided apart from the gate electrode and in contact with the electron supply layer; a second opening that passes through the electron supply layer and the electron transit layer and reaches the first p-type nitride semiconductor layer; a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening; a drain electrode provided below the substrate; Nitride semiconductor devices.

2. The first high resistance layer is a GaN layer containing carbon. The nitride semiconductor device of claim 1 .

3. The first high resistance layer is an undoped GaN layer. The nitride semiconductor device of claim 1 .

4. the potential fixed electrode is formed using a material that forms a Schottky contact with the first p-type nitride semiconductor layer; The nitride semiconductor device according to any one of claims 1 to 3.

5. a layer thickness of a contact portion of the first p-type nitride semiconductor layer in contact with the potential fixed electrode is 50% or more of a layer thickness of a non-contact portion of the first p-type nitride semiconductor layer not in contact with the potential fixed electrode; The layer thickness of the non-contact portion is 400 nm or more. The nitride semiconductor device according to any one of claims 1 to 4.

6. A substrate; a first nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a first opening penetrating the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from the substrate side so as to cover an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode provided above the electron supply layer so as to cover the first opening; a source electrode provided apart from the gate electrode and in contact with the electron supply layer; a second opening that passes through the electron supply layer and the electron transit layer and reaches the first p-type nitride semiconductor layer; a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening; a drain electrode provided below the substrate; the potential fixed electrode is formed using a material that forms a Schottky contact with the first p-type nitride semiconductor layer; Nitride semiconductor devices.

7. A substrate; a first nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a first opening penetrating the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from the substrate side so as to cover an upper portion of the first p-type nitride semiconductor layer and the first opening; a gate electrode provided above the electron supply layer so as to cover the first opening; a source electrode provided apart from the gate electrode and in contact with the electron supply layer; a second opening that passes through the electron supply layer and the electron transit layer and reaches the first p-type nitride semiconductor layer; a potential fixed electrode in contact with the first p-type nitride semiconductor layer at a bottom of the second opening; a drain electrode provided below the substrate; a layer thickness of a contact portion of the first p-type nitride semiconductor layer in contact with the potential fixed electrode is 50% or more of a layer thickness of a non-contact portion of the first p-type nitride semiconductor layer not in contact with the potential fixed electrode; The layer thickness of the non-contact portion is 400 nm or more, the potential fixed electrode is formed using a material that forms a Schottky contact with the first p-type nitride semiconductor layer; Nitride semiconductor devices.

8. Further, a second p-type nitride semiconductor layer is provided between the gate electrode and the electron supply layer. The nitride semiconductor device according to any one of claims 1 to 7.

9. The semiconductor device further includes a second high-resistance layer provided above the first p-type nitride semiconductor layer and having a higher resistance than the first p-type nitride semiconductor layer, the first opening further penetrates the second high-resistance layer; the electron transit layer and the electron supply layer cover an upper portion of the second high resistance layer; The nitride semiconductor device according to any one of claims 1 to 8.

10. The potential fixing electrode is electrically connected to the source electrode. The nitride semiconductor device according to any one of claims 1 to 9.

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