MEMORY SYSTEM FOR SELECTING ERROR RESPONSE ACTION THROUGH ANALYSIS OF PREVIOUSLY OCCURRENT ERRORS AND DATA PROCESSING SYSTEM INCLUDING THE MEMORY SYSTEM - Patent application

Abstract

To provide a data processing system for selecting a counter-error operation by analyzing errors previously occurred.SOLUTION: The data processing system includes: a memory system 110 including a plurality of memory devices 1501 to 1508, each of which includes a first error correction unit and a plurality of cell array regions (memory banks BK<1> to <4>) in which a plurality of memory cells are coupled in an array form; and a host 102 including a second error correction unit which corrects an error of data transferred from the memory system, generating error correction information on the error correction operation, setting an error strength for each of the plurality of memory devices using the error correction information and log information generated in each of the plurality of memory devices, and performing a counter-error operation on each of the plurality of memory devices according to the error correcting strength. In each of the plurality of memory devices, an error of access data occurred during access operation with respect to the plurality of cell array regions is corrected by the first error correction unit so as to generate log information.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a data processing system, and more particularly to a memory system capable of selecting an error response operation through analysis of previously occurring errors, and a data processing system including the memory system. [Background technology]

[0002] Computer devices or wired and wireless electronic devices, for example, computer devices such as servers, desktop computers, and laptop computers, or electronic devices such as mobile phones, game consoles, TVs, and projectors, can generate and process a great deal of data during operation. Thus, in order to store the data generated and processed during operation, a memory system that generally uses a memory device, in other words, a data storage device, can be used. The data storage device can be used as a main memory device or an auxiliary memory device of the computer device or electronic device.

[0003] Meanwhile, a memory system may include multiple memory devices, and during the process of writing / reading data from the multiple memory devices, errors may occur in which some data is not written / read properly. Generally, most data in which an error has occurred can be processed as normal data through an error recovery algorithm. However, serious errors that cannot be processed even through the error recovery algorithm may exist, and if such serious errors occur, the reliability of the entire memory system may be significantly reduced.

[0004] Therefore, it is very important to predict whether a serious error will occur in a certain area at a certain time. However, in the past, the occurrence of an error was predicted statistically by counting the number of times an error occurred, which resulted in a very low accuracy. Summary of the Invention [Problem to be solved by the invention]

[0005] An embodiment of the present invention provides a data processing system including an apparatus and method for analyzing previously occurring errors and performing error response operations on each of the memory devices in a memory system including a plurality of memory devices. [Means for solving the problem]

[0006] A data processing system according to an embodiment of the present invention includes a memory system including a plurality of memory devices, each of which includes a plurality of cell array regions in which a plurality of memory cells are connected in an array form to a plurality of word lines and a plurality of bit lines, and a first error correction unit; and a host including a second error correction unit, wherein the second error correction unit corrects errors in data transmitted from the memory system, generates error correction information for the error correction operation of the second error correction unit, sets an error strength for each of the plurality of memory devices using the error correction information and log information generated in each of the plurality of memory devices, and performs an error response operation for each of the plurality of memory devices according to the error strength. Each of the plurality of memory devices can have the first error correction unit correct errors in access data occurring during an access operation to the plurality of cell array regions, and generate the log information for the error correction operation of the first error correction unit.

[0007] In addition, each of the plurality of memory devices may operate the first error correction unit included therein to correct an error that occurs in access data during an access operation including a read / write operation, accumulate and store raw data of the data whose error has been corrected by the first error correction unit in an internal information storage area to generate the log information, and output the log information to the host via the memory system at the request of the host.

[0008] The host may further include an error collection unit that collects the error correction information in real time or at a set time point and collects the log information from the memory system at the set time point; a first error analysis unit that analyzes the log information and the error correction information to confirm the number and type of errors occurred in each of the plurality of memory devices and determines an error grade for each of the plurality of memory devices according to the confirmation result; a second error analysis unit that determines an error strength for some of the plurality of memory devices by confirming the type and number of errors through additional analysis of the log information and the error correction information according to the error grade determined by the first error analysis unit, and determines an error strength for the remaining memory devices so as to correspond to the error grade determined by the first error analysis unit; and a response operation unit that performs the error response operation for each of the plurality of memory devices according to the error strength determined by the second error analysis unit.

[0009] In addition, the first error analysis unit may classify a memory device having a number of errors occurring therein equal to or greater than a first reference number as a first memory device, and if the type of error occurring in the first memory device is a first error occurring in a word line equal to or greater than a second reference number, classify the corresponding first memory device as a second memory device having a first error class, and if the type of error occurring in the first memory device is another type of error other than the first error, classify the corresponding first memory device as a third memory device having a second error class.

[0010] In addition, each of the first and second error correction units performs an error correction operation on data input / output from each of the plurality of memory devices in the unit of a code word including an error correction code (ECC). The second error analysis unit may classify the corresponding second memory device as a fourth memory device having a first error strength when an error type occurring in the second memory device crosses a third reference number or more of codeword units and a total number of errors included is a fourth reference number or more, and may classify the corresponding second memory device as a fifth memory device having a second error strength when an error type occurring in the second memory device crosses the third reference number or more of codeword units and a total number of errors included is less than the fourth reference number or crosses codewords less than the third reference number, and may assign the second error strength to the third memory device to classify it as the fifth memory device.

[0011] In addition, the corresponding operation unit can select and perform one of the following operations as the error response operation depending on a state of the fourth memory device: an operation of selecting an area in the fourth memory device where an error has occurred and blocking access to it, an operation of selecting an area in the fourth memory device where an error has occurred and repairing it, and an operation of selecting an area in the fourth memory device where an error has occurred and disabling it.

[0012] In addition, the host can select at least one of the following operations: designating a point in time that is repeated at specific time intervals from the point in time when power is supplied to the memory system as the set point in time; counting the number of errors that occur in access data during an access operation to the memory system, and designating the point in time at which a fifth reference number is exceeded as the set point in time and then initializing the count of the number of errors; and designating a point in time at which an error correction operation for correcting errors that occur in access data during an access operation to the memory system takes more than a specific time as the set point in time.

[0013] According to an embodiment of the present invention, a memory system may include a plurality of memory devices each including a plurality of cell array regions in which a plurality of memory cells are connected in an array form to a plurality of word lines and a plurality of bit lines, the first error correction unit correcting an error in access data occurring during an access operation to the plurality of cell array regions and generating log information for the error correction operation of the first error correction unit; and a controller including a second error correction unit, the second error correction unit correcting an error in data transmitted from the plurality of memory devices and generating error correction information for the error correction operation of the second error correction unit, setting an error strength for each of the plurality of memory devices using the log information and the error correction information, and performing an error response operation for each of the plurality of memory devices corresponding to the error strength.

[0014] In addition, each of the plurality of memory devices may operate the first error correction unit included therein to correct an error that occurs in access data during an access operation including a read / write operation, accumulate and store raw data of the data whose error has been corrected by the first error correction unit in an internal information storage area to generate the log information, and output the log information to the controller upon request of the controller.

[0015] The controller may further include an error collection unit that collects the error correction information in real time or at a set time point and collects the log information from each of the plurality of memory devices at the set time point; a first error analysis unit that analyzes the log information and the error correction information to confirm the number and type of errors occurring in each of the plurality of memory devices and determines an error grade for each of the plurality of memory devices according to the confirmation result; a second error analysis unit that determines an error strength for some of the plurality of memory devices by additionally analyzing the log information and the error correction information according to the error grade determined by the first error analysis unit, and determines an error strength for the remaining memory devices so as to correspond to the error grade determined by the first error analysis unit; and a response operation unit that performs the error response operation for each of the plurality of memory devices according to the error strength determined by the second error analysis unit.

[0016] In addition, the first error analysis unit may classify a memory device having a number of errors occurring therein equal to or greater than a first reference number as a first memory device, and if the type of error occurring in the first memory device is a first error occurring in a word line equal to or greater than a second reference number, classify the corresponding first memory device as a second memory device having a first error class, and if the type of error occurring in the first memory device is another type of error other than the first error, classify the corresponding first memory device as a third memory device having a second error class.

[0017] In addition, each of the first and second error correction units performs an error correction operation on data input / output from each of the plurality of memory devices in the unit of a code word including an error correction code (ECC). The second error analysis unit may classify the corresponding second memory device as a fourth memory device having a first error strength when an error type occurring in the second memory device crosses a third reference number or more of codeword units and a total number of errors included is a fourth reference number or more, and may classify the corresponding second memory device as a fifth memory device having a second error strength when an error type occurring in the second memory device crosses the third reference number or more of codeword units and a total number of errors included is less than the fourth reference number or crosses codewords less than the third reference number, and may assign the second error strength to the third memory device to classify it as the fifth memory device.

[0018] In addition, the corresponding operation unit can select and perform one of the following operations as the error response operation depending on a state of the fourth memory device: an operation of selecting an area in the fourth memory device where an error has occurred and blocking access to it, an operation of selecting an area in the fourth memory device where an error has occurred and repairing it, and an operation of selecting an area in the fourth memory device where an error has occurred and disabling it.

[0019] In addition, the controller may select at least one of the following operations: designating a point in time that is repeated at specific time intervals from the point in time when power is supplied as the set point in time; counting the number of errors that occur in access data during an access operation to the plurality of memory devices, and designating the point in time at which a fifth reference number is exceeded as the set point in time each time the fifth reference number is exceeded, and then initializing the count of the number of errors; and designating a point in time at which an error correction operation for correcting errors that occur in access data during an access operation to the plurality of memory devices takes more than a specific time as the set point in time.

[0020] In addition, a method for operating a memory system according to an embodiment of the present invention, in a method for operating a memory system including a plurality of memory devices each having a plurality of cell array regions in which a plurality of memory cells are connected in an array form to a plurality of word lines and a plurality of bit lines, and an error correction unit, may include a generating step in which the error correction unit corrects an error in access data occurring during an access operation for each of the plurality of memory devices and generates log information on the error correction operation of the error correction unit, an analyzing step in which an error grade for each of the plurality of memory devices is set using the log information, and a corresponding step in which an error response operation is performed for each of the plurality of memory devices according to the error grade.

[0021] The generating step may further include an operating step of operating the error correction unit to correct an error that occurs in access data when an error occurs in access data during an access operation for each of the plurality of memory devices, and a step of accumulating and storing raw data for data in which an error has been corrected by the error correction unit in the operating step in an information storage area included in each of the plurality of memory devices to generate the log information.

[0022] The analysis step may also include a collection step of collecting the log information stored in the information storage area at each set time point, and an error analysis step of analyzing the log information collected in the collection step to confirm the number and type of errors that have occurred in each of the plurality of memory devices, and determining an error grade for each of the plurality of memory devices based on the confirmation results.

[0023] The error analysis step may further include a step of classifying a memory device having a number of errors occurring therein equal to or greater than a first reference number as a first memory device, a step of classifying the corresponding first memory device as a second memory device having a first error class if the type of error occurring in the first memory device is a first error occurring in a word line equal to or greater than a second reference number, and a step of classifying the corresponding first memory device as a third memory device having a second error class if the type of error occurring in the first memory device is another type of error other than the first error.

[0024] In addition, the response step may select one of the following operations as the error response operation depending on the state of the second memory device: an operation of selecting an area in the second memory device where an error has occurred and blocking access to it; an operation of selecting an area in the second memory device where an error has occurred and repairing it; and an operation of selecting an area in the second memory device where an error has occurred and disabling it.

[0025] The method may further include at least one of the following steps: designating a point in time that is repeated at specific time intervals from a point in time when power is supplied as the set point in time; counting the number of errors that occur in access data during an access operation to the plurality of memory devices, and designating the point in time at which a fifth reference number is exceeded as the set point in time each time the fifth reference number is exceeded, and then initializing the count of the number of errors; and designating a point in time at which an error correction operation for correcting errors that occur in access data during an access operation to the plurality of memory devices takes more than a specific time as the set point in time. Effect of the Invention

[0026] The present technology generates log information of errors that occur during access operations to each of the memory devices in a memory system including a plurality of memory devices, and then analyzes the error log information based on the number, type, and form of errors, and sets different error strengths for each of the plurality of memory devices, thereby enabling error response operations to be performed for each of the plurality of memory devices.

[0027] This has the effect of predicting in advance which memory device or specific area of ​​the memory device is likely to have a serious error among a plurality of memory devices, and performing an appropriate error response operation. [Brief description of the drawings]

[0028] [Figure 1A] 1 is a diagram for explaining the configuration of a data processing system according to a first embodiment of the present invention; [Figure 1B] FIG. 11 is a diagram for explaining the configuration of a memory system according to a second embodiment of the present invention. [Figure 1C] FIG. 11 is a diagram for explaining the configuration of a memory system according to a third embodiment of the present invention. [Diagram 2] FIG. 4 is a diagram for explaining a log information analysis operation according to an embodiment of the present invention. [Diagram 3]FIG. 4 is a diagram for explaining a log information analysis operation according to an embodiment of the present invention. [Figure 4] FIG. 4 is a diagram for explaining a log information analysis operation according to an embodiment of the present invention. [Figure 5A] FIG. 4 is a diagram for explaining a log information analysis operation according to an embodiment of the present invention. [Figure 5B] FIG. 4 is a diagram for explaining a log information analysis operation according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be configured in various different forms. However, the present embodiments are provided so that the disclosure of the present invention will be complete and will fully convey the scope of the present invention to those skilled in the art.

[0030] FIG. 1A is a diagram shown for explaining the configuration of a data processing system according to a first embodiment of the present invention.

[0031] 1A, the data processing system according to the first embodiment of the present invention may include a host 102 and a memory system 110. Here, the memory system 110 may include a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. And, the host 102 may include an error collection unit 1021, a first error analysis unit 1023, a second error analysis unit 1024, a corresponding operation unit 1025, and a host ECC 1026.

[0032] Each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may have multiple memory banks BK<1:4>, memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8), and information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8.

[0033] For reference, the drawing shown in FIG. 1A assumes that each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is a DRAM, and the detailed configuration may be changed if the memory device 10 is another type of memory device. Specifically, each of the plurality of memory banks BK<1:4> may include a plurality of memory cells (CELL) connected in an array form to a plurality of word lines WL1, WL2, ..., WLX and a plurality of bit lines BL1, BL2, BL3, ..., BLY, and each of the plurality of memory cells may store at least one bit of data. That is, each of the plurality of memory banks BK<1:4> may be considered as a "cell array region" in which a plurality of memory cells are provided in an array form. Therefore, the expression "a plurality of memory banks" is assumed to be a DRAM, and may be replaced with the expression "a plurality of cell array regions" if the memory device 10 is another type of memory device. In summary, the internal configuration of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can be designed and modified depending on the characteristics of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, the purpose for which the memory system 110 is used, or the specifications of the memory system 110 required by the host 102, etc.

[0034] Furthermore, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110 can generate log information LOG_INFO for data from which the error has been recovered by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) when an error occurs during an access operation, for example, a data read / write operation, and the error is recovered through the operation of the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) included therein. That is, each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may accumulate and store raw data related to an error in an access operation, which is corrected by memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8) during an access operation, in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8, to generate log information LOG_INFO. At this time, the raw data related to an error included in the log information LOG_INFO may mean all data that can be generated in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in relation to the occurrence of an error. That is, the raw data related to the errors included in the log information LOG_INFO may be data indicating the time, location, type, and number of errors. For example, it may be data indicating the number of bits of data in which an error occurred, the physical storage location of the data in which an error occurred, the absolute time when the error occurred, the range of the physical area in which the error occurred, and the type of error that occurred. And, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be storage spaces included in the form of registers in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.In addition, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be at least a partial space in at least one of a plurality of banks BK<1:4> provided in each of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0035] The host 102 can then collect raw data related to errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110 through the following operations.

[0036] In the first operation, as described above, during an access operation to each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, raw data related to an error in an access operation in which the error is corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8) may be accumulated and stored as log information LOG_INFO in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8. Thus, the host 102 may collect log information LOG_INFO from each of the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0037] In the second operation, the host 102 may generate and collect, as error correction information ERR_CO_INFO, raw data related to an error in an access operation in which an error is corrected by the internal host ECC 1026 during an access operation, for example, a data read operation, to each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. In this case, in the case of an access operation in which an error is corrected by the host ECC 1026 provided in the host 102, it may be assumed that the access operation is an access operation in which an error could not be corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) provided in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. At this time, the raw data related to the error included in the error correction information ERR_CO_INFO may mean all data that can be generated by the host ECC 1026 in relation to the occurrence of an error. That is, the raw data related to the error included in the error correction information ERR_CO_INFO may be data representing the time, location, type, and number of errors. For example, it may be data representing the number of bits of data in which an error has occurred, the physical storage location of data in which an error has occurred, the absolute time when the error has occurred, the range of the physical area in which the error has occurred, and the type of error that has occurred.

[0038] The host 102 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to grasp the number, type, and form of errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Therefore, the host 102 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO based on the number, type, and form of errors to set different error strengths for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110. In addition, the host 102 can perform different error handling operations for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error strength.

[0039] More specifically, the error collection unit 1021 in the host 102 may transmit a command (not shown) for collecting information to the memory system 110 at a set time point, and then, in response to the command for collecting information, may receive and collect log information LOG_INFO output from information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in the memory system 110. In addition, the error collection unit 1021 may collect error correction information ERR_CO_INFO generated by the host ECC 1026 in real time or at set time points.

[0040] Here, the host 102 can select and specify at least one of the following several time points as the set time point.

[0041] First, a point in time that is repeated at a specific time interval from the point in time when power is supplied to the memory system 110 can be designated as a set point in time.

[0042] Secondly, the number of errors occurring during an access operation to the memory system 110, i.e., an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, may be counted, and whenever the counted number exceeds a predetermined reference number, the time at which the counted number exceeds the predetermined reference number may be designated as a set time point. At this time, whenever the set time point is designated, the counted number may be initialized. For example, the counting of the number of errors may be performed by the host ECC 1026.

[0043] Third, an error recovery operation is performed to recover an error that occurs during an access operation to the memory system 110, i.e., an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and a time point at which the error recovery operation takes more than a specific time can be designated as the set time point. In this case, the time point at which the error recovery operation takes more than a specific time can mean that a relatively simple error recovery operation using a Hamming code has failed in the process of recovering the error that has occurred, and a relatively complicated error recovery operation using a Reed-Solomon code has been used. For example, the error recovery operation can be performed using the host ECC 1026.

[0044] The error collection unit 1021 can store the log information LOG_INFO and the error correction information ERR_CO_INFO in a set space in the host 102. At this time, as shown in the drawing, the inside of the error collection unit 1021 can be a separate storage area. Also, although not directly shown in the drawing, the set space in the host 102 can be a specific storage space of a host memory included in the host 102 and used as an operating memory of the host 102. The first error analysis unit 1023 analyzes the log information LOG_INFO and the error correction information ERR_CO_INFO collected by the error collection unit 1021 to check the number and type of errors occurring in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and can determine an error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 according to the number and type of errors confirmed. At this time, information related to the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1023 can be stored in a set space inside the host 102.

[0045] The second error analysis unit 1024 can select some of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1023. In addition, the second error analysis unit 1024 may determine the error strength by checking the type and number of errors through additional analysis of the log information LOG_INFO and the error correction information ERR_CO_INFO for some selected memory devices among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and may determine the error strength for the remaining memory devices excluding the some memory devices so as to correspond to the error grade determined by the first error analysis unit 1023. At this time, the second error analysis unit 1024 may read the error strength for each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1023 from a set space inside the host 102. In addition, information related to the error grade for each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the second error analysis unit 1024 may be stored in a designated space within the host 102.

[0046] The response operation unit 1025 can perform different error response operations for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 depending on the error strength for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 determined by the second error analysis unit 1024. In this case, the response operation unit 1025 can read out the error strength for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 determined by the second error analysis unit 1024 from a set space inside the host 102.

[0047] The host ECC 1026 can generate an error correction code (ECC) by performing an error correction encoding operation on data generated to be stored in the memory system 110. The host 102 can transmit data in units of code words, which includes an error correction code in data to be stored in the memory system 110, to the memory system 110. The memory system 110 can store the data in units of code words input from the host 102 in a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. The host ECC 1026 can check whether an error has occurred in data input from the memory system 110, and if an error has occurred in the input data, can perform an error correction decoding operation, i.e., an error recovery operation, to recover normal data before the error occurred. At this time, since the data transmitted from the host 102 to the memory system 110 is data in units of codewords, the data input from the memory system 110 to the host 102 may also be data in units of codewords. Therefore, the host ECC 1026 can perform an error recovery operation using an error correction code included in the codeword-based data input to the host 102. At this time, if the number of error bits occurs exceeds a correctable error bit limit value, the host ECC 1026 may fail the error recovery operation and may not be able to correct the bit in which the error occurred.Meanwhile, the host ECC 1026 may perform error correction using coded modulation such as, but not limited to, a Hamming code, a low density parity check (LDPC) code, a Bose, Chaudhri, Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a block coded modulation (BCM). Also, the host ECC 1026 may include a code, a circuit, a module, a system, or a device for error correction.

[0048] For reference, there may be a difference in the size of error correctable data between the host ECC 1026 in the host 102 and the memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508. For example, the size of data that can be corrected by the host ECC 1026 may be larger than the size of data that can be corrected by the memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8). In addition, in the above description, it has been described that both the host ECC 1026 and the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) can perform error correction operations, but this is merely one embodiment and is not limited to this. For example, there are many possible embodiments in which the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) only performs an operation to check whether an error has occurred, and the host ECC 1026 performs both an operation to check whether an error has occurred and an error correction operation.

[0049] FIG. 1B is a diagram shown for explaining the configuration of a data processing system according to the second embodiment of the present invention.

[0050] 1B, a data processing system according to a second embodiment of the present invention may include a host 102 and a memory system 110. Here, the memory system 110 may include a controller 130 and a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. And, the controller 130 may include an error collection unit 1301, a first error analysis unit 1303, a second error analysis unit 1304, a corresponding operation unit 1305, and a system ECC 1306.

[0051] Each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may have multiple memory banks BK<1:4>, memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8), and information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8.

[0052] For reference, the drawing shown in FIG. 1B assumes that each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is a DRAM, and the detailed configuration may be changed if the memory device 10 is another type of memory device. Specifically, each of the plurality of memory banks BK<1:4> may include a plurality of memory cells (CELL) connected in an array form to a plurality of word lines WL1, WL2, ..., WLX and a plurality of bit lines BL1, BL2, BL3, ..., BLY, and each of the plurality of memory cells may store at least one bit of data. That is, each of the plurality of memory banks BK<1:4> may be considered as a "cell array region" in which a plurality of memory cells are provided in an array form. Therefore, the expression "a plurality of memory banks" is assumed to be a DRAM, and may be replaced with the expression "a plurality of cell array regions" if the memory device 10 is another type of memory device. In summary, the internal configuration of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can be designed and modified depending on the characteristics of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, the purpose for which the memory system 110 is used, or the specifications of the memory system 110 required by the host 102, etc.

[0053] Furthermore, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110 can generate log information LOG_INFO for data from which an error has been recovered by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) when an error occurs during an access operation, e.g., a data read / write operation, and the error is recovered through the operation of the internal memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8). That is, each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may accumulate and store raw data related to an error in an access operation, which is corrected by memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8) during an access operation, in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8, to generate log information LOG_INFO. At this time, the raw data related to an error included in the log information LOG_INFO may mean all data that can be generated in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in relation to the occurrence of an error. That is, the raw data related to the errors included in the log information LOG_INFO may be data indicating the time, location, type, and number of errors. For example, it may be data indicating the number of bits of data in which an error occurred, the physical storage location of the data in which an error occurred, the absolute time when the error occurred, the range of the physical area in which the error occurred, and the type of error that occurred. And, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be storage spaces included in the form of registers in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.In addition, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be at least a partial space in at least one of a plurality of banks BK<1:4> provided in each of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0054] The controller 130 can collect raw data related to errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110 through the following operations.

[0055] In the first operation, as described above, during an access operation to each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, raw data related to an error of the access operation, which is corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8), may be accumulated and stored as log information LOG_INFO in the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8. Thus, the controller 130 may collect log information LOG_INFO from each of the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0056] In the second operation, the controller 130 may generate and collect, as error correction information ERR_CO_INFO, raw data related to an error in an access operation in which an error is corrected by the system ECC 1306 provided therein during an access operation, for example, a data read operation, to each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. In this case, in the case of an access operation in which an error is corrected by the system ECC 1306 provided in the controller 130, it may be assumed that the access operation is an access operation in which an error could not be corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) provided in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. At this time, the raw data related to the error included in the error correction information ERR_CO_INFO may mean all data that can be generated by the system ECC 1306 in relation to the occurrence of an error. That is, the raw data related to the error included in the error correction information ERR_CO_INFO may be data representing the time, location, type, and number of errors. For example, it may be data representing the number of bits of data in which an error has occurred, the physical storage location of data in which an error has occurred, the absolute time when the error has occurred, the range of the physical area in which the error has occurred, and the type of error that has occurred.

[0057] The controller 130 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to ascertain the number, type and form of errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Therefore, the controller 130 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO based on the number, type and form of errors to set different error strengths for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110. In addition, the controller 130 can perform different error handling operations for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error strength.

[0058] More specifically, the error collection unit 1301 included in the controller 130 may transmit a command (not shown) for collecting information to the memory system 110 at a set time point, and then, in response to the command for collecting information, may receive and collect log information LOG_INFO output from information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110. Also, the error collection unit 1301 may collect error correction information ERR_CO_INFO generated by the system ECC 1306 in real time or at set time points.

[0059] Here, the controller 130 may select and specify at least one of the following several time points as the set time point.

[0060] First, a point in time that is repeated at a specific time interval from the point in time when power is supplied to the memory system 110 can be designated as a set point in time.

[0061] Secondly, the number of errors occurring during an access operation to the memory system 110, i.e., an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, may be counted, and whenever the counted number exceeds a predetermined reference number, the time at which the counted number exceeds the predetermined reference number may be designated as a set time point. At this time, whenever a set time point is designated, the counted number may be initialized. For example, the counting of the number of errors may be performed by the system ECC 1306.

[0062] Third, an error recovery operation is performed to recover an error that occurs during an access operation to the memory system 110, i.e., an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and a time point at which the error recovery operation takes more than a specific time can be designated as the set time point. In this case, the time point at which the error recovery operation takes more than a specific time can mean that a relatively simple error recovery operation using a Hamming code has failed in the process of recovering the error that has occurred, and a relatively complicated error recovery operation using a Reed-Solomon code has been used. For example, the error recovery operation can be performed by the system ECC 1306.

[0063] The error collection unit 1301 may store the log information LOG_INFO and the error correction information ERR_CO_INFO in a set space within the controller 130. At this time, as shown in the drawing, the inside of the error collection unit 1301 may be a separate storage area. Also, although not directly shown in the drawing, the set space within the controller 130 may be a specific storage space of a system memory included within the controller 130 and used as an operating memory of the memory system 110.

[0064] The first error analysis unit 1303 analyzes the log information LOG_INFO and the error correction information ERR_CO_INFO collected by the error collection unit 1301 to check the number and type of errors occurring in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and may determine an error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 according to the number and type of errors checked. At this time, information related to the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1303 may be stored in a set space inside the controller 130.

[0065] The second error analysis unit 1304 can select some of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1303. In addition, the second error analysis unit 1304 may determine the error strength by checking the type and number of errors through additional analysis of the log information LOG_INFO and the error correction information ERR_CO_INFO for some selected memory devices among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and may determine the error strength for the remaining memory devices excluding the certain memory devices so as to correspond to the error grade determined by the first error analysis unit 1303. In this case, the second error analysis unit 1304 may read the error strength for each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1303 from a set space inside the controller 130. In addition, information related to the error grade for each of the memory devices 1501 , 1502 , 1503 , 1504 , 1505 , 1506 , 1507 , and 1508 determined by the second error analysis unit 1304 may be stored in a designated space within the controller 130 .

[0066] The response operation unit 1305 can perform different error response operations for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 depending on the error strength for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 determined by the second error analysis unit 1304. In this case, the response operation unit 1305 can read out the error strength for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 determined by the second error analysis unit 1304 from a set space inside the controller 130.

[0067] The system ECC 1306 may generate an error correction code (ECC) by performing an error correction encoding operation on data to be stored in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. The controller 130 may transmit data in codeword units, in which the error correction code is included in the data to be stored in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, to each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can store data in units of code words input from the controller 130. In addition, the system ECC 1306 can check whether an error occurs in data read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and if an error occurs in the read data, can perform error correction decoding, i.e., an error recovery operation, to recover normal data before the error occurred. At this time, since the data stored in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is data in units of codewords, the data read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may also be data in units of codewords. Therefore, the system ECC 1306 may perform an error recovery operation using an error correction code included in the codeword-based data read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. At this time, if the number of error bits occurs exceeds a correctable error bit limit value, the system ECC 1306 may fail in the error recovery operation and may not be able to correct the erroneous bit.Meanwhile, the system ECC 1306 may perform error correction using coded modulation such as, but not limited to, a Hamming code, a low density parity check (LDPC) code, a Bose, Chaudhri, Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a block coded modulation (BCM). Also, the system ECC 1306 may include any code, circuit, module, system, or device for error correction.

[0068] For reference, there may be a difference in the size of error correctable data between the system ECC 1306 in the controller 130 and the memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508. For example, the size of data that can be corrected by the system ECC 1306 may be larger than the size of data that can be corrected by the memory ECCs (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8). In the above description, it has been described that both the system ECC 1306 and the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) can perform error correction operations, but this is merely one embodiment and is not limited thereto. For example, there are many possible embodiments in which the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) only performs an operation to check whether an error has occurred, and the system ECC 1306 performs both an operation to check whether an error has occurred and an error correction operation.

[0069] FIG. 1C is a diagram shown for explaining the configuration of a memory system according to a third embodiment of the present invention.

[0070] 1C, the memory system 110 according to the third embodiment of the present invention may include a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may include a plurality of memory banks BK<1:4>, an error collection unit 1511, an error analysis unit 1513, a corresponding operation unit 1515, a memory ECC 1516, and information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8.

[0071] For reference, the drawing shown in FIG. 1C assumes that each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is a DRAM, and the detailed configuration may be changed if the memory device 10 is another type of memory device. Specifically, each of the plurality of memory banks BK<1:4> may include a plurality of memory cells (CELL) connected in an array form to a plurality of word lines WL1, WL2, ..., WLX and a plurality of bit lines BL1, BL2, BL3, ..., BLY, and each of the plurality of memory cells may store at least one bit of data. That is, each of the plurality of memory banks BK<1:4> may be considered as a "cell array region" in which a plurality of memory cells are provided in an array form. Therefore, the expression "a plurality of memory banks" is assumed to be a DRAM, and may be replaced with the expression "a plurality of cell array regions" if the memory device 10 is another type of memory device. In summary, the internal configuration of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can be designed and modified depending on the characteristics of each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, the purpose for which the memory system 110 is used, or the specifications of the memory system 110, etc.

[0072] Furthermore, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 included in the memory system 110 can generate log information LOG_INFO for data from which the error has been recovered by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) when an error occurs during an access operation, for example, a data read / write operation for each of the multiple memory banks BK<1:4>, and the error is recovered through the operation of the internal memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8). That is, each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may accumulate and store raw data related to an error in an access operation, which is corrected by memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, and ECC8) during an access operation, in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8, to generate log information LOG_INFO. At this time, the raw data related to an error included in the log information LOG_INFO may mean all data that can be generated in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in relation to the occurrence of an error. That is, the raw data related to the errors included in the log information LOG_INFO may be data indicating the time, location, type, and number of errors. For example, it may be data indicating the number of bits of data in which an error occurred, the physical storage location of the data in which an error occurred, the absolute time when the error occurred, the range of the physical area in which the error occurred, and the type of error that occurred. And, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be storage spaces included in the form of registers in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.In addition, the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 may be at least a partial space in at least one of a plurality of banks BK<1:4> provided in each of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0073] Specifically, the error collection unit 1511 can collect log information LOG_INFO generated in the memory ECC 1516 and stored in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8 in real time or at set time points.

[0074] Here, the error collection unit 1511 can select and specify at least one of the following several time points as the set time point.

[0075] First, a point in time that is repeated at a specific time interval from the point in time when power is supplied to the memory system 110 can be designated as a set point in time.

[0076] Secondly, the number of errors occurring during an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may be counted, and whenever the counted number exceeds a predetermined reference number, the time at which the counted number exceeds the predetermined reference number may be designated as a set time point. At this time, whenever the set time point is designated, the counted number may be initialized. For example, the counting of the number of errors may be performed by the memory ECC 1516.

[0077] Third, an error recovery operation is performed to recover an error that occurs during an access operation to the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and a time point at which the error recovery operation takes more than a specific time can be designated as the set time point. In this case, the time point at which the error recovery operation takes more than a specific time can mean that a relatively simple error recovery operation using a Hamming code has failed in the process of recovering the error that occurred, and a relatively complicated error recovery operation using a Reed-Solomon code has been used. For example, the error recovery operation can be performed by the memory ECC 1516.

[0078] The error analysis unit 1513 can analyze the log information LOG_INFO collected by the error collection unit 1511 to ascertain the number, type and form of errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507 and 1508. In particular, the error analysis unit 1513 can analyze the log information LOG_INFO collected by the error collection unit 1511 to ascertain the number and type of errors that have occurred in each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507 and 1508, and determine an error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507 and 1508 according to the number and type of errors that have been confirmed. At this time, information related to the error grade for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the error analysis unit 1513 can be stored in information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8.

[0079] The response operation unit 1515 can perform different error response operations for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the error analysis unit 1513. In this case, the response operation unit 1515 can read the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the error analysis unit 1513 from the information storage areas PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PA8.

[0080] The memory ECC 1516 can generate an error correction code (ECC) by performing an error correction encoding operation on data to be stored in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. The memory ECC 1516 can store data in codeword units, in which the error correction code is included in the data to be stored in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, in the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Also, the memory ECC 1516 can check whether an error occurs in data read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and if an error occurs in the read data, can perform an error correction decoding, i.e., an error recovery operation, to recover normal data before the error occurred. At this time, since the data stored in each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is data in units of codewords, the data read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can also be data in units of codewords. Therefore, the memory ECC 1516 can perform an error recovery operation using an error correction code included in the data in units of code words read from each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. At this time, if the number of error bits generated exceeds a correctable error bit limit value, the memory ECC 1516 may fail in the error recovery operation and may not be able to correct the bit in which the error occurred.Meanwhile, the memory ECC 1516 may perform error correction using coded modulation such as, but not limited to, a parity code, a Hamming code, a low density parity check (LDPC) code, a Bose, Chaudhri, Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a block coded modulation (BCM). Also, the memory ECC 1516 may include a code, a circuit, a module, a system, or a device for error correction.

[0081] 2 to 5B are diagrams shown for explaining the log information analysis operation of the data processing system according to the embodiment of the present invention.

[0082] First, as shown in FIGS. 1A and 2, it is possible to know how the error grade for each of a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is determined by analyzing the log information LOG_INFO and the error correction information ERR_CO_INFO.

[0083] Specifically, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can generate log information LOG_INFO for data from which the error has been recovered by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) when an error occurs during an access operation, for example, a data read / write operation, and the error is recovered through the operation of the internal memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8).

[0084] Furthermore, during an access operation, such as a data read operation, to each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, if an error is corrected through the operation of the internal host ECC 1026, the host 102 can generate error correction information ERR_CO_INFO for the data in which the error has been corrected by the host ECC 1026.

[0085] The host 102 may collect and analyze the log information LOG_INFO and the error correction information ERR_CO_INFO, i.e., may determine the error grade and error intensity for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0086] For reference, although not specifically illustrated in the drawings, the memory system 110 may further include a host interface (not shown) for transmitting signals between the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 and the host 102. That is, each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 may output internally generated log information LOG_INFO to the host 102 via the host interface.

[0087] Similarly, although not specifically illustrated in the drawings, the host 102 may further include a memory interface (not shown) for transmitting signals between the memory system 110 and other components 1021, 1023, 1024, 1025, and 1026 within the host 102. That is, the host 102 may receive log information LOG_INFO output from a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 via the memory system 110 via the memory interface.

[0088] Meanwhile, the first error analysis unit 1023 provided in the host 102 analyzes the log information LOG_INFO and error correction information ERR_CO_INFO collected by the error collection unit 1021 to identify memory devices among the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in which the number of errors occurring is equal to or greater than a first reference number, and classifies the corresponding memory device as a "first memory device" (S10).

[0089] For example, it may be assumed that the number of errors corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) or the host ECC 1026 during an access to the first memory device 1501 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 is 12, and the number of errors corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) or the host ECC 1026 during an access to each of the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, 1508 is less than 10. The first reference number may be assumed to be 10. In this case, the first error analyzer 1023 may classify the first memory device 1501 as the "first memory device" and may not determine an error class for each of the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0090] Specifically, the first error analysis unit 1023 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to check the type of error that occurred in the memory device classified as the "first memory device" (YES in S10). At this time, the first error analysis unit 1023 can classify the type of error that occurred in the memory device classified as the "first memory device" into an error that occurred in a word line unit (S20), an error that occurred in a single bit unit (S30), an error that occurred in a bit line unit (S40), and other errors (S50).

[0091] Here, the error occurring in the word line unit (S20) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same word line in the same bank. And the error occurring in the single bit unit (S30) may mean a case where one or less errors occur in the same word and the same bit line. And the error occurring in the bit line unit (S40) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same bit line. And the other error (S50) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" do not have a specific distribution, for example, it is not determined that they occurred in the word line unit, the single bit unit, and the bit line unit.

[0092] Then, if the first error analyzer 1023 checks the type of error that has occurred in the memory device classified as the "first memory device" and finds that the error occurred in units of a word line (S20), it can count the number of errors that have occurred in the same word line in the memory device classified as the "first memory device" (S60). If the counting result shows that the number of errors is equal to or greater than a second reference number (YES in S70), it can determine the memory device as having a first error class and classify it as a "second memory device" (S90). If the counting result shows that the number of errors is less than the second reference number (NO in S70), it can determine the memory device as having a second error class and classify it as a "third memory device" (S80).

[0093] Then, when the first error analysis unit 1023 checks the type of error that has occurred in the memory device 1501 classified as the "first memory device," if the memory device only has errors that have occurred on a single bit basis (YES in S30), errors that have occurred on a bit line basis (YES in S40), and other errors (YES in S50), the memory device can be determined to have a second error class and classified as a "third memory device" (S80).

[0094] To summarize by way of example, it may be assumed that errors occurring in a first memory device 1501 classified as a "first memory device" are errors occurring in units of word lines, and the number of errors occurring in the same word line is equal to or greater than a second reference number. Therefore, the first error analyzer 1023 may determine that the first memory device 1501 classified as the "first memory device" has a first error class and classify it as a "second memory device."

[0095] As shown in Figures 1A, 2 and 3, the second error analysis unit 1024 included in the host 102 can select some of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1023. In addition, the second error analysis unit 1024 determines the error severity by checking the type and number of errors through additional analysis of the log information LOG_INFO and error correction information ERR_CO_INFO for some selected memory devices among the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and can determine the error severity for the remaining memory devices excluding some of the memory devices so as to correspond to the error grade determined by the first error analysis unit 1023.

[0096] Specifically, the first error analysis unit 1023 classified the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 into memory devices whose error grade was not determined, a “second memory device” whose error grade was determined to be the first error grade, and a “third memory device” whose error grade was determined to be the second error grade.

[0097] The second error analysis unit 1024 can then check whether the error grade determined by the first error analysis unit 1023 is the first error grade (K10).

[0098] As a result of the check of the K10 operation, in the case of a memory device that has not been determined to have the first error grade by the first error analysis unit 1023 (NO in K10), i.e., a memory device for which an error grade has not been determined and a "third memory device" that has been determined to have the second error grade, the second error analysis unit 1024 can add a second error strength to the memory device and classify it as a "fifth memory device" (K70). At this time, for the memory device that has been classified as the "fifth memory device" with the second error strength added, the response operation unit 1025 can perform a second error response operation (K80).

[0099] As a result of the check of the K10 operation, in the case of a memory device determined to have a first error grade by the first error analyzer 1023 (YES in K10), i.e., in the case of the "second memory device" determined to have the first error grade, the second error analyzer 1024 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to check the type and number of errors and then determine the error severity. Specifically, the second error analyzer 1024 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the "second memory device" determined to have the first error grade to check whether the type of error occurring in the "second memory device" spans a third reference number or more of codeword units (K30).

[0100] Here, in order to explain what is meant by the operation of checking for errors "across" codeword units, the following will be described with reference to FIGS. 4 to 5B.

[0101] First, as shown in FIG. 4, the basic meaning of a codeword unit may be a unit representing the amount of data that is the basis of an operation when the host ECC 1026 in the host 102 performs an error correction operation. For example, when the host 102 generates 512-bit data to be stored in the memory system 110 (401), the host ECC 1026 may perform an error correction encoding operation (402) on the 512-bit data to generate a 64-bit error correction code (403). At this time, the host 102 may manage (404) a total of 572 bits of data, which is a combination of the 512-bit data and the 64-bit error correction code generated internally, by dividing the data into two codeword units. That is, one codeword unit may include 288 bits of data, which is a combination of the 256-bit data and the 32-bit error correction code generated internally in the host 102. The host 102 may output (405) the 572-bit data to the memory system 110. For reference, the drawing illustrates an example of managing 572-bit data in units of two codewords, but in reality, it is possible to manage the data in units of fewer or more codewords.

[0102] 4, unlike the embodiment of FIG. 1, it is assumed that the memory system 110 includes a total of 18 memory devices (18 devices). In this case, the memory system 110 can distribute and store 572-bit data (405) input from the host 102 to the 18 memory devices (18 devices). Thus, 32-bit data can be stored in each of the 18 memory devices (18 devices). Also, the memory system 110 can store data corresponding to two codeword units in each of the 18 memory devices (18 devices) by dividing the 572 bits in the host 102 into two codeword units and managing them. Thus, 16-bit data corresponding to a first codeword unit (Codeword0) and 16-bit data corresponding to a second codeword unit (Codeword1) can be stored in each of the 18 memory devices (18 devices). That is, the memory system 110 can distribute and store 288 bits of data corresponding to the first codeword unit (Codeword 0) and 288 bits of data corresponding to the second codeword unit (Codeword 1) across 18 memory devices.

[0103] When storing 572-bit data input from the host 102 in each of the 18 memory devices, the memory system 110 may recognize that the 572-bit data is continuous data and set a burst length (BL) to store the data. At this time, it may be assumed that each of the 18 memory devices (18 devices) has four data input / output terminals (×4). Therefore, the memory system 110 may designate 288-bit data corresponding to the first codeword unit (Codeword0) as upper burst length 4 (BL4) in the 18 memory devices (18 devices) and store the data in 16 bits, and designate 288-bit data corresponding to the second codeword unit (Codeword1) as lower burst length 4 (BL4) in the 18 memory devices (18 devices) and store the data in 16 bits.

[0104] 4, the host 102 can output data managed in units of at least one codeword to the memory system 110. In addition, the memory system 110 can distribute and store data input from the host 102 in a plurality of memory devices in a format corresponding to the codeword unit.

[0105] As shown in Fig. 5A, as described in Fig. 4, 32-bit data in one memory device is divided into 16-bit data corresponding to each of two codeword units (Codeword0, Codeword1) and then read out to four data I / O terminals (x4, DQ<0:3>). At this time, it can be seen from the drawing that an error bit occurs in the data read out through a specific data I / O terminal, for example, the first and third data I / O terminals DQ<1,3>. That is, although the cause of the error is not shown in the drawing, it can be seen that the error bit spans two codeword units (Codeword0, Codeword1) due to the occurrence of an error in the data read out to the specific data I / O terminal.

[0106] As shown in FIG 5B, as in FIG 5A, 32-bit data in one memory device is divided into 16-bit data corresponding to each of two codeword units (Codeword0, Codeword1) and then read out to four data I / O terminals (×4, DQ<0:3>). At this time, it can be seen from the drawing that an error bit occurs in the read data included in the first codeword unit (Codeword0), but no error occurs in the read data included in the second codeword unit (Codeword1). That is, although the cause of the error is not shown in the drawing, it can be seen that the error bit is only included in one codeword unit (Codeword0) and does not span across two codeword units (Codeword0, Codeword1).

[0107] Furthermore, as shown in FIGS. 1A, 2 and 3, the operation (K30) of additionally analyzing the log information LOG_INFO for the “second memory device” determined to have a first error class by the second error analysis unit 1024 to determine whether the type of error occurring in the “second memory device” spans more than a third reference number of codeword units may be an operation of determining whether the type of error occurring in the “second memory device” spans two codeword units as illustrated in FIG. 5A, or is included in only one codeword unit as illustrated in FIG. 5B, assuming that the third reference number is two.

[0108] As a result of checking the K30 operation, if the type of error occurring in the "second memory device" is a type that spans a third reference number or more of codeword units (YES in K30), the second error analyzer 1024 can check whether the total number of errors that span the third reference number or more of codewords is a fourth reference number or more (K40). For example, assuming that the fourth reference number is 8, as illustrated in FIG. 5A, the total number of error bits that span two codeword units (Codeword0, Codeword1) is 16, so the fourth reference number can be 8.

[0109] As a result of checking the K40 operation, if the type of error occurring in the "second memory device" is a type that spans a third reference number or more of codeword units (YES in K30) and the total number of errors spanning the third reference number or more of codewords is equal to or greater than a fourth reference number (YES in K40), the second error analysis unit 1024 can add a first error strength to the corresponding "second memory device" and classify it as a "fourth memory device" (K50). At this time, the response operation unit 1025 can perform a first error response operation on the memory device that is classified as the "fourth memory device" by adding the first error strength (K60).

[0110] As a result of the check in K30, if the type of error occurring in the "second memory device" is a type that is included only in codeword units less than the third reference number (NO in K30), the second error analysis unit 1024 can add a second error strength to the corresponding "second memory device" and classify it as a "fifth memory device" (K70). At this time, the response operation unit 1025 can perform a second error response operation on the memory device that is classified as the "fifth memory device" with the second error strength added (K80).

[0111] The operation of the second error analyzer 1024 will be described by way of example as follows.

[0112] First, as explained using an example in FIG. 2, the first error analysis unit 1023 determines the first memory device 1501 among a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 as a first error class and classifies it as a "second memory device", and does not determine error classes for the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and assumes that there are no memory devices determined to be the second error class and classified as a "third memory device".

[0113] At this time, in the case of a memory device that has not been determined to have the first error grade by the first error analyzer 1023 (NO in K10), i.e., a memory device whose error grade has not been determined and a "third memory device" whose error grade has been determined to have the second error grade, the second error analyzer 1024 may add a second error strength to the memory device and classify it as a "fifth memory device" (K70). Therefore, the second error analyzer 1024 may add a second error strength to the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 whose error grades have not been determined, and classify them as a "fifth memory device" (K70).

[0114] In addition, in the case of a memory device determined to have the first error grade by the first error analysis unit 1023 (YES in K10), i.e., in the case of a "second memory device" determined to have the first error grade, the second error analysis unit 1024 can additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to confirm the type and number of errors, and then determine the error severity. Therefore, the second error analysis unit 1024 can additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the first memory device 1501 determined to have the first error grade and classified as the "second memory device", to confirm the type and number of errors, and then determine the error severity.

[0115] Specifically, the second error analysis unit 1024 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the first memory device 1501 to determine whether the type of error spans a third reference number or more of codeword units (K30). As a result, it may be assumed that the type of error occurring in the first memory device 1501 spans a third reference number or more of codeword units (YES in K30). Thus, the second error analysis unit 1024 may determine whether the total number of error bits included in the errors spanning a third reference number or more of codeword units in the first memory device 1501 is a fourth reference number or more (K40). As a result of the determination, it may be assumed that the number of errors spanning a third reference number or more of codeword units in the first memory device 1501 is a fourth reference number or more (YES in K40). Therefore, the second error analyzer 1023 may assign a first error strength to the first memory device 1501 and classify it as a "fourth memory device" (K60).

[0116] Meanwhile, the response operation unit 1025 included in the host 102 can perform different error response operations for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error strength for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the second error analysis unit 1024.

[0117] Specifically, the response operation unit 1025 can perform a first error response operation on a memory device classified as a "fourth memory device" by adding a first error strength in the second error analysis unit 1024 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Also, the response operation unit 1025 can perform a second error response operation on a memory device classified as a "fifth memory device" by adding a second error strength in the second error analysis unit 1024 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0118] Here, the first error handling operation may include at least one of the following operations:

[0119] The first operation is an operation of selecting an area where an error occurs in a memory device classified as a "fourth memory device" and blocking access. For example, the corresponding operation unit 1025 can select a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device" and block access. In this case, the corresponding operation unit 1025 can perform an access blocking operation after copying data stored in the specific block, the specific word line, or the specific bit line to be blocked and storing the data in an "other area." In this case, the "other area" can be another normal block, another normal word line, or another normal bit line in the first memory device 1501. In addition, the "other area" can be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason that the operation of storing data stored in a particular block, word line, or bit line that is the target of access blocking in “another area” can be performed normally is because the particular block, word line, or bit line was selected as the target of the access blocking operation in anticipation of a high probability of an unrecoverable error occurring at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0120] The second operation is an operation of selecting and repairing an area where an error occurs in a memory device classified as a "fourth memory device". For example, the corresponding operation unit 1025 may repair a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device" with another normal redundancy block, a redundancy word line, or a redundancy bit line. At this time, the host 102 may suspend access to the first memory device 1501 until the repair operation is completed in the first memory device 1501 to be repaired. Then, the first memory device 1501 to be repaired may copy data stored in the specific block, the specific word line, or the specific bit line to be repaired to an internal information storage area PA1 and then perform a repair operation. After the repair operation is completed, the first memory device 1501 may restore the data copied to the information storage area PA1 to the redundancy block, the redundancy word line, or the redundancy bit line that has been repaired. For reference, the reason why the operation of copying data stored in a specific block, word line, or bit line that is the target of repair to the internal information storage area PA1 can be performed normally is because the specific block, word line, or bit line was selected as the target of repair based on the prediction that there is a high possibility that an unrecoverable error will occur at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0121] The third operation is an operation of selecting and disabling an area where an error occurs in a memory device classified as a "fourth memory device". For example, the corresponding operation unit 1025 can disable a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device". At this time, the first memory device 1501 to be disabled can copy data stored in the specific block, the specific word line, or the specific bit line to be disabled and store it in an "other area", and can notify the host 102 that the data has been moved to the "other area". At this time, the "other area" can be another normal block, another normal word line, or another normal bit line of the first memory device 1501. Also, the "other area" can be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason why the operation of storing data stored in a particular block, word line, or bit line to be disabled in an internal "other area" can be performed normally is because the particular block, word line, or bit line was selected as a target for disabling based on the prediction that there is a high possibility that an unrecoverable error will occur at a future point in time, and at the present time, it is in a state where it is operating normally or where only recoverable errors will occur.

[0122] The second error response operation may include an error recovery operation using an error correction code on the codeword-unit data in which an error occurred via the host ECC 1026 when an error occurs during an access operation to a memory device classified as the "fifth memory device."

[0123] Also, as shown in FIG. 1B and FIG. 2, by analyzing the log information LOG_INFO and the error correction information ERR_CO_INFO, it can be known how the error grade for each of the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is determined.

[0124] Specifically, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can generate log information LOG_INFO for data from which an error has been recovered by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) when an error occurs during an access operation, e.g., a data read / write operation, and the error is recovered through the operation of the internal memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8).

[0125] Furthermore, during an access operation, such as a data read operation, to each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, if an error is corrected by the internal system ECC 1306, the controller 130 can generate error correction information ERR_CO_INFO for the data whose error has been corrected by the system ECC 1306.

[0126] The controller 130 may collect and analyze the log information LOG_INFO and the error correction information ERR_CO_INFO, that is, the controller 130 may determine an error grade and an error intensity for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0127] Meanwhile, the first error analysis unit 1303 provided in the controller 130 analyzes the log information LOG_INFO and error correction information ERR_CO_INFO collected by the error collection unit 1301 to identify memory devices among the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in which the number of errors occurring is equal to or greater than a first reference number, and classifies the corresponding memory device as a "first memory device" (S10).

[0128] For example, it may be assumed that the number of errors corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) or the system ECC 1306 during an access to the first memory device 1501 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508 is 12, and the number of errors corrected by the memory ECC (ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8) or the system ECC 1306 during an access to each of the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, 1508 is less than 10. The first reference number may be assumed to be 10. In this case, the first error analyzer 1303 may classify the first memory device 1501 as the “first memory device” and may not determine an error class for each of the remaining memory devices 1502 , 1503 , 1504 , 1505 , 1506 , 1507 , and 1508 .

[0129] Specifically, the first error analysis unit 1303 can analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to check the type of error that occurred in the memory device classified as the "first memory device" (YES in S10). At this time, the first error analysis unit 1303 can classify the type of error that occurred in the memory device classified as the "first memory device" into an error that occurred in a word line unit (S20), an error that occurred in a single bit unit (S30), an error that occurred in a bit line unit (S40), and other errors (S50).

[0130] Here, the error occurring in the word line unit (S20) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same word line in the same bank. And the error occurring in the single bit unit (S30) may mean a case where one or less errors occur in the same word and the same bit line. And the error occurring in the bit line unit (S40) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same bit line. And the other error (S50) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" do not have a specific distribution, for example, it is not determined that they occurred in the word line unit, the single bit unit, and the bit line unit.

[0131] Then, if the first error analyzer 1303 checks the type of error that has occurred in the memory device classified as the "first memory device" and finds that the error occurred in units of a word line (S20), it can count the number of errors that have occurred in the same word line in the memory device classified as the "first memory device" (S60). If the counting result shows that the number of errors is equal to or greater than a second reference number (YES in S70), it can determine the memory device as having a first error class and classify it as a "second memory device" (S90). If the counting result shows that the number of errors is less than the second reference number (NO in S70), it can determine the memory device as having a second error class and classify it as a "third memory device" (S80).

[0132] Then, if the first error analysis unit 1303 checks the type of error that has occurred in the memory device classified as the "first memory device" and finds that the memory device only has errors that have occurred on a single bit basis (YES in S30), errors that have occurred on a bit line basis (YES in S40), and other errors (YES in S50), the memory device can be determined to have a second error class and classified as a "third memory device" (S80).

[0133] To summarize by way of example, it may be assumed that errors occurring in the first memory device 1501 classified as the "first memory device" are errors occurring in units of word lines, and the number of errors occurring in the same word line is equal to or greater than a second reference number. Therefore, the first error analyzer 1303 may determine that the first memory device 1501 classified as the "first memory device" has a first error class and classify it as a "second memory device."

[0134] As shown in Figures 1B, 2 and 3, the second error analysis unit 1304 included in the controller 130 can select some of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the first error analysis unit 1303. In addition, the second error analysis unit 1304 determines the error severity by checking the type and number of errors through additional analysis of the log information LOG_INFO and error correction information ERR_CO_INFO for some selected memory devices among the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and can determine the error severity for the remaining memory devices excluding some of the memory devices so as to correspond to the error grade determined by the first error analysis unit 1303.

[0135] Specifically, the first error analysis unit 1303 classified the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 into memory devices whose error grade was not determined, a “second memory device” whose error grade was determined to be the first error grade, and a “third memory device” whose error grade was determined to be the second error grade.

[0136] The second error analysis unit 1304 can then check whether the error grade determined by the first error analysis unit 1303 is the first error grade (K10).

[0137] As a result of the check of the K10 operation, in the case of a memory device that has not been determined to have the first error grade by the first error analysis unit 1303 (NO in K10), i.e., a memory device for which an error grade has not been determined and a "third memory device" that has been determined to have the second error grade, the second error analysis unit 1304 can add a second error strength to the memory device and classify it as a "fifth memory device" (K70). At this time, the response operation unit 1305 can perform a second error response operation on the memory device that has been classified as the "fifth memory device" with the second error strength added (K80).

[0138] As a result of the check of the K10 operation, in the case of the memory device determined to have the first error grade by the first error analyzer 1303 (YES in K10), i.e., in the case of the "second memory device" determined to have the first error grade, the second error analyzer 1304 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to check the type and number of errors and then determine the error severity. Specifically, the second error analyzer 1304 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the "second memory device" determined to have the first error grade to check whether the type of error occurring in the "second memory device" spans a third reference number or more of codeword units (K30).

[0139] Here, the meaning of the operation of checking for errors "across" codeword units has been described above in connection with Figures 1A and 4 to 5B, and therefore a more detailed description thereof will be omitted here.

[0140] The operation (K30) of further analyzing the log information LOG_INFO for the “second memory device” determined to have the first error grade by the second error analysis unit 1304 to determine whether the type of error occurring in the “second memory device” spans more than a third reference number of codeword units may be an operation of determining whether the type of error occurring in the “second memory device” spans two codeword units as illustrated in FIG. 5A, or is included in only one codeword unit as illustrated in FIG. 5B, assuming that the third reference number is two.

[0141] As a result of checking the K30 operation, if the type of error occurring in the "second memory device" is a type that spans a third reference number or more of codeword units (YES in K30), the second error analyzer 1304 can check whether the total number of errors spanning the third reference number or more of codewords is equal to or greater than a fourth reference number (K40). For example, assuming that the fourth reference number is 8, as illustrated in FIG. 5A, the total number of error bits spanning two codeword units (Codeword0, Codeword1) is 16, which may be equal to or greater than the fourth reference number of 8.

[0142] As a result of checking the K40 operation, if the type of error occurring in the "second memory device" is a type that spans a third reference number or more of codeword units (YES in K30) and the total number of errors spanning the third reference number or more of codewords is equal to or greater than a fourth reference number (YES in K40), the second error analysis unit 1304 can add a first error strength to the corresponding "second memory device" and classify it as a "fourth memory device" (K50). At this time, the response operation unit 1305 can perform a first error response operation on the memory device that is classified as the "fourth memory device" by adding the first error strength (K60).

[0143] As a result of checking the K30 operation, if the type of error occurring in the "second memory device" is a type that is included only in codeword units less than the third reference number (NO in K30), the second error analysis unit 1304 can add a second error strength to the corresponding "second memory device" and classify it as a "fifth memory device" (K70). At this time, the response operation unit 1305 can perform a second error response operation on the memory device that is classified as the "fifth memory device" with the second error strength added (K80).

[0144] The operation of the second error analysis unit 1304 will be described with an example as follows.

[0145] First, as explained using an example in FIG. 2, the first error analysis unit 1303 determines the first memory device 1501 among a plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 as a first error class and classifies it as a "second memory device", and does not determine error classes for the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508, and assumes that there are no memory devices determined to be the second error class and classified as a "third memory device".

[0146] At this time, in the case of a memory device that has not been determined to have the first error grade by the first error analyzer 1303 (NO in K10), i.e., a memory device whose error grade has not been determined and a "third memory device" whose error grade has been determined to have the second error grade, the second error analyzer 1304 may add a second error strength to the memory device and classify it as a "fifth memory device" (K70). Therefore, the second error analyzer 1304 may add a second error strength to the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 whose error grades have not been determined, and classify them as a "fifth memory device" (K70).

[0147] In addition, in the case of a memory device determined to have the first error grade by the first error analysis unit 1303 (YES in K10), i.e., in the case of a "second memory device" determined to have the first error grade, the second error analysis unit 1304 can additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO to confirm the type and number of errors, and then determine the error severity. Therefore, the second error analysis unit 1304 can additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the first memory device 1501 determined to have the first error grade and classified as the "second memory device", to confirm the type and number of errors, and then determine the error severity.

[0148] Specifically, the second error analysis unit 1304 may additionally analyze the log information LOG_INFO and the error correction information ERR_CO_INFO for the first memory device 1501 to determine whether the type of error spans a third reference number or more of codeword units (K30). As a result, it may be assumed that the type of error occurring in the first memory device 1501 spans a third reference number or more of codeword units (YES in K30). Thus, the second error analysis unit 1304 may determine whether the total number of error bits included in the errors spanning a third reference number or more of codeword units in the first memory device 1501 is a fourth reference number or more (K40). As a result of the determination, it may be assumed that the number of errors spanning a third reference number or more of codeword units in the first memory device 1501 is a fourth reference number or more (YES in K40). Therefore, the second error analyzer 1303 may assign a first error strength to the first memory device 1501 and classify it as a "fourth memory device" (K60).

[0149] Meanwhile, the response operation unit 1305 included in the controller 130 can perform different error response operations for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error strength for each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the second error analysis unit 1304.

[0150] Specifically, the response operation unit 1305 can perform a first error response operation on a memory device classified as a "fourth memory device" by adding a first error strength in the second error analysis unit 1304 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508. Also, the response operation unit 1305 can perform a second error response operation on a memory device classified as a "fifth memory device" by adding a second error strength in the second error analysis unit 1304 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0151] Here, the first error handling operation may include at least one of the following operations:

[0152] The first operation is an operation of selecting an area where an error occurs in a memory device classified as a "fourth memory device" and blocking access. For example, the corresponding operation unit 1305 may select a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device" and block access. In this case, the corresponding operation unit 1305 may perform an access blocking operation after copying data stored in the specific block, the specific word line, or the specific bit line to be blocked and storing the data in an "other area." In this case, the "other area" may be another normal block, another normal word line, or another normal bit line in the first memory device 1501. In addition, the "other area" may be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason that the operation of storing data stored in a particular block, word line, or bit line that is the target of access blocking in “another area” can be performed normally is because the particular block, word line, or bit line was selected as the target of the access blocking operation in anticipation of a high probability of an unrecoverable error occurring at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0153] The second operation is an operation of selecting and repairing an area where an error occurs in a memory device classified as a "fourth memory device". For example, the corresponding operation unit 1305 may repair a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device" with another normal redundancy block, a specific word line, or a specific bit line. In this case, the controller 130 may suspend access until the repair operation is completed in the first memory device 1501 to be repaired. Then, the first memory device 1501 to be repaired may perform a repair operation after copying data stored in the specific block, the specific word line, or the specific bit line to be repaired to an internal information storage area PA1. After the repair operation is completed, the first memory device 1501 may restore the data copied in the information storage area PA1 to the redundancy block, the redundancy word line, or the redundancy bit line that has been repaired. For reference, the reason why the operation of copying data stored in a specific block, word line, or bit line that is the target of repair to the internal information storage area PA1 can be performed normally is because the specific block, word line, or bit line was selected as the target of repair based on the prediction that there is a high possibility that an unrecoverable error will occur at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0154] The third operation is an operation of selecting and disabling an area where an error occurs in a memory device classified as a "fourth memory device". For example, the corresponding operation unit 1305 can disable a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "fourth memory device". At this time, the first memory device 1501 to be disabled can copy data stored in the specific block, the specific word line, or the specific bit line to be disabled and store it in an "other area", and can notify the controller 130 that the data has been moved to the "other area". At this time, the "other area" can be another normal block, another normal word line, or another normal bit line of the first memory device 1501. Also, the "other area" can be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason why the operation of storing data stored in a particular block, word line, or bit line to be disabled in an internal "other area" can be performed normally is because the particular block, word line, or bit line was selected as a target for disabling based on the prediction that there is a high possibility that an unrecoverable error will occur at a future point in time, and at the present time, it is in a state where it is operating normally or where only recoverable errors will occur.

[0155] The second error response operation may include an error recovery operation using an error correction code on the codeword unit data in which an error occurred via the system ECC 1306 when an error occurs during an access operation to a memory device classified as the "fifth memory device."

[0156] Also, as shown in FIGS. 1C and 2, by analyzing the log information LOG_INFO, it is possible to know how the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is determined.

[0157] Specifically, each of the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 can generate log information LOG_INFO for data from which an error has been recovered by the memory ECC 1516 when an error occurs during an access operation, e.g., a data read / write operation, and the error is recovered through the operation of the memory ECC 1516 provided therein.

[0158] The error collection unit 1511 and the error analysis unit 1513 may collect and analyze the log information LOG_INFO. That is, the error collection unit 1511 and the error analysis unit 1513 may determine an error level for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0159] Specifically, the error analysis unit 1513 analyzes the log information LOG_INFO collected by the error collection unit 1511 to identify memory devices among the multiple memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 in which the number of errors occurring is equal to or greater than a first reference number, and classifies the corresponding memory device as a "first memory device" (S10).

[0160] For example, it may be assumed that the number of errors corrected by the memory ECC 1516 during an access to the first memory device 1501 among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is 12, and the number of errors corrected by the memory ECC 1516 during an access to each of the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 is less than 10. And, it may be assumed that the first reference number is 10. In this case, the error analyzer 1513 may classify the first memory device 1501 as a "first memory device" and may not determine an error grade for each of the remaining memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508.

[0161] More specifically, the error analysis unit 1513 can analyze the log information LOG_INFO to check the type of error that occurred in the memory device classified as the "first memory device" (YES in S10). At this time, the error analysis unit 1513 can classify the type of error that occurred in the memory device classified as the "first memory device" into an error that occurred in a word line unit (S20), an error that occurred in a single bit unit (S30), an error that occurred in a bit line unit (S40), and other errors (S50).

[0162] Here, the error occurring in the word line unit (S20) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same word line in the same bank. And the error occurring in the single bit unit (S30) may mean a case where one or less errors occur in the same word and the same bit line. And the error occurring in the bit line unit (S40) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" occur in the same bit line. And the other error (S50) may mean a case where at least two or more errors occurring in the memory device classified as the "first memory device" do not have a specific distribution, for example, it is not determined that they occurred in the word line unit, the single bit unit, and the bit line unit.

[0163] Then, if the error analysis unit 1513 checks the type of error that occurred in the memory device classified as the "first memory device" and finds that the error occurred in the word line unit (S20), it can count the number of errors that occurred in the same word line in the memory device classified as the "first memory device" (S60). If the counting result shows that the number of errors is equal to or greater than a second reference number (YES in S70), it can determine that the memory device has a first error class and classify it as a "second memory device" (S90). If the counting result shows that the number of errors is less than the second reference number (NO in S70), it can determine that the memory device has a second error class and classify it as a "third memory device" (S80).

[0164] Then, when the error analysis unit 1513 checks the type of error that has occurred in the memory device classified as the "first memory device," if the memory device only has errors that have occurred on a single bit basis (YES in S30), errors that have occurred on a bit line basis (YES in S40), and other errors (YES in S50), the memory device can be determined to have a second error class and classified as a "third memory device" (S80).

[0165] To summarize by way of example, it may be assumed that errors occurring in a first memory device 1501 classified as a "first memory device" are errors occurring in units of word lines, and the number of errors occurring in the same word line is equal to or greater than a second reference number. Therefore, the error analyzer 1513 may determine that the first memory device 1501 classified as the "first memory device" has a first error class and classify it as a "second memory device."

[0166] The response operation unit 1515 can perform different error response operations for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 depending on the error grade for each of the memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 determined by the error analysis unit 1513.

[0167] Specifically, the response operation unit 1515 may perform a first error response operation on a memory device classified as a "second memory device" by adding a first error grade to the memory device among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 by the error analysis unit 1513. Also, the response operation unit 1515 may perform a second error response operation on a memory device classified as a "third memory device" by adding a second error grade to the memory device among the plurality of memory devices 1501, 1502, 1503, 1504, 1505, 1506, 1507, and 1508 by the error analysis unit 1513.

[0168] Here, the first error handling operation may include at least one of the following operations:

[0169] The first operation is an operation of selecting an area where an error occurs in a memory device classified as a "second memory device" and blocking access. For example, the corresponding operation unit 1515 can select a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "second memory device" and block access. In this case, the corresponding operation unit 1515 can perform an access blocking operation after copying data stored in the specific block, specific word line, or specific bit line to be blocked and storing it in an "other area." In this case, the "other area" can be another normal block, another normal word line, or another normal bit line in the first memory device 1501. In addition, the "other area" can be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason that the operation of storing data stored in a particular block, word line, or bit line that is the target of access blocking in “another area” can be performed normally is because the particular block, word line, or bit line was selected as the target of the access blocking operation in anticipation of a high probability of an unrecoverable error occurring at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0170] The second operation is an operation of selecting and repairing an area where an error occurs in a memory device classified as a "second memory device". For example, the corresponding operation unit 1515 may repair a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "second memory device" with another normal redundancy block, a specific word line, or a specific bit line. At this time, the access to the first memory device 1501 may be interrupted during the section where the repair operation is performed. The first memory device 1501 to be repaired may perform the repair operation after copying data stored in the specific block, the specific word line, or the specific bit line to be repaired to the internal information storage area PA1. After the repair operation is completed, the first memory device 1501 may restore the data copied to the information storage area PA1 to the redundancy block, the redundancy word line, or the redundancy bit line that has been repaired. For reference, the reason why the operation of copying data stored in a specific block, word line, or bit line that is the target of repair to the internal information storage area PA1 can be performed normally is because the specific block, word line, or bit line was selected as the target of repair based on the prediction that there is a high possibility that an unrecoverable error will occur at an adjacent future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0171] The third operation is an operation of selecting and disabling an area where an error occurs in a memory device classified as a "second memory device". For example, the corresponding operation unit 1515 can disable a specific block, a specific word line, or a specific bit line in the first memory device 1501 classified as the "second memory device". In this case, the corresponding operation unit 1515 can copy data stored in the specific block, the specific word line, or the specific bit line to be disabled and store it in "another area". In this case, the "other area" can be another normal block, another normal word line, or another normal bit line in the first memory device 1501. In addition, the "other area" can be another normal block, another normal word line, or another normal bit line included in other memory devices 1502, 1503, 1504, 1505, 1506, 1507, and 1508 other than the first memory device 1501. For reference, the reason why the operation of storing data stored in a particular block, word line, or bit line to be disabled in a "different area" can be performed normally is because the particular block, word line, or bit line was selected as a target for disabling in anticipation of a high probability of an unrecoverable error occurring at a future point in time, and at the present point in time, it is in a state where it is operating normally or where only recoverable errors occur.

[0172] The second error response operation may include an error recovery operation using an error correction code on the codeword-unit data in which an error occurred via system ECC1516 when an error occurs during an access operation to a memory device classified as the "third memory device."

Claims

1. a memory system including a plurality of memory devices, each of which includes a plurality of cell array regions in which a plurality of memory cells are connected in an array form to a plurality of word lines and a plurality of bit lines, and a first error correction unit; a host including a second error correction unit, the second error correction unit correcting an error in data transferred from the memory system, generating error correction information for an error correction operation of the second error correction unit, setting an error strength for each of the plurality of memory devices using the error correction information and log information generated in each of the plurality of memory devices, and performing an error response operation for each of the plurality of memory devices according to the error strength; Equipped with Each of the plurality of memory devices comprises: The data processing system further includes a first error correction unit that corrects an error in access data that occurs during an access operation to the plurality of cell array regions, and generates the log information regarding the error correction operation of the first error correction unit.

2. Each of the plurality of memory devices comprises:

2. The data processing system of claim 1, wherein when an error occurs in access data during an access operation including a read / write operation, the data processing system operates the first error correction unit included therein to correct the error that occurred, accumulates and stores raw data of the data whose error has been corrected by the first error correction unit in an internal information storage area to generate the log information, and outputs the log information to the host via the memory system at the request of the host.

3. The host is an error collector that collects the error correction information in real time or at a preset time point, and collects the log information from the memory system at the preset time point; a first error analysis unit that analyzes the log information and the error correction information to check the number and type of errors occurring in each of the plurality of memory devices, and determines an error grade for each of the plurality of memory devices according to the checking result; a second error analyzer that, for some of the memory devices according to the error grade determined by the first error analyzer, determines an error strength by checking a type and a number of errors through an additional analysis of the log information and the error correction information, and determines an error strength for the remaining memory devices so as to correspond to the error grade determined by the first error analyzer; a response operation unit that performs the error response operation on each of the plurality of memory devices according to the error strength determined by the second error analysis unit; 3. The data processing system of claim 2, comprising:

4. The first error analysis unit classifying a memory device having a number of errors occurring therein equal to or greater than a first reference number among the plurality of memory devices as a first memory device; classifying the corresponding first memory device as a second memory device having a first error class when the type of the error that occurred in the first memory device is a first error that occurred in a word line having a second reference number or more; 4. The data processing system of claim 3, wherein if the type of error occurring in the first memory device is a type of error other than the first error, the corresponding first memory device is classified as a third memory device having a second error class.

5. Each of the first and second error correction units performs an error correction operation on data input / output from each of the plurality of memory devices in a code word unit including an error correction code (ECC), and the second error analysis unit classifying the second memory device as a fourth memory device having a first error strength when the type of error that has occurred in the second memory device spans a third reference number or more of codeword units and the total number of errors included in the second memory device is a fourth reference number or more; classifying the second memory device as a fifth memory device having a second error strength when an error type occurs across the third reference number or more of code words and the total number of errors included is less than the fourth reference number, or across less than the third reference number of code words; 5. The data processing system of claim 4, wherein said third memory device is assigned said second error strength and is classified as said fifth memory device.

6. The corresponding operation unit is selecting an area in the fourth memory device where an error has occurred and blocking access to the area; selecting and repairing an area in the fourth memory device where an error has occurred; and an operation of selecting and disabling an area in the fourth memory device in which an error has occurred.

7. The host is designating a time point, which is repeated at specific time intervals from a time point when power is supplied to the memory system, as the set time point; counting the number of errors occurring in access data during an access operation to the memory system, and whenever the number of errors exceeds a fifth reference number, designating the time when the fifth reference number is exceeded as the set time, and then initializing the count of the number of errors; and an operation of designating as the set time a time point at which an error correction operation for correcting an error that occurs in access data during an access operation to the memory system takes a specific time or more.

8. a plurality of memory devices each including a plurality of cell array regions, each having a plurality of memory cells connected in an array form to a plurality of word lines and a plurality of bit lines, and a first error correction unit, the first error correction unit correcting an error in access data occurring during an access operation to the plurality of cell array regions, and generating log information regarding the error correction operation of the first error correction unit; a controller including a second error correction unit, the second error correction unit correcting errors in data transferred from the plurality of memory devices, generating error correction information for an error correction operation of the second error correction unit, setting an error strength for each of the plurality of memory devices using the log information and the error correction information, and performing an error response operation for each of the plurality of memory devices according to the error strength; A memory system comprising:

9. Each of the plurality of memory devices comprises:

10. The memory system of claim 8, wherein when an error occurs in access data during an access operation including a read / write operation, the memory system operates a first error correction unit included therein to correct the error that occurs, accumulates and stores raw data of the data whose error has been corrected by the first error correction unit in an internal information storage area to generate the log information, and outputs the log information to the controller at the request of the controller.

10. The controller: an error collector that collects the error correction information in real time or at a set time point, and collects the log information from each of the plurality of memory devices at the set time point; a first error analysis unit that analyzes the log information and the error correction information to check the number and type of errors occurring in each of the plurality of memory devices, and determines an error grade for each of the plurality of memory devices according to the checking result; a second error analyzer that, for some of the memory devices according to the error grade determined by the first error analyzer, determines an error strength by checking a type and a number of errors through an additional analysis of the log information and the error correction information, and determines an error strength for the remaining memory devices so as to correspond to the error grade determined by the first error analyzer; a response operation unit that performs the error response operation on each of the plurality of memory devices according to the error strength determined by the second error analysis unit; The memory system of claim 9 .

11. The first error analysis unit classifying a memory device having a number of errors occurring therein equal to or greater than a first reference number among the plurality of memory devices as a first memory device; classifying the corresponding first memory device as a second memory device having a first error class when the type of the error that occurred in the first memory device is a first error that occurred in a word line having a second reference number or more; 11. The memory system of claim 10, wherein if the type of error that occurs in the first memory device is a type of error other than the first error, the corresponding first memory device is classified as a third memory device having a second error class.

12. each of the first and second error correction units performs an error correction operation on data input / output from each of the plurality of memory devices in a code word unit including an error correction code (ECC); The second error analysis unit classifying the second memory device as a fourth memory device having a first error strength when the type of error that has occurred in the second memory device spans a third reference number or more of codeword units and the total number of errors included in the second memory device is a fourth reference number or more; classifying the second memory device as a fifth memory device having a second error strength when an error type occurs across the third reference number or more of code words and the total number of errors included is less than the fourth reference number, or across less than the third reference number of code words; 12. The memory system of claim 11, wherein the third memory device is assigned the second error strength and is classified as the fifth memory device.

13. The corresponding operation unit is selecting an area in the fourth memory device where an error has occurred and blocking access to the area; selecting and repairing an area in the fourth memory device where an error has occurred; and an operation of selecting and disabling an area in the fourth memory device in which an error has occurred, as the error response operation depending on the state of the fourth memory device.

14. The controller: an operation of designating a time point, which is repeated at a specific time interval from the time point when power is supplied, as the set time point; counting the number of errors occurring in access data during an access operation to the plurality of memory devices, and whenever the number of errors exceeds a fifth reference number, designating the time at which the number of errors exceeds the fifth reference number as the set time, and then initializing the count of the number of errors; and an operation of designating as the set time a time point at which an error correction operation for correcting an error that occurs in access data during an access operation to the plurality of memory devices takes a specific time or more.

15. A method for operating a memory system including a plurality of memory devices each including a plurality of cell array regions in which a plurality of memory cells are connected in an array form to a plurality of word lines and a plurality of bit lines, and an error correction unit, a generating step of correcting an error in access data generated during an access operation to each of the plurality of memory devices by the error correction unit, and generating log information regarding the error correction operation of the error correction unit; an error analysis step of analyzing the log information to check the number and type of errors occurring in each of the plurality of memory devices, and determining an error grade for each of the plurality of memory devices according to the check result; performing an error response operation on each of the plurality of memory devices according to the error grade determined for each of the plurality of memory devices; Including, The error analysis step includes: classifying a memory device having a number of errors occurring therein equal to or greater than a first reference number as a first memory device among the plurality of memory devices; classifying the corresponding first memory device as a second memory device having a first error class when the type of the error that occurred in the first memory device is a first error that occurred in a second reference number or more of word lines; classifying the corresponding first memory device as a third memory device having a second error class when the type of the error that occurred in the corresponding first memory device is a type of error other than the first error; A method of operating a memory system comprising:

16. The generating step includes: an operation step of operating the error correction unit to correct an error that occurs in access data during an access operation to each of the plurality of memory devices; generating the log information by accumulating and storing raw data for data in which an error has been corrected by the error correction unit in an information storage area included in each of the plurality of memory devices; 20. The method of claim 15, comprising:

17. The method further includes a collection step of collecting the log information stored in the information storage area at each set time point, The error analysis step includes: The method of claim 16 , further comprising: analyzing the log information collected in the collecting step.

18. The corresponding step includes: selecting an area in the second memory device where an error has occurred and blocking access to the area; selecting and repairing an area in the second memory device where an error has occurred; and an operation of selecting and disabling an area in the second memory device where an error has occurred, depending on a state of the second memory device, to perform the error response operation.

19. designating a time point that is repeated at specific time intervals from the time point when power is supplied as the set time point; counting a number of errors occurring in access data during an access operation to the plurality of memory devices, and whenever the number of errors exceeds a fifth reference number, designating a time point at which the number of errors exceeds the fifth reference number as the set time point, and then initializing the count of the number of errors; and designating as the set time a time point at which an error correction operation for correcting an error occurring in access data during an access operation to the plurality of memory devices takes more than a specific time.

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