Limited granting module for computing chips

Abstract

The present invention relates to provide limited granting module for computing chips A Granting module is provided as a main module for limiting the computational operations of the computing chips. The Granting module through enable signal grants the operations of an actual design in a computing device, such as CPU, GPU, Artificial Intelligence based Neural Network models, any primitive logic gates such as AND, OR, NOT, XOR, XNOR, NAND, NOR and the like. An encrypted enable logic may be provided for non-System on Chip. A replaceable and / or reconfigurable measuring unit is provided to measure one or more parameters, wherein the measuring unit is adapted to reconfigure for a System on Chip if the Limited grantor is meant for repetitive operations. Different kind of the secured mode settings are implemented which triggers to reset in case of re-configurable measuring unit. Limited grantor Design logic is operative when measuring unit is not reached to measuring limit. The measuring unit provides enable logic triggering that further provide the actual design to operate, whereas if the measuring unit reaches to a measuring limit, the measuring unit triggers enable logic which makes the actual design non operative.

Description

LIMITED GRANTING MODULE FOR COMPUTING CHIPSFIELD OF INVENTION

[0001] The present invention relates to computing systems. Particularly, the present invention relates to a technology of implementing a granting module to control the functioning of semiconductor logic modules.BACKGROUND OF THE INVENTION

[0002] As the chips are advancing with saturated foundry technology with a lot of features, they are unable to keep up with Moore's law to keep pace in the market. Computing chips can greatly assist human intelligence in almost all fields. Licensing is used in the present day for regulating software applications, which are merely computer programs and algorithms implemented using generic or specialized computing hardware. However, such licensing does not pertains to regulating the computing hardware or components. Presently, a number of subscription-based services exist, limited to webbased online and computing services and does not extend to limit the hardware based computing operations.

[0003] Moore's law was the key to guide the semiconductor chip industry in terms of long term planning to introduce more computing power, higher efficiency, and more complex functions in the computing devices. But due to varying market demands and requirements, the law is not keeping pace with the expectations.

[0004] Reference may be made to US Patent No. US 8,509,449 B2 that discloses a key protector for a storage volume using multiple keys. A key protector for a storage volume is created by generating an intermediate key and protecting, based at least in part on a public / private key pair, the intermediate key. A volume master key for encrypting and decrypting one or more volume encryption keys that are used to encrypt the storage volume can be encrypted in different manners, including being encrypted based at least in part on the intermediate key. A key protector for the storage volume is stored that includes both the encrypted volume master key and information indicating how to obtain the intermediate key. Subsequently, the key protector can be accessed and, basedat least in part on a private key of the entity associated with the key protector, the intermediate key can be decrypted. The intermediate key can then be used to decrypt the volume master key.

[0005] Therefore, keeping in view the problems associated with the state of the art there is a need for a mechanism that may provide limitation or regulation of one or more embedded hardware components in a computing device.OBJECTIVES OF THE INVENTION

[0006] The primary objective of the present invention is to control or regulate the functioning of logic modules in a computing device.

[0007] Another objective of the present invention is to provide a grantor module that controls or regulate one or more semiconductor logic modules.

[0008] Yet another objective of the present invention is to provide a grantor module to enable a design logic module in accordance with an enabler logic module and a measuring unit.

[0009] Yet another objective of the present invention is to provide a measuring unit which verifies utilized limit and a limit is fixed based on one or more parameters, for example, time, count, fees, etc.BRIEF DESCRIPTION OF DRAWINGS

[0010] The present invention will be better understood after reading the following detailed description of the presently preferred aspects thereof with reference to the appended drawings, in which the features, other aspects and advantages of certain exemplary embodiments of the invention will be more apparent from the accompanying drawing in which:[Oil] Figure 1 illustrates a diagrammatic representation of a computing device incorporating plurality of logic modules to perform limited granting on one or more logic modules.

[0012] Figure 2 illustrates a component diagram of a grantor module in a non SoC environment.

[0013] Figure 3 illustrates a component diagram of a SoC chip with limited grantor module.

[0014] Figure 4 illustrates a component diagram of a grantor module for multiple design units.

[0015] Figure 5 illustrates a component diagram depicting multiple grantor modules for multiple design units.

[0016] Figure 6 illustrates a secured enable logic.

[0017] Figure 7 illustrates a mode based reconfigurable measuring unit.

[0018] Figure 8 illustrates measuring unit key aspects.

[0019] Figure 9 illustrates an example of Hardware Description Language for Design with Limited Grantor module.SUMMARY OF THE INVENTION

[0020] The present invention relates to provide limited granting module for computing chips. A Granting module is provided as a main module for limiting the computational operations of the semiconductor chips. The Granting module through enable signal grants the operations of an actual design in a computing device, such as CPU, GPU, Artificial Intelligence based Neural Network models, design with any primitive logic gate and the like. An encrypted enable logic may be provided for non-System on Chip. A replaceable and / or reconfigurable measuring unit is provided to measure one or more parameters, wherein the measuring unit is adapted to reconfigure for a System on Chip if the Limited grantor is meant for repetitive operations. Different kind of the secured mode settings are implemented which triggers to reset in case of re-configurable measuring unit. Limited grantor Design logic is operative when measuring unit is notreached to measuring limit. The measuring unit provides enable logic triggering that further provide the actual design to operate, whereas if the measuring unit reaches to a measuring limit, the measuring unit triggers enable logic which makes the actual design non operative.DETAILED DESCRIPTION OF THE INVENTION

[0021] The following description describes various features and functions of the disclosed system and method with reference to the accompanying figure. In the figure, similar symbols identify similar components, unless context dictates otherwise. The illustrative aspects described herein are not meant to be limiting. It may be readily understood that certain aspects of the disclosed system and method can be arranged and combined in a wide variety of different configurations, all of which are contemplated herein.

[0022] Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0023] Features that are described and / or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and / or in combination with or instead of the features of the other embodiments.

[0024] The terms and words used in the following description and claims are not limited to the bibliographical meanings but are merely used to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention.

[0025] It is to be understood that the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise.

[0026] It should be emphasized that the term “comprises / comprising” when used in this specification is taken to specify the presence of stated features, integers, steps, or components but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. The equations used in the specification are only for computation purpose.

[0027] Fig 1 illustrates a diagrammatic representation of a computing device incorporating plurality of logic modules to perform limited granting on one or more logic modules.

[0028] In one embodiment, the computing device comprises a main design module (100) configured to operate on a standalone platform or in a specialised computing environment. In a non-limiting example, the standalone platform may include a computing device with a main design comprising a Central Processing Unit (CPU), one or more Graphical Processing Units (GPU), and other auxiliary components, for example, communication modules, volatile and non-volatile memory units such as RAM, ROM, and the like, and peripheral interface components. In another non-limiting example, the specialised computing environment may include a cloud-based computing system, an Artificial Intelligence (Al) model based computing environment, which may include Artificial Neural networks, Deep Learning systems, etc. It may be appreciated by person skilled in the art that binary operations such as arithmetic operations may be performed by one or more components of the computing device implemented using primitive logic hardware units such as logic gates, for example, AND, NOT, OR, NAND, NOR, BUF, XOR, XNOR logic gates. Also, plurality of other logic hardware such as flip-flop registers may be provided to control the operations in the computing device. The hardware works in conjunction with the software stored in the memory of the computing device to perform plurality of operations, such as fetching, decoding, executing of the instructions. In another embodiment, the logic modules may include an enabler logic module (101) and a grantor module (102). Enabler logic is configured to enable the main design module to perform one or more operations in a secure environment. As main design module is operably coupled with the enabler logic module through a general wire or a combination logic, the interface of main design module and enabler logic module is made secure to the external access.

[0029] In yet another embodiment, the logic module may include a grantor module (102) operably and communicatively coupled with the enabler logic module (101) and a measuring unit (103), and configured to regulate or control one or more operations in the main design module (100). In some embodiments, said operations are granting operations. The measuring unit (103) is configured to verify the utilized limit by the main design module (100) when said main design module (100) completes operations for a pre-defined limiting parameter such as a timer limit. The pre-defined limiting parameter may be a time limit, a count, or any preferred parameter based on the preferences set by user or operator of the device, as described in Figure 8.

[0030] Fig 2 illustrates a grantor module in a non soc configuration. An actual design (200) that may be described as any kind of design having primitive logic gates and a design level enable logic (201). This design enable logic could be a simple wire or a simple AND gate or a complex logic which may be configured to compare output and triggers the design operations. The design enable logic (201) receives an input from a grantor module (203). The grantor module (203) has a grantor enable logic (202) and a measuring unit (204). The grantor module (203) gets input from the actual design (200). The measuring unit (204) measures the utilized limit with a pre-defined limit and when the limit is reached, it limits the enable signal, whereas the utilized limit can be reconfigurable which is described in Fig 7. The grantor module (203) passes the enable signal received from the measuring unit (204) to the actual design (200) with a combination of the grantor enable logic (202) outputs. The grantor enable logic (202) could be a simple wire or a simple primitive gate or a combinational logic, as described in Fig 6. If in any case secure enable logic is required, then combinational logic may be used which secures data signals values. The grantor module (202) may be replaced with a software module with similar logic. The grantor module (202) can be implemented as a chip which is replaceable on Printed Circuit Board, off the Printed Circuit Board chip which can be communicated with any of the communication protocols such as U.S.B, ETHERNET, WIRELESS ETHERNET, which includes a cloud based grantor, BLUETOOTH, UART to actual design (200).

[0031] Fig 3 illustrates a system on chip (300) which comprises a design (301) which may be any computing design such as CPU, GPU, Neural Network, Cryptographic Network,Block chain, Memory and any other designed with primitive logic gate such as AND, OR, NOT, BUF, NAND, NOR, XOR, XNOR. A design enable logic A (302), a design enable logic B (303) may be a separate logic or simply a combined logic which may be a simple enable wire since it is a system on chip that does not require any secure logic. A Grantor module (304) may comprise an Enable logic B (303) and a Measuring unit (305). The measuring unit (305) is same as the measuring unit (205). The measuring unit (305) may require reconfiguration of predefined limit in cases where repetition is required, as described in Fig 7.

[0032] Fig 4 illustrates a plurality of designs including designl (400), design2 (401), design-n (402), where n may be an integer, which are actual designs comprising of the design enabler logic and designs including but not limited to CPU, GPU, Neural Network, Cryptographic Network, Block chain, Memory and any other designs designed with primitive logic gate such as AND, OR, NOT, BUF, NAND, NOR, XOR, XNOR. Multiple designs with different design enable logics, designl enable logic (404), design2 enable logic (405), design-n enable logic (406), where n may be an integer. Any design enable logic may be a simple wire or a combinational logic for secure enable which is described in the design enable logic (201). A grantor module (403) which is common for all the actual designs (400, 401, 402). The grantor module (403) consists of a grantor enable logic (407) which is described in the grantor enable logic (202) and a measuring unit (408) which is described in the measuring unit (204). For example, CISC based CPU may be implemented as design 1, GPU as design 2, RISC based CPU as design3, cryptographic network as design4, Artificial Intelligence based network as design 5, which may have inbuilt design enable logic with simple wire connectivity. The Grantor module with common enable which may be a simple wire and the measuring unit measures and provides signal to enable. In an exemplary illustration, the pre-defined time that may be utilized to operate any of the disclosed design in the measuring unit is 10 years, wherein the design gets active enable signal till the design working time reaches to 10 years. Once it reaches to 10 years, the design receives a deactivated enable signal which turns off the computing operations of the design. In order to activate the computing operations of the design, the grantor module chip may be required to replace or the grantor module chip may be reconfigured in caseof non soc based configuration. In case of soc, we should reconfigure the chip to activate the designs

[0033] Fig 5 illustrates plurality of design including designl (500), design2 (501), design-n (502), where n may be an integer, which may be implemented using actual designs such as CPU, GPU, Neural Network, Cryptographic network, Memory, Block chain and any other design with primitive logic gate such as AND, OR, NOT, BUF, NAND, NOR, XOR, XNOR. All the designs can be configured on SOC or on PCB as separate chips. 509, 510, 511 are the separate grantor modules to specific design which comprises of plurality of grantor enable logics (503, 504, 505) and measuring units (506, 507, 508), as described in the grantor module (203). In this way every grantor module has a different measuring unit which can activate or deactivate the enable to the design. For example, CISC based CPU as designl, RISC based CPU as design2, GPU as design3, Cryptographic based design as design4, Artificial Intelligence as design5, which are having inbuilt design enable logic. CISC based CPU grantor module Gl, RISC based CPU grantor module G2, GPU based grantor module G3, Cryptographic grantor module as G4, Artificial Intelligence as G5. Gl grantor module has a measuring unit with limit of 10 years, G2 grantor module has a measuring unit with limit of 8 years, G3 grantor module has a measuring unit with limit of 6 years, G4 grantor module has a measuring unit with limit of 4 years, G5 grantor module has a measuring unit with limit of 2 years. In this case when Gl time limit reaches to 10 years then CISC based CPU gets deactivated, and said design may be activated either by replacing or reconfiguring the measuring unit. When G2 time reaches to 8 years then the RISC based CPU gets deactivated, and said design may be activated either by replacing or reconfiguring the measuring unit. When G3 time reaches 6 years then GPU gets deactivated, and said design may be activated either by replacing or reconfiguring the measuring unit. When G4 time reaches 4 years then Cryptographic gets deactivated and, and said design may get activated either by replacing or reconfiguring the measuring unit. When G5 time reaches 2 years then Artificial Intelligence gets deactivated, and said design may activated either by replacing or reconfiguring the measuring unit. A grantor module is replaceable or not replaceable depends on type of chip, i.e., either S.O.C or non-S.O.C type of chip.

[0034] Fig 6 illustrates a secured enable logic which comprises a design enabler (600) consisting of an enable design logic (602) and a comparator (601), as described in the design enable logic (201) where secure enable logic may be required in case of grantor module in non SOC configuration. The secure logic connects through logic instead of simple wire couple. This enable logic is a fixed combinational logic at design side. Similarly, a grantor module (604) consist of a grantor enable logic (603), which is in synchronization with the design enabler logic. Both enabler logics design (602) and grantor (603) match with each other. The results of both 602 and 603 are compared with equivalent the comparator (601), which may be a simple OR gate or AND gate or XOR or complex comparator logic, at designer enabler that may trigger activate or deactivate signal at the design outputs or design computation. For example, Design of 32-bit Digital FM where ADC are coupled to receiver antenna. At digital we get 32 bit of equivalent analog signal which may be used as an input to secure logic, here the secure logic is 10-bit simple 5 XOR gates which are connected directly in sequentially to 10-bit input pins and the same 5 XOR gates with same way of 10-bit connections used in grantor enable logic. The choice of 10-bit input connection is random of 32-bit digital inputs and the same connects to grantor enable logic. Further, the Grantor module verifies with the measuring unit and couples with the grantor enable logic which means if activate signal generates from measuring unit then output of grantor enable logic passes design level comparator otherwise a deactivated signal generates from the measuring unit then non intended result of grantor module enable logic sends to design enabler comparator. The Comparator verifies both outputs which means design enabler logic 5 XOR outputs and grantor module transmitted outputs are matched then it activates FM design computation which means FM output voice receives to speakers. In case comparator output is mismatched, then deactivated signal is generated and no sound comes to speaker from FM processor.

[0035] Fig 7 illustrates the 700 mode based reconfigurable measuring unit limits changes or reset to original values grantor module. As discussed in 204 where measuring unit deactivate the enable signal when it reaches to utilized value. In such cases, either the replaceable or reconfigurable measuring units are required to repetitively use grantor module to enable the design. Once deactivated the enable signal, we need to use reconfigurable to reset the limits. For an SOC or non-SOC, architecture linked mode setting pins may be used. As mode pins physically coupled to a reconfigurable logic(701). When the mode pins pattern matches then triggers the reconfigurable logic (701), then the reconfigurable logic (701) which coupled with a measuring unit (703) limits are reset to original values which makes an enable logic (704) activated. For example, A0, Al, A3 are mode setting pins for an SOC or non-SOC then the pattern A0, Al, A3 equals to 111 which makes activate of reconfigurable logic. Assume our grantor module limit is 100 days which means design is operative only for 100 days. If grantor module reaches to 100 days it deactivates the design computation. Now, if pattern of A0, Al, A3 sets to 1 1 1 then it starts activate to reconfigurable logic then measuring unit utilized limit to 0 days. As utilized limit becomes 0 days then it triggers / activates the enable logic signal of the design then restarts the design computation or computation results producing outputs.

[0036] Fig 8 illustrates a Measuring unit (800) of grantor module. The measuring unit (800) comprises of a counter (801) or an ALU with a comparator, an inbuilt memory (802) and a triggering enable logic signal (803). The counter (801) or the ALU with the comparator operates for counting of utilized limit and then compares results with pre designed limit using comparator. A comparator could be simple XOR gate or any other complex logic works for comparison. The inbuilt memory (802) is any memory such as register flip-flop, EEPROM, ROM, PROM and any other which can store, uses for pre-defined criteria limit. The enable signal (803) triggering, triggers the enable signal from measuring unit based on the limit matches. Enable signal or utilized limit value which generates from grantor module connects to an indicator which shows as limit is reaches or not reached for design computation. For example, the inbuilt memory (802) loaded with count of 500 which uses flip-flops with constants connecting. For every input design computation counts as increment of one to utilized limit using counter, now comparator in this example XNOR with AND gates of every bit compare to 500 decimal equal binary bit registers. Output of 801 activates the enable signal if the compares output is not matches which means 0, upon reaching to 500 counts the output of 801 is 1 then deactivates 803 enable signal using simple NOT gate.

[0037] Fig 9 illustrates a simplified example of Hardware Description Language for Design with Limited Grantor module. 900 describes the connectivity of actual design in this case 2 bit adder with module ADDER_2BIT (901) and a grantor module with GRANT (902). CLK, RST, DPI are the input pins and LED out pin for the top module which issingle chip in case of soc and PCB in case of non soc. Enable, sum, cout are used as interconnect wire between 2bit adder and grantor module. DPI as 2bit, elk, enable pins are connected as input pins and sum, cout pins are connected as output pins to 2bit adder (901). The 2bit adder (901) adds upon enable pin positive and elk pin positive edge. The GRANT (902) module connects with elk, reset are input pins and enable pin as outpin. Grant logic is coded with 30 sec at 50MHZ to make enable pin to zero. Here, the measuring unit is measuring with the count of 30 sec based on the increment of every clock cycle and enable becomes zero as and when it reaches to 30 multiply with clock frequency. When enable zero then 2bit adder module becomes non-operative, the reset pin resets the enable to one and the counter again starts from zero for this activity and it becomes repetitive.

[0038] While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

Claims:

1. A limited grantor module for controlling a computing chip, comprising: an enable unit comprising a grantor enable logic, and a measuring unit, wherein the computing chip comprises a design logic module configured to communicate with the limited grantor module to receive an input from the grantor enable logic and to send a result thereto, the measuring unit is configured to compare utilized limit with pre-defined limit for which the computing chip can be allowed to operate.

2. The limiting grantor module as claimed in claim 1, wherein the computing chip is selected from a group of design units including a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an application specific computing unit configured to run Artificial Neural Networks, Block-chain Networks, or Machine Learning networks, or a logic circuit implemented with primitive logic gates.

3. The limiting grantor module as claimed in claim 1, wherein the pre-defined limit is loaded or logically connected to memory of measuring unit.

4. The limiting grantor module as claimed in claim 1, wherein the measuring unit is configured to reset the utilized limit to an initial value or incrementable the utilized limit.

5. The limiting grantor module as claimed in claim 1, wherein the measuring unit is configured to reset using mode settings of the chip through pins thereof.

6. The limiting grantor module as claimed in claim 1, wherein the limiting granting module is configured to provide an indication of enabling the computing chip or utilizing of the limit to the computing chip.

7. The limiting grantor module as claimed in claim 1, wherein the enable unit is securely coupled with the design logic module through a secured logic, the secured logic may be a combinational logic circuit.

8. The limiting grantor module as claimed in claim 1, wherein the limiting granting module is a standalone replaceable module communicatively coupled with the computing chip through a wired or a wireless medium.

9. The limiting grantor module as claimed in claim 1 and 2, wherein the computing chip comprises a plurality of design units ranging from design- 1, design-2, design-3, and likewise up to design-n, where n is an integer, the design units are communicatively coupled with the limited grantor module.

10. The limiting grantor module as claimed in claim 1 and 2, wherein the computing chip comprises a plurality of design units including design- 1, design-2, design-3, and likewise up to design-n, and the limited grantor module comprises a plurality of grantor module units including Gl, G2, G3, and likewise up to Gn, where n is an integer, each design unit is communicatively coupled with a corresponding grantor module unit.

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