Support substrate for passive electronic components, passive electronic components, semiconductor device, matching circuit, and filter circuit

Abstract

A passive electronic component support substrate 1 comprises: a semiconductor substrate 10; a charge-trapping layer 11 provided on the semiconductor substrate 10 and having a high density of crystal defects in relation to the semiconductor substrate 10; and an insulation layer 21 provided on the charge-trapping layer 11. The insulation layer 21 comprises a silicon nitride. The N atom concentration ratio to the total amount of Si and N contained in the insulation layer 21 is 45 atom% or less. Alternatively, the insulation layer 21 includes: a first insulation layer 21A that is provided on the charge-trapping layer 11; and a second insulation layer 21B that is provided on the first insulation layer 21A. The internal fixed charge polarities in the first insulation layer 21A and the second insulation layer 21B are opposite. The thickness of the first insulation layer 21 is 0.5-3 nm inclusive.

Description

[Technical field]

[0001] The present invention relates to a support substrate for passive electronic components. The present invention further relates to a passive electronic component and a semiconductor device comprising the support substrate, and a matching circuit and a filter circuit comprising the semiconductor device. [Background technology]

[0002] A typical capacitor element used in semiconductor integrated circuits is, for example, a metal insulator metal (MIM) capacitor, which has a parallel plate structure in which an insulator is sandwiched between a lower electrode and an upper electrode.

[0003] As a support substrate for use in passive electronic components such as capacitors, Patent Document 1 discloses a substrate comprising a planar silicon wafer, a planar layer of polycrystalline silicon on the wafer, and an insulating layer on the polycrystalline silicon layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-258713 A Summary of the Invention [Problem to be solved by the invention]

[0005] The support substrate described in Patent Document 1 is made of a high-resistance single crystal silicon substrate and SiO 2 By forming a polycrystalline silicon layer between the single crystal silicon substrate and an insulating layer made of a material such as a silicon nitride, it is possible to prevent a low resistance layer from being generated at the interface between the single crystal silicon substrate and the insulating layer, thereby reducing the deterioration of the Q characteristic of passive electronic components such as MIM capacitors formed on the supporting substrate, more specifically, the deterioration of the Q characteristic due to parasitic capacitance in the high frequency range.

[0006] Fig. 1 is a schematic diagram showing an example of a conventional support substrate. In Fig. 1, as the state of charge, + surrounded by square represents a positive fixed charge, - surrounded by circle represents a negative mobile charge (electron), and + surrounded by circle represents a positive mobile charge.

[0007] The support substrate 1a shown in FIG. 1 includes a semiconductor substrate 10 which is a p-type single crystal Si substrate, a charge trapping layer 11 which is provided on the semiconductor substrate 10 and is made of polycrystalline Si, and a SiO 2 The insulating layer 21 is made of SiO 2 1, the fixed charges inside the insulating layer 21 are positive. The accumulated charges (here, electrons) attracted to the fixed charges inside the insulating layer 21 are trapped in the charge trapping layer 11.

[0008] Patent Document 1 describes SiO 2 Although oxides such as SiO are disclosed as materials for the insulating layer 21, 2 Since a large amount of positive fixed charges are present in the insulating layer 21 made of polycrystalline Si, a large amount of electrons are generated in the charge trap layer 11 made of polycrystalline Si. Therefore, if the density of charge trap sites (crystal defects) in the charge trap layer 11 is insufficient, some of the generated electrons may not be trapped. Similarly, the density of charge trap sites (crystal defects) decreases as the crystallization of polycrystalline Si progresses due to thermal load during the device fabrication process, changes over time, etc., so that it may become impossible to trap all the generated electrons. In such a case, deterioration of characteristics occurs due to parasitic capacitance.

[0009] The present invention has been made to solve the above problems, and aims to provide a support substrate for passive electronic components that can reduce mobile charges generated in a charge trapping layer. It is also an object of the present invention to provide a passive electronic component and a semiconductor device that include the support substrate, and a matching circuit and a filter circuit that include the semiconductor device. [Means for solving the problem]

[0010] The support substrate for a passive electronic component of the present invention comprises a semiconductor substrate, a charge trapping layer provided on the semiconductor substrate and having a higher density of crystal defects relative to the semiconductor substrate, and an insulating layer provided on the charge trapping layer.

[0011] In a first embodiment, the insulating layer is made of silicon nitride, and the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 45 atom % or less.

[0012] In a second aspect, the insulating layer includes a first insulating layer provided on the charge trapping layer and a second insulating layer provided on the first insulating layer, the polarities of the internal fixed charges in the first insulating layer and the second insulating layer are opposite, and the thickness of the first insulating layer is 0.5 nm or more and 3 nm or less.

[0013] The passive electronic component of the present invention comprises the supporting substrate of the present invention.

[0014] The semiconductor device of the present invention comprises a supporting substrate of the present invention, a first electrode layer provided on the supporting substrate, a dielectric film provided on the first electrode layer, a second electrode layer provided on the dielectric film, a protective layer covering the first electrode layer and the second electrode layer, and an external electrode penetrating the protective layer.

[0015] A matching circuit of the present invention includes the semiconductor device of the present invention.

[0016] A filter circuit of the present invention includes the semiconductor device of the present invention. Effect of the Invention

[0017] According to the present invention, it is possible to provide a support substrate for passive electronic components, which can reduce mobile charges generated in a charge trapping layer. Furthermore, according to the present invention, it is possible to provide a passive electronic component and a semiconductor device including the support substrate, and a matching circuit and a filter circuit including the semiconductor device. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic diagram showing an example of a conventional supporting substrate. [Diagram 2] FIG. 2 is a schematic diagram showing an example of a support substrate according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a schematic view showing another example of the supporting substrate according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a graph showing the relationship between the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer and the fixed charge density. [Diagram 5] 5A to 5D are schematic diagrams showing the state of mobile charges when the fixed charges inside the insulating layer are positive. [Figure 6] FIG. 6 is a top view for explaining a method for measuring the fixed charge. [Figure 7] FIG. 7 is a cross-sectional view for explaining a method for measuring the fixed charge. [Figure 8] FIG. 8 is a graph showing an example of a CV curve. [Figure 9] FIG. 9 is a schematic diagram showing an example of a support substrate according to the second embodiment of the present invention. [Figure 10] FIG. 10 is a graph showing the relationship between the thickness of SiO2 and the fixed charge density in an insulating layer having a two-layer structure including a first insulating layer made of SiO2 and a second insulating layer made of SiN. [Figure 11] FIG. 11 is a cross-sectional view that illustrates an example of a capacitor including a support substrate of the present invention. [Figure 12] FIG. 12 is a plan view illustrating an example of a capacitor including a support substrate of the present invention. [Figure 13] FIG. 13 is a cross-sectional view illustrating a schematic diagram of another example of a capacitor including a support substrate of the present invention. [Figure 14] FIG. 14 is a cross-sectional view that illustrates an example of a surface acoustic wave element including a support substrate according to the present invention. [Figure 15] FIG. 15 is a cross-sectional view illustrating an example of a bulk acoustic wave element including a support substrate according to the present invention. [Figure 16]FIG. 16 is an explanatory diagram illustrating an example of a matching circuit. [Figure 17] FIG. 17 is an explanatory diagram illustrating an example of a filter circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, the support substrate for passive electronic components of the present invention (hereinafter, "support substrate for passive electronic components" may be abbreviated to "support substrate") will be described. However, the present invention is not limited to the following configurations, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual preferred configurations of the present invention described below.

[0020] The following embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in the different embodiments is possible. In the second and subsequent embodiments, the description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects and advantages due to the same configuration will not be mentioned one by one for each embodiment.

[0021] [First embodiment] A supporting substrate according to a first embodiment of the present invention comprises a semiconductor substrate, a charge trapping layer provided on the semiconductor substrate and having a high density of crystal defects relative to the semiconductor substrate, and an insulating layer provided on the charge trapping layer.

[0022] In the first embodiment of the present invention, the insulating layer is made of silicon nitride, and the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 45 atom % or less.

[0023] Fig. 2 is a schematic diagram showing an example of a support substrate according to the first embodiment of the present invention. Fig. 3 is a schematic diagram showing another example of a support substrate according to the first embodiment of the present invention. In Fig. 2 and Fig. 3, - surrounded by square represents a negative fixed charge, + surrounded by square represents a positive fixed charge, - surrounded by circle represents a negative mobile charge (electron), and + surrounded by circle represents a positive mobile charge.

[0024] 2 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, and an insulating layer 21 provided on the charge trapping layer 11. In the support substrate 1 shown in FIG. 2, the fixed charge inside the insulating layer 21 is positive.

[0025] 3 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, and an insulating layer 21 provided on the charge trapping layer 11. In the support substrate 1A shown in FIG 3, the fixed charges inside the insulating layer 21 are negative.

[0026] In the support substrate according to the first embodiment of the present invention, the fixed charge inside the insulating layer is adjusted so as to reduce the mobile charge generated at the interface between the insulating layer and the charge trapping layer. Specifically, by forming an insulating layer with a reduced fixed charge inside at the interface with the charge trapping layer, the mobile charge generated inside the charge trapping layer can be reduced.

[0027] This provides the following effects. By further increasing the resistivity of the charge trapping layer, the effect of parasitic capacitance from the semiconductor substrate can be further reduced. The performance requirements for the charge trapping layer can be lowered. For example, the heat resistance temperature and heat resistance time of the constituent materials of the charge trapping layer can be extended, which reduces the restrictions on the manufacturing method and temperature in the device fabrication process.

[0028] The semiconductor substrate is preferably a high-resistance Si substrate, and more preferably a single crystal Si substrate.

[0029] The resistivity of the semiconductor substrate is preferably 3 kΩ·cm or more, and more preferably 5 kΩ·cm or more.

[0030] The Si substrate such as a single crystal Si substrate may be either p-type or n-type, but since a high-resistance n-type Si substrate is brittle and the resistance is difficult to control, the p-type is preferred.

[0031] The charge trapping layer, which has a high density of crystal defects relative to the semiconductor substrate, traps mobile charges generated between the charge trapping layer and the insulating layer. The material constituting the charge trapping layer is preferably a high-resistance semiconductor material such as polycrystalline silicon or amorphous silicon that has sites for trapping charges.

[0032] The resistivity of the charge trapping layer is preferably equal to or higher than the resistivity of the semiconductor substrate.

[0033] The region in the charge trapping layer where the mobile charges exist is densest near the interface with the insulating layer, and decreases with increasing distance from the insulating layer, but still extends to a depth of about 1 to 2 μm. Therefore, the thickness of the charge trapping layer is preferably 1 μm or more, more preferably 2 μm or more. On the other hand, the thickness of the charge trapping layer is, for example, 10 μm or less.

[0034] Specific examples of the charge trapping layer include polycrystalline Si film, amorphous Si film, a crystal destruction layer formed by ion implantation of rare gas into the Si surface, and a crystal distortion layer formed by grinding or polishing. Among these, the material constituting the charge trapping layer is preferably polycrystalline Si or amorphous Si, in view of the thermal stability of the film structure and ease of thickness control. The polycrystalline Si film or amorphous Si film can be formed by vapor deposition such as chemical vapor deposition (CVD) or sputtering, respectively.

[0035] It is preferable that the insulating layer has as small a fixed charge as possible inside. As described above, the commonly used SiO 2An insulating layer made of silicon has a positive fixed charge, but because it is difficult to control the composition ratio and bonds of Si / O, it is not easy to adjust or reverse the amount of fixed charge as a stable film. For this reason, thermal oxide films, which are the most stable way to reduce fixed charge, have been used. However, because the amount of fixed charge is large even in thermal oxide films, improvements to the charge trapping layer have been studied.

[0036] In contrast, in the first embodiment of the present invention, the Si / N composition ratio of the insulating layer made of silicon nitride is adjusted to change it from N-rich to Si-rich, thereby making it possible to control the generated fixed charges from negative to positive.

[0037] FIG. 4 is a graph showing the relationship between the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer and the fixed charge density.

[0038] Stoichiometric silicon nitride, Si 3 N 4 In the case of Si, the atomic concentration ratio of N to the total amount of Si and N is 57.2 atom%. 3 N 4 An insulating layer made of Si has a negative fixed charge. As shown in Figure 4, the fixed charge can be reduced by setting the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer to 46 atom % or less. In particular, when the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 45 atom % or less, the fixed charge can be reduced significantly.

[0039] When the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is more than 44 atom% and is 45 atom% or less, the magnitude of the fixed charge inside the insulating layer can be made very small negative. On the other hand, when the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 44 atom% or less, the magnitude of the fixed charge inside the insulating layer can be made very small positive. In order to make it more stable positive, it is preferably 43 atom% or less. The above-mentioned FIG. 2 shows the state of the mobile charge generated at the interface with the charge trap layer when the fixed charge inside the insulating layer is positive, and FIG. 3 shows the state of the mobile charge generated at the interface with the charge trap layer when the fixed charge inside the insulating layer is negative.

[0040] Although there is no particular lower limit for the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer, if it is less than 38 atom%, the Q characteristic may deteriorate because the parasitic capacitance increases due to deterioration of the insulating properties. Therefore, it is preferable that the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 38 atom% or more.

[0041] The atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer can be calculated by analyzing the constituent elements of the insulating layer by X-ray photoelectron spectroscopy (XPS).

[0042] The XPS measurement conditions are as follows. Measurement equipment: ULVAC-PHI Quantes Measurement area: 100μmφ Measurement depth: 100 nm

[0043] The insulating layer made of silicon nitride can be formed by using a deposition method such as CVD or sputtering.

[0044] The thickness of the insulating layer made of silicon nitride is preferably 10 nm or more and 2000 nm or less.

[0045] 5A to 5D are schematic diagrams showing the state of mobile charges when the fixed charges inside the insulating layer are positive.

[0046] As shown in Figs. 5A to 5D, the effect of suppressing the mobile charges varies depending on the combination of the conductivity type of the semiconductor substrate 10, the conductivity type of the charge trapping layer 11, and the polarity of the fixed charges inside the insulating layer 21. When the fixed charges inside the insulating layer 21 are positive, as shown in Fig. 5D, if the conductivity type of the semiconductor substrate 10 is n-type and the conductivity type of the charge trapping layer 11 is n-type, the inversion region 12 and the depletion layer 13 (see Figs. 5A to 5C) are not formed inside the charge trapping layer 11, and the region of the mobile charges becomes 5 μm or more, so that the mobile charges cannot be contained in the charge trapping layer 11. As a result, a part of the mobile charges leaks into the semiconductor substrate 10, and a low-resistance region is formed. From the above, when the fixed charges inside the insulating layer 21 are positive, it is preferable that the combination of the conductivity type of the semiconductor substrate 10 and the conductivity type of the charge trapping layer 11 is p-type-p-type, p-type-n-type, or n-type-p-type, as shown in Figs. 5A to 5C.

[0047] On the other hand, when the fixed charge inside the insulating layer 21 is negative, if the conductivity type of the semiconductor substrate 10 is p-type and the conductivity type of the charge trapping layer 11 is p-type, the inversion region 12 and the depletion layer 13 (see FIGS. 5A to 5C) are not formed inside the charge trapping layer 11, and the region of the mobile charges becomes 5 μm or more, so that the mobile charges cannot be contained in the charge trapping layer 11. As a result, some of the mobile charges leak into the semiconductor substrate 10, creating a low-resistance region. For these reasons, when the fixed charge inside the insulating layer 21 is negative, the combination of the conductivity types of the semiconductor substrate 10 and the charge trapping layer 11 is preferably n-type-n-type, n-type-p-type, or p-type-n-type.

[0048] Furthermore, the mobility of holes is smaller than that of electrons among the charges generated at the interface between insulating layer 21 and charge trapping layer 11. In the case of operation at high frequencies, the degree of reduction in resistance is small, so that the charges generated at the interface between insulating layer 21 and charge trapping layer 11 are preferably holes.

[0049] Fig. 6 is a top view for explaining a method for measuring the fixed charge, and Fig. 7 is a cross-sectional view for explaining a method for measuring the fixed charge.

[0050] 6 and 7, an insulating layer 121 is formed on one main surface of a semiconductor substrate 100, which is a Si substrate having a resistivity of 1 Ω·cm or more and 10 Ω·cm or less, and an electrode 122 is formed on the insulating layer 121. Furthermore, an electrode 123 is formed on the other main surface of the semiconductor substrate 100. Thereafter, as shown in FIG. 7, the CV characteristics between the electrodes 122 and 123 are evaluated.

[0051] FIG. 8 is a graph showing an example of a CV curve.

[0052] As shown in Figure 8, the ideal curve S obtained from the CV curve calculation 0 Actual CV characteristics from S 1 The total amount of fixed charge can be calculated by multiplying the shift amount ΔV by the capacitance C of the insulating layer. 0 If the shift from is to the left, the polarity of the fixed charge is positive, and if it is to the right, the polarity of the fixed charge is negative. Equation 1: Total amount of fixed charge = capacitance of insulating layer C × shift amount ΔV Equation 2: Shift amount due to total amount of fixed charge ΔV = Shift amount due to fixed charge at interface ΔV IFC + Shift amount due to fixed charges in the insulating layer ΔV OFC

[0053] [Second embodiment] In a second embodiment of the present invention, the insulating layer includes a first insulating layer provided on the charge trapping layer and a second insulating layer provided on the first insulating layer, the polarities of the internal fixed charges are opposite in the first insulating layer and the second insulating layer, and the thickness of the first insulating layer is 0.5 nm or more and 3 nm or less.

[0054] Fig. 9 is a schematic diagram showing an example of a support substrate according to the second embodiment of the present invention, in which a - surrounded by a square represents a negative fixed charge, a + surrounded by a square represents a positive fixed charge, and a - surrounded by a circle represents a negative mobile charge (electron).

[0055] The support substrate 2 shown in FIG. 9 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, and an insulating layer 21 provided on the charge trapping layer 11. The insulating layer 21 includes a first insulating layer 21A provided on the charge trapping layer 11 and a second insulating layer 21B provided on the first insulating layer 21A. In the support substrate 2 shown in FIG. 9, the fixed charges inside the first insulating layer 21A are positive, and the fixed charges inside the second insulating layer 21B are negative. That is, the polarities of the fixed charges inside the first insulating layer 21A and the second insulating layer 21B are opposite to each other.

[0056] In the support substrate according to the second embodiment of the present invention, the insulating layer has a multi-layer structure to reduce the apparent fixed charge of the insulating layer so as to reduce the mobile charge generated at the interface between the insulating layer and the charge trapping layer. Specifically, the first insulating layer in contact with the charge trapping layer is made very thin, and the polarity of the fixed charge inside the second insulating layer in contact therewith is made opposite to the polarity of the fixed charge inside the first insulating layer, thereby reducing the mobile charge generated inside the charge trapping layer.

[0057] In the second embodiment of the present invention, an insulating layer having a large internal fixed charge can be used, and therefore the material options are wider than in the first embodiment.

[0058] This provides the following effects. By further increasing the resistivity of the charge trapping layer, the effect of parasitic capacitance from the semiconductor substrate can be further reduced. The performance requirements for the charge trapping layer can be lowered. For example, the heat resistance temperature and heat resistance time of the constituent materials of the charge trapping layer can be extended, which reduces the restrictions on the manufacturing method and temperature in the device fabrication process. · The magnitude of the mobile charge generated can be precisely controlled, increasing process margins.

[0059] The supporting substrate according to the second embodiment of the present invention has the same configuration as the supporting substrate according to the first embodiment of the present invention, except for the insulating layer.

[0060] FIG. 10 shows the SiO 2 In the insulating layer having a two-layer structure including a first insulating layer made of SiO 2 10 is a graph showing the relationship between the film thickness and the fixed charge density of the insulating layer 10. FIG. 10 shows the combined fixed charge density (total fixed charge density of the two layers) of the insulating layer 10 at the interface with the charge trapping layer 10 made of polycrystalline Si.

[0061] The apparent fixed charge of the insulating layer that affects the interface between the charge trap layer and the first insulating layer has a relationship with the thickness of the first insulating layer as shown in FIG. 10. As shown in FIG. 10, the apparent fixed charge can be made very small by setting the thickness of the first insulating layer to 0.5 nm or more and 3 nm or less. Therefore, the thickness of the first insulating layer is 0.5 nm or more and 3 nm or less, and preferably 0.5 nm or more and 1.5 nm or less. The appropriate thickness of the first insulating layer varies depending on the magnitude of the fixed charge of the second insulating layer.

[0062] In order to suppress the variation of the fixed charge, it is preferable to use a material having a stable fixed charge as the constituent material of the first insulating layer. Specifically, the constituent material of the first insulating layer is preferably a compound containing Si and at least one selected from the group consisting of O, N, F, and C, or a compound containing Al and O, such as SiO 2 , SiN, SiOF, SiOC or Al 2 O 3 It is preferable that SiO 2 has a positive fixed charge, and SiOF, SiOC, and Al 2 O 3 has a negative fixed charge. SiN can be made to have a positive or negative fixed charge depending on the formation conditions. These materials can be formed by thermal oxidation treatment of the surface of polycrystalline Si or the like that constitutes the charge trapping layer, oxidation treatment using plasma, nitridation treatment using plasma, fluorination treatment using plasma, carbonization treatment using plasma, film formation methods (CVD, sputtering, ALD, deposition), etc. Among these, it is preferable to form the first insulating layer by surface treatment of polycrystalline Si, since this can eliminate the unstable state of the natural oxide film on the polycrystalline Si surface and make the surface stable.

[0063] The material of the second insulating layer may be any material having a fixed charge of opposite polarity to that of the first insulating layer, such as SiN or SiO 2 It is preferable that:

[0064] The thickness of the second insulating layer is preferably 3 nm or more. If the thickness of the second insulating layer is 3 nm or more, the effect is constant, so the thicker the second insulating layer, the better, but for example, the thicker the second insulating layer is, for example, 2000 nm or less.

[0065] The second insulating layer can be formed by using a deposition method such as CVD or sputtering.

[0066] The thickness of each layer, such as the first insulating layer, the second insulating layer, etc., can be calculated by measuring the thickness at any ten points on a cross section observed with a transmission electron microscope (TEM) and averaging the measured values.

[0067] The support substrate of the present invention can be used, for example, as a support substrate for a low-capacity capacitor for high-frequency applications to suppress the deterioration of Q characteristics due to parasitic capacitance with a semiconductor substrate in high-frequency bands. Similarly, the support substrate can be used as a support substrate for passive electronic components such as surface acoustic wave elements having single-crystal piezoelectric thin films and membrane-type bulk acoustic wave elements (FBARs) used in high-frequency bands to obtain the same effect as a capacitor. Thus, passive electronic components having the support substrate of the present invention are also one aspect of the present invention.

[0068] Specific examples of passive electronic components including the support substrate of the present invention will be described below. Examples of passive electronic components include capacitors, surface acoustic wave elements, and bulk acoustic wave elements. A semiconductor device including the support substrate of the present invention is also one aspect of the present invention. The semiconductor device may be a passive electronic component such as a capacitor, or may be a device including a passive electronic component such as a capacitor.

[0069] Fig. 11 is a cross-sectional view showing an example of a capacitor including a support substrate of the present invention. Fig. 12 is a plan view showing an example of a capacitor including a support substrate of the present invention. Fig. 11 is a cross-sectional view taken along line XI-XI of the capacitor shown in Fig. 12.

[0070] 11 and 12 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, an insulating layer 21 provided on the charge trapping layer 11, a first electrode layer 22 provided on the insulating layer 21, a dielectric film 23 provided on the first electrode layer 22, a second electrode layer 24 provided on the dielectric film 23, a protective layer 25 covering the first electrode layer 22 and the second electrode layer 24, and an external electrode 26 penetrating the protective layer 25. The external electrode 26 includes a first external electrode 26A connected to the first electrode layer 22 and a second external electrode 26B connected to the second electrode layer 24. The first external electrode 26A penetrates the protective layer 25 and the dielectric film 23, and the second external electrode 26B penetrates the protective layer 25.

[0071] In the capacitor 200, the supporting substrate of the present invention is composed of the semiconductor substrate 10, the charge trapping layer 11, and the insulating layer 21. The insulating layer 21 may have the configuration described in the first embodiment of the present invention or the configuration described in the second embodiment.

[0072] The first electrode layer 22 is provided at a position away from the edge of the semiconductor substrate 10. In other words, the edge of the first electrode layer 22 is located inside the edge of the semiconductor substrate 10.

[0073] The material constituting the first electrode layer 22 is not particularly limited, but is preferably Cu, Ag, Au, Al, Ni, Cr or Ti, or an alloy containing at least one of these metals.

[0074] The dielectric film 23 is provided so as to cover the first electrode layer 22 except for the opening, and the end of the dielectric film 23 is also provided on the surface of the insulating layer 21 from the end of the first electrode layer 22 to the end of the semiconductor substrate 10.

[0075] The material constituting the dielectric film 23 is not particularly limited, but is preferably SiO 2 , SiN, Al 2 O 3 , HfO 2 , Ta 2 O 5 and the like oxides or nitrides.

[0076] The second electrode layer 24 is provided opposite the first electrode layer 22 with the dielectric film 23 interposed therebetween.

[0077] The material constituting the second electrode layer 24 is not particularly limited, but is preferably Cu, Ag, Au, Al, Ni, Cr or Ti, or an alloy containing at least one of these metals.

[0078] The protective layer 25 is provided so as to cover the dielectric film 23 and the second electrode layer 24 except for the opening overlapping the second electrode layer 24. Furthermore, the protective layer 25 has an opening at a position overlapping the opening of the dielectric film 23 (the opening overlapping the first electrode layer 22). By providing the protective layer 25, the capacitor element, in particular the dielectric film 23, is protected from moisture.

[0079] The material constituting the protective layer 25 is not particularly limited, but preferable examples include resin materials such as polyimide resin and resin in solder resist.

[0080] A moisture-resistant film may be provided between the dielectric film 23 and the protective layer 25. In this case, the moisture-resistant film is provided so as to cover the dielectric film 23 and the second electrode layer 24 except for an opening overlapping the second electrode layer 24 and an opening overlapping the first electrode layer 22. By providing the moisture-resistant film, the moisture resistance of the capacitor element, in particular the dielectric film 23, is improved.

[0081] The material constituting the moisture-resistant film is not particularly limited, but is preferably SiO 2 Examples of the material include moisture-resistant materials such as SiN.

[0082] The material constituting the external electrode 26 is not particularly limited, but preferably includes Cu, Ni, Ag, Au, Al, etc. The external electrode 26 may have a single-layer structure or a multi-layer structure. The outermost surface of the external electrode 26 is preferably made of Au or Sn.

[0083] A capacitor having the above structure can be manufactured by a known method, for example, as described in International Publication No. 2019 / 021827, after producing the support substrate of the present invention.

[0084] FIG. 13 is a cross-sectional view illustrating a schematic diagram of another example of a capacitor including a support substrate of the present invention.

[0085] 13 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, an insulating layer 21 provided on the charge trapping layer 11, a first electrode layer 22 provided on the insulating layer 21, a dielectric film 23 provided on the first electrode layer 22, a second electrode layer 24 provided on the dielectric film 23, a third electrode layer 27 provided on the dielectric film 23 away from the second electrode layer 24, a protective layer 25 covering the second electrode layer 24 and the third electrode layer 27, and an external electrode 26 penetrating the protective layer 25. The external electrode 26 includes a first external electrode 26A connected to the third electrode layer 27 and a second external electrode 26B connected to the second electrode layer 24. The first external electrode 26A penetrates the protective layer 25, and the second external electrode 26B penetrates the protective layer 25.

[0086] In the configuration of the capacitor 200 shown in FIG. 11, a capacitor is formed on the left side, whereas in the configuration of the capacitor 210 shown in FIG. 13, capacitors are formed on the left and right sides. In the configuration shown in FIG. 13, the portion where the first external electrode 26A is connected to the first electrode layer 22 in the configuration shown in FIG. 11 is simply replaced with a configuration in which the first electrode layer 22, the dielectric film 23, and the third electrode layer 27 are provided in this order. Therefore, the configuration shown in FIG. 13 does not require additional element formation space compared to the configuration shown in FIG. 11. Therefore, a capacitor with a low capacitance can be fabricated while maintaining the same element area. Such a structure is effective when it is not possible to form a dielectric film with a certain thickness or more.

[0087] FIG. 14 is a cross-sectional view that illustrates an example of a surface acoustic wave element including a support substrate according to the present invention.

[0088] The surface acoustic wave element 300 shown in FIG. 14 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, an insulating layer 21 provided on the charge trapping layer 11, a single crystal piezoelectric thin film 31 provided on the insulating layer 21, an IDT (InterDigital Transducer) electrode 32 provided on the single crystal piezoelectric thin film 31, a protective layer 35 covering the IDT electrode 32, and an external electrode 36 penetrating the protective layer 35.

[0089] In the surface acoustic wave element 300, the supporting substrate of the present invention is composed of the semiconductor substrate 10, the charge trapping layer 11, and the insulating layer 21. The insulating layer 21 may have the configuration described in the first embodiment of the present invention or the configuration described in the second embodiment.

[0090] FIG. 15 is a cross-sectional view illustrating an example of a bulk acoustic wave element including a support substrate according to the present invention.

[0091] 15 includes a semiconductor substrate 10, a charge trapping layer 11 provided on the semiconductor substrate 10 and having a higher density of crystal defects than the semiconductor substrate 10, an insulating layer 21 provided on the charge trapping layer 11, a first electrode layer 42 provided on the insulating layer 21, a piezoelectric film 43 provided on the first electrode layer 42, a second electrode layer 44 provided on the piezoelectric film 43, a protective layer 45 covering the first electrode layer 42, the piezoelectric film 43 and the second electrode layer 44, and an external electrode 46 penetrating the protective layer 45. The external electrode 46 includes a first external electrode 46A connected to the first electrode layer 22 and a second external electrode 46B connected to the second electrode layer 24. The first external electrode 46A penetrates the protective layer 45, and the second external electrode 46B penetrates the protective layer 45.

[0092] 15, a cavity 47 is formed in at least a part of the semiconductor substrate 10 below a region where the first electrode layer 42 and the second electrode layer 44 overlap each other. Therefore, the bulk acoustic wave element 400 has a so-called membrane structure.

[0093] In the bulk acoustic wave element 400, the supporting substrate of the present invention is composed of the semiconductor substrate 10, the charge trapping layer 11, and the insulating layer 21. The insulating layer 21 may have the configuration described in the first embodiment of the present invention or the configuration described in the second embodiment.

[0094] The semiconductor device of the present invention, which is an example of the passive electronic component of the present invention, has a high Q characteristic and is therefore suitable for use as a capacitor in a matching circuit or a filter circuit. A matching circuit or a filter circuit including the semiconductor device of the present invention is also one aspect of the present invention.

[0095] FIG. 16 is an explanatory diagram illustrating an example of a matching circuit.

[0096] For example, by using the semiconductor device of the present invention for the capacitor C of the matching circuit shown in FIG. 16, the power consumption of the entire circuit can be suppressed.

[0097] FIG. 17 is an explanatory diagram illustrating an example of a filter circuit.

[0098] For example, by using the semiconductor device of the present invention for the capacitor C1 of the filter circuit shown in FIG. 17, the power consumption of the entire circuit can be reduced. [Explanation of symbols]

[0099] 1, 1A, 1a, 2 Support substrate (support substrate for passive electronic components) 10, 100 Semiconductor substrate 11 Charge trapping layer 12 Inversion Region 13 Depletion Layer 21, 121 Insulating layer 21A First insulating layer 21B Second insulating layer 22, 42 1st electrode layer 23 Dielectric Film 24, 44 Second electrode layer 25, 35, 45 protective layer 26, 36, 46 external electrode 26A, 46A 1st external electrode 26B, 46B 2nd external electrode 27 Third electrode layer 31 Single crystal piezoelectric thin film 32 IDT electrode 43 Piezoelectric Film 47 Cavity 122, 123 electrode 200, 210 Capacitor (semiconductor device) 300 Surface acoustic wave element (semiconductor device) 400 Bulk acoustic wave elements (semiconductor devices)

Claims

1. A semiconductor substrate; a charge trapping layer provided on the semiconductor substrate, the charge trapping layer having a high density of crystal defects relative to the semiconductor substrate; an insulating layer provided on the charge trapping layer; Equipped with the insulating layer is made of silicon nitride; A support substrate for passive electronic components, wherein the atomic concentration ratio of N to the total amount of Si and N contained in the insulating layer is 45 atom % or less.

2. The support substrate according to claim 1 , wherein the semiconductor substrate is a single crystal Si substrate.

3. The supporting substrate according to claim 1 , wherein the charge trapping layer is made of polycrystalline Si or amorphous Si.

4. 2. The supporting substrate according to claim 1, wherein the atomic concentration ratio of N to the total amount of Si and N contained in said insulating layer is 44 atom % or less.

5. The supporting substrate according to claim 1 , wherein the fixed charge within the insulating layer is positive.

6. 6. The supporting substrate according to claim 5, wherein a combination of the conductivity type of said semiconductor substrate and the conductivity type of said charge trapping layer is p-type-p-type, p-type-n-type or n-type-p-type.

7. 2. The supporting substrate according to claim 1, wherein the atomic concentration ratio of N to the total amount of Si and N contained in said insulating layer is more than 44 atom % and is 45 atom % or less.

8. The supporting substrate according to claim 1 , wherein the fixed charge within the insulating layer is negative.

9. 9. The supporting substrate according to claim 8, wherein a combination of the conductivity type of said semiconductor substrate and the conductivity type of said charge trapping layer is n-type-n-type, n-type-p-type or p-type-n-type.

10. A semiconductor substrate; a charge trapping layer provided on the semiconductor substrate, the charge trapping layer having a high density of crystal defects relative to the semiconductor substrate; an insulating layer provided on the charge trapping layer; Equipped with the insulating layer includes a first insulating layer provided on the charge trapping layer and a second insulating layer provided on the first insulating layer; the polarity of the fixed charges inside the first insulating layer is opposite to that of the second insulating layer, A support substrate for passive electronic components, wherein the first insulating layer has a thickness of 0.5 nm or more and 3 nm or less.

11. The support substrate according to claim 10 , wherein the semiconductor substrate is a single crystal Si substrate.

12. The supporting substrate according to claim 10 , wherein the charge trapping layer is made of polycrystalline Si or amorphous Si.

13. The supporting substrate according to claim 10, wherein the constituent material of the first insulating layer is a compound containing Si and at least one selected from the group consisting of O, N, F, and C, or a compound containing Al and O.

14. The supporting substrate according to claim 10 , wherein the first insulating layer is formed by subjecting a surface of the charge trapping layer to a thermal oxidation treatment, a plasma oxidation treatment, a plasma nitridation treatment, a plasma fluoridation treatment, or a plasma carbonization treatment.

15. The second insulating layer is made of SiN or SiO ２ The supporting substrate according to claim 10 ,

16. The supporting substrate according to claim 10 , wherein the second insulating layer has a thickness of 3 nm or more.

17. A passive electronic component comprising the support substrate according to any one of claims 1 to 16.

18. A supporting substrate according to any one of claims 1 to 16, A first electrode layer provided on the support substrate; a dielectric film provided on the first electrode layer; a second electrode layer provided on the dielectric film; a protective layer covering the first electrode layer and the second electrode layer; and an external electrode penetrating the protective layer.

19. A matching circuit comprising the semiconductor device according to claim 18.

20. A filter circuit comprising the semiconductor device according to claim 18.

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