Fast Fourier transform device and digital filter device

Abstract

To solve a problem that a conventional high-speed Fourier transformation device has a small processing latency in digital signal processing using high-speed Fourier transformation, and is insufficient in suppressing a circuit scale and power consumption of a circuit that implements digital signal processing.SOLUTION: A high-speed Fourier transformation device of the present invention includes: a data rearrangement processing unit 12 that rearranges N pieces of first input data in a first order and outputs N pieces of the first output data in a second order; a twist multiplication processing unit 31 that performs twist multiplication processing by multiplying the N pieces of first output data by a twist coefficient and outputs the N pieces of first output data in the second order; and a butterfly computation processing unit 22 that performs butterfly computation processing on the N pieces of first output data and outputs the N pieces of second output data in the second order. The second order is an order in which the N pieces of second output data X(k) and X(N-k) have a time difference within one cycle and a bit transition rate between consecutive cycles of a twist coefficient is small.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a fast Fourier transform device and a digital filter device for performing digital signal processing. [Background technology]

[0002] Fast Fourier Transform (hereinafter referred to as "FFT") processing is one of the important processes in digital signal processing. For example, frequency domain equalization (FDE) technology is known as a technique for compensating for waveform distortion during signal transmission in wireless and wired communications. In frequency domain equalization, first, signal data in the time domain is converted to data in the frequency domain by fast Fourier transform, and then filtering is performed for equalization. The filtered data is then reconverted to signal data in the time domain by inverse fast Fourier transform (hereinafter referred to as "IFFT"), thereby compensating for waveform distortion of the original time domain signal. Hereinafter, when there is no distinction between FFT and IFFT, it will be written as "FFT / IFFT".

[0003] Generally, in FFT / IFFT processing, a "butterfly operation" is used. In this butterfly operation, data arranged in a sequential order is read out and processed in an order that follows a predetermined rule. For this reason, butterfly operation requires rearrangement of data, and a RAM (Random Access Memory) circuit is mainly used to realize the circuit. In this case, when realizing high-speed and low-power consumption of the downstream processing of the FFT device, the order of data output from the FFT device becomes important. Therefore, Patent Document 1 describes a technology for optimizing the output timing and output order of the processing results of FFT processing, with the aim of high-speed and low-power consumption of the downstream processing of the FFT device.

[0004] The fast Fourier transform device described in Patent Document 1 includes a first transform means that performs a fast Fourier transform or an inverse fast Fourier transform to generate a plurality of first output data and output the data in a first order, and a first data rearrangement processing means that rearranges the plurality of first output data output in the first order into a second order based on an output order setting. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6358096 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 describes an FFT device capable of inputting data to be processed and outputting the processing results in any order, and is capable of outputting outputs X(k) and X(Nk) with a time difference of at most one cycle or less. However, Patent Document 1 discloses a method of implementing FFT processing by repeatedly using one butterfly computation circuit assigned to each of the two stages of butterfly processing multiple times for an FFT data flow decomposed into two stages of butterfly processing by the Prime Factor method, but does not disclose an optimal configuration when the parallelism of processing is further increased to further speed up FFT processing. More specifically, Patent Document 1 describes a method of implementing FFT processing by repeatedly using one butterfly computation circuit assigned to each of the two stages of butterfly processing multiple times for an FFT data flow decomposed into two stages of butterfly processing by the Prime Factor method, but does not disclose an optimal configuration when the parallelism of processing is further increased to further speed up FFT processing. More specifically, Patent Document 1 describes a method of implementing FFT processing by repeatedly using one butterfly computation circuit assigned to each of the two stages of butterfly processing multiple times for a ... Large However, there is a problem in that it is not possible to suppress the circuit scale and power consumption of the circuit that realizes the digital signal processing. [Means for solving the problem]

[0007] One aspect of a fast Fourier transform device according to the present invention includes a data rearrangement processing unit that rearranges N pieces of first input data (N is an integer) in a first order and outputs N pieces of first output data in a second order; a twiddle multiplication processing unit that performs a twiddle multiplication process on the N pieces of first output data by a twiddle coefficient and outputs N pieces of first output data in the second order; and a butterfly calculation processing unit that performs a butterfly calculation process on the N pieces of first output data and outputs N pieces of second output data in the second order, wherein the second order is an order in which, for any index k of N pieces of second output data X(k) (0≦k≦N-1) ranging from 1 to N-1, there is a time difference between X(k) and X(Nk) of one cycle or less, and the bit transition rate between successive cycles of the twiddle coefficient is small.

[0008] Moreover, one aspect of a digital filter device according to the present invention includes the above-mentioned fast Fourier transform device; complex conjugate generation means for generating second complex data including respective complex conjugates from first complex data which is a time domain complex number and is constituted by the N second output data outputted by the fast Fourier transform device; filter coefficient generation means for generating first and second frequency domain filter coefficients of complex numbers from first, second and third input filter coefficients of an input complex number; first filter means for filtering the first complex data with the first frequency domain filter coefficient and outputting third complex data; second filter means for filtering the second complex data with the second frequency domain filter coefficient and outputting fourth complex data; and complex conjugate synthesis means for synthesizing the third complex data and the fourth complex data to generate fifth complex data. Effect of the Invention

[0009] The present invention provides a digital filter device that has a small processing latency in digital signal processing using fast Fourier transform, and has a small circuit scale and small power consumption for implementing the digital signal processing. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of an FFT device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an arrangement of data sets in a sequential order according to the first embodiment. [Diagram 3] FIG. 2 is a diagram showing an arrangement of data sets in a bit reverse order according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the calculation order of radix-8 butterfly calculation processing according to the first embodiment. [Diagram 5] FIG. 4 is a diagram showing an arrangement of data sets in a power optimization data set sequential order according to the first embodiment. [Figure 6] FIG. 4 is a diagram showing an arrangement of twiddle coefficients in a sequential order of a power optimization data set according to the first embodiment; [Figure 7] FIG. 4 is a diagram showing the calculation order of radix-8 butterfly calculation processing according to the first embodiment. [Figure 8] FIG. 2 is a block diagram showing an example of the configuration of a first data rearrangement circuit and a second data rearrangement circuit according to the first embodiment. [Figure 9] FIG. 13 is a block diagram showing an example of the configuration of a third data rearrangement processing circuit according to the first embodiment. [Figure 10] 1 is a block diagram showing an example of the configuration of a digital filter circuit according to a first embodiment. [Figure 11] 1 is a block diagram showing a configuration of a complex conjugate generating circuit according to a first embodiment. [Figure 12] 1 is a block diagram showing a configuration of a filter circuit according to a first embodiment. [Figure 13] 1 is a block diagram showing a configuration of a filter circuit according to a first embodiment. [Figure 14] 1 is a block diagram showing a configuration of a complex conjugate synthesis circuit according to a first embodiment. FIG. [Figure 15] 1 is a block diagram showing a configuration of a filter coefficient generating circuit according to a first embodiment. [Figure 16]FIG. 5 illustrates a data flow 500 for 64-point FFT processing using two stages of butterfly operations. [Figure 17] FIG. 1 is a block diagram showing a configuration of an FFT device including a data rearrangement circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) Fig. 1 is a block diagram showing an example of the configuration of an FFT device 10 according to the first embodiment. The FFT device 10 processes a 64-point FFT decomposed into two stages of radix-8 butterfly processing using a pipeline circuit system in accordance with a data flow 500 shown in Fig. 16. The FFT device 10 inputs time domain data x(n) (n = 0, 1,..., N-1), performs a Fourier transform on x(n) using FFT processing, and generates and outputs a frequency domain signal X(k) (k = 0, 1,..., N-1). Here, N is a positive integer representing an FFT block size.

[0012] The FFT device 10 includes a first data rearrangement unit 11, a first butterfly calculation unit 21, a second data rearrangement unit 12, a twiddle multiplication unit 31, a second butterfly calculation unit 22, and a read address generation unit 41. The FFT device 10 performs pipeline processing of the first data rearrangement process, the first butterfly calculation process, the second data rearrangement process, the twiddle multiplication process, and the second butterfly calculation process.

[0013] The first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 are buffer circuits for rearrangement of data. The first data rearrangement processing unit 11 rearranges the data sequence before the first butterfly calculation processing unit 21 based on the data dependency on the algorithm of the FFT processing. Similarly, the second data rearrangement processing unit 12 inputs the read address 51 after the first butterfly calculation processing unit 21 and rearranges the data sequence based on the data dependency on the algorithm of the FFT processing. Furthermore, in addition to the above rearrangement, the second data rearrangement processing unit 12 performs rearrangement processing for outputting the outputs X(k) and X(Nk) of the FFT device 10 in the same cycle for any k between 1 and N-1.

[0014] The FFT device 10 performs 64-point FFT processing with 8 data in parallel. In this case, the FFT circuit 10 inputs time domain data x(n), and generates and outputs a frequency domain signal X(k) that has been Fourier transformed by FFT processing. At this time, a total of 64 pieces of data are input as the input data x(n) in the order shown in Fig. 2 for a period of 8 cycles, with 8 pieces of data input at a time. Note that the numbers from 0 to 63 shown as the contents of the table in Fig. 2 refer to the subscript n of x(n).

[0015] Specifically, in the 0th cycle, eight pieces of data x(0), x(1),..., x(7) constituting the data set P0 are input. Then, in the 1st cycle, eight pieces of data x(8), x(9),..., x(15) constituting the data set P1 are input. Similarly, in the 2nd to 7th cycles, data constituting the data sets P2 to P7 are input.

[0016] Next, the first data rearrangement unit 11 rearranges the input data x(n) from the “sequential order” shown in FIG. 2, which is the input order, into the “bit-reverse order” shown in FIG. 3, which is the order in which the data is input to the first butterfly calculation unit 21.

[0017] The bit reverse order shown in Fig. 3 corresponds to the input data set to the first-stage radix-8 butterfly process 502 in the data flow diagram shown in Fig. 16. Specifically, the first data rearrangement unit 11 outputs eight pieces of data, x(0), x(8), . . . , x(56), constituting data set Q0, in the 0th cycle. Then, it outputs eight pieces of data, x(1), x(9), . . . , x(57), constituting data set Q1, in the 1st cycle. Thereafter, it outputs the data constituting data sets Q3 to Q7 in the same manner in the 2nd to 7th cycles.

[0018] Here, the "sequential order" and "bit reverse order" will be specifically explained. The "sequential order" refers to the order related to the eight data sets P0 to P7 shown in FIG. 2. Each data set Ps (s=0, 1, . . . , 7) is made up of eight data items arranged in order from ps(0) to ps(7), and ps(i) is p(i)=8x+i In other words, sequential ordering is when i·s pieces of data are arranged in order starting from the first piece of data, with each piece being arranged in i-piece order, to create s sets of data.

[0019] The "bit reverse order" refers to the order of the eight data sets Q0 to Q7 shown in Fig. 3. Each data set Qs (s = 0, 1, ..., 7) is made up of eight data items qs(0) to qs(7), and qs(i) is qs(i)=s+8i In other words, bit reverse order is when i·s pieces of data are arranged in 8-bit order starting from the first piece of data, i pieces at a time, to create s data sets.

[0020] As described above, the i-th data constituting each data set Qs (s=0, 1, . . . , 7) in the bit-reverse order is the s-th data constituting the data set Pi in the sequential order. That is, Qs(i)=Pi(s) In this way, Qs(i) and Pi(s) are in a relationship in which the order of the data sets and the order of the data positions within the data sets are interchanged for the data that make up each data set. Therefore, when data input in bit reverse order is rearranged according to the bit reverse order, it becomes sequential order.

[0021] Each row ps(i) in Fig. 2 and each row qs(i) in Fig. 3 indicate data to be input to the i-th data in the next stage. The eight numbers included in each data set are identification information that specifies one of the FFT points, specifically, the value of the subscript n of x(n).

[0022] The sequential order and bit reverse order are not limited to those exemplified in Figures 2 and 3. That is, each data set in the sequential order may be created by arranging data in order according to the number of FFT points, the number of cycles, and the number of data to be processed in parallel, as described above. And each data set in the bit reverse order may be created by interchanging the order of the data input in the sequential order with respect to the progress of the cycles and the order with respect to the data positions, as described above.

[0023] The first butterfly calculation processing unit 21 is a butterfly circuit that processes a first butterfly calculation process 502 (first butterfly calculation process) of the radix-8 butterfly calculation process performed in two stages in the data flow 500 in Fig. 16. The first butterfly calculation processing unit 21 is composed of a radix-8 butterfly calculation processing unit 21a, and performs radix-8 butterfly calculation process. Specifically, the first butterfly calculation processing unit 21 processes eight radix-8 butterfly calculation processes #0 to #7 constituting the butterfly calculation process 502 in the order shown in Fig. 4.

[0024] That is, in cycle 0, the radix-8 butterfly calculation processing unit 21a inputs a data set Q0 in a bit-reverse order corresponding to the radix-8 butterfly calculation process #0 output by the first data rearrangement processing unit 11, and performs a radix-8 butterfly calculation process #0. In cycle 1, the radix-8 butterfly calculation processing unit 21a inputs a data set Q1 in a bit-reverse order corresponding to the radix-8 butterfly calculation process #1 output by the first data rearrangement processing unit 11, and performs a radix-8 butterfly calculation process #1. In cycle 2, the radix-8 butterfly calculation processing unit 21a inputs a data set Q2 in a bit-reverse order corresponding to the radix-8 butterfly calculation process #2 output by the first data rearrangement processing unit 11, and performs a radix-8 butterfly calculation process #2. In cycle 3, the radix-8 butterfly calculation processing unit 21a inputs data set Q3 in bit-reverse order output by the first data rearrangement processing unit 11 and corresponding to the radix-8 butterfly calculation process #3, and performs the radix-8 butterfly calculation process #3. Similarly, in the subsequent cycles, in cycles 4 to 7, the radix-8 butterfly calculation processing unit 21a inputs data sets Q4 to Q7 in bit-reverse order output by the first data rearrangement processing unit 11 and corresponding to the radix-8 butterfly calculation processes #4 to #7, respectively, and performs the radix-8 butterfly calculation processes #4 to #7.

[0025] The first butterfly calculation unit 21 outputs the results of the butterfly calculation process as data y(n)(0, 1, . . . , 63) in the sequential order shown in FIG.

[0026] The second data rearrangement unit 12 rearranges the data y(n) output in sequential order by the first butterfly computation unit 21 into the order shown in Fig. 5 (hereinafter referred to as the "power-optimized data set bit-reverse order"). The "power-optimized data set bit-reverse order" refers to the order in which s data sets Qs created in the bit-reverse order are output as the cycle progresses, and is the output order setting52. In this embodiment, the power optimized data set bit reverse order is specified as Q3, Q5, Q1, Q7, Q0, Q2, Q6, Q4, and the data set Q3 is output in cycle 0, the data set Q5 in cycle 1, the data set Q1 in cycle 2, the data set Q7 in cycle 3, the data set Q0 in cycle 4, the data set Q2 in cycle 5, the data set Q6 in cycle 6, and the data set Q4 in cycle 7.

[0027] The second data rearrangement unit 12 inputs the read addresses 51 output by the read address generation unit 41 and determines the output order. The read address generation unit 41 refers to an output order setting 52 provided from a higher-level circuit (not shown) such as a CPU (Central Processing Unit), Second data sorting unit 12 The read address 51 is generated and output to the

[0028] The twiddle multiplication processing unit 31 is a circuit that processes complex rotation on a complex plane in an FFT operation after the first butterfly operation processing, and corresponds to the twiddle multiplication processing 504 in the data flow 500 in Fig. 16. Note that in the twiddle multiplication processing, data rearrangement is not performed.

[0029] The twiddle multiplication processing unit 31 is composed of a twiddle coefficient table 31a and a twiddle multiplication unit 31b. The twiddle coefficient table 31a outputs a twiddle coefficient W(n) (n=0,1,...,63) corresponding to the data y(n) (n=0,1,...,63) output by the second data rearrangement processing unit 12 in the "power optimized data set bit reverse order". W(n) is a twiddle coefficient corresponding to the data y(n). Therefore, the order in which the twiddle multiplication processing unit 31 outputs the twiddle coefficient W(n) is uniquely determined by the "power optimized data set bit reverse order" which is the order in which the second data rearrangement processing unit 12 outputs the rearranged data. Specifically, when the second data rearrangement processing unit 12 outputs in the "power optimized data set bit reverse order" shown in FIG. 5, the twiddle coefficient table 31a outputs the twiddle coefficient in the order shown in FIG. 6. As is clear from FIGS. 5 and 6, the twiddle coefficients W(n) (n=0, 1, . . . , 63) output by the twiddle multiplication processing unit 31 correspond to y(n) output by the second data rearrangement processing unit 12.

[0030] The twiddle multiplication unit 31b performs twiddle multiplication processing by multiplying y(n) output by the second data rearrangement unit 12 by the twiddle coefficient W(n) output by the twiddle multiplication unit 31, and outputs the result to the second butterfly calculation processing unit 22.

[0031] The second butterfly computation unit 22 is a butterfly circuit that processes a second butterfly computation process 503 (second butterfly computation process) of the radix-8 butterfly computation process performed in two stages in the data flow 500 in Fig. 16. The second butterfly computation unit 22 is composed of a radix-8 butterfly computation unit 22a, and processes the radix-8 butterfly computation process. Specifically, the second butterfly computation unit 22 processes eight radix-8 butterfly computation processes #0 to #7 constituting the butterfly computation process 503 in the order shown in Fig. 7.

[0032] That is, in cycle 0, the radix-8 butterfly computation processing unit 22a inputs a data set Q3 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #3 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #3. In cycle 1, the radix-8 butterfly computation processing unit 22a inputs a data set Q5 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #5 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #5. In cycle 2, the radix-8 butterfly computation processing unit 22a inputs a data set Q1 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #1 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #1. In cycle 3, the radix-8 butterfly computation processing unit 22a inputs a data set Q7 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #7 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #7. In cycle 4, the radix-8 butterfly computation processing unit 22a inputs a data set Q0 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #0 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #0. In cycle 5, the radix-8 butterfly computation processing unit 22a inputs a data set Q2 in the bit-reverse order of the power-optimized data set corresponding to the radix-8 butterfly computation process #2 output by the second data rearrangement processing unit 12, and performs the radix-8 butterfly computation process #2. In cycle 6, the radix-8 butterfly computation unit 22a inputs a data set Q6 in the bit-reverse order of the power optimized data set corresponding to the radix-8 butterfly computation process #6 output by the second data rearrangement unit 12, and performs the radix-8 butterfly computation process #6. In cycle 7, the radix-8 butterfly computation unit 22a inputs a data set Q4 in the bit-reverse order of the power optimized data set corresponding to the radix-8 butterfly computation process #4 output by the second data rearrangement unit 12, and performs the radix-8 butterfly computation process #4.

[0033] The second butterfly calculation unit 22 outputs the butterfly calculation result X(k) (k=0, 1, . . . , 63) in the same power-optimized data set bit-reverse order.

[0034] The first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 temporarily store input data and control the selection and output of the stored data, thereby realizing data rearrangement processing according to the bit reverse order of Fig. 3 and the power optimized data set bit reverse order of Fig. 5. A specific example of a data rearrangement processing unit is shown below.

[0035] The first data rearrangement processing unit 11 can be realized by, for example, a data rearrangement processing unit 100 shown in FIG.

[0036] Data rearrangement processing unit 100 inputs data sets D0 to D7 consisting of eight pieces of data input as input information 103, two data sets at a time in first-in order in a FIFO buffer (First In First Out Buffer), and writes and stores the data sets in data storage locations 101a to 101h. Specifically, data sets D0 to D7 are stored in data storage locations 101a to 101h, respectively.

[0037] Next, the data rearrangement processing unit 100 outputs the stored data in units of two data sets in the first-out order in the FIFO buffer. Specifically, the data rearrangement processing unit 100 reads eight data from each of the data read positions 102a to 102h, organizes them into one data set, and outputs the eight data sets D0' to D7' as output information 104. In this way, the data sets D0' to D7' are formed by rearranging the data included in the data sets D0 to D7 arranged in cycle order in the order of the data positions into one set.

[0038] 8 is a configuration diagram of a data rearrangement processing unit 200 showing an example of realizing the second data rearrangement processing unit 12. The data rearrangement processing unit 200 inputs data sets P0 to P7 consisting of eight pieces of data input as input information 203, two data sets at a time in the first-in order in the FIFO buffer, and writes and stores them in data storage positions 201a to 201h. That is, data sets D0 to D7 are stored in order in the data storage positions 201a to 201h corresponding to the cycle order. At this time, when the stored data is viewed in the order of the data positions, that is, in the order of the data storage positions 202a to 202h, data sets D0' to D7' are stored in each of the data storage positions 202a to 202h.

[0039] Next, the data rearrangement processing unit 200 reads the stored data one data set at a time by the read circuit 205 and outputs it as output information 204. At this time, the read circuit 205 refers to the read address 51, selects one of the data storage locations 202a to 202h, and reads one of the eight data stored in the data storage locations 202a to 202h in one read operation. In this way, by providing the read addresses in a desired combination and order that can be arbitrarily specified to the read address 51, data can be read in an arbitrary combination and order. For example, when the read addresses are provided to the read address 51 in the order of addresses 3, 5, 1, 7, 0, 2, 6, and 4, the data rearrangement processing unit 200 outputs the stored data in the order of data sets D3', D5', D1', D7', D0', D2', D6', and D4'. That is, the data is output in the power optimization data set bit reverse order shown in FIG. 5. Here, the data sets D0' to D7' are formed by rearranging the data included in the data sets D0 to D7, which are arranged in cycle order, in the order of data position into one set.

[0040] As described above, in the FFT device 10, the first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 perform two rearrangement processes according to the sequential order in FIG. 2, the bit-reverse order in FIG. 3, and the power-optimized data set bit-reverse order in FIG. 5, respectively.

[0041] By controlling the first data rearrangement unit 11 and the second data rearrangement unit 12 as described above, the processing order of the radix-8 butterfly computation processing performed by the first butterfly computation unit 21 and the second butterfly computation unit 22 can be controlled to the order shown in Fig. 4 and Fig. 7, respectively. As a result, multiple data required for the next stage of processing can be output at the same timing, eliminating the need for further data rearrangement. The data rearrangement in the second data rearrangement unit 12 and the processing order in the second butterfly computation unit 22 will be described below as examples.

[0042] An example will be described in which 64-point FFT processing is performed with 8 data in parallel using the FFT device 10 shown in Fig. 1. The FFT device 10 inputs time domain data x(n) (n = 0, 1, . . . , 63), and generates and outputs frequency domain signals X(k) (k = 0, 1, . . . , 63) that have been Fourier transformed by FFT processing. The input data x(n) is input in the sequential order shown in Fig. 2, with 8 data pieces per 8 cycles, and a total of 64 pieces of data x(n) are input. Note that only the suffix n of x(n) is shown in Fig. 2.

[0043] in particular, 0 In the 1st cycle, eight pieces of data x(0), x(1),..., x(7) constituting data set P0 are input. Then, in the 1st cycle, eight pieces of data x(8), x(9),..., x(15) constituting data set P1 are input. Similarly, in the 2nd to 7th cycles, data constituting data sets P2 to P7 are input.

[0044] On the other hand, the output data X(k) outputs 64 pieces of data in total, for example, in the power optimization data set bit reverse order shown in Fig. 5, for a period of 8 cycles, with 8 pieces of data each. Note that Fig. 5 only shows the subscript k of X(k). Specifically, the following data is output in each cycle. In cycle 0, eight pieces of data X(3), X(11), . . . , X(59) constituting data set Q3 are output. In cycle 1, eight data items X(5), X(13), . . . , X(61) constituting data set Q5 are output. In cycle 2, eight data items X(1), X(9), . . . , X(57) constituting data set Q1 are output. In cycle 3, eight data items X(7), X(15), . . . , X(63) constituting data set Q7 are output. In cycle 4, eight pieces of data X(0), X(8), . . . , X(56) constituting data set Q0 are output. In cycle 5, eight data items X(2), X(10), . . . , X(58) constituting data set Q2 are output. In cycle 6, eight data items X(6), X(14), . . . , X(62) constituting data set Q6 are output. In cycle 7, eight data items X(4), X(12), . . . , X(60) constituting data set Q4 are output.

[0045] In this way, two output data X1(k1) and X2(k2) whose sum of subscripts k1 and k2 is 64 corresponding to the number of FFT points are always output in consecutive cycles. That is, the FFT device 10 can output outputs X(k) and X(Nk) (N=64) for any subscript k between 1 and N-1 with a time difference of at most one cycle.

[0046] As described above, in this embodiment, by outputting the data sets Q3, Q5, Q1, Q7, Q0, Q2, Q6, Q4 in the order in cycles 0 to 7, it is possible to output the outputs X(k) and X(Nk) (N=64) with a time difference of at most one cycle. However, there are a number of data set orders that can output the outputs X(k) and X(Nk) (N=64) with a time difference of at most one cycle other than the order in this embodiment. For example, even if the data sets are output in the order Q0, Q7, Q1, Q6, Q2, Q5, Q3, Q4, or the order Q0, Q7, Q2, Q5, Q3, Q4, Q1, Q6, the outputs X(k) and X(Nk) (N=64) can be output with a time difference of at most one cycle. Hereinafter, the order that can output the outputs X(k) and X(Nk) (N=64) with a time difference of at most one cycle is called the "optimized data set bit reverse order."

[0047] Here, we will explain the difference between the "power optimized data set bit reverse order" adopted in this embodiment, which is the order of data sets Q3, Q5, Q1, Q7, Q0, Q2, Q6, Q4, and the "optimized data set bit reverse order" which is the order of data sets Q0, Q7, Q1, Q6, Q2, Q5, Q3, Q4, etc.

[0048] In this embodiment, the output order of the FFT device 10 is determined by the power optimized data set bit reverse order, which is the output order of the second data rearrangement processing unit 12. Similarly, the order in which the twiddle multiplication processing unit 31 of this embodiment outputs the twiddle coefficients W(n) is determined by the power optimized data set bit reverse order, which is the output order of the second data rearrangement processing unit 12, and specifically, the order shown in FIG.

[0049] The value of the twiddle coefficient W(n) is a value specific to the FFT process and does not depend on the value of the data input by the FFT device 10. In FIG. 6, the data sets W0 to W7 are each composed of eight pieces of data from ws(0) to ws(7), and the values ​​of ws(0) to ws(7) change from cycle 0 to cycle 7 according to the order of W3, W5, W1, W7, W0, W2, W6, and W4, which is the bit reverse order of the power optimization data sets. Here, when focusing on the power consumption of the twiddle multiplication processing unit 31, the magnitude of change in the values ​​of the eight pieces of data from ws(0) to ws(7) greatly affects the power consumption. Specifically, in the binary value obtained by expressing the twiddle coefficient W(n) in binary, the bit-wise operation rate (toggle rate) of the eight pieces of data from ws(0) to ws(7) greatly affects the power consumption. The dynamic power consumption (P) of a digital signal processing circuit implemented using a CMOS (Complementary Metal Oxide Semiconductor) circuit can be expressed by the following formula (1): P = (1 / 2) * a * C * V2 * f (1) Where: a: circuit operation rate, C: Load capacity, V: voltage, f: Operating frequency This is because the bitwise operation rate of the eight data from ws(0) to ws(7) greatly affects the circuit operation rate a. In other words, selecting an output order that reduces the bitwise operation rate of the eight data from ws(0) to ws(7) is effective in reducing the power consumption of the twiddle multiplication processing unit 31.

[0050] As a specific method for selecting the output order that reduces the bitwise operation rate of the eight data from ws(0) to ws(7), there is a method that uses the Hamming distance as an index. The Hamming distance is the distance between two pieces of data, and in the case of binary data, it is equal to the number of bits that differ between the two binary data. In other words, the operation rate when a certain twiddle coefficient data is changed is equal to the Hamming distance between the coefficient data value before the change and the coefficient data value after the change. Therefore, the operation rate for the twiddle coefficient W(n) can be calculated by the sum of the Hamming distances for the twiddle coefficient W(n) during FFT processing.

[0051] For example, the operation rate for the twiddle factor W(n) in the power-optimized data set bit-reverse order shown in FIG. 6 is expressed as follows: If the Hamming distance between twiddle factors W(i) and W(j) is expressed as Hamming(i,j) and the Hamming distance for data ws(i) is expressed as H(i), then data ws(0) is W(3) in cycle 0, W(5) in cycle 1, W(1) in cycle 2, W(7) in cycle 3, W(0) in cycle 4, W(2) in cycle 5, W(6) in cycle 6, and W(4) in cycle 7. H(0)=Hamming(3,5)+Hamming(5,5)+Hamming(1,7)+Hamming(7,0)+Hamming(0,2)+Hamming(2,6)+Hamming(6,4) It can be calculated as follows.

[0052] Similarly, for H(1) to H(7), H(1)=Hamming(11,13)+Hamming(13,9)+Hamming(9,15)+Hamming(15,8)+Hamming(8,10)+Hamming(10,14)+Hamming(14,12) H(2)=Hamming(19,21)+Hamming(21,17)+Hamming(17,23)+Hamming(23,16)+Hamming(16,18)+Hamming(18,22)+Hamming(22,20) H(3)=Hamming(27,29)+Hamming(29,25)+Hamming(25,31)+Hamming(31,24)+Hamming(24,26)+Hamming(26,30)+Hamming(30,28) H(4)=Hamming(35,37)+Hamming(37,33)+Hamming(33,39)+Hamming(39,32)+Hamming(32,34)+Hamming(34,38)+Hamming(38,36) H(5)=Hamming(43,45)+Hamming(45,41)+Hamming(41,47)+Hamming(47,40)+Hamming(40,42)+Hamming(42,46)+Hamming(46,44) H(6)=Hamming(51,53)+Hamming(53,49)+Hamming(49,55)+Hamming(55,48)+Hamming(48,50)+Hamming(50,54)+Hamming(54,52) H(7)=Hamming(59,61)+Hamming(61,57)+Hamming(57,63)+Hamming(63,56)+Hamming(56,58)+Hamming(58,62)+Hamming(62,60) It can be calculated as follows.

[0053] Therefore, the operation rate A for the twist coefficient W(n) is calculated by the sum P of the Hamming distances for the twist coefficient W(n) as follows: A=P=H(0)+H(1)+H(2)+H(3)+H(4)+H(5)+H(6)+H(7) It can be calculated as follows.

[0054] The "power optimized data set bit reverse order" of this embodiment is an order selected from among multiple candidates of the "optimized data set bit reverse order" that is an order that can output the outputs X(k) and X(Nk) (N=64) with a time difference of at most one cycle or less, with the smallest operation rate A for this twiddle coefficient W(n). In other words, the "power optimized data set bit reverse order" of this embodiment can be said to be an order with the smallest power consumption related to the twiddle coefficient table 31a that outputs the twiddle coefficient W(n) among multiple candidates of the "optimized data set bit reverse order".

[0055] On the other hand, the twiddle multiplication unit 31b constituting the twiddle multiplication processing unit 31 is affected by the operation rate of y(n) output by the second data rearrangement processing unit 12 in addition to the operation rate of the twiddle coefficient W(n). However, since the FFT device 10 inputs arbitrary data, the operation rate of y(n) is considered to be constant in the long term regardless of the order in which y(n) is output. Similarly, since the FFT device 10 inputs arbitrary data, the operation rates of the data rearrangement processing unit and butterfly calculation processing unit constituting the FFT device 10 are also considered to be constant in the long term regardless of the order of processing. Therefore, the "power optimized data set bit reverse order" of this embodiment can be said to be the order that consumes the least power of the FFT device 10 among multiple candidates for the "optimized data set bit reverse order".

[0056] (Effects of the First Embodiment) As described above, in this embodiment, the FFT device 10 can output data in any order by specifying the order using the output order setting 52.

[0057] For example, in the case where a calculation is performed between X(k) and X(Nk) for output data X(k) (k=0, 1, . . . , N-1) and an arbitrary subscript k is 1 or more and N-1 or less inclusive, in the latter stage of the FFT device 10, X(k) and X(Nk) can be output with a time difference of at most one cycle or less. As a result, there is no need to add a circuit for newly rearranging the output.

[0058] Moreover, the only circuit that needs to be added to enable specification of the order in which the output data is to be output is the read address generation unit 41, and the circuit scale is very small.

[0059] Therefore, it is possible to suppress increases in the overall processing latency, circuit size, and power consumption, including the processing at the subsequent stages.

[0060] Furthermore, in this embodiment, the twiddle multiplication process is performed in an order that minimizes the power consumption, thereby reducing the power consumption of the entire FFT process.

[0061] In this embodiment, FFT processing has been described as an example, but the same applies to IFFT. That is, by applying the control method of this embodiment to an IFFT processing device and optimizing the output order of the processing results in consideration of the processing contents of the latter stages of the IFFT processing, it is possible to speed up the processing of the latter stages of the IFFT processing.

[0062] Second embodiment 10 is a block diagram showing a configuration of a digital filter circuit 400 according to the second embodiment of the present invention. The digital filter circuit 400 includes an FFT circuit 413, an IFFT circuit 414, a complex conjugate generation circuit 415, a complex conjugate synthesis circuit 416, a filter circuit 421, a filter circuit 422, and a filter coefficient generation circuit 441.

[0063] The digital filter circuit 400 is a filter for a complex signal in the time domain. x(n) = r(n) + j(n) (1) Enter.

[0064] The FFT circuit 413 converts the input complex signal x(n) into a frequency domain complex signal 431 by FFT. X(k) = A(k) + jB(k) (2) Convert to.

[0065] Here, n is an integer where 0 ≦ n ≦ N - 1 indicating the signal sample number in the time domain, N is an integer where 0 < N indicating the number of conversion samples of the FFT, and k is an integer where 0 ≦ k ≦ N - 1 indicating the frequency number in the frequency domain.

[0066] Also, the FFT circuit 413, from X(k), X(N - k)=A(N - k)+jB(N - k) ···(3) generates and outputs it.

[0067] The complex conjugate generation circuit 415 inputs X(N - k) output by the FFT circuit 413 for each frequency number k where 0 ≦ k ≦ N - 1, and the complex conjugate of X(N - k) X*(N - k)=A(N - k)-jB(N - k) ···(4) is generated.

[0068] The complex conjugate generation circuit 415 outputs the input complex number signal X(k) as the complex number signal 432, and outputs the generated complex number signal X*(N - k) as the complex number signal 433.

[0069] Next, the filter coefficient generation circuit 441, for each frequency number k where 0 ≦ k ≦ N - 1, from the input complex number coefficients V(k), W(k), and H(k), the complex number coefficients C1(k)={V(k)+W(k)}×H(k) ···(5) and the complex number coefficient C2(k)={V(k)-V(k)}×H(k) ···(6) are generated.

[0070] Here, the complex number coefficients V(k), W(k), and H(k) are coefficients in the frequency domain given from an upper circuit (not shown) of the digital filter circuit 400, and correspond to the real filter coefficients in the case of performing filter processing by real number operations in the time domain. Details of V(k), W(k), and H(k) will be described later.

[0071] The filter coefficient generation circuit 441 outputs the generated complex coefficient C1(k) as a complex signal 445. The filter coefficient generation circuit 441 also generates a complex signal C2(Nk) from the complex signal C2(k) (equation (6)) and outputs it as a complex signal 446.

[0072] Next, the filter circuit 421 performs complex filtering by complex multiplication on X(k) (equation (2)) output by the complex conjugate generation circuit 415 to the complex signal 432, using C1 (equation (5)) output by the filter coefficient generation circuit 441 to the complex signal 445. Specifically, the filter circuit 421 performs complex filtering by complex multiplication on X(k) (equation (2)) output by the complex conjugate generation circuit 415 to the complex signal 432, using C1 (equation (5)) output by the filter coefficient generation circuit 441 to the complex signal 445. X'(k) = X(k) × C1(k) (7) and outputs it as a complex signal 434.

[0073] Similarly, the filter circuit 422 performs complex filtering by complex multiplication on X*(Nk) (equation (4)) output by the complex conjugate generation circuit 415 to the complex signal 433, using C2(Nk) (equation (6)) output by the filter coefficient generation circuit 441 to the complex signal 446. Specifically, the filter circuit 422 performs complex filtering by complex multiplication on X*(Nk) (equation (4)) output by the complex conjugate generation circuit 415 to the complex signal 433, using C2(Nk) (equation (6)) output by the filter coefficient generation circuit 441 to the complex signal 446. X * '(Nk)=X * (Nk) × C2(Nk) (8) and outputs it as a complex signal 435. C1(k) and C2(k) are divided into real and imaginary parts, respectively. C1(k)=C1I(k)+jC1Q(k) ···(9) C2(k)=C2I(k)+JC2Q(k) ···(10) can be written as:

[0074] Next, the complex conjugate synthesis circuit 416 is a filter circuit 4The complex conjugate synthesis circuit 416 generates a complex signal X"(k) by synthesizing X'(k) (equation (7)) output by the filter circuit 421 to the complex signal 434 and X*'(Nk) (equation (8)) output by the filter circuit 422 to the complex signal 435. Specifically, for each frequency number k in the range of 0≦k≦N-1, the complex conjugate synthesis circuit 416 calculates X"(k)=1 / 2×{X'(k)+X * '(Nk)} ···(11) and outputs it as a complex signal 436.

[0075] Next, for each frequency number k (0≦k≦N−1), the IFFT circuit 414 generates and outputs a time-domain complex signal x″(n) by IFFT for X″(k) (equation (11)) output by the complex conjugate synthesis circuit 416 to the complex signal 436.

[0076] The FFT circuit 413 can be realized by using the FFT circuit 10 according to the first embodiment of the present invention. Alternatively, the FFT circuit 413 can be realized by using the FFT circuit 20 according to the second embodiment of the present invention.

[0077] 11 is a block diagram showing the detailed configuration of the complex conjugate generation circuit 415. The complex conjugate generation circuit 415 receives X(k) (=A(k)+jB(k), equation (2)) included in the output of the FFT circuit 413 and outputs it as is. Furthermore, the complex conjugate generation circuit 415 receives the output X(Nk) (=A(Nk)+jB(Nk), equation (3)) included in the output of the FFT circuit 413 and outputs X * (Nk) = A(Nk) - jB(Nk) (4) Calculate and output. X(k), X * (Nk) is divided into real and imaginary parts, X(k) = XI(k) + jXQ(k) (12) X * (Nk)=X * I(Nk)+jX * Q(Nk) (13) can be written as:

[0078] 12 is a block diagram showing the detailed configuration of the filter circuit 421. The filter circuit 421 receives X(k) (=XI(k)+jXQ(k), equation (12)) output from the complex conjugate generating circuit 415 to the complex signal line 432 and the complex coefficient C1(k) (=C1I(k)+jC1Q(k), equation (9)) and performs the following: X'(k) = XI'(k) + jXQ'(k) = X(k) × C1(k) (14) Calculate and output. Here, XI'(k) and XQ'(k) are the real and imaginary parts of X'(k), respectively, and are given by the following equations: XI'(k)=XI(k)×C1I(k)-XQ(k)×C1Q(k) ···(15) XQ'(k)=XI(k)×C1Q(k)+XQ(k)×C1I(k) ···(16)

[0079] 13 is a block diagram showing the detailed configuration of the filter circuit 422. The filter circuit 422 filters the X * (Nk)(=X * I(Nk)+jX * Q(Nk). Equation (13)) and the complex coefficient C2(k) = C2I(k) + JC2Q(k). Equation (10)) are input, X *’ (Nk)=X * I'(Nk)+jX * Q'(Nk) =X*(Nk)×C2(Nk) (17) Calculate and output. where X * I'(Nk) and X * Q'(Nk) is X *’ (Nk) are the real and imaginary parts, given by: X * I'(Nk)=X * I(Nk)×C2I(Nk)-X * Q(Nk) × C2Q(Nk) (18) X * Q'(Nk)=X * I(Nk)×C2Q(Nk)-X * Q(Nk) × C2I(Nk) (19)

[0080] 14 is a block diagram showing the detailed configuration of the complex conjugate synthesis circuit 416. The complex conjugate synthesis circuit 416 is configured such that, for each frequency number k in the range of 0≦k≦N−1, the filter circuit 421 Complex Signal Line 434 and the X′(k) (=XI′(k)+jXQ′(k), equation (14)) output by the filter circuit 422 to the complex signal 435. *' (Nk)(=X * I'(Nk)+jX * Q'(Nk). Enter equation (17) and X"(k)=XI"(k)+jXQ"(k) =1 / 2{X'(k)+X * '(Nk)} ···(20) Calculate and output. where XI″(k) and XQ″(k) are the real and imaginary parts of X″(k), respectively, given by: XI"(k)=1 / 2{XI'(k)+X * I'(Nk)} ···(21) XQ"(k)=1 / 2{XQ'(k)+X * Q'(Nk)} (22) where XI'(k), XQ'(k), and X * I'(Nk), X * Q'(Nk) is expressed by equations (15), (16), (18), and (19), respectively.

[0081] The filter coefficient generation circuit 441 generates complex coefficients C1(k) and C2(k) used in the filter circuits 421 and 422. Fig. 18 is a block diagram showing the detailed configuration of the filter coefficient generation circuit 441. The filter coefficient generation circuit 441 calculates V(k)+W(k) and V(k)-W(k) from the complex coefficients V(k) and W(k) input from a higher-level circuit (not shown) for each frequency number k in the range of 0≦k≦N-1. Where: V(k)+W(k)=VI(k)+WI(k)+jVQ(k)+jWQ(k) ···(23) V(k)-W(k)=VI(k)-WI(k)+jVQ(k)-jWQ(k) ···(24) where VI(k) and VQ(k) are the real and imaginary parts of V(k), respectively, and WI(k) and WQ(k) are the real and imaginary parts of W(k), respectively. Also, H(k) can be divided into real and imaginary parts, H(k) = HI(k) + jHQ(k) (25) can be written as:

[0082] Next, the filter coefficient generation circuit 441 calculates and outputs complex coefficients C1(k) and C2(k) defined by the following equations: C1(k) = C1I(k) + jC1Q(k) = {V(k) + W(k)} × H(k) (26) C2(k) = C2I(k) + jCQ(k) = {V(k)-W(k)}×H(k) (27) Here, C1I(k) and C1Q(k) are the real and imaginary parts of C1(k), respectively, and C2I(k) and C2Q(k) are the real and imaginary parts of C2(k), respectively. Substituting equations (23) and (25) into equation (26), we get C1(k)={VI(k)+WI(k)+jVQ(k)+jWQ(k)}×{HI(k)+jHQ(k)}···(28) It is. Therefore, C1I(k)={VI(k)+WI(k)}×HI(k)-{VQ(k)+WQ(k)}×HQ(k)...(29) C1Q(k)={VQ(k)+WQ(k)}×HI(k)+{VI(k)+WI(k)}×HQ(k)...(30) It is. Similarly, substituting equations (24) and (25) into equation (27), we get C2(k) = C2I(k) + jC2Q(k) = {V(k)-W(k)}×H(k) ={VI(k)-WI(k)+jVQ(k)-jWQ(k)}×{HI(k)+jHQ(k)}···(31) It is. Therefore, C2I(k)={VI(k)-WI(k)}×HI(k)-{VQ(k)-WQ(k)}×HQ(k)...(32) C2Q(k)={VQ(k)-WQ(k)}×HI(k)+{VI(k)-WI(k)}×HQ(k)...(33) It is.

[0083] As described above, the digital filter circuit 400 performs FFT conversion on the input signal in the time domain to generate a complex signal in the frequency domain. The digital filter circuit 400 then performs independent filtering on the real part and the imaginary part of the complex signal in the frequency domain using two types of coefficients generated from V(k), W(k), and H(k), and converts the results into a signal in the time domain by IFFT. In this way, in the digital filter circuit 400, the FFT and IFFT are each performed only once on the input signal in the time domain.

[0084] The two types of coefficients used in the filter processing make it possible to minimize the number of FFTs and IFFTs. Below, we explain the physical meanings of V(k), W(k), and H(k) and the principle that filter processing using the coefficients C1(k) and C2(k) generated from them enables filter processing in the frequency domain that is equivalent to the desired filter processing in the time domain.

[0085] In this embodiment, a complex signal in the frequency domain obtained by complex FFT of an input time domain complex signal x(n) (=r(n)+js(n), Equation (1)) is X(k) = R(k) + jS(k) (34) Then, the complex conjugate generator 15 calculates X * Generate (Nk). Here, R(k) is a frequency domain complex signal obtained by transforming the real part signal r(n) of a real number in the time domain using a real-valued FFT, and S(k) is a frequency domain complex signal obtained by transforming the imaginary part signal s(n) of a real number in the time domain using a real-valued FFT. At this time, the following equation is established due to the symmetry of complex conjugates. X * (Nk) = R(k) - jS(k) (35) where X * (Nk) is the complex conjugate of X(Nk). From equations (14), (34) and (26), X'(k) = X(k) × C1(k) ={R(k)+jS(k)}×{V(k)+W(k)}×H(k) =R(k)V(k)H(k)+R(k)W(k)H(k)+jS(k)V(k)H(k)+jS(k)W(k)H(k) ···(36) It becomes. Moreover, from equations (17), (35) and (27), X * '(Nk)=X * (Nk) × C2(Nk) ={R(k)-jS(k)}×{V(k)-W(k)}×H(k) =R(k)V(k)H(k)-R(k)W(k)H(k)-jS(k)V(k)H(k)+jS(k)W(k)H(k) ···(37) It becomes. Substituting equations (36) and (37) into equation (20), we get X”(k)=1 / 2×{X’(k)+X * '(Nk)} =1 / 2×{2×R(k)V(k)H(k)+2×jS(k)W(k)H(k)} = R(k) V(k) H(k) + jS(k) W(k) H(k) ={R(k)V(k)+jS(k)W(k)}×H(k) ···(38) It becomes.

[0086] Equation (38) expresses the signal X″(k) before IFFT using filter coefficients V(k), W(k), and H(k) and R(k) and S(k) in the signal X(k) after FFT. R(k) is a complex signal in the frequency domain obtained by transforming a real part signal r(n) of a real number in the time domain by a real FFT. S(k) is a complex signal in the frequency domain obtained by transforming a real imaginary part signal s(n) of a real number in the time domain by a real FFT. In other words, equation (38) expresses the content of the filter processing performed on the signal X(k) after FFT. It can be seen from equation (38) that the digital filter circuit 400 performs processing equivalent to the following three filter processes on the frequency domain complex signal X(k) (=R(k)+jS(k); equation (34)) generated by transforming the complex signal x(n)=r(n)+js(n) by a real FFT.

[0087] 1) Filtering R(k) with coefficient V(k) First, the digital filter circuit 400 performs a filter process using a filter coefficient V(k) on a complex signal R(k) in the frequency domain, which is a result of transforming a real part signal r(n) in the time domain by a real-number FFT. Therefore, V(k) is assigned a complex filter coefficient in the frequency domain, which corresponds to a real filter coefficient when a filter process using real-number arithmetic is performed on the real part signal r(n) in the time domain.

[0088] 2) Filtering S(k) with coefficient W(k) Similarly, the digital filter circuit 400 performs filtering using a filter coefficient W(k) on a complex signal S(k) in the frequency domain obtained by converting an imaginary part signal s(n) in the time domain using a real-number FFT. Therefore, a complex filter coefficient in the frequency domain that corresponds to a real filter coefficient when filtering is performed on the imaginary part signal s(n) in the time domain using a real-number operation is assigned to W(k).

[0089] 3) Filtering the results of 1) and 2) using coefficient H(k) Next, the digital filter circuit 400 performs a filter process using a filter coefficient H(k) on a complex signal R(k)V(k)+jS(k)W(k) consisting of R(k)V(k) and S(k)W(k) after the above two independent filter processes.

[0090] R(k)V(k)+jS(k)W(k) is a complex signal in the frequency domain that corresponds to a time domain signal consisting of two signals obtained by independently filtering the real part signal r(n) and the imaginary part signal s(n) in the time domain. The signals obtained by independently filtering the real part signal r(n) and the imaginary part signal s(n) are X'(k) and X'(k) in Figs. 12 and 13. * 10. The time domain signal consisting of r'(n) and s'(n) corresponds to x''(n) in FIG. 10. In this way, R(k)V(k)+jS(k)W(k) is a frequency domain signal that corresponds to the time domain signal obtained by independently filtering the real and imaginary parts in the time domain.

[0091] Therefore, to perform a process equivalent to a filter process using complex arithmetic on a complex signal in the time domain on a frequency domain signal R(k)V(k)+jS(k)W(k), the following coefficients should be used: That is, H(k) should be assigned a complex filter coefficient in the frequency domain that corresponds to the complex filter coefficient when a filter process using complex arithmetic is performed on a complex signal x(n) in the time domain.

[0092] As described above, in this embodiment, three types of coefficients are set from the outside. That is, frequency domain filter coefficients V(k) and W(k) corresponding to the filter coefficients in the time domain for the real part and imaginary part of the complex signal x(n), respectively, and a frequency domain coefficient H(k) corresponding to the filter coefficient in the time domain for x(n) are set. By performing a filter process using two coefficients obtained from the above three coefficients, it is possible to perform the FFT before the filter process and the IFFT after the filter process only once each.

[0093] (Effects of the second embodiment) As described above, according to this embodiment, a filter process is performed using two types of frequency domain filter coefficients corresponding to the filter coefficients in the time domain for the real part and the imaginary part of the complex signal, and a frequency domain coefficient corresponding to the filter coefficients in the time domain for the complex signal. That is, a filter process is performed in the frequency domain corresponding to an independent filter process by real number arithmetic for each of the real part and the imaginary part of the complex signal in the time domain, and a filter process by complex number arithmetic for the complex signal in the time domain. Therefore, a desired filter process can be realized by using only one FFT circuit for performing FFT before the filter process and one IFFT circuit for performing IFFT after the filter process. As a result, there is an effect that the circuit scale and power consumption for performing the filter process can be reduced.

[0094] Furthermore, the FFT circuit 10 according to the first embodiment of the present invention or the FFT circuit 20 according to the second embodiment of the present invention can be used to realize an FFT circuit or an IFFT circuit. As described above, the FFT circuit according to the embodiment of the present invention can output X(k) and X(Nk) in the same cycle for any index k between 1 and N-1. Therefore, in the filter processing, it is not necessary to add a circuit for rearrangement. Therefore, by using the FFT circuit according to the embodiment of the present invention for the filter processing, there is an effect that the circuit scale and power consumption for performing the filter processing can be reduced.

[0095] The present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0096] 10 FFT device 11, 12 Data sorting processing unit 21, 22 Butterfly calculation processing unit 21a, 22a Radix-8 butterfly calculation processing unit 31 Twist multiplication processing unit 41 Read address generator 51 Read Address 52 Output Order Settings 100, 200 Data sorting processing unit 101a~101h Data storage location 102a~102h Data read position 201a~201h Data storage location 202a~202h Data read position 400 Digital Filter Circuit 413 FFT circuit 414 IFFT circuit 415 Complex Conjugate Generator 416 Complex Conjugate Synthesis Circuit 421 Filter Circuit 422 Filter Circuit 431~436 Complex signal 441 Filter coefficient generation circuit 445, 446 Complex Signals 500 Data Flow 501 Data sorting process 502, 503 Butterfly calculation processing 504 Twist Calculation Processing 505 Partial Data Flow 600 FFT equipment 601 FFT section 602 Data sorting processing unit

Claims

1. a data rearrangement processing unit that rearranges N pieces of first input data (N is an integer) in a first order and outputs N pieces of first output data in a second order; a twiddle multiplication processing unit that performs a twiddle multiplication process by multiplying the N pieces of first output data by a twiddle coefficient and outputs the N pieces of first output data in the second order; a butterfly operation processing unit that performs butterfly operation processing on the N pieces of first output data and outputs N pieces of second output data in the second order; Has The second order is an order in which, for any index k of N pieces of second output data X(k) (0≦k≦N-1) that is 1 or more and N-1 or less, there is a time difference between X(k) and X(N-k) that is within one cycle, and the bit-wise operation rate (toggle rate) between successive cycles of the twiddle coefficients is smallest.

2. 2. The fast Fourier transform device according to claim 1, wherein when the N pieces of second output data are X(k) (k is an integer of 0≦k≦N-1, and N is a number of points of fast Fourier transform or inverse fast Fourier transform where N>0), the data rearrangement processing unit outputs X(k) and X(N-k) for any k with a time difference of one cycle or less.

3. 3. The fast Fourier transform device according to claim 1, wherein the data rearrangement processing unit selects a candidate that has the smallest sum of Hamming distances related to the twiddle coefficients from among a plurality of candidates for an optimized data set bit reverse order that is an order that can output the second output data X(k) and X(N−k) with a time difference of at most one cycle or less.

4. A stage preceding the data sorting unit, 4. The fast Fourier transform device according to claim 1, further comprising a front-stage butterfly operation processing unit that performs butterfly operation processing on front-stage input data and outputs the first input data.

5. A fast Fourier transform device according to any one of claims 1 to 4, a complex conjugate generating means for generating second complex data including complex conjugates of the first complex data, the second output data being a complex number in the time domain and being configured by the N pieces of second output data outputted by the fast Fourier transform device; a filter coefficient generating means for generating first and second frequency domain filter coefficients of complex numbers from the first, second and third input filter coefficients of complex numbers; a first filter means for filtering the first complex data with the first frequency domain filter coefficient and outputting third complex data; a second filter means for filtering the second complex data with the second frequency domain filter coefficient and outputting fourth complex data; a complex conjugate synthesis means for synthesizing the third complex data and the fourth complex data to generate fifth complex data; A digital filter device comprising:

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