FILTER PROCESSING DEVICE, FILTER PROCESSING METHOD, COMMUNICATION SYSTEM, AND PROGRAM

Abstract

In order to perform subcarrier separation without adding a dedicated storage unit, provided is a filter processing device comprising: an address control unit that specifies, on the basis of the offset amount of a light source frequency and a subcarrier center point for each subcarrier, a write address and a read address for a plurality of items of data included in Fourier transform data based on an optical signal; and a storage unit in which a plurality of items of data are written to the write address specified by the address control unit and in which data is read out from the read address specified by the address control unit. The address control unit specifies the write address and the read address so that compensation for the offset amount and the separation of the subcarrier are performed in the same storage unit.

Description

[Technical field]

[0001] The present disclosure relates to a filter device and the like used in optical communications. [Background technology]

[0002] Multi-subcarrier communication has been developed to accommodate the increased distances and capacity of optical communication. In multi-subcarrier communication, optical communication is carried out using multiple carrier waves called subcarriers. Therefore, in multi-subcarrier communication, it is necessary to separate the subcarriers from the optical signal used in optical communication.

[0003] Patent Document 1 discloses a communication device that transmits multiple optical signals by frequency multiplexing. The device of Patent Document 1 sets the transmission band of the optical filter unit to match the signal band of the transmission signal after band narrowing in the transmission path to the receiving communication device. The device of Patent Document 1 inputs the transmission signal before transmission into the optical filter unit to limit the signal band, and transmits the transmission signal with the limited signal band. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 134889 Summary of the Invention [Problem to be solved by the invention]

[0005] The method of Patent Document 1 required a dedicated storage unit to perform subcarrier separation. If a dedicated storage unit is provided to perform subcarrier separation, the circuit size and power consumption will increase. Therefore, a technology for performing subcarrier separation without adding a dedicated storage unit is required.

[0006] An object of the present disclosure is to provide a filter processing device and the like that can perform subcarrier separation without adding a dedicated storage unit. [Means for solving the problem]

[0007] A filter processing device according to an aspect of the present disclosure includes an address control unit that specifies write addresses and read addresses of a plurality of data included in Fourier transform data based on an optical signal based on an offset amount of a light source frequency and a subcarrier center point for each subcarrier, and a storage unit that writes the plurality of data to the write addresses specified by the address control unit and reads the data from the read addresses specified by the address control unit. The address control unit specifies the write addresses and read addresses such that compensation for the offset amount and separation of the subcarriers are performed in the same storage unit.

[0008] In a filter processing method according to one aspect of the present disclosure, a computer specifies write addresses and read addresses for multiple pieces of data contained in Fourier transform data based on an optical signal in a memory unit, writes the multiple pieces of data to the write addresses in the specified memory unit, and reads the data from the read addresses in the specified memory unit, so that compensation for the offset amount and separation of the subcarriers are performed in the same memory unit based on the offset amount of the light source frequency and the subcarrier center point for each subcarrier.

[0009] A program of one embodiment of the present disclosure causes a computer to execute the following processes: designating write addresses and read addresses of multiple pieces of data contained in Fourier transform data based on an optical signal to a memory unit, writing multiple pieces of data to the write addresses of the designated memory unit, and reading data from the read addresses of the designated memory unit, so that compensation for the offset amount and separation of the subcarriers are performed in the same memory unit based on the offset amount of the light source frequency and the subcarrier center point for each subcarrier. Effect of the Invention

[0010] According to the present disclosure, it is possible to provide a filter processing device or the like that can perform subcarrier separation without adding a dedicated storage unit. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of a configuration of a communication system according to a first embodiment. [Diagram 2] 2 is a conceptual diagram showing an example of FFT (Fast Fourier Transform) data input to the filter processing device according to the first embodiment. FIG. [Diagram 3] 4 is a conceptual diagram for explaining a light source frequency offset compensation process executed by the filter processing device according to the first embodiment. FIG. [Figure 4] FIG. 2 is a conceptual diagram for explaining a subcarrier separation process executed by the filter processing device according to the first embodiment. [Diagram 5] 3A to 3C are conceptual diagrams for explaining data arrangements before and after offset compensation processing and subcarrier separation processing by the filter processing device according to the first embodiment. [Figure 6] 5 is a flowchart illustrating an example of an operation of the filter processing device according to the first embodiment. [Figure 7] FIG. 1 is a block diagram showing an example of a configuration of a filter processing device according to Related Art 1. [Figure 8] 1A and 1B are conceptual diagrams for explaining data arrangements before and after offset compensation processing by a filter processing device according to Related Art 1. [Figure 9] 1A and 1B are conceptual diagrams for explaining data arrangements before and after a subcarrier separation process performed by a filter processing device according to Related Art 1. [Figure 10] FIG. 11 is a block diagram showing an example of a configuration of a communication system according to a second embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a coefficient calculation processing unit of a filter processing device according to a second embodiment. [Figure 12]10 is a flowchart illustrating an example of an operation of the filter processing device according to the second embodiment. [Figure 13] FIG. 13 is a block diagram showing an example of a configuration of a filter processing device according to Related Art 2. [Figure 14] 13 is a conceptual diagram for explaining compensation coefficients used in compensation processing other than offset compensation processing and subcarrier separation processing by the filter processing device according to the second embodiment. FIG. [Figure 15] FIG. 11 is a block diagram showing an example of a configuration of a communication system according to a third embodiment. [Figure 16] FIG. 13 is a block diagram showing an example of the configuration of a storage unit of a filter processing device according to a third embodiment. [Figure 17] FIG. 13 is a block diagram showing an example of the internal configuration of a partial storage unit included in a storage unit of a filter processing device according to a third embodiment. [Figure 18] FIG. 13 is a conceptual diagram for explaining an offset compensation process executed by a filter processing device according to a third embodiment. [Figure 19] 13A and 13B are conceptual diagrams for explaining data arrangements before and after offset compensation processing and subcarrier separation processing by a filter processing device according to a third embodiment. [Figure 20] 13 is a conceptual diagram for explaining an example of writing data to a plurality of partial memories included in a memory unit of a filter processing device according to a third embodiment. FIG. [Figure 21] FIG. 13 is a conceptual diagram for explaining another example of writing data to a plurality of partial memories included in a memory unit of the filter processing device according to the third embodiment. [Figure 22] FIG. 13 is a conceptual diagram for explaining an example of reading data from a plurality of partial memories included in a memory unit of a filter processing device according to a third embodiment. [Figure 23] FIG. 13 is a block diagram showing an example of a configuration of a filter processing device according to a fourth embodiment. [Figure 24]FIG. 2 is a block diagram showing an example of a hardware configuration for implementing control and processing of a filter processing device according to each embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments for carrying out the present invention will be described with reference to the drawings. However, the embodiments described below are limited in a manner that is technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following. In all the drawings used to explain the following embodiments, the same reference numerals are used for similar parts unless otherwise specified. Furthermore, in the following embodiments, repeated explanations of similar configurations and operations may be omitted.

[0013] (First embodiment) First, a communication system according to a first embodiment will be described with reference to the drawings. The communication system of this embodiment is used for optical communication. The communication system of this embodiment performs offset compensation processing and subcarrier separation processing on digital data (hereinafter also referred to as data) that has been subjected to Fast Fourier Transform (FFT). In this embodiment, attention is focused on the offset compensation processing and the subcarrier separation processing, and the filtering processing that is usually performed is omitted.

[0014] (composition) 1 is a block diagram showing an example of the configuration of a communication system 1 according to this embodiment. The communication system 1 includes a Fourier transform device 110, a filtering device 10, and an inverse Fourier transform device 120. The filtering device 10 is connected to the Fourier transform device 110 and the inverse Fourier transform device 120.

[0015] The Fourier transform unit 110 performs FFT processing on the AD (Analog Digital) converted time domain signal to convert it into frequency domain data (also called FFT data). The Fourier transform unit 110 outputs the FFT data to the filter processing unit 10.

[0016] FIG. 2 is a conceptual diagram for explaining FFT data X(ω) input to the filter processing device 10. In the example of FIG. 2, the FFT data X(ω) is composed of 16 discrete data. One cycle includes four data. Data numbers 1 to 4 are assigned to the data for each cycle. In the example of FIG. 2, numbers 0 to 15 (also called sample numbers) are written on the 16 data included in the FFT data X(ω) before rearrangement. In the following, sample numbers are assigned to each of the multiple data based on the arrangement of data in the FFT data X(ω) before rearrangement. The sample numbers are assigned according to the frequency of the data. For example, data with data number 2 in cycle 2 is written as data 5. Even after the data constituting the FFT data X(ω) is rearranged, the sample numbers assigned to the data are maintained as they are. In this embodiment, an example in which the number of data constituting the FFT data X(ω) is 16 is given, but the number of data constituting the FFT data X(ω) is not particularly limited. For example, when 256 pieces of data are processed in parallel in 16 cycles, the number of pieces of data is 4096.

[0017] The filter processing device 10 includes an address control unit 11 and a storage unit 13. Sixteen pieces of data constituting FFT data X(ω) are input in parallel to the filter processing device 10 in four cycles. In the example of FIG. 2, data 0, data 4, data 8, and data 12 are input to the filter processing device 10 in the first cycle. Data 1, data 5, data 9, and data 13 are input to the filter processing device 10 in the second cycle. Data 2, data 6, data 10, and data 14 are input to the filter processing device 10 in the third cycle. Data 3, data 7, data 11, and data 15 are input to the filter processing device 10 in the fourth cycle. The data input to the filter processing device 10 is stored in the storage unit 13 in response to address designation by the address control unit 11. The data input to the filter processing device 10 is stored in a write address designated by the address control unit 11. The data stored in the storage unit 13 is read from a read address designated by the address control unit 11.

[0018] An offset amount based on an oscillation frequency (also called a light source frequency) of a local light source of the communication system 1 including the filter processing device 10 is input to the address control unit 11. For example, the offset amount is input to the address control unit 11 via an input device (not shown). The offset amount may be registered in advance in the address control unit 11. Also, the offset amount may be configured to be estimated by an offset estimation circuit (not shown).

[0019] FIG. 3 is a conceptual diagram for explaining the offset compensation process of the light source frequency. A plurality of data constituting the FFT data X(ω) are distributed around data 0, which is the strongest DC (Direct Current) component. The order of the compensation process before the offset (1) is data 0, data 1, data 2, . . . , data 14, and data 15. The offset amount of the signal input to the filter processing device 10 is compensated according to the light source frequency of the communication system 1. In the example of FIG. 3, the offset amount is +2. The order of the compensation process after the offset (2) is data 14, data 15, data 0, . . . , data 12, and data 13. In the example of FIG. 3, the signal values ​​of the data with weak intensity (data 7, data 8, and data 9) are set to 0. Setting the signal values ​​of unnecessary data to 0 is also called zero padding.

[0020] Further, the center point of each subcarrier (called a subcarrier center point) is input to the address control unit 11. For example, the subcarrier center point is input via an input device (not shown). The subcarrier center point may be registered in advance in the address control unit 11. In this embodiment, an example including two subcarriers is given, but the number of subcarriers is not particularly limited.

[0021] FIG. 3 is a conceptual diagram for explaining subcarriers included in FFT data X(ω). FFT data X(ω) includes subcarrier data SC0 and subcarrier data SC1. Subcarrier data SC0 is data 3 (frequency ω 0The subcarrier data SC1 includes eight pieces of data (15, 0, 1, 2, 3, 4, 5, 6) before and after (-4, +3). 1 ), and eight pieces of data (9, 10, 11, 12, 13, 14, 15, 0) before and after (-4, +3). When frequency offset compensation is performed, the sample number of the data included in each subcarrier data is shifted by +2. In the example of FIG. 3, subcarrier data SC0 and subcarrier data SC1 have partial overlapping signals. In this embodiment, the number of data for each subcarrier is preset, and the subcarrier data can be identified if the frequency of the center point of the subcarrier is identified.

[0022] The address control unit 11 generates data write addresses and read addresses based on the offset amount of the light source frequency and the center point of each subcarrier. The address control unit 11 specifies the generated write addresses and read addresses to the storage unit 13. The data written to the storage unit 13 according to the specification of the address control unit 11 is read from the storage unit 13 in an array in which the offset compensation process and the subcarrier separation process have been performed collectively.

[0023] A plurality of data constituting the FFT data X(ω) Fourier-transformed by the Fourier transform device 110 are input to the storage unit 13. For example, the storage unit 13 is realized by a storage device such as a memory such as a RAM (Random Access Memory) or a register. The storage unit 13 stores the plurality of data constituting the input FFT data X(ω) at a write address specified by the address control unit 11. The plurality of data stored in the storage unit 13 is read according to a read address specified by the address control unit 11. The plurality of data stored in the storage unit 13 is offset-compensated according to the designation by the address control unit 11, and is separated for each subcarrier and output. In this embodiment, the subcarrier data SC0 and the subcarrier data SC1 are output from the storage unit 13. For example, a configuration for performing serial-parallel conversion processing may be added as a pre-processing for subcarrier separation. In addition, a circuit or processing for compensating for skew of data after parallel conversion may be added.

[0024] FIG. 5 is a conceptual diagram showing a state in which data constituting the FFT data X(ω) input to the storage unit 13 is rearranged from an array (1) before rearrangement to an array (2) after rearrangement. The order of data in the array (1) before rearrangement is continuous in the time direction of the output of the Fourier transform device 110. The order of data in the array (2) after rearrangement is continuous in the parallel direction of the same time. In this embodiment, data is rearranged into an array that has been subjected to offset compensation processing and subcarrier separation processing by performing operations of writing and reading data to the storage unit 13 in parallel by address control. As a result, the FFT data X(ω) is offset compensated and separated for each subcarrier. In the example of FIG. 5, the data of the subcarrier data SC0 is rearranged to cycle 1-2, and the data of the subcarrier data SC1 is rearranged to cycle 3-4. The array of data constituting the subcarrier data is rearranged in an order that is easy to process in the inverse Fourier transform device 120.

[0025] The filter processing device 10 outputs subcarrier data separated for each of a plurality of subcarriers. The data constituting the subcarrier data is rearranged in an order that makes it easy to process in the inverse Fourier transform device 120. The plurality of subcarrier data output from the filter processing device 10 is input to the inverse Fourier transform device 120.

[0026] The inverse Fourier transform device 120 receives the plurality of subcarrier data output from the filter processing device 10. The inverse Fourier transform device 120 includes a transform circuit for each subcarrier. The inverse Fourier transform device 120 performs an inverse Fourier transform on the plurality of subcarrier data for each subcarrier, and converts the data into a time domain signal. The inverse Fourier transform device 120 outputs the subcarrier data converted into a time domain signal.

[0027] (operation) Next, an example of the operation of the filter processing device 10 of the communication system 1 will be described with reference to the drawings. Fig. 6 is a flowchart for explaining the operation of the filter processing device 10. In the process according to the flowchart of Fig. 6, the filter processing device 10 will be described as the subject of the operation.

[0028] In FIG. 6, first, the filter processing device 10 acquires the FFT data output from the Fourier transform device 110 (step S11).

[0029] Next, the filter processing device 10 generates write addresses and read addresses for FFT data based on the offset amount of the light source frequency and the subcarrier center point for each subcarrier (step S12).

[0030] Next, the filter processing device 10 stores the data constituting the FFT data in the storage unit 13 according to the set write address (step S13).

[0031] Next, the filter processing device 10 outputs the data stored in the storage unit 13 according to the set read address (step S14). The data output in step S14 is subcarrier data that has been offset compensated and separated for each subcarrier. The subcarrier data output from the filter processing device 10 is input to the inverse Fourier transform device 120. The subcarrier data input to the inverse Fourier transform device 120 is inverse Fourier transformed for each subcarrier.

[0032] [Related Technology 1] Here, a related technique 1 of the first embodiment will be described with reference to the drawings. This related technique is an example in which offset compensation processing and subcarrier separation processing are performed separately.

[0033] 7 is a block diagram showing an example of a configuration of a communication system 100 of the related art. The communication system 100 includes a Fourier transform device 115, a filtering device 150, and an inverse Fourier transform device 125. The filtering device 150 includes a first storage unit 151 and a second storage unit 152. The filtering device 150 is connected to the Fourier transform device 115 and the inverse Fourier transform device 125. The Fourier transform device 115 has a similar configuration to the Fourier transform device 110 of the first embodiment. The inverse Fourier transform device 125 has a similar configuration to the inverse Fourier transform device 120 of the first embodiment.

[0034] Data constituting the FFT data X(ω) is input to the first storage unit 151. The first storage unit 151 is a storage unit for offset compensation processing. The data input to the first storage unit 151 is rearranged according to the set offset amount and output. In the example of FIG. 7, the offset-compensated data Y(ω) is output from the first storage unit 151.

[0035] Data constituting the offset-compensated data Y(ω) is input to the second storage unit 152. The second storage unit 152 is a storage unit for separating subcarriers. The data input to the second storage unit 152 is rearranged according to the frequency of the center point of each subcarrier and output. In the example of FIG. 7, the subcarrier-separated subcarrier data SC0' and subcarrier data SC1' are output from the second storage unit 152 to the inverse Fourier transform device 120. The arrangement of the data constituting the subcarrier data is rearranged in an order that makes it easy to process in the inverse Fourier transform device 120. The subcarrier data SC0' and subcarrier data SC1' output from the second storage unit 152 are subjected to inverse Fourier transform processing for each subcarrier in the inverse Fourier transform device 120.

[0036] 8 is a conceptual diagram showing a state in which the data constituting the FFT data X(ω) input to the first storage unit 151 has been rearranged from an array before rearrangement (1) to an array during rearrangement (2). The data array during rearrangement (2) is the data configuration of offset-compensated data Y(ω). The data array during rearrangement (2) is the data array before rearrangement (1) that has been offset compensated by +2.

[0037] FIG. 9 is a conceptual diagram showing a state in which the data constituting the data Y(ω) input to the second storage unit 152 has been rearranged from an intermediate arrangement (2) to an arrangement (3) after rearrangement. The data Y(ω) is separated for each subcarrier. In the example of FIG. 9, the data of the subcarrier data SC0 is rearranged to cycle 1-2, and the data of the subcarrier data SC1 is rearranged to cycle 3-4. The subcarrier data SC0 includes data 13, data 14, data 15, data 0, data 1, data 2, data 3, and data 4. The subcarrier data SC1 includes data 7, data 8, data 9, data 10, data 11, data 12, data 13, and data 14.

[0038] In the technique of Related Art 1, a first storage unit 151 dedicated to offset compensation processing and a second storage unit 152 dedicated to subcarrier separation processing are provided. Also, in the technique of Related Art 1, offset compensation processing and subcarrier separation processing are performed in two stages. In contrast, according to the technique of the first embodiment, the write address and read address of data constituting the FFT data in the storage unit 13 are controlled according to the designation of the address control unit 11. Therefore, according to the technique of the first embodiment, offset compensation processing and subcarrier separation processing can be performed collectively without adding a dedicated storage unit for each processing.

[0039] As described above, the communication system of the present embodiment includes a Fourier transform device, a filter processing device, and an inverse Fourier transform device. The Fourier transform device performs a Fourier transform on a signal based on an optical signal. The Fourier transform device outputs Fourier transform data including a plurality of pieces of data after Fourier transform to the filter processing device. The filter processing device includes an address control unit and a storage unit. The address control unit specifies write addresses and read addresses of a plurality of pieces of data included in the Fourier transform data based on the optical signal based on an offset amount of the light source frequency and a subcarrier center point for each subcarrier. The address control unit specifies write addresses and read addresses so that the compensation of the offset amount and the separation of the subcarriers are performed in the same storage unit. The storage unit writes a plurality of pieces of data to the write addresses specified by the address control unit. The storage unit reads data from the read addresses specified by the address control unit. The inverse Fourier transform device acquires a plurality of pieces of data that have been subjected to the offset compensation process and the subcarrier separation process by the filter processing device. The inverse Fourier transform device performs an inverse Fourier transform on the plurality of pieces of data that have been subjected to the offset compensation process and the subcarrier separation process.

[0040] According to the method of the present embodiment, by addressing so that offset compensation processing and subcarrier separation processing are performed, subcarrier separation can be performed without adding a dedicated storage unit. That is, according to the present embodiment, the number of storage units is not increased for the subcarrier separation processing, so that the subcarrier separation processing can be performed while suppressing an increase in power consumption. In a general method, writing / reading to / from a storage unit is performed twice. According to the method of the present embodiment, writing / reading to / from the same storage unit only needs to be performed once. Therefore, according to the method of the present embodiment, the overall processing speed in the filter processing is improved by reducing the number of times of writing / reading to / from a storage unit.

[0041] In one aspect of the present embodiment, the address control unit specifies a write address and a read address so that offset compensation and subcarrier separation are performed simultaneously. According to this aspect, offset compensation processing and subcarrier separation processing can be performed simultaneously by writing / reading data to / from the address specified by the address control unit.

[0042] In one aspect of this embodiment, the address control unit sets the value of data that becomes unnecessary due to the frequency offset compensation process to 0. According to this aspect, it is possible to delete the value of unnecessary data included in the plurality of data.

[0043] Second Embodiment Next, a communication system according to a second embodiment will be described with reference to the drawings. An optical signal used in optical communication is converted by AD (Analog Digital) conversion and then FFT (Fast Fourier Transform). The FFT converted signal is subjected to multiple processes in the frequency domain. The communication system of this embodiment differs from the first embodiment in that after offset compensation and subcarrier separation, processes other than offset compensation and subcarrier separation are performed collectively.

[0044] (composition) 10 is a block diagram showing an example of the configuration of a communication system 2 according to this embodiment. The communication system 2 includes a Fourier transform device 210, a filtering device 20, and an inverse Fourier transform device 220. The filtering device 20 is connected to the Fourier transform device 210 and the inverse Fourier transform device 220.

[0045] The Fourier transform device 210 has the same configuration as the Fourier transform device 110 of the first embodiment. The Fourier transform device 210 performs FFT transformation on the AD converted signal to convert it into frequency domain data (also called FFT data). The Fourier transform device 210 outputs the FFT data to the filter processing device 20.

[0046] The filter processor 20 includes an address control unit 21, a storage unit 23, a coefficient calculation processing unit 25, and a calculation unit 27. To the filter processor 20, output data (also called FFT data) of a Fourier transform unit 210 is input.

[0047] The address control unit 21 has the same configuration as the address control unit 11 of the first embodiment. An offset amount of the light source frequency and a center point (subcarrier center point) for each subcarrier are input to the address control unit 21. The offset amount and the subcarrier center point may be input via an input device (not shown) or may be set in advance in the address control unit 21. The address control unit 21 generates a write address and a read address for data based on the offset amount of the light source frequency and the center frequency for each subcarrier. The address control unit 21 specifies the generated write address and read address to the storage unit 23.

[0048] The storage unit 23 has the same configuration as the storage unit 13 of the first embodiment. A plurality of data constituting the FFT data X(ω) Fourier-transformed by the Fourier transform device 210 is input to the storage unit 23. The storage unit 23 stores the plurality of data constituting the input FFT data X(ω) at a write address specified by the address control unit 21. The plurality of data stored in the storage unit 23 is read out according to a read address specified by the address control unit 21. The plurality of data stored in the storage unit 23 is offset-compensated according to the specification by the address control unit 21, and is separated for each subcarrier and output.

[0049] The coefficient calculation processing unit 25 calculates coefficients (also called compensation coefficients) for compensation processing other than the offset compensation processing and the subcarrier separation processing (also called other compensation processing). The coefficient calculation processing unit 25 calculates a compensation coefficient for each subcarrier data based on the offset amount and the frequency of the subcarrier center point. There are no particular limitations on the other compensation processing as long as it depends on the offset amount and the frequency of the subcarrier center point. For example, the other compensation processing includes skew compensation processing that compensates for the difference in arrival time of XY polarization and I / Q signals that are orthogonal in phase. For example, the other compensation processing is skew compensation processing that compensates for the difference in arrival time of the signal value (X and Y) of the I / Q signal. i , X q , Y i , Y q ) depending on the degree of degradation. For example, the other compensation processes include a frequency response adjustment process that compensates for degradation of the frequency response caused by manufacturing variations in the receiving analog front end, environmental fluctuations, etc. For example, the other compensation processes include a chromatic dispersion compensation process and a spectrum shaping process. The coefficient calculation processing unit 25 may also perform zero padding.

[0050] The offset amount of the light source frequency and the subcarrier center point are input to the coefficient calculation processing unit 25. The offset amount and the subcarrier center point may be input via an input device (not shown) or may be registered in advance in the coefficient calculation processing unit 25. The coefficient calculation processing unit 25 calculates compensation coefficients related to processes other than the offset compensation process and the subcarrier separation process based on the offset amount of the light source frequency and the center frequency of each subcarrier. For example, the coefficient calculation processing unit 25 calculates a compensation coefficient for each subcarrier.

[0051] Here, we will give an example of calculating the compensation coefficient when there are two subcarriers, subcarrier 0 and subcarrier 1. Let f be the offset frequency of the light source compensation, and ω 0 The frequency of the center point of subcarrier 1, ω 1 In addition, the frequency of the multiple data constituting the FFT data is denoted by ω. For example, the coefficient calculation processing unit 25 uses the following Equations 1 and 2 to calculate the compensation coefficient C0 for the subcarrier data SC0 and the compensation coefficient C1 for the subcarrier data SC1. C0=H 1 (ω-f-ω 0 )×H 2 (ω-ω 0 ) · · · (1) C1=H 1 (ω-f-ω 1 )×H 2 (ω-ω 1 ) · · · (2) The above formulas 1 and 2 are examples of compensation coefficients calculated by the coefficient calculation processing unit 25, and do not limit the calculation formulas of the compensation coefficients by the coefficient calculation processing unit 25. The compensation coefficients are calculated based on the offset frequency f of the light source compensation and the frequency ω 0 oh oh 1 It is enough to depend on.

[0052] The calculation unit 27 performs compensation processing on the subcarrier data by using the compensation coefficient for each subcarrier calculated by the coefficient calculation processing unit 25. For example, the coefficient calculation processing unit 25 performs compensation processing by multiplying the subcarrier data by the compensation coefficient for each subcarrier.

[0053] FIG. 11 is a conceptual diagram for explaining multiplication of compensation coefficients calculated for each subcarrier separately for each subcarrier. The calculation unit 27 includes a multiplier 270-0 and a multiplier 270-1. A compensation coefficient C0 for subcarrier 0 is set in the multiplier 270-0. The multiplier 270-0 multiplies the input subcarrier data SC0 by the compensation coefficient C0 in response to the input of the subcarrier data SC0. The multiplier 270-0 outputs subcarrier data SC0' in which the subcarrier data SC0 is multiplied by the compensation coefficient C0. On the other hand, a compensation coefficient C1 for subcarrier 0 is set in the multiplier 270-1. The multiplier 270-1 multiplies the input subcarrier data SC1 by the compensation coefficient C1 in response to the input of the subcarrier data SC1. The multiplier 270-1 outputs subcarrier data SC1' in which the subcarrier data SC1 is multiplied by the compensation coefficient C1.

[0054] The filter processing device 20 outputs subcarrier data that has been separated into a plurality of subcarriers and subjected to other compensation processing. The data constituting the subcarrier data is rearranged in an order that makes it easy to process in the inverse Fourier transform device 220. The plurality of subcarrier data output from the filter processing device 20 is input to the inverse Fourier transform device 220.

[0055] The inverse Fourier transform device 220 has the same configuration as the inverse Fourier transform device 120 of the first embodiment. The inverse Fourier transform device 220 performs an inverse Fourier transform on a plurality of subcarrier data for each subcarrier, and converts the data into a time domain signal. The inverse Fourier transform device 220 outputs the subcarrier data converted into a time domain signal.

[0056] (operation) Next, an example of the operation of the filter processing device 20 of the communication system 2 will be described with reference to the drawings. Fig. 12 is a flowchart for explaining the operation of the filter processing device 20. In the following explanation based on the flowchart of Fig. 12, the filter processing device 20 will be described as the subject of the operation.

[0057] In FIG. 11, first, the filter processing device 20 acquires the FFT data output from the Fourier transform device 210 (step S21).

[0058] Next, the filter processing device 20 generates write addresses and read addresses for FFT data based on the offset amount of the light source frequency and the subcarrier center point for each subcarrier (step S22).

[0059] Next, the filter processing device 20 stores the data constituting the FFT data in the storage unit 23 according to the set write address (step S23).

[0060] Next, the filter processing device 20 calculates a compensation coefficient for each subcarrier (step S24). The process of step S24 may be performed after step S25 or may be performed beforehand.

[0061] Next, the filter processing device 20 outputs the data stored in the storage unit 23 according to the set read address (step S25). The data output in step S25 is subcarrier data that has been offset compensated and separated for each subcarrier.

[0062] Next, the filter processing device 20 multiplies the subcarrier data by the calculated compensation coefficient for each subcarrier (step S26).

[0063] Next, the filter processing device 20 outputs the subcarrier data that has been subjected to the compensation process (step S27). The subcarrier data output from the filter processing device 10 is input to the inverse Fourier transform device 220. The subcarrier data input to the inverse Fourier transform device 220 is subjected to an inverse Fourier transform for each subcarrier.

[0064] [Related Technology 2] Here, Related Art 2 of the second embodiment will be described with reference to the drawings. This related art is an example in which compensation processing is performed separately in the stages prior to each of offset compensation processing and subcarrier separation processing.

[0065] 13 is a block diagram showing an example of a configuration of a communication system 200 of the related art. The communication system 200 includes a Fourier transform device 215, a filter processing device 250, and an inverse Fourier transform device 225. The filter processing device 250 includes a first multiplier 251, a first storage unit 252, a second multiplier 253, and a second storage unit 254. The filter processing device 250 is connected to the Fourier transform device 215 and the inverse Fourier transform device 225. The Fourier transform device 215 has a configuration similar to that of the Fourier transform device 210 of the second embodiment. The inverse Fourier transform device 225 has a configuration similar to that of the inverse Fourier transform device 220 of the second embodiment.

[0066] Data constituting the FFT data X(ω) is input to the first multiplier 251. The first multiplier 251 multiplies the data constituting the FFT data X(ω) by a compensation coefficient H1. The first multiplier 251 outputs the data multiplied by the compensation coefficient H1 to the first storage unit 252.

[0067] The data multiplied by the compensation coefficient H1 is input to the first storage unit 252. The first storage unit 252 is a storage unit for offset compensation processing. The data input to the first storage unit 252 is rearranged according to the set offset amount and output. In the example of FIG. 13, the offset-compensated data Y'(ω) is output from the first storage unit 252.

[0068] The offset-compensated data Y'(ω) is input to the second multiplier 253. The second multiplier 253 multiplies the data constituting the FFT data X(ω) by a compensation coefficient H2. The second multiplier 253 outputs the data multiplied by the compensation coefficient H2 to the second storage unit 254.

[0069] The data multiplied by the compensation coefficient H2 is input to the second storage unit 254. The second storage unit 254 is a storage unit for separating subcarriers. The data input to the second storage unit 254 is rearranged according to the frequency of the center point of each subcarrier and output. In the example of FIG. 13, the subcarrier-separated subcarrier data SC0' and subcarrier data SC1' are output from the second storage unit 254 to the inverse Fourier transform device 220. The arrangement of the data constituting the subcarrier data is rearranged in an order that makes it easy to process in the inverse Fourier transform device 220. The subcarrier data SC0' and subcarrier data SC1' output from the second storage unit 254 are individually inverse Fourier transform processed in the inverse Fourier transform device 220.

[0070] FIG. 14 is a table for explaining the compensation coefficients used in the method of the second embodiment. In the example of FIG. 11, the compensation coefficients used for each of the 16 data constituting the FFT data similar to that of the first embodiment are summarized. The table of FIG. 14 shows compensation coefficients for enabling the compensation processing in the related art 2 to be performed collectively. H1(ω) and H2(ω) are compensation coefficients used for the data ω when the method of the related art 2 is used. C(ω) is a compensation coefficient used when performing the same compensation as in the related art 2 when the method of the second embodiment is used. The compensation coefficient C(13) is a compensation coefficient for the data 13. For example, the compensation coefficient C(13) is obtained by multiplying the compensation coefficient H1(12) and the compensation coefficient H2(13). For example, the compensation coefficient C(14) is obtained by multiplying the compensation coefficient H1(13) and the compensation coefficient H2(14). By using the compensation coefficient C(ω) of FIG. 14, the compensation processing similar to that in the related art 2 can be performed collectively.

[0071] In the method of Related Art 2, necessary compensation processing is performed immediately before each of the frequency offset and subcarrier separation. Therefore, in the method of Related Art 2, compensation processing is performed immediately before each of the frequency offset and subcarrier separation. In contrast, in the method of the second embodiment, the compensation coefficient calculated by the coefficient calculation processing unit 25 is multiplied by the subcarrier data after the subcarrier separation, so that the compensation processing can be performed all at once.

[0072] As described above, the communication system of the present embodiment includes a Fourier transform device, a filter processing device, and an inverse Fourier transform device. The Fourier transform device performs a Fourier transform on a signal based on an optical signal. The Fourier transform device outputs Fourier transform data including a plurality of data after the Fourier transform to the filter processing device. The filter processing device includes an address control unit, a storage unit, a coefficient calculation processing unit, and a calculation unit. The address control unit specifies write addresses and read addresses of a plurality of data included in the Fourier transform data based on the optical signal based on an offset amount of the light source frequency and a subcarrier center point for each subcarrier. The address control unit specifies write addresses and read addresses so that compensation of the offset amount and separation of the subcarriers are performed in the same storage unit. The storage unit writes a plurality of data to the write addresses specified by the address control unit. The storage unit reads data from the read addresses specified by the address control unit. The coefficient calculation processing unit calculates a compensation coefficient used for other compensation processing for each subcarrier based on the offset amount and the subcarrier center point. The calculation unit collectively performs compensation processing other than the offset compensation processing and the subcarrier separation processing for each of the plurality of subcarrier data separated for each subcarrier. For example, the calculation unit multiplies each of the plurality of subcarrier data separated for each subcarrier by the compensation coefficient calculated for each subcarrier by the coefficient calculation processing unit. The inverse Fourier transform device acquires the plurality of data that have been subjected to the offset compensation processing and the subcarrier separation processing by the filter processing device. The inverse Fourier transform device performs an inverse Fourier transform on the plurality of data that have been subjected to the offset compensation processing and the subcarrier separation processing.

[0073] In the method of this embodiment, after the offset compensation process and the subcarrier separation process, other compensation processes other than the offset compensation process and the subcarrier separation process are executed collectively. Therefore, according to the method of this embodiment, the circuit scale and the calculation procedure for the other processes can be simplified, and power consumption can be reduced.

[0074] In one aspect of this embodiment, the coefficient calculation processing unit uses a first compensation coefficient and a second compensation coefficient to calculate a compensation coefficient for each subcarrier. The first compensation coefficient is a coefficient used in a first compensation process performed in a stage before the offset compensation process. The second compensation coefficient is a coefficient used in a second compensation process performed in a stage before the subcarrier separation process. For example, the coefficient calculation processing unit calculates a compensation coefficient using a first compensation coefficient that depends on the offset amount and the subcarrier center point, and a second compensation coefficient that depends on the subcarrier center point. According to this aspect, the compensation processes performed in the stages before and after the offset compensation process can be performed together, so that the circuit size and calculation process can be simplified.

[0075] In one aspect of this embodiment, the coefficient calculation processing unit sets the value of data that becomes unnecessary due to the frequency offset compensation process to 0. According to this aspect, it is possible to delete the value of unnecessary data included in the plurality of data.

[0076] (Third embodiment) Next, a communication system according to a third embodiment will be described with reference to the drawings. The filter processing device of the communication system of this embodiment has a storage unit including a plurality of partial storage units. In the following, an example in which the filter processing device of this embodiment is incorporated into the communication system of the first embodiment will be described. The filter processing device of this embodiment may be incorporated into the communication system of the second embodiment.

[0077] (composition) 15 is a block diagram showing an example of the configuration of a communication system 3 according to this embodiment. The communication system 3 includes a Fourier transform device 310, a filtering device 30, and an inverse Fourier transform device 320. The filtering device 30 is connected to the Fourier transform device 310 and the inverse Fourier transform device 320.

[0078] The Fourier transform device 310 has the same configuration as the Fourier transform device 110 of the first embodiment. The Fourier transform device 310 performs FFT transformation on the AD converted signal to convert it into frequency domain data (also called FFT data). The Fourier transform device 310 outputs the FFT data to the filter processing device 30.

[0079] The filter processor 30 includes an address control unit 31 and a storage unit 33. To the filter processor 30, output data (also called FFT data) of a Fourier transform unit 310 is input.

[0080] The offset amount of the light source frequency and the center point of each subcarrier (subcarrier center point) are input to the address control unit 31. The offset amount and the subcarrier center point may be input via an input device (not shown) or may be set in advance in the address control unit 31. The address control unit 31 outputs the offset amount and the subcarrier center point to the storage unit 33. The address control unit 31 may generate a write address and a read address for data to the storage unit 33 based on the offset amount of the light source frequency and the center frequency of each subcarrier. In this case, the address control unit 31 specifies the generated write address and read address to the storage unit 33.

[0081] The storage unit 33 receives a plurality of data constituting the FFT data X(ω) Fourier-transformed by the Fourier transform device 310. The FFT data X(ω) includes a plurality of subcarrier data. The plurality of data constituting the FFT data X(ω) is input for each cycle. The storage unit 33 includes a plurality of partial storage units (described later). The plurality of partial storage units are configured to correspond to the cycles. The storage unit 33 stores the plurality of data constituting the input FFT data X(ω) in the partial storage unit for each cycle. The plurality of data constituting the subcarrier data have consecutive sample numbers, so they are input to the storage unit 33 in different cycles. Therefore, the data constituting the subcarrier data are distributed and stored in different partial storage units. When a write address is specified by the address control unit 31, the storage unit 33 stores the data in the specified write address.

[0082] The multiple data stored in the storage unit 33 are read from each of the multiple partial storage units in the order in which the offset compensation and subcarrier separation were performed based on the offset amount and the subcarrier center point. The data constituting the subcarrier data are stored in different partial storage units. Therefore, by reading the multiple data constituting the subcarrier data from each of the multiple partial storage units, the subcarrier data for which the offset amount has been compensated can be separated. When a read address is specified by the address control unit 31, the multiple data stored in the storage unit 33 are read according to the read address specified by the address control unit 31. As a result, the multiple data stored in the storage unit 33 are offset compensated and separated for each subcarrier before being output.

[0083] The filter processing device 30 outputs subcarrier data separated for each of the plurality of subcarriers. When the filter processing device 30 is incorporated in the communication system 2 of the second embodiment, the filter processing device 30 outputs subcarrier data subjected to compensation processing other than offset compensation and subcarrier separation (also called other compensation processing). The arrangement of data constituting the subcarrier data is rearranged in an order that makes it easy to process in the inverse Fourier transform device 320. The plurality of subcarrier data output from the filter processing device 30 is input to the inverse Fourier transform device 320. The example of FIG. 15 conceptually illustrates a state in which a plurality of subcarrier data (SC0, SC1, . . . , SCn) is output from the storage unit 33 (n is a natural number). The plurality of subcarrier data may be output serially or in parallel for each subcarrier.

[0084] The inverse Fourier transform device 320 has the same configuration as the inverse Fourier transform device 120 of the first embodiment. The inverse Fourier transform device 320 performs an inverse Fourier transform on a plurality of subcarrier data for each subcarrier, and converts the data into a time domain signal. The inverse Fourier transform device 320 outputs the subcarrier data converted into a time domain signal.

[0085] [Storage section] Next, a detailed configuration of the storage unit 33 will be described with reference to the drawings. Fig. 16 is a block diagram showing an example of a detailed configuration of the storage unit 33. The storage unit 33 has a write destination selection unit 331, a first selection unit 332, a plurality of partial storage units 335-1 to m, an output data selection unit 336, and a rearrangement unit 337 (m is a natural number of 2 or more). The plurality of partial storage units 335-1 to m configure a partial storage device group 350. In the following, when describing commonalities among the plurality of partial storage units 335-1 to m, the plurality of partial storage units 335-1 to m may be referred to as partial storage unit 335 without distinguishing between them.

[0086] The write destination selection unit 331 outputs a selection control signal (also called an input control signal) that specifies the partial storage unit 335 to which the multiple data constituting the FFT data X(ω) is to be written, to the first selection unit 332. The partial storage unit 335 to which the multiple data constituting the FFT data X(ω) is to be written is set for each cycle. For example, the write destination selection unit 331 may be omitted, and the selection control signal may be output from the address control unit 31.

[0087] A plurality of data constituting the FFT data X(ω) are input to the first selection unit 332 for each cycle. The first selection unit 332 distributes the plurality of data to the partial storage unit 335 for each cycle in response to a selection control signal from the write destination selection unit 331. The first selection unit 332 functions as a distributor. For example, the first selection unit 332 is realized by a demultiplexer (selector).

[0088] Each of the plurality of partial storage units 335-1 to m is configured to correspond to a cycle of input of a plurality of data constituting the FFT data X(ω). The plurality of data constituting the FFT data X(ω) is input in sequence to the partial storage unit 335 for each cycle. Each of the plurality of partial storage units 335-1 to m stores data of a cycle corresponding to each of the partial storage units 335-1 to m. For example, the cycle of input of a plurality of data constituting the FFT data X(ω) is assumed to be 0 to m-1 (m is a natural number of 2 or more). In this case, data of cycle 0 is stored in the partial storage unit 335-1. Moreover, data of cycle m-1 is stored in the partial storage unit 335-m.

[0089] The multiple data constituting the subcarrier data have consecutive sample numbers. Therefore, the multiple data constituting the subcarrier data are input to different storage units 33 in different cycles. Therefore, the data constituting the subcarrier data are distributed and stored in different partial storage units 335. Note that, when the number of data constituting the subcarrier data exceeds the number of data for one cycle, multiple data constituting the same subcarrier data may be stored in the same partial storage unit 335. When a write address is specified by the address control unit 31, the data is stored at the write address of the specified partial storage unit 335.

[0090] The output data selection unit 336 is connected to each of the plurality of partial storage units 335-1 to m. Although the output data selection unit 336 is shown in FIG. 16 as being connected to the partial storage device group 350, the output data selection unit 336 is connected to each of the plurality of partial storage units 335-1 to m. The output data selection unit 336 outputs a selection control signal (also called an output control signal) that specifies the data to be read out to each of the plurality of partial storage units 335-1 to m based on the offset amount and the subcarrier center point. For example, the output data selection unit 336 may be omitted, and the selection control signal may be output from the address control unit 31.

[0091] Fig. 17 is a conceptual diagram for explaining an example of the internal configuration of the partial storage unit 335. Fig. 17 shows only the internal configuration of the partial storage unit 335-1, and omits the internal configurations of the other partial storage units 335-2 to m. The partial storage unit 335 has a memory element array 351 and a second selection unit 353.

[0092] The memory element array 351 is a storage structure in which a plurality of memory elements are arranged in an array. A plurality of data constituting the FFT data X(ω) are stored in the memory element array 351. For example, the partial storage unit 335 is realized by a storage device such as a memory or a register. In this embodiment, the partial storage unit 335 is assumed to be a memory, but the partial storage unit 335 may be realized by a storage device other than a memory. For example, the partial storage unit 335 may be realized by an auxiliary storage device including a hard disk drive, a solid state drive, a magnetic disk, an optical disk, a magneto-optical disk, a flash memory, or the like.

[0093] The second selection unit 353 reads out a plurality of data constituting the subcarrier data from each of the plurality of partial storage units 335-1 to m in response to a selection control signal from the output data selection unit 336. The plurality of data read out from each of the plurality of partial storage units 335-1 to m in response to a selection control signal from the output data selection unit 336 is data constituting the subcarrier data with the offset amount compensated for. The second selection unit 353 functions as a multiplexer. For example, the second selection unit 353 is realized by a multiplexer (selector). The second selection unit 353 may be disposed between the plurality of partial storage units 335-1 to m and the rearrangement unit 337. In this case, the plurality of data distributed and stored in the plurality of partial storage units 335-1 to m is read out via the single second selection unit 353.

[0094] In response to the selection control signal input to the second selection unit 353, data for each subcarrier is read out from each of the plurality of partial storage units 335-1 to m at the same timing. As a result, a plurality of data constituting the same subcarrier data is output from each of the plurality of partial storage units 335-1 to m at the same timing. For example, when a plurality of data constituting the subcarrier data is a data amount for one cycle, the data is output from different partial storage units 335-1 to m at the same timing. For example, when a plurality of data constituting the subcarrier data is a data amount for multiple cycles, the data is output from different partial storage units 335-1 to m at multiple consecutive timings. In response to the selection control signal, the data output from each of the plurality of partial storage units 335-1 to m is output to the rearrangement unit 337.

[0095] The rearrangement unit 337 receives data output from each of the partial storage units 335-1 to m. The data input to the rearrangement unit 337 is not arranged in the order of the subcarrier data. The rearrangement unit 337 rearranges the input data into the order of the subcarrier data and outputs the rearranged data. The data output from the rearrangement unit 337 constitutes subcarrier data with the offset amount compensated for. The subcarrier data (SC0, SC1, . . . , SCn) output from the rearrangement unit 337 is grouped for each subcarrier and output to the inverse Fourier transform device 320. In the example of FIG. 16, a state in which multiple subcarrier data (SC0, SC1, . . . , SCn) is output from the rearrangement unit 337 is conceptually illustrated (n is a natural number). The multiple subcarrier data may be output serially or in parallel for each subcarrier. When a configuration for rearranging data is provided between the filter processing device 30 and the inverse Fourier transform device 320, the rearrangement unit 337 may be omitted.

[0096] Next, the processing by the filter processing device 30 of this embodiment will be described with reference to the drawings. Fig. 18 is a conceptual diagram for explaining the offset compensation processing. In the example of Fig. 18, FFT data X(ω) is composed of 64 discrete data (data 0 to 63). In the following description, when illustrating the internal configuration of the storage unit 33, some components may be omitted.

[0097] In the example of FIG. 18, 64 pieces of data included in the FFT data X(ω) before rearrangement are numbered from 0 to 63 (also called sample numbers). In the following, a sample number is assigned to each of a plurality of pieces of data based on the arrangement of data in the FFT data X(ω) before rearrangement. The sample number is assigned according to the frequency of the data. Even after the data constituting the FFT data X(ω) is rearranged, the sample number assigned to the data is maintained as it is. In the example of FIG. 18, the offset amount based on the light source frequency is +4. In FIG. 18, the sample numbers of most of the data are omitted, and only the sample numbers of some of the data are illustrated. In FIG. 18, the arrows indicating the subcarrier data are conceptual, and the ends of the arrows do not match the exact sample numbers.

[0098] Before offset compensation (upper row), multiple data constituting FFT data X(ω) are distributed with data 0 of the DC (Direct Current) component at the center. FFT data X(ω) includes four subcarrier data (SC0, SC1, SC2, SC3). Each of the four subcarrier data (SC0, SC1, SC2, SC3) includes 16 pieces of data. The four subcarrier data (SC0, SC1, SC2, SC3) include data that overlap with each other. Subcarrier data SC0 before offset compensation has data 6 as the subcarrier center point and includes 16 pieces of data (data 62 to 13). Subcarrier data SC1 before offset compensation has data 16 as the subcarrier center point and includes 16 pieces of data (data 8 to 23). Subcarrier data SC2 before offset compensation has data 48 as the subcarrier center point and includes 16 pieces of data (data 40 to 55). The subcarrier data SC3 before offset compensation has data 58 as the subcarrier center point and includes 16 data items (data 50 to 1).

[0099] The multiple data after offset compensation (lower row) are data that have been offset compensated by offset compensation processing (+4) based on the light source frequency. The multiple data after offset compensation (lower row) are distributed with data 4 at the center by offset compensation processing (+4) based on the light source frequency. The ends of the multiple data (data 32 to 35, 28 to 31) are padded with 0s.

[0100] Subcarrier data SC0 after offset compensation has data 10 as its subcarrier center point and includes 16 pieces of data (data 2-17). Subcarrier data SC1 after offset compensation has data 20 as its subcarrier center point and includes 16 pieces of data (data 12-27). Subcarrier data SC2 after offset compensation has data 52 as its subcarrier center point and includes 16 pieces of data (data 44-59). Subcarrier data SC3 after offset compensation has data 62 as its subcarrier center point and includes 16 pieces of data (data 54-5).

[0101] FIG. 19 is a conceptual diagram for explaining the arrangement of a plurality of data (data 0 to 63) constituting the FFT data X(ω) before and after the offset compensation process and the subcarrier separation process by the filter processing device 30. FIG. 19 shows the arrangement of data (1) before rearrangement and (2) after rearrangement. Eight pieces of data per cycle are input in sequence to the storage unit 33 in cycles 0 to 7. In the example of FIG. 19, eight pieces of data are included per cycle. (2) The arrangement of data after rearrangement shows a state in which the subcarrier data is integrated for each cycle. Subcarrier data SC0 is integrated in cycles 0 to 1. Subcarrier data SC1 is integrated in cycles 2 to 3. Subcarrier data SC2 is integrated in cycles 4 to 5. Subcarrier data SC3 is integrated in cycles 6 to 7.

[0102] FIG. 20 is a conceptual diagram for explaining an example of writing data to a plurality of partial storage sections 335-1 to 8 included in the storage section 33. A plurality of data items are input to the first selection section 332 for each cycle. The plurality of data items input to the first selection section 332 are distributed to the partial storage sections 335 for each cycle in response to a selection control signal from the write destination selection section 331. Data 0, data 8, data 16, data 24, data 32, data 40, data 48, and data 56 input in the 0th cycle are stored in the partial storage section 335-1. Data 1, data 9, data 17, data 25, data 33, data 41, data 49, and data 57 input in the 1st cycle are stored in the partial storage section 335-2 (data input in the 2nd to 6th cycles is omitted). Data 7, data 15, data 23, data 31, data 39, data 47, data 55, and data 63 input in the seventh cycle are stored in partial storage unit 335-8.

[0103] FIG. 21 is a conceptual diagram for explaining another example of writing data to a plurality of partial storage units 335-1 to m included in the storage unit 33. In the example of FIG. 21, a plurality of data items shown in an 8×8 matrix are divided into two parts, an upper part and a lower part, and input to the partial storage units 335-1 to m for each cycle. The data group in the upper part is input to the first selection unit 332 as is. A register 370 is disposed on the input side of the data group in the lower part. The register 370 functions as a buffer that generates a delay of one cycle. The data group in the lower part is input to the first selection unit 332 with the input timing delayed by the register 370 for one cycle. The register 370 may be included in the filter processing device 30 or may be disposed outside the filter processing device 30. For example, the register 370 may be included in the storage unit 33. FIG. 21 shows an example in which a plurality of data items are divided into two parts and input to the storage unit 33 for each cycle, but the number of divisions of the plurality of data items may be three or more. 21, the amount of data written in one cycle can be reduced, and the bit width of the write portion and read portion of the memory unit 33 and partial memory unit 335 can be reduced. This allows the area of ​​the memory unit 33 and partial memory unit 335 to be reduced. Amplifiers (not shown) and the like are disposed in the write portion and read portion. If the bit width of the write portion and read portion can be reduced, the number of amplifiers and the like can be reduced.

[0104] Fig. 22 is a conceptual diagram for explaining an example of reading data from the plurality of partial storage units 335-1 to m included in the storage unit 33. Data is read from the plurality of partial storage units 335-1 to m in response to a selection control signal from the output data selection unit 336. Fig. 22 illustrates only the internal configuration of the partial storage unit 335-1, and omits the internal configurations of the other partial storage units 335-2 to m. The output data selection unit 336 outputs a selection control signal to each of the plurality of partial storage units 335-1 to m to read data in the order of subcarrier data SC0, subcarrier data SC1, subcarrier data SC2, and subcarrier data SC3.

[0105] Subcarrier data SC0 after offset compensation is made up of 16 pieces of data (data 2 to 17) centered around subcarrier center point 10. Partial storage unit 335-1 stores data 8 and data 16. Partial storage unit 335-2 stores data 9 and data 17. Partial storage unit 335-3 stores data 2 and data 10. Partial storage unit 335-4 stores data 3 and data 11. Partial storage unit 335-5 stores data 4 and data 12. Partial storage unit 335-6 stores data 5 and data 13. Partial storage unit 335-7 stores data 6 and data 14. Partial storage unit 335-8 stores data 7 and data 15.

[0106] In the example of FIG. 22, first, data 2 to 9 included in the offset-compensated subcarrier data SC0 are read from the partial storage units 335-1 to 8. The data 2 to 9 read from the partial storage units 335-1 to 8 are rearranged in ascending order by the rearrangement unit 337 and output. Next, data 10 to 17 included in the offset-compensated subcarrier data SC0 are read from the partial storage units 335-1 to 8. The data 10 to 17 read from the partial storage units 335-1 to 8 are rearranged in ascending order by the rearrangement unit 337 and output. As a result, the offset-compensated subcarrier data SC0 is separated into subcarriers and output. The subcarrier data SC1, subcarrier data SC2, and subcarrier data SC3 are also offset compensated and separated into subcarriers and output in the same manner as the subcarrier data SC0.

[0107] As described above, the communication system of the present embodiment includes a Fourier transform device, a filter processing device, and an inverse Fourier transform device. The Fourier transform device performs a Fourier transform on a signal based on an optical signal. The Fourier transform device outputs Fourier transform data including a plurality of pieces of data after Fourier transform to the filter processing device. The filter processing device includes an address control unit and a storage unit. The address control unit specifies write addresses and read addresses of a plurality of pieces of data included in the Fourier transform data based on the optical signal based on an offset amount of the light source frequency and a subcarrier center point for each subcarrier. The address control unit specifies write addresses and read addresses so that the compensation of the offset amount and the separation of the subcarriers are performed in the same storage unit. The storage unit has a plurality of partial storage units in which a plurality of pieces of data constituting the Fourier transform data are stored. In each of the plurality of partial storage units, a data group consisting of data of any one of the cycles is written in accordance with an input control signal that distributes the plurality of pieces of data for each cycle. Data for each subcarrier is sequentially read from each of the plurality of partial storage units in accordance with an output control signal based on the offset amount and the subcarrier center point. The inverse Fourier transform device acquires a plurality of pieces of data that have been subjected to offset compensation processing and subcarrier separation processing by the filter processing unit. The inverse Fourier transform device performs an inverse Fourier transform on the multiple data that have been subjected to the offset compensation process and the subcarrier separation process.

[0108] In the method of this embodiment, multiple data included in the Fourier transform data are stored in different partial storage units for each cycle. Since the multiple data constituting the subcarrier data have consecutive sample numbers, they are distributed to different partial storage units corresponding to different cycles. Therefore, according to the method of this embodiment, the multiple data constituting the subcarrier data that has been subjected to offset compensation processing are sequentially read out from each of the multiple partial storage units, thereby making it possible to simultaneously execute offset compensation processing and subcarrier separation processing. Therefore, according to the method of this embodiment, subcarrier separation can be performed without adding a dedicated storage unit for performing subcarrier separation. In one aspect of this embodiment, the storage unit has a write destination selection unit, a first selection unit, an output data selection unit, and a rearrangement unit. The write destination selection unit outputs an input control signal. A plurality of data are input to the first selection unit. The first selection unit distributes the input data to a plurality of partial storage units in response to the input control signal. The output data selection unit outputs an output control signal based on an offset amount and a subcarrier center point. The rearrangement unit rearranges and outputs data output from the plurality of partial storage units in response to a data configuration of subcarrier data separated for each subcarrier based on an offset amount and a subcarrier center point. The partial storage unit includes a storage element array and a second selection unit. The storage element array has a structure in which a plurality of storage elements are arranged in an array, and data is stored. The second selection unit selects and outputs the data stored in the storage element array in response to an output control signal. In this aspect, a plurality of data included in the Fourier transform data is stored in different partial storage units for each cycle. In this aspect, a plurality of data constituting the subcarrier data subjected to the offset compensation process are sequentially read from each of the plurality of partial storage units, and the read plurality of data are rearranged according to the data configuration of the subcarrier data and output. According to this aspect, the subcarrier data can be restored by rearranging the plurality of data read from each of the plurality of partial storage units according to the data configuration of the subcarrier data.

[0109] The communication system according to one aspect of the present embodiment includes a buffer that delays the timing at which at least one of a plurality of data included in the Fourier transform data is input to the filter processing device by at least one cycle. According to this aspect, the bit width of the write portion and read portion of the memory unit and partial memory unit can be reduced, so that the area of ​​the memory unit and partial memory unit can be reduced. Furthermore, if the bit width of the write portion and read portion can be reduced, the number of amplifiers and the like arranged in the write portion and read portion can be reduced.

[0110] (Fourth embodiment) Next, a filter processing device according to a fourth embodiment will be described with reference to the drawings. The filter processing device of this embodiment has a simplified configuration of the filter processing device of each embodiment. FIG. 15 is a block diagram showing an example of the configuration of a filter processing device 40 of this embodiment. The filter processing device 40 includes an address control unit 41 and a storage unit 43.

[0111] The address control unit 41 specifies write addresses and read addresses for multiple pieces of data included in the Fourier transform data based on the optical signal, based on the offset amount of the light source frequency and the subcarrier center point for each subcarrier. The address control unit 41 specifies write addresses and read addresses so that the offset amount compensation and subcarrier separation are performed in the same storage unit 43. The storage unit 43 writes multiple pieces of data to the write addresses specified by the address control unit 41. The storage unit 43 reads data from the read addresses specified by the address control unit 41.

[0112] According to the filter processing device of this embodiment, by specifying addresses so that offset compensation processing and subcarrier separation processing are performed, subcarrier separation can be performed without adding a dedicated storage unit.

[0113] (Hardware) Here, a hardware configuration for executing the control and processing according to each embodiment of the present disclosure will be described using an information processing device 90 in FIG. 16 as an example. Note that the information processing device 90 in FIG. 16 is an example of a configuration for executing the control and processing according to each embodiment, and does not limit the scope of the present disclosure. For example, the control and processing according to each embodiment of the present disclosure may be executed by a microcomputer, a microcontroller, or the like.

[0114] As shown in Fig. 16, an information processing device 90 includes a processor 91, a main storage device 92, an auxiliary storage device 93, an input / output interface 95, and a communication interface 96. In Fig. 16, the interface is abbreviated as I / F (Interface). The processor 91, the main storage device 92, the auxiliary storage device 93, the input / output interface 95, and the communication interface 96 are connected to each other via a bus 98 so as to be able to communicate data with each other. In addition, the processor 91, the main storage device 92, the auxiliary storage device 93, and the input / output interface 95 are connected to a network such as the Internet or an intranet via the communication interface 96.

[0115] The processor 91 loads a program stored in the auxiliary storage device 93 or the like into the main storage device 92. The processor 91 executes the program loaded into the main storage device 92. In this embodiment, a software program installed in the information processing device 90 may be used. The processor 91 executes the control and processing according to this embodiment.

[0116] The main memory device 92 has an area in which a program is loaded. The processor 91 loads a program stored in the auxiliary memory device 93 or the like in the main memory device 92. The main memory device 92 is realized by a volatile memory such as a dynamic random access memory (DRAM). Furthermore, a non-volatile memory such as a magnetoresistive random access memory (MRAM) may be configured / added to the main memory device 92.

[0117] The auxiliary storage device 93 stores various data such as programs. The auxiliary storage device 93 is realized by a local disk such as a hard disk or a flash memory. Note that it is also possible to configure the main storage device 92 to store various data and omit the auxiliary storage device 93.

[0118] The input / output interface 95 is an interface for connecting the information processing device 90 to peripheral devices based on standards and specifications. The communication interface 96 is an interface for connecting to external systems and devices through a network such as the Internet or an intranet based on standards and specifications. The input / output interface 95 and the communication interface 96 may be a common interface for connecting to external devices.

[0119] Input devices such as a keyboard, a mouse, and a touch panel may be connected to the information processing device 90 as necessary. These input devices are used to input information and settings. When a touch panel is used as an input device, the display screen of the display device may also serve as an interface for the input device. Data communication between the processor 91 and the input devices may be mediated by an input / output interface 95.

[0120] The information processing device 90 may be equipped with a display device for displaying information. When the display device is equipped, the information processing device 90 is preferably equipped with a display control device (not shown) for controlling the display of the display device. The display device may be connected to the information processing device 90 via the input / output interface 95.

[0121] The information processing device 90 may also be provided with a drive device. The drive device mediates between the processor 91 and a recording medium (program recording medium) for reading data and programs from the recording medium, writing the processing results of the information processing device 90 to the recording medium, and the like. The drive device may be connected to the information processing device 90 via an input / output interface 95.

[0122] The above is an example of a hardware configuration for enabling the control and processing according to each embodiment of the present invention. The hardware configuration in FIG. 16 is an example of a hardware configuration for executing the control and processing according to each embodiment, and does not limit the scope of the present invention. In addition, a program for causing a computer to execute the control and processing according to each embodiment is also included in the scope of the present invention. Furthermore, a program recording medium on which a program according to each embodiment is recorded is also included in the scope of the present invention. The recording medium can be realized, for example, by an optical recording medium such as a CD (Compact Disc) or a DVD (Digital Versatile Disc). The recording medium may be realized by a semiconductor recording medium such as a USB (Universal Serial Bus) memory or an SD (Secure Digital) card. In addition, the recording medium may be realized by a magnetic recording medium such as a flexible disk or other recording medium. When a program executed by a processor is recorded on a recording medium, the recording medium corresponds to a program recording medium.

[0123] The components of each embodiment may be combined in any manner. Furthermore, the components of each embodiment may be realized by software or by a circuit.

[0124] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-mentioned embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

[0125] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes. (Appendix 1) an address control unit that specifies write addresses and read addresses of a plurality of data included in the Fourier transform data based on the optical signal, based on an offset amount of the light source frequency and a subcarrier center point for each subcarrier; a storage unit in which the data is written to the write address designated by the address control unit and the data is read from the read address designated by the address control unit; The address control unit The write address and the read address are designated so that the compensation of the offset amount and the separation of the subcarriers are performed in the same storage unit. 23. A filter processing device comprising: (Appendix 2) The address control unit 2. The filter processing device according to claim 1, wherein the write address and the read address are designated so that the compensation for the offset amount and the separation of the subcarriers are performed collectively. (Appendix 3) 3. The filter processing device according to claim 1, further comprising a calculation unit that collectively performs offset compensation processing and other compensation processing different from subcarrier separation processing on each of a plurality of subcarrier data separated for each subcarrier. (Appendix 4) a coefficient calculation processing unit that calculates a compensation coefficient used in the other compensation processing for each of the subcarriers based on the offset amount and the subcarrier center point; The calculation unit is 4. The filter processing device according to claim 3, wherein the compensation coefficient calculated for each of the subcarriers by the coefficient calculation processing unit is multiplied by each of the plurality of subcarrier data separated for each of the subcarriers. (Appendix 5) The coefficient calculation processing unit is 5. The filter processing device according to claim 4, wherein the compensation coefficient is calculated for each of the subcarriers by using a first compensation coefficient used in a first compensation process performed in a stage preceding the offset compensation process and a second compensation coefficient used in a second compensation process performed in a stage preceding the subcarrier separation process. (Appendix 6) The coefficient calculation processing unit is 6. The filter processing device according to claim 5, wherein the compensation coefficient is calculated using the first compensation coefficient that depends on the offset amount and the subcarrier center point, and the second compensation coefficient that depends on the subcarrier center point. (Appendix 7) Either the address control unit or the coefficient calculation processing unit, 7. The filter processing device according to claim 4, wherein the value of the data that becomes unnecessary by the offset compensation process is set to 0. (Appendix 8) The storage unit is a plurality of partial storage units in which a plurality of the data constituting the Fourier transform data are stored; Each of the plurality of partial storage units includes: A data group composed of the data of any one of the cycles is written in response to an input control signal that allocates the plurality of data for each cycle; From each of the plurality of partial storage units, 8. The filter processing device according to claim 1, wherein the data for each subcarrier is read out sequentially in response to an output control signal based on the offset amount and the subcarrier center point. (Appendix 9) The storage unit is A write destination selection unit that outputs the input control signal; a first selection unit that receives a plurality of the data and distributes the input data to a plurality of the partial storage units in response to the input control signal; an output data selection unit that outputs the output control signal based on the offset amount and the subcarrier center point; a sorting unit that sorts and outputs the data output from the plurality of partial storage units in accordance with a data structure of the subcarrier data separated for each subcarrier based on the offset amount and the subcarrier center point, The partial storage unit includes: a memory element array having a structure in which a plurality of memory elements are arranged in an array and in which the data is stored; and a second selection unit that selects and outputs the data stored in the memory element array in response to the output control signal. (Appendix 10) A filter processing device according to any one of claims 1 to 9, a Fourier transform device that performs a Fourier transform on a signal based on an optical signal and outputs Fourier transform data including a plurality of pieces of data after the Fourier transform to the filter processing device; a communication system including: an inverse Fourier transform device that acquires the plurality of data that have been subjected to offset compensation processing and subcarrier separation processing by the filter processing device, and performs an inverse Fourier transform on the plurality of data that have been subjected to the offset compensation processing and the subcarrier separation processing. (Appendix 11) 11. The communication system according to claim 10, further comprising a buffer that delays by at least one cycle the timing at which at least any of the plurality of data included in the Fourier transform data is input to the filter processing device. (Appendix 12) The computer specifying write addresses and read addresses of a plurality of data included in the Fourier transform data based on the optical signal to a storage unit so that compensation of the offset amount and separation of the subcarriers are performed in the same storage unit based on an offset amount of a light source frequency and a subcarrier center point for each subcarrier; writing a plurality of said data to said write addresses of said designated storage unit; A filtering method comprising the steps of: reading the data from the read address of the specified storage unit. (Appendix 13) A process of specifying, in a storage unit, write addresses and read addresses of a plurality of data included in Fourier transform data based on an optical signal, so that compensation of the offset amount and separation of the subcarriers are performed in the same storage unit based on an offset amount of a light source frequency and a subcarrier center point for each subcarrier; A process of writing a plurality of the data to the write addresses of the designated storage unit; and reading the data from the specified read address of the storage unit. [Explanation of symbols]

[0126] 10, 20, 30, 40 Filter Processing Device 11, 21, 31, 41 Address control section 13, 23, 33, 43 storage section 25 Coefficient calculation processing section 27 Arithmetic section 110, 210, 310 Fourier transform device 120, 220, 320 Inverse Fourier Transform Device 270 Multiplier 331 Write destination selection section 332 First Selection Section 335 Partial memory section 336 Output Data Selection Unit 337 Sorting Department 350 Partial storage device group 351 Memory Element Array 352 Second Selection Section

Claims

1. an address control means for specifying write addresses and read addresses of a plurality of data included in the Fourier transform data based on the optical signal, based on an offset amount of the light source frequency and a subcarrier center point for each subcarrier; a storage means for writing a plurality of the data to the write address designated by the address control means and for reading the data from the read address designated by the address control means, The address control means specifying the write address and the read address so that the compensation of the offset amount and the separation of the subcarriers are performed by the same storage means; The storage means includes: a plurality of partial storage means for storing a plurality of the data constituting the Fourier transform data; a write destination selection means for outputting an input control signal for allocating the plurality of data for each cycle; a first selection means for receiving a plurality of the data and distributing the input data to a plurality of the partial storage means in response to the input control signal; an output data selection means for outputting an output control signal based on the offset amount and the subcarrier center point; a sorting means for sorting and outputting the data output from the plurality of partial storage means in accordance with a data structure of the subcarrier data separated for each of the subcarriers based on the offset amount and the subcarrier center point; The partial storage means includes: a memory element array having a structure in which a plurality of memory elements are arranged in an array and in which the data is stored; a second selection means for selecting and outputting the data stored in the memory element array in response to the output control signal; Each of the plurality of partial storage means includes: a data group constituted by the data in any one of the cycles is written in response to the input control signal; From each of the plurality of partial storage means, The data for each of the subcarriers is read out sequentially in response to the output control signal.

23. A filter processing device comprising:

2. The address control means 2. The filter processing device according to claim 1, wherein the write address and the read address are designated so that the compensation for the offset amount and the separation of the subcarriers are performed simultaneously.

3. 3. The filter processing device according to claim 1, further comprising a calculation means for collectively executing an offset compensation process and a compensation process other than the subcarrier separation process on each of the plurality of subcarrier data separated for each subcarrier.

4. a coefficient calculation processing means for calculating a compensation coefficient used in the other compensation processing for each of the subcarriers based on the offset amount and the subcarrier center point; The calculation means includes:

4. The filter processing device according to claim 3, wherein the compensation coefficient calculated for each of the subcarriers by the coefficient calculation processing means is multiplied by each of the plurality of subcarrier data separated for each of the subcarriers.

5. Either the address control means or the coefficient calculation processing means The filter processing device according to claim 4 , wherein the value of the data that becomes unnecessary as a result of the offset compensation process is set to zero.

6. A filter processing device according to any one of claims 1 to 5, a Fourier transform device that performs a Fourier transform on a signal based on an optical signal and outputs Fourier transform data including a plurality of pieces of data after the Fourier transform to the filter processing device; a communication system including: an inverse Fourier transform device that acquires the plurality of data that have been subjected to offset compensation processing and subcarrier separation processing by the filter processing device, and performs an inverse Fourier transform on the plurality of data that have been subjected to the offset compensation processing and the subcarrier separation processing.

7. The computer a storage element array having a structure in which a plurality of storage elements in which a plurality of data included in Fourier transform data based on an optical signal are stored are arranged in an array, and the data stored in the storage element array are selected and output in response to an output control signal based on the offset amount and the subcarrier center point, and write addresses and read addresses of the plurality of data included in the Fourier transform data are specified for the storage means, so that compensation of the offset amount and separation of the subcarriers are performed based on an offset amount of a light source frequency and a subcarrier center point for each subcarrier by a same storage means having a plurality of partial storage means in which the plurality of data constituting the Fourier transform data are stored; writing a plurality of said data to said write addresses of said designated storage means; reading the data from the read address of the designated storage means; In the above specification, outputting an input control signal for allocating the plurality of data for each cycle; The storage means Distributing the input data to a plurality of the partial storage means in response to the input control signal; outputting the output control signal based on the offset amount and the subcarrier center point; rearrange and output the data output from the plurality of partial storage means in accordance with a data structure of the subcarrier data separated for each subcarrier based on the offset amount and the subcarrier center point; The computer, In the above writing, writing a data group constituted by the data of any one of the cycles into each of the plurality of partial storage means in response to the input control signal; In the reading, a filtering method for sequentially reading out the data for each subcarrier from each of the plurality of partial storage means in response to the output control signal;

8. A computer comprising: a process of specifying write addresses and read addresses of a plurality of the data included in the Fourier transform data to a storage means, so that compensation of the offset amount and separation of the subcarriers based on an offset amount of a light source frequency and a subcarrier center point for each subcarrier are performed by a same storage means including a storage element array having a structure in which a plurality of storage elements in which a plurality of data included in Fourier transform data based on an optical signal are stored are arranged in an array, the storage element array selects and outputs the data stored in the storage element array in response to an output control signal based on the offset amount and the subcarrier center point, and the storage means has a plurality of partial storage means in which a plurality of the data constituting the Fourier transform data are stored; A process of writing the plurality of data to the write addresses of the designated storage means; A process of reading the data from the specified read address of the storage means; In the above-mentioned designation process, and outputting an input control signal for allocating the plurality of data items for each cycle. The storage means includes: a process of distributing the input data to a plurality of the partial storage means in response to the input control signal; outputting the output control signal based on the offset amount and the subcarrier center point; a process of rearranging and outputting the data output from the plurality of partial storage means in accordance with a data structure of the subcarrier data separated for each subcarrier based on the offset amount and the subcarrier center point; In the writing process, a process of writing a data group constituted by the data of any one of the cycles into each of the plurality of partial storage means in response to the input control signal; In the reading, and sequentially reading out the data for each of the subcarriers from each of the plurality of partial storage means in response to the output control signal.

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