Method and apparatus for current sensing and current limiting - Patents.com

Abstract

Methods, devices, systems, and articles of manufacture for current sensing and current limiting are disclosed. An exemplary device includes a first main transistor (302) including a first main transistor gate terminal (306) coupled between the output terminal (108) and an intermediate node (201); a second main transistor (312) including a second main transistor gate terminal (318) coupled between the intermediate node (201) and a ground terminal; a first amplifier (350) including a first amplifier output (362) coupled to the first main transistor gate terminal (306); a second amplifier (310) including a second amplifier output (364) coupled to the second main transistor gate terminal (318); and a third amplifier (330) including a third amplifier inverting input coupled to the intermediate node (201), a third amplifier non-inverting input coupled to the sense transistor (314), and a third amplifier output coupled to a third gate terminal (338) of a third transistor (332).

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to electrical current, and more particularly, to current sensing and limiting. [Background technology]

[0002] Current sensing is a technique used to measure electrical current. The measured current ranges from picoamps to tens of thousands of amps. There are several ways to implement current sensing to determine the current measurement range. The choice of current sensing method depends on the current requirements of the circuit, such as the magnitude of the current, the accuracy of the measured current, the bandwidth, the robustness of the components conducting the current, the cost of the circuit implementing the current sensing method if current isolation is to be considered, or the size of the circuit. A current value may be generated during current sensing and displayed directly by an instrument, or may be converted from analog to digital form for use by a monitoring or control system. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a system in which a power sourcing equipment (PSE) provides power to a powered device (PD) over an Ethernet connection.

[0004] [Diagram 2] 2 is a schematic diagram showing additional details of an implementation of the current limiting circuit of FIG. 1.

[0005] [Diagram 3] 2 is a schematic diagram illustrating additional details of one disclosed implementation of the current limiting circuit of FIG. 1 including cascoded transistors.

[0006] [Figure 4] 4 is a signal plot illustrating current and voltage signals of the example current limiter of FIG. 3.

[0007] The drawings are not to scale. Generally, the same reference numerals are used throughout the drawings and the accompanying specification to refer to the same or similar parts. As used herein, stating that any part (e.g., a layer, film, area, region, or plate) is on another part in any manner (e.g., placed, located, disposed, or formed on another part, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intervening parts located therebetween. Stated that any part is in contact with another part means that there are no intervening parts between the two parts. Although the drawings show layers and regions with distinct lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may not be observable, may be blended, and / or may be irregular. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Connection references (e.g., attached, coupled, connected, and joined) should be interpreted broadly and, unless otherwise specified, may include intervening members between a group of elements and may include relative movement between the elements. As such, connection references do not necessarily imply that two elements are directly connected and in a fixed relationship to each other.

[0009] In this application, a method for current sensing and limiting is disclosed. Many applications require sensing the current through a power metal oxide semiconductor field effect transistor (MOSFET). Applications such as Power over Ethernet (PoE) require sensing the current through a Power Sourcing Equipment (PSE) by using a current sensing method within the PSE.

[0010] PoE is a standard that allows network cables to carry data and power to end nodes such as telephones in telecommunications systems, digital cameras in security systems, wireless adapters, etc.

[0011] A PSE is a device that provides power over an Ethernet cable and determines how much current a powered device can use before the current the PSE is overloading to provide to that device in the system. The PSE includes a current sensing and current limiting design that measures the amount of current a device draws and limits the current when the device is at or above full capacity. Examples disclosed herein include such designs for high voltage applications, such as PoE applications.

[0012] In some current sensing design examples, a sense MOSFET (sense FET) is used to "sense" (e.g., identify, identify, etc.) the current conducting through the main MOSFET (main FET). As used herein, the sense FET is of the same type as the main FET, but the width / length (W / L) ratio of the sense FET is smaller, so that only negligible current flows through the sense FET. The W / L ratio is the ratio of the physical width to the physical length of the MOSFET channel that determines the current flow through the MOSFET. For example, in a MOSFET, the channel acts as a conductor when it is in the saturation region (e.g., the region where the drain current is approximately independent of the drain-source voltage). The channel also acts as a conductor when it is in the linear region (e.g., the region where the drain-source voltage is small and therefore the relationship between the drain-source voltage and the drain-source current is approximately linear). In the linear region, the size (e.g., width and length) of the channel determines the resistance of the channel and therefore controls the amount of drain current when a particular voltage is applied to the drain terminal. In the saturation region, a pinch-off region forms at the drain end of the channel. If there is a further increase in the drain-source voltage, the voltage appears across the pinch-off region and does not affect the channel (e.g., the channel remains pinched off) and the drain current is fixed (e.g., saturated). Examples disclosed herein include a sense FET of the same length but different width as the main FET to sense the current sourced by the PSE to an end node (e.g., a powered device, PD).

[0013] In some current limiting design examples, a first amplifier is used to compare an analog value of a voltage (e.g., a voltage representing the current of an end node such as a PD) to a predefined current limiting voltage. A second amplifier is used to regulate the drain current through the sense FET so that the drain-source voltages of the main FET and the sense FET are equal, and therefore the current conducted through the sense FET is a replica of the current conducted through the main FET (e.g., similar to a current mirror). Typically, the second amplifier requires a low input offset voltage (e.g., a voltage difference between the inputs of the amplifier to operate in a closed feedback loop) to ensure that the drain voltages for each MOSFET are only a percentage of the threshold difference (e.g., an acceptably small difference).

[0014] The examples disclosed herein utilize cascoded power MOSFETs to isolate the high voltage of a PoE application from the internal circuitry used to sense the current of the end nodes. Cascoding power MOSFETs means stacking two or more MOSFETs in series. The upper power main FET (e.g., cascode) is coupled to the external load and arranged to receive a larger portion of the external load output voltage compared to the lower power main FET (e.g., cascoded transistor). The lower power main FET is coupled to the upper power main FET and arranged to control the current through the two main FETs. In the examples disclosed herein, the upper power main FET is designed for high voltage (e.g., 40 volts, 50 volts, 60 volts, 70 volts, etc.) and therefore dissipates substantially all of the heat during current limiting. In this way, the lower power main FET has less voltage, which reduces the heat generated in the lower power main FET and therefore improves the accuracy of current sensing.

[0015] FIG 1 is a block diagram of an example PoE environment 100 for providing power and data to a powered device (PD). A PoE switch includes internal circuitry that monitors and controls the current provided to a PD, as illustrated in FIG 2 and FIG 3. The example PoE environment 100 includes an example power sourcing equipment (PSE) 102 and an example PD 114 for communication over an example Ethernet cable 112. The example PSE 102 includes an example current limiter 106 and an example PSE port 110, and the example PD includes an example PD port 116, an example controller 118, and an example DC-DC converter 120.

[0016] 1 includes an example PSE 102 for detecting an example PD 114 and negotiating the amount of power available or required to provide to the example PD 114. For example, the PSE 102 provides network data and power to the PD 114 via an Ethernet cable 112. The example PSE 102 receives power via an example input terminal 104 from a DC power supply, a DC-DC converter, or the like. The example PSE 102 is typically used in wired Ethernet local area networks (LANs) to allow the current required for operation of each PD 114 to be carried by a data cable rather than by a power cord, thereby minimizing the number of wires used to install the network. The PSE 102 can also be utilized because the voltages used in PoE powered devices are very low, eliminating the need for a qualified electrician to install the PoE powered devices, a cord inspector to test the PoE powered devices, and the like.

[0017] 1, the example PSE 102 includes an example current limiter 106 for providing an applicable current to an example PD 114 via an example Ethernet cable 112. The example current limiter 106 is coupled to an example PSE port 110 via a current limit terminal output 108. The example current limiter 106 regulates the current provided to the example PD 114 via the example PSE port 110. The example current limiter 106 is described in further detail below in conjunction with FIG.

[0018] FIG. 1 includes an example PSE port 110 for distributing voltage over an example Ethernet cable 112. In some examples, the PSE port 110 includes two center-tapped transformers, with the input terminal 104 including a positive lead coupled to the center tap of one transformer and a negative lead coupled to a current limiter and further coupled to the center tap of another transformer via a current limiting terminal output 108. A transformer is an electrical device that transfers electrical energy from one circuit to another through a core and two coil windings. A center-tapped transformer is a contact made at a midpoint of one of the transformer windings to extract a common mode voltage (e.g., the average of the voltages at the two ends of the windings). The example PSE port 110 can be a standard Ethernet isolation transformer as required by IEEE 802.3 for data and power transmission over the Ethernet cable 112.

[0019] FIG. 1 includes an example Ethernet cable 112 for transmitting power and data from an example PSE 102 to an example PD 114. In some examples, the Ethernet cable 112 is Gigabit Ethernet (e.g., 1000BASE-T, requiring Category 5 cabling), which includes four twisted pairs: a main receive pair, a main transmit pair, a spare receive pair, and a spare transmit pair. The example PSE port 110 may be coupled to either end of the main receive pair and the main transmit pair, or to either end of the spare receive pair and the spare transmit pair. A two-pair PSE solution (e.g., the PSE 102) may choose to power either the main pair or the spare pair. The example PD 114 receives power on either the main pair or the spare pair and does so by inserting two bridge rectifiers, one of which is coupled to the center tap of the main pair and the other of which is coupled to the center tap of the spare pair. In this example, the bridge rectifier couples to the example controller 118. In this way, any PD receives power from the main pair or from the spare pair. For example, the main receive pair is coupled to the upper and lower taps of one of the transformers at the PSE port 110, and the main transmit pair is coupled to the upper and lower taps of another transformer at the PSE port 110. In some examples, all four pairs of the Ethernet cable 112 may be coupled to the PSE port 110 and the PD port 116. For example, in a four-pair PoE implementation, the PSE 102 injects power onto the main pair from one port (e.g., PSE port 110) and onto the spare pair from a second port (e.g., PSE port 110). In this example, the PD 114 remains the same, and the bridge rectifier directs power from both sets of pairs into the PD power path to the example controller 118.

[0020] The example Ethernet cable 112 may be used to carry signals such as video and current on two or all four of the pairs. The example Ethernet cable 112 assists the example PSE 102 and the example PD 114 in communicating to determine when power to the example PD 114 should be removed, limited, or provided.

[0021] 1 includes an example PD 114 for receiving and utilizing power provided via the example PSE 102. The example PD 114 may be a telephone system phone, a security camera, a network switch, etc. The example PD 114 communicates, transmits, and receives data, etc. from the example PSE 102 over an example Ethernet cable 112. In some examples, the PD 114 continuously draws current from the PSE 102 while the PSE 102 monitors how much current is being drawn. If the example PSE 102 or PD 114 is drawing too much current (e.g., exceeding a maximum current requirement set by the PD manufacturer or exceeding the amount of current the PSE 102 can supply), the example current limiter 106 applies a current limiting technique to reduce the current being drawn by the example PD 114. For example, when a connection is made between the PSE 102 and the PD 114, the PSE 102 and the PD 114 negotiate how much power the PD 114 is allowed to draw during a so-called "classification" process. After this process is completed, the PSE 102 limits the current that the PSE 102 provides to a maximum based on this negotiation. The example disclosed in FIG. 3 facilitates current sensing and current limiting of an exemplary PD 114.

[0022] In FIG. 1, the example PD 114 includes an example PD port 116 for receiving power from the example Ethernet cable 112 and transmitting power to the example controller 118. For example, the PD port 116 includes a four-center tap transformer, with the center taps coupled to a diode bridge rectifier. A diode bridge is an arrangement of four or more diodes in a bridge circuit configuration to make the PD 114 polarity independent, ensuring that the PoE environment 100 transmits DC power rather than AC power. For example, if the main transmit pair is positive and the main receive pair is negative, the diode bridge rectifier ensures that the example PD 114 can still extract power. Also, if the main transmit pair is negative and the main receive pair is positive, the diode bridge rectifier ensures that the example PD 114 can still extract power. The example PD port 116 maintains a constant flow of current from the Ethernet cable 112 through a diode bridge rectifier, allowing the PSE 102 to accurately sense the amount of current the PD 114 is drawing.

[0023] In FIG. 1, the example PD 114 includes an example controller 118 to support detection, classification, and overcurrent protection. For example, when the PD 114 is implemented in a PoE environment 100, a resistor of a certain value is coupled to the back side of two bridge rectifiers. The example PSE 102 then probes the example Ethernet cable 112 to determine the resistance, which is a detection signature. In some examples, a non-PoE Ethernet cannot apply this detection signature, and the example PSE 102 does not provide power to the non-PoE Ethernet. In some examples, the PSE 102 identifies the detection signature and applies a pattern of voltages to the Ethernet cable 112, and the example PD 114 applies a load current in response to these voltages. This is considered a classification process. For example, classification is a negotiation between the PSE 102 and the PD 114, which is a negotiation of the amount of current that the PD 114 can draw. Once this process is complete, the example PSE 102 applies sufficient voltage to the example Ethernet cable 112 and the example PD 114 uses (e.g., draws, absorbs) this voltage via the example controller 118. The example controller 118 provides inrush current limiting due to the capacitance of the applied voltage, and once inrush is complete, the current of the example PD 114 drops below the current limit.

[0024] In FIG. 1, the example PD 114 includes an example DC-DC converter 120 for further converting the output of the example PD port 116 to a desired voltage for an end device. For example, the end device may be a phone or a security camera that requires a different amount of voltage than the voltage provided by the PSE 102. The example DC-DC converter 120 may down-convert the voltage. For example, if the PD 114 receives a steady 48 volts from the example PSE 102, the DC-DC converter 120 reduces the 48 volts to 5 volts, which may be required by a phone. The example DC-DC converter 120 outputs the converted voltage to the end device via a DC-DC output 122. FIG. 2 shows a schematic diagram of current sensing and limiting without integrated pass transistor high-voltage and low-voltage MOSFETs using a sense FET. The current sense and limit schematic includes an example PD 114 and an example PSE port 110 for enabling the current sense and limit schematic high and low voltage MOSFETs to sense the current drawn by the PD 114. In FIG. 2, the pass FET 202 and the sense FET 204 are N-channel metal oxide semiconductor field effect transistors (MOSFETs). The pass FET 202 includes a first drain terminal 206 coupled to the example PSE port 110 at an intermediate node 201, a first gate terminal 208 coupled to the output of the second amplifier 248, and a first source terminal 210. The sense FET 204 includes a second drain terminal 212, a second gate terminal 214 coupled to the first gate terminal 208 at a node 218, and a second source terminal 216.

[0025] 2, the pass FET 202 is a low side drive power FET with a drain-source resistance that can be, for example, up to 60 milliohms, that controls the current provided to the PD 114. The pass FET 202 enters a linear mode of operation when the gate 208-source 210 voltage minus a threshold voltage is less than the drain terminal 206-source terminal 210 voltage and current freely conducts through the first drain terminal 206 to the first source terminal 210. The pass FET 202 enters a cutoff mode of operation when the voltage across the first gate terminal 208 to the first source terminal 210 is less than the threshold voltage. In the cutoff mode of operation, current stops conducting through the first drain terminal 206 to the first source terminal 210.

[0026] 2, sense FET 204 is the same type of low-side drive power FET as pass FET 202, but its W / L ratio is smaller, so that only negligible current conducts through sense FET 204. One typical W / L ratio is 1(W / L). P = 10,000 (W / L) S The sense FET 204 includes a second drain terminal 212 coupled to the servo amplifier 220 at a third node 240, a second gate terminal 214 coupled to the first gate terminal 208 at a second node 218, and a second source terminal 216. The sense FET 204 enters a linear mode of operation when the gate 214-source 216 voltage minus the threshold voltage is less than the drain 212-source 216 voltage and current is freely conducted through the second drain terminal 212 to the second source terminal 216. The sense FET 204 enters a cutoff mode of operation when the voltage across the second gate terminal 214 to the second source terminal 216 is less than the threshold voltage. In the cutoff mode of operation, current stops conducting through the second drain terminal 212 to the second source terminal 216.

[0027] In FIG. 2, a schematic diagram of current sensing and limiting without high and low voltage MOSFETs includes a servo amplifier 220 for adjusting the drain current conducted to the sense FET 204 through MOSFET M1 224 until the voltages on the intermediate node 201 and node 240 are substantially equal. The servo amplifier 220 includes a first inverting input coupled to the intermediate node 201, a first non-inverting input coupled to a third node 240, and a first output coupled to a third gate terminal 230 at a fourth node 222. The servo amplifier 220 compares the difference between the first inverting input and the first non-inverting input and generates a first output based on the difference. When the drain-source voltage of the sense FET 204 is lower than the drain-source voltage of the pass FET 202, the output voltage of the servo amplifier 220 is reduced, increasing the current through M1 and increasing the voltage on node 240. If the drain-source voltage of sense FET 204 is greater than the drain-source voltage of pass FET 202, the servo amplifier 220 output voltage increases, reducing the current through M1 224 and reducing the voltage on node 240 to substantially the same voltage as that on intermediate node 201.

[0028] 2, the schematic diagram of the current sensing and limiting without high and low voltage MOSFETs includes M1 224 for regulating the current conducted through the second drain terminal 212 and the second source terminal 216 of the sense FET based on the first output of the servo amplifier 220 coupled to the third gate terminal 230. M1 224 is a P-channel metal oxide semiconductor field effect transistor (P-channel MOSFET) and includes a third source terminal 228, a third gate terminal 230, and a third drain terminal 232 coupled to the second drain terminal 212 of the sense FET 204 at a third node 240. M1 224, being a P-channel MOSFET, begins to carry current through the third drain terminal 232 when the voltage at the third gate terminal 230 plus the threshold voltage of the third transistor 224 is less than the voltage at the third source node 228. The P-channel MOSFET ceases to carry current through the third drain terminal 232 when the voltage at the third gate terminal 230 plus the threshold voltage of the third transistor 224 is greater than the voltage at the third source node 228 .

[0029] 2, the current sensing and limiting schematic without high and low voltage MOSFETs includes M2 226 for imposing a current on resistor 246 to generate a voltage. M2 226 is a P-channel MOSFET that forms a current mirror with M1 224. M2 226 includes a fourth source terminal 234, a fourth gate terminal 236 coupled to the third gate terminal 230 at a fifth node 242, and a fourth drain terminal 238 coupled to the resistor 246 at a sixth node 244. M2 226 is controlled by a first output of the servo amplifier 220 and operates in a saturation mode when M1 224 operates in a saturation mode.

[0030] 2, the current sensing and limiting schematic without high and low voltage MOSFETs includes a resistor 246 for generating a voltage based on the current conducted from the fourth drain terminal 238. The resistor 246 is coupled to a second inverting input of a second amplifier 248 at a sixth node 244.

[0031] In FIG. 2, the current sensing and limiting schematic without high and low voltage MOSFETs includes a second amplifier 248 for controlling the pass FET 202 and therefore limiting the current in the load by adjusting the voltage of the first gate terminal 208. The second amplifier 248 includes a second non-inverting input 250, a second inverting input coupled to the resistor 246, and a second output coupled to the first gate terminal 208. The voltage at the second non-inverting input 250 is a current limit voltage that represents an analog value of the desired current limit to impose on the PD 114. The voltage at the second non-inverting input 250 is compared to the voltage at the second inverting input from the resistor 246 to limit the current drawn by the example PD 114 by reducing the current conducted to the first source terminal 210 via the first drain terminal 206.

[0032] In operation of the current sensing and limiting schematic without high and low voltage transistors to sense the current being provided by the Ethernet cable 112 to the PD 114, when the voltage at the first gate terminal 208 and the first source terminal 210 exceeds the threshold voltage of the pass FET 202, a current Iload 252 from the PSE port 110 is conducted to the first source terminal 210 of the pass FET 202 via the first drain terminal 206. Also, the voltage difference between the intermediate node 201 and the pass FET 202 is provided to a first inverting input of the servo amplifier 220 at the intermediate node 201.

[0033] The servo amplifier 220 compares the voltage at the first inverting input to the voltage at the first non-inverting input, which is also the voltage across the second drain terminal 212 to the second source terminal 216, which is coupled to the first non-inverting input at a third node 240. If the servo amplifier 220 determines that the voltage at the first non-inverting input is lower than the voltage at the first inverting input, the servo amplifier 220 generates an output voltage on a node 222 whose magnitude is proportional to the difference between the non-inverting and inverting inputs of the servo amplifier 220. A reduction in the voltage at the node 222 causes an increase in the current conducted through the transistor 224. Similarly, an increase in the voltage at the node 222 causes a reduction in the current conducted through M1 224.

[0034] When the servo amplifier 220 determines that the voltage at the first non-inverting input is progressively greater than the voltage at the first inverting input, the output of the servo amplifier 220 increases, thus decreasing the current conducted from the third drain terminal 232 of M1 224, which reduces the voltage at the first non-inverting input. The loop consisting of amplifier A1 220, M1 224, and sense FET 204 settles at an equilibrium point where the voltages at drain terminals 206 and 212 are substantially equal.

[0035] The loop consisting of the servo amplifier 220, M1 224, and the sense FET 204 constantly tries to match the drain-source voltage of the sense FET 204 with the drain-source voltage of the pass FET 202 by adjusting the voltage of the third gate terminal 230 as described in the paragraph above. The current IM1 254 conducted to the third drain terminal 232 through the third source 228 of M1 224 is the same as the current conducted to the second source terminal 216 through the second drain terminal 212. When the current IM1 254 conducted to the third drain terminal 232 increases, the voltage across the second drain terminal 212 to the second source terminal 216 increases. The third node 240 constantly supplies a voltage to the first non-inverting input of the servo amplifier 220 that represents the voltage difference between the voltage at the third node 240 and the voltage of the sense FET 204. In response, the servo amplifier 220 responds by increasing or decreasing its output voltage to match the voltage of the sense FET 204 with the voltage of the pass FET 202 .

[0036] A challenge arises for the pass FET 202 when its voltage is equal to the sense FET 204 voltage. In an ideal world, the servo amplifier 220 would have zero offset, but in reality, the two input pins of the servo amplifier 220 have different voltage potentials. The servo amplifier 220 must have a low input offset voltage in order for the servo amplifier 220 to accurately match the drain-source voltage of the sense FET 204 with the pass FET 202. These voltages must match very accurately when the MOSFET is operating in its linear region (e.g., when the gate-source voltage minus the threshold voltage is less than the drain-source voltage). The input offset requirement becomes stricter as the current conducted through the pass FET 202 is reduced to a low value.

[0037] A typical application of the current sensing and limiting schematic without high and low voltage transistors includes a power sourcing equipment (PSE) of a PSE 102 (e.g., current limiter 106 of FIG. 1). As used herein, a PSE is a device that provides source power onto an Ethernet cable 112. The PSE uses a pass FET 202 to control the current injected into the Ethernet cable 112. To meet the requirements of the highest power (e.g., Type-4) PSE defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3bt and to limit self-heating, the pass FET 202 has a worst-case maximum resistance of approximately 200 milliohms and a minimum resistance of approximately 60 milliohms (assuming a junction temperature of -40 to 125°C and normal process variations).

[0038] The PSE must sense currents as low as 5 milliamps to within an accuracy of a few milliamps to implement the DC-DC disconnect feature described in IEEE 802.3bt. If 5 milliamps is conducted through a pass FET 202 with a minimum resistance of 60 milliohms, then 0.3 millivolts will be conducted across the first drain terminal 206 to the first source terminal 210 of the pass FET 202. Any mismatch in the drain-source voltages of the pass FET 202 and the sense FET 204 will produce an equal percentage error in the current conducted through the second drain terminal 212 of the sense FET 204. The percentage error in the drain-source voltage is equal to the difference between the voltages at nodes 240 and 201 divided by the voltage at node 240 multiplied by 100%. The percentage error of the current at the second drain terminal 212 is equal to the deviation between the actual value of this current and the value this current would have if the voltages at nodes 240 and 201 were equal, divided by the actual value of this current, multiplied by 100%. A user may require the equal percentage error to be less than 5 percent or greater, in which case the servo amplifier 220 has an input offset voltage less than 5 percent of 0.3 millivolts (e.g., 5 percent of 0.3 millivolts is 15 microvolts). An offset voltage this small is difficult to obtain due to the large changes in the temperature gradient (e.g., heat up, heat down, etc.) created by the power dissipation in the pass FET 202, which disrupts the operation of the servo amplifier 220. For example, any two dissimilar materials in contact will generate a contact potential difference. In an isothermal system, all contact potential differences around any loop sum to zero. However, if the various contacts in the loop are at different temperatures, a net voltage difference will appear due to the Seebeck effect (e.g., more commonly called the thermoelectric effect). For example, the Seebeck potentials of metal-silicon contacts can be equal to within about 1 mV / °C. This means that the manufacturer or designer must control the temperature differences within parts of the amplifier to within a fraction of a degree Celsius to achieve microvolt-level accuracy.

[0039] In operation of the current sense and limit schematic without high and low voltage transistors to limit the current supplied to PD 114, pass FET 202 limits the current to a maximum value where the voltage on node 244 is approximately equal to the current limit voltage on the second non-inverting input 250. If PD 114 is drawing 1 amp and the W / L ratio is 1 (W / L), P = 10,000 (W / L) S , 1 amp is conducting through the first drain terminal 206 of the pass FET 202 and 0.1 milliamp is conducting through the second drain terminal 212 of the sense FET 204. This is due to the different sizes of the two MOSFETs. Since 0.1 milliamp is conducting through the sense FET 204, 0.1 milliamp is also conducting through M1 224.

[0040] In FIG. 2, M2 226 is a replica of M1 224. M2 226 is controlled by the servo amplifier 220 via a fifth node 242 that is coupled to the fourth node 222 of the first output. M2 226 operates in the same manner as M1 224. The current IM1 254 carried by M2 226 is imposed on a resistor 246 to generate a voltage. The resistor 246 is, for example, 10 kilohms, and since the current conducting M1 224 is 0.1 milliamps, the current conducting M2 226 is also 0.1 milliamps, thus generating a voltage of 1 volt across the resistor 246. The voltage generated across the resistor 246 is provided to a second inverting input of a second amplifier 248 via a sixth node 244. The second amplifier 248 compares the voltage at the second inverting input to the current limit voltage at the second non-inverting input 250. The current limit voltage is a preset voltage, so when the current limit voltage exceeds this preset voltage by 1 volt, the second amplifier 248 reduces the voltage at the first gate terminal 208 until the voltage of the resistor 246 drops to equal the current limit voltage at the second non-inverting input 250. When the second amplifier 248 reduces the voltage at the second output to the first gate terminal 208 and the second gate terminal 214, this limits the current of the PD 114 because reducing the voltage at the first gate terminal 208 reduces the current flow from the first drain terminal 206 to the first source terminal 210, providing less current to the PD 114.

[0041] However, when the second amplifier 248 reduces the voltage at the first gate terminal 208 and the current conducted across the first drain terminal 206 reduces, the pass FET 202 leaves the linear region and enters the saturation region (e.g., where the MOSFET acts as a voltage-controlled current source). This occurs when the end device of the PD 114 has a resistance below a certain threshold and the current exceeds the current limit, or when the end device of the PD 114 is shorted and equals the supply voltage (e.g., the voltage provided by the PD port 116). When the voltage of the pass FET 202 is high, the voltage of the sense FET 204 is also high, indicating that the servo amplifier 220 includes a rail-to-rail input common-mode range. The common-mode range is the range of voltages at the input of an amplifier over which the amplifier provides at least its minimum rated DC open-loop gain (e.g., the gain obtained when no feedback is used in the circuit). The rail-to-rail input common mode range is the range over which the voltage includes the positive supply to the amplifier and ground, which is typically large (e.g., the positive supply may be 50 volts) especially in PoE applications, in order to operate as intended. For example, a single supply amplifier is powered by a positive supply and includes a return path back to ground referenced to this supply. In another example, there is a dual supply amplifier that is powered by a positive and negative supply referenced to ground, in which case the input common mode range extends from the positive supply voltage to the negative supply voltage. This presents a challenge for current sensing and limiting schematics without high and low voltage transistors, because the servo amplifier 220 must also have a low input offset, which can be difficult to obtain. This is made more difficult by the high voltage on the input stage, since the input stage must be built to withstand the high voltage.

[0042] The example of FIG. 3 illustrates an example current limiting circuit that overcomes the challenges of the current sensing and limiting schematic without high and low voltage transistors described in the paragraph related to FIG. 2. A method for overcoming the challenges of the current limiting schematic without high and low voltage MOSFETs of FIG. 2 is described below in connection with FIG. 3. FIG. 3 includes an example current limiting circuit 106, an example power sourcing equipment port (PSE port) 110, an example Ethernet cable 112, and an example PD 114. The example current limiting circuit 106 of FIG. 3 is a cascoded circuit that includes an example high voltage MOSFET (Mph) 302, an example amplifier (A3) 310, an example low voltage MOSFET (Mpl) 312, an example sense FET 314, an example current sense amplifier (Al) 330, an example first control MOSFET (M1) 332, an example second control MOSFET (M2) 334, an example resistor 348, and an example current limiting amplifier (A2) 350.

[0043] 3 includes an example PSE port 110 for transmitting and receiving data and power over an example Ethernet cable 112. PSE port 110 is described in relation to FIG.

[0044] 3 includes an example Ethernet cable 112 for communicating between an example PSE 102 and an example PD 114 in a Power over Ethernet application. The example Ethernet cable 112 is described in connection with FIG.

[0045] 3 includes an example PD 114 for utilizing current provided by the example current limiting circuit 106 via the example Ethernet cable 112. The example PD 114 is a powered device circuit. The example PSE port 110 is coupled to the example PD 114 via the example Ethernet cable 112 and includes a main receive pair and a main transmit pair. The example PD 114 receives power from the example PSE 102 by a DC current imposed on the main transmit pair and the main receive pair. The main receive pair of the example Ethernet cable 112 may be coupled to one of the transformers of the example PSE port 110 and the example PD port 116, and the main transmit pair of the example Ethernet cable 112 may be coupled to another transformer of the example PSE port 110 and the example PD port 116.

[0046] 3 includes an example high voltage MOSFET Mph 302 for limiting the current provided by the example current limiting circuit 106 and for isolating the example PD 114 high voltage received by the example Ethernet cable 112 from a current sensing MOSFET, which will be further described below. The example Mph 302 is a low side drive N-channel MOSFET and includes an example Mph drain terminal 304, an example Mph gate terminal 306, and an example Mph source terminal 308. The example Mph drain terminal 304 is coupled to the output terminal 108 (e.g., current limiting terminal 108) at node 360 ​​to receive voltage from the example PD 114 via a center tap of a transformer at the example PSE port 110, the example Mph gate terminal 306 is coupled to the example current limiting amplifier (A2) 350, and the example Mph source terminal 308 is coupled to the example Mpl drain terminal 316 of the example low voltage MOSFET (Mpl) 312.

[0047] In some examples, Mph302 is an upper transistor because it is placed above a lower transistor (e.g., Mpl 312). Mph302 can also be a first main transistor including a first main transistor drain terminal, a first main transistor gate terminal, and a first main transistor source terminal. Alternatively, Mph302 can be a high side drive N-channel MOSFET, a low side drive P-channel MOSFET, or a high side drive P-channel MOSFET, and Mph302 can be coupled to different features of the schematic diagram in terms of type of MOSFET.

[0048] 3 includes an example low voltage MOSFET (Mpl) 312 for providing a small voltage to an example sense amplifier 330 for an example sense FET 314 to accurately sense the current drawn by the example PD 114. The example Mpl 312 is a low side drive N-channel MOSFET and includes an example Mpl drain terminal 316, an example Mpl gate terminal 318, and an example Mpl source terminal 320. The example Mpl drain terminal 316 is coupled to an example Mph source terminal 308 and an example A1 inverting input at the intermediate node 201. The example Mpl gate terminal 318 is coupled to an example A3 output, which controls the gate-source voltage of Mpl 312. The example Mpl source terminal 320 is coupled to a ground terminal.

[0049] In some examples, Mpl 312 is a lower transistor because it is below an upper transistor (e.g., Mph 302). Mpl 312 may also be a second main transistor including a second main transistor drain terminal, a second main transistor gate terminal, and a second main transistor source terminal. Alternatively, Mpl 312 may be a second main FET, a high side drive N-channel MOSFET, a low side drive P-channel MOSFET, or a high side drive P-channel MOSFET.

[0050] To alleviate the issues of the current sensing and limiting schematic without high and low voltage MOSFETs, an example high voltage MOSFET Mph 302 and an example low voltage MOSFET Mpl 312 replace the single pass FET 202 illustrated in FIG. 2. In some examples, the current sensing and limiting schematic of FIG. 3 is applied to the example current limiting circuit 106 of the PSE 102 to limit self-heating and further improve the accuracy of the current sensing. Although there are two MOSFETs (e.g., Mph 302 and Mpl 312) instead of one (e.g., pass FET 202), the IEEE 802.3bt requirement of worst case maximum resistance applies to the sum of the resistances of the MOSFETs (e.g., Mph 302 and Mpl 312). For example, the sum of the on resistances of the example Mph 302 and example Mpl 312 is equal to the worst case maximum resistance, resulting in a minimal increase in the total area size used relative to the pass FET 202 of FIG. 2.

[0051] An exemplary scheme for determining the dimensions of the two MOSFETs Mph 302 and Mpl 312 is described below. To minimize the total area consumed by the two MOSFETs Mph 302 and Mpl 312, the on-resistance of each MOSFET satisfies Equation 1. TIFF0007641265000001.tif20136

[0052] In Equation 1, the variable R onH corresponds to the on-resistance of the exemplary Mph302. As used herein, the on-resistance of a MOSFET is the drain-source resistance between the drain and source terminals when the MOSFET is operating in a linear mode with the maximum allowable gate-source voltage. In Equation 1, the variable R onL corresponds to the on-resistance of an example Mpl 312. In some instances, the on-resistance of a high-voltage MOSFET (e.g., Mph 302) is greater than the on-resistance of a low-voltage MOSFET (e.g., Mpl 312) because high-voltage MOSFET device structures typically require a larger rain-source spacing than low-voltage MOSFET device structures.

[0053] In Equation 1, the variable R spH corresponds to the specific on-resistance of the example Mph302. As used herein, specific on-resistance is a figure of merit for a power transistor that is determined by measuring the Rds(on) of a MOSFET of a known area. The Rds(on) of a MOSFET is also multiplied by its area, and the result is the specific on-resistance. In this manner, the equation Rds(on)=Rsp / A can be used to determine the Rds(on) for a MOSFET of any desired area, or alternatively, the area required for a MOSFET of any desired on-resistance. In Equation 1, the variable R spL corresponds to the specific on-resistance of the exemplary Mpl 312. Typically, the specific on-resistance of a high-voltage transistor is greater than the specific on-resistance of a low-voltage transistor. For example, R spH R spL If the value is 16 times that of R, then according to Eq. onH is R onL (For example, R onH is equal to 4 / 5 of the total Ron of the stacked devices, and R onL (Equal to 1 / 5). This example suggests that adding a low voltage Mpl 312 does not significantly increase the area of ​​the example schematic.

[0054] 3 includes an example amplifier (A3) 310 for providing voltages to the example Mpl 312 and the gate terminals of the example sense FET 314 to regulate the voltage across the example Mpl drain terminal 316 to the example Mpl source terminal 320 to a value that is sufficient to ensure that the sense amplifier 330 does not have to accommodate for low voltages (e.g., microvolts) while the example PD 114 current Iload 252 changes. The example amplifier A3 310 includes an example A3 amplifier non-inverting input, an example A3 amplifier inverting input, and an example A3 amplifier output. The example amplifier A3 310 changes the voltage at the Mpl gate terminal 318 as the PD 114 current Iload 252 changes. For example, the amplifier A3 310 regulates the voltage at the example Mpl drain terminal by adjusting the A3 output to make the A3 inverting input equal to the set voltage (Vs) 309 at the A3 non-inverting input.

[0055] 3, if the gate-source voltage is set to the maximum allowed value (e.g., 3 volts) and the drain current is set to the current limit, the example Vs 309 is typically set to approximately equal the voltage that can be produced at Mpl 312 (e.g., 25 millivolts). A higher voltage would unnecessarily increase the power dissipation in Mpl 312 at high currents, while a lower voltage would increase the effect of offsets in the sense amplifier 330. For example, without amplifier A3 310, if Mpl 312 is 50 milliohms when fully enhanced, a 10 milliamp Mpl drain 316 current would generate 0.5 millivolts (e.g., 500 microvolts). Therefore, the sense amplifier 330 is configured to accommodate input offsets as low as 0.5 millivolts. Also, to achieve the desired accuracy of + / - 2%, the sense amplifier 330 is configured to tolerate input offset voltages of less than 10 microvolts, which can be difficult to achieve.

[0056] To address the above issues, the example amplifier A3 310 is configured to regulate the drain-source voltage of the example Mpl 312 to a value large enough for the sense amplifier 330 to detect. In this manner, good accuracy of current sensing can be achieved. For example, the operation of the sense transistor 314 is optimized by the regulated voltage provided by A3 310. In one implementation, for example, A3 310 optimizes the operation of the sense FET 314 by regulating the voltage applied to the Mpl gate terminal 318 and the sense FET gate terminal 324 to a set voltage value Vs 309.

[0057] If the current Iload 252 of the PD 114 becomes too large (e.g., near the current limit), the amplifier A3 310 does not increase the voltage at the Mpl gate terminal 318 to a value large enough to cause the voltage at the Mpl drain terminal 316 to the value of the set voltage 309. In this manner, the voltage at the Mpl gate terminal 318 rails out to a constant value, and the voltage at the Mpl drain terminal 316 varies as a function of the drain current. As a result, the example sense amplifier 330 is configured to regulate the voltage at the sense FET drain terminal 322 to vary with the voltage at the Mpl drain terminal 316.

[0058] The example current limiting circuit 106 continues to operate properly carrying the voltage at node 244, where the voltage at node 244 is proportional to the current conducting through the example PSE port 110, and furthermore, even if the voltage at Mpl drain terminal 316 exceeds the voltage at Vs 309, the example current limiting circuit 106 implements current limiting via voltage Vcl 352. Advantageously, by controlling Mph 302 rather than Mpl 312, Mpl 312 continues to operate in the triode region. In this manner, the need for amplifier A1 330 to have a rail-to-rail input stage is eliminated.

[0059] 3 includes an example sense FET 314 for sensing the current conducted through the low voltage MOSFET 312 and determining an example A1 output of an example sense amplifier 330. The example sense FET 314 includes an example sense FET drain terminal 322, an example sense FET gate terminal 324, and an example sense FET source terminal 326. The example sense FET drain terminal 322 is coupled to an example A1 non-inverting input of the sense amplifier 330 via an example third node 240. The example sense FET gate terminal 324 is coupled to an example Mpl gate terminal 318 via a second node 218. The example Mpl source terminal 326 is coupled to a ground terminal.

[0060] The example sense FET 314 is a low side drive N-channel MOSFET of the same type as the example low voltage MOSFET 312, but with a different W / L ratio. Also, the sense FET 314 may be a sense transistor including a sense transistor drain terminal, a sense transistor gate terminal, and a sense transistor source terminal. Alternatively, the sense FET 314 may be a high side drive N-channel MOSFET, a low side drive P-channel MOSFET, or a high side drive P-channel MOSFET.

[0061] 3 includes an example current sense amplifier 330 for matching a voltage across an example Mpl drain terminal 316 to an example Mpl source terminal 320 with a voltage across an example sense FET drain terminal 322 to an example sense FET source terminal 326 by adjusting an example A1 output to a voltage value that increases or decreases the current conducted through an example first control MOSFET M1 332. The example sense amplifier 330 includes an example sense amplifier inverting input, an example sense amplifier non-inverting input, and an example sense amplifier output. The sense amplifier inverting input is coupled to the Mpl drain terminal 316 via the intermediate node 201, the sense amplifier non-inverting input is coupled to the sense FET drain terminal 322 via the third node 240, and the sense amplifier output is coupled to the M1 gate terminal 338 via the fourth node 222.

[0062] 3 includes an example first control MOSFET M1 332 for matching a current conducted through an example sense FET drain terminal 322 with a current conducted through an example Mpl drain terminal 316. The example first control MOSFET M1 332 is a P-channel MOSFET including an example M1 source terminal 336, an example M1 gate terminal 338, and an example M1 drain terminal 340. In some examples, the M1 drain terminal is coupled to the sense FET drain terminal 322 through a third node 240. A first current IM1 341 conducted through the example M1 drain terminal when the first control MOSFET M1 332 is in a saturation mode of operation is provided to the example sense FET drain terminal 322. Additionally or alternatively, the example first control MOSFET 332 may be an N-channel MOSFET, a bipolar junction transistor (BJT), or the like.

[0063] 3 includes an example second control MOSFET M2 334 for imposing a voltage across an example resistor R1 348. The example second control MOSFET M2 334 is a replica of the example first control MOSFET M1 332 and is therefore a P-channel MOSFET. The example second control MOSFET M2 334 includes an example M2 source terminal 342, an example M2 gate terminal 344, and an example M2 drain terminal 346. The example M2 gate terminal 344 is coupled to the M1 gate terminal 338 via the fifth node 242, and the example M2 drain terminal is coupled to the example resistor 348 via the sixth node 244. The current conducted through the example M2 drain terminal 346 is of the same magnitude as the current conducted through the example M1 drain terminal 340 and is therefore labeled as IM1 341. For example, the two MOSFETs M1 332 and M2 334 are replicas of each other and receive the same voltage at their gate terminals (M1 gate terminal 338, M2 gate terminal 344) via the example A1 output. Additionally or alternatively, the example second control MOSFET M2 332 may be an N-channel MOSFET, a bipolar junction transistor (BJT), or the like.

[0064] 3 includes an example resistor 348 for generating a voltage based on the first current IM1 341 conducted from the example M2 drain terminal 346 when the example second control MOSFET M2 334 is operating in a saturated mode of operation. The example resistor 348 is coupled to an example A2 inverting input of the example current limiting amplifier 350 at the sixth node 244 and provides a generated voltage to the example A2 inverting input.

[0065] FIG. 3 includes an example current limiting amplifier A2 350 for controlling the example high voltage MOSFET 302 by adjusting the voltage on the example Mph gate terminal 306, thus limiting the current provided to the example PD 114. The example current limiting amplifier A2 350 includes an example A2 amplifier non-inverting input, an example A2 amplifier inverting input, and an example A2 amplifier output 362. The example A2 amplifier output 362 is coupled to the example Mph gate terminal 306 and determines the current conducted through the example Mph 302. A current limiting voltage Vcl 352 is provided to the example A2 non-inverting input. The voltage value of Vcl 352 is a set value that is compared to the voltage on the sixth node 244. If the voltage at node 244 exceeds the value of Vcl 352, the example A2 output 362 decreases and in response, the current conducted through Mph 302 decreases. This reduction in current through Mph302 limits the current provided to the exemplary PD114.

[0066] 3, the example Mpl 312 is not rated to withstand the voltage at node 360 ​​(e.g., Mpl 312 will not operate as intended when the voltage at node 360 ​​is disturbed at Mpl 312), but rather the example Mpl 312 is rated to operate at the maximum current limit voltage Vcl 352 imposed by the example amplifier A2 350 minus the gate-source voltage of the example Mph 302. In some examples, a transient event may occur and A3 310 cannot regulate the voltage at the intermediate node 201, but Mph 302 still protects Mpl 312 from receiving the transient voltage because Mph 302 drops most of the voltage across the Mph drain terminal 304 and the Mph source terminal 308.

[0067] This is the first challenge overcome by the current limiting circuit of FIG. 3, shown in the paragraph above corresponding to the schematic diagram of current sensing and limiting without high and low voltage MOSFETs of FIG. 2. In some techniques for sensing current, a problem occurs in matching the pass FET 202 and the sense FET 204 due to heat dissipation in the pass FET 202. If the pass FET 202 gets hotter (e.g., dissipates more heat) than the sense FET 204, the matching between the two MOSFETs 202, 204 is disturbed and the pass FET drain terminal 206 current and the sense FET drain terminal 212 current do not have the same W / L ratio. By splitting the pass FET 202 of FIG. 2 into a high voltage upper MOSFET (e.g., Mph 302) and a low voltage lower MOSFET (e.g., Mpl 312), Mph 302 dissipates most of the power (e.g., heat) and Mpl 312 associated with the sense FET 314 does not dissipate power. Because the low-voltage MOSFET 312 dissipates little power, the accuracy of current sensing is improved due to the reduced importance of the problems discussed above. Therefore, the current limit circuit 106 includes a more accurate current sensing capability than the current limit circuit of FIG. 2 without the high and low voltage transistors.

[0068] The example A3 inverting input is compared to the value of the set voltage 309 at the example A3 non-inverting input, and the example amplifier A3 310 acts to match the two inputs. For example, the set voltage 309 may be 25 millivolts, and the voltage at the Mpl drain terminal may be greater than such set voltage 309 value, so that the amplifier 310 generates an output voltage for the Mpl gate terminal 318 that is small enough to keep the low voltage MOSFET 312 in triode mode operation and match the voltage at the Mpl drain terminal 316 to Vs 309. The example current sense amplifier 330 operates similarly to the servo amplifier 220 of FIG. 2, where the example servo amplifier 330 generates an output that matches the voltage at the example sense FET drain terminal 322 to the voltage at the example Mpl drain terminal.

[0069] This is the second challenge overcome by the current sensing and limiting schematic of FIG. 3, shown in the paragraph above corresponding to the current sensing and limiting schematic without high and low voltage MOSFETs of FIG. 2. The example amplifier A3 310 regulates the drain-source voltage of the low voltage MOSFET Mpl 312 to a small value, which is the input voltage to the example A1 inverting input. This regulation of the input voltage relaxes the requirement for a low input offset voltage of the servo amplifier 330, compared to the servo amplifier 220 of FIG. 2. For example, without drain voltage regulation, the servo amplifier 220 required a total input offset voltage of 15 microvolts or less to guarantee a 5 percent or less mismatch in drain voltage for two MOSFETs (e.g., pass FET 202 and sense FET 204) with a minimum on-resistance of 60 milliohms, operating at a minimum current of 5 milliamps. By regulating the drain-source voltage of the example Mpl 312 to a small voltage value (e.g., 25 millivolts), the 5 percent mismatch requirement dictates that the example current sense amplifier 330 will have an input offset of a few millivolts (e.g., 1.25 millivolts, which is 5 percent of 25 millivolts) or less. This input offset value is approximately 80 times larger than the input offset of the current sense and limit schematic without the high and low voltage MOSFETs presented, which improves the accuracy of sensing the current in the example current limit circuit 106.

[0070] The example sense amplifier 330 overcomes the third problem shown in the current sensing and limiting schematic without high and low voltage MOSFETs in FIG. 2. Due to the regulated drain-source voltage of the low voltage MOSFET Mpl 312, the example servo amplifier 330 does not need to be built to handle rail-to-rail input voltages like the servo amplifier 220. The rail-to-rail input voltage of the schematic without high and low voltage MOSFETs was due to the high voltage provided by the example Ethernet cable 112 through the example PD 114. The voltage of the intermediate node 201 is regulated by the example amplifier A3 310 and is also input to the A1 inverting input of the example current sense amplifier 330. This means that the example sense amplifier 330 can be built for input voltages near ground. In some worst case scenarios, due to a transient, the voltage of the intermediate node 201 may increase.

[0071] In another example, Mpl 312 may operate at worst case maximum on-resistance and highest Iload252, resulting in Mpl 312 entering saturation region. When these two worst case examples occur, the common mode range for the example servo amplifier 330 extends 1-2 volts above ground to accommodate these difficulties, which is better than designing the amplifier to handle rail-to-rail input voltages. For example, a rail-to-rail design may include two input differential pairs, one optimized for low voltages and the other for high voltages. By reducing the required input common mode range, the example of FIG. 3 eliminates the need for a separate input differential pair.

[0072] 3, the example sense FET 314 operates in conjunction with the example low voltage MOSFET Mpl 312 such that when Mpl 312 is in a linear mode of operation, the sense FET 314 is also in a linear mode of operation. For example, when the amplifier A3 310 generates an output voltage at the Mpl gate terminal 318 that regulates the drain-source voltage of Mpl 312 to operate in a triode mode, the output voltage is also generated at the sense FET gate terminal 324, thus acting to keep the sense FET 314 in a triode mode of operation. When the voltage across the example sense FET gate terminal 324 to the example sense FET source terminal 326 is positive and exceeds the threshold voltage of the example sense FET 314, the example sense FET 314 conducts a first current IM1 341 through the example sense FET drain terminal 322.

[0073] In some examples, the first current IM1 341 is provided by the example first control MOSFET M1 332 and changes when the A1 output changes. For example, the sense amplifier 330 controls the current IM1 341 by using M1 332, and the current IM1 341 imposed on the drain-source resistance of the sense FET 314 generates a voltage. The sense amplifier 330 makes this voltage approximately match the voltage generated by Iload 252 conducted through Mpl 312. In this way, the currents IM1 341 and Iload 252 are made to be in the same ratio as the W / L values ​​of the example Mpl 312 and the example sense FET 314.

[0074] In this way, the example of FIG. 3 has advantages over the current sensing and limiting schematic without high and low voltage MOSFETs illustrated in FIG. 2. Because the gate terminal 324 of the example sense FET 314 receives the output voltage of the example amplifier 310, the sense FET 314 is operating in a linear region (e.g., triode mode operation). Therefore, the example sense FET 314 does not need to be optimized for robustness because it operates in a linear region, and when a transient event (e.g., a short-term surge of electrical energy) occurs, the drain-source voltage of Mpl 312 is limited to the difference between the Mph gate terminal 306 voltage and the Mpl gate-source voltage. The example schematic of FIG. 3 does not need to correct for hot carrier generation of the example sense FET 314, which simplifies the circuit elements. Hot carriers are defined as holes or electrons that have gained high kinetic energy after being accelerated by a strong electric field in areas of high magnetic field strength within the MOSFET, and due to their high kinetic energy, they can be injected into areas of the MOSFET, forming space charges and degrading or destabilizing the device.

[0075] In FIG. 3, the example schematic includes a second control MOSFET M2 334 for imposing a first current IM1 341 across an example resistor 348 to generate a voltage. The generated voltage is provided to an A2 inverting input of an example current limit amplifier 350 and compared to a current limit voltage Vcl 352 at the A2 non-inverting input. The voltage generated by the example resistor 348 is proportional to the current drawn by the example PD 114. The example current limit voltage 352 is a value that represents a desired current limit for the example PD 114. If the example PD 114 does not draw too much current, no current limiting occurs. If the example PD 114 draws too much current, current limiting occurs, as indicated by the voltage generated by the resistor 348. In this manner, the voltage at node 244 increases above Vcl 352, the current limiting amplifier A2 350 throttles the voltage provided to the Mph gate terminal 306, and the current to the example PD 114 is reduced until the voltage at node 244 equals Vcl 352.

[0076] 4 is an example graph illustrating voltage and current signals of an example PD 114, an example high voltage MOSFET Mph 302, and an example low voltage MOSFET Mpl 312. FIG. 4 includes an example first graph 400, an example second graph 402, an example third graph 404, an example fourth graph 406, and an example fifth graph 408. The example first graph 400 illustrates the external load Iload current 252, the example second graph 402 illustrates the voltage at an example node 360, the example third graph 404 illustrates the voltage at an example Mpl drain terminal 316, the example fourth graph 406 illustrates the voltage at an example A2 output pin 362, and the example fifth graph 408 illustrates the voltage at an example A3 output pin 364.

[0077] In FIG. 4, the example first graph 400 shows the example PD 114 current Iload 252 as a signal increasing up to a current limit imposed by the example current limiting amplifier A2 350. For example, the resistance of the PD 114 end device may decrease, and therefore the current conducting the PD 114 end device is increasing. As the Iload 252 current is increasing, the example current limiting amplifier 350 outputs a high voltage (e.g., Vg(max)) to the example Mph gate terminal 306 to keep the example Mph 302 on until the PD 114 current Iload 252 reaches the current limit at time t1. In the example fourth graph 406, Vg(max) is defined as the maximum voltage the circuit applies to the gate, which should not exceed the maximum operating voltage allowed by the device specifications. In this way, providing the maximum amount of voltage to the example Mph gate terminal 306 sufficiently enhances the high voltage MOSFET 302 and minimizes its on-resistance (e.g., Rdson). For example, the second graph 402 shows the voltage at node 360 ​​at a low voltage (e.g., near zero volts) when the current Iload 252 starts at zero, and because Mph 302 is operating in its linear region, the voltage at node 360 ​​rises linearly with the current Iload 252 until time t1.

[0078] 4, the example third graph 404 shows the voltage at the Mpl drain terminal 316 being regulated by the example amplifier A3 310 to be equal to Vs 309. For example, A3 310 matches the Mpl drain terminal 316 to be equal to the value of Vs 309 by adjusting the voltage of the A3 output 364 that is coupled to the Mpl gate terminal 318. By adjusting the voltage applied to the example Mpl gate terminal 318, the example A3 output 364 controls the amount of voltage that flows through the example Mpl 312, which is why the voltage signal at the example Mpl drain terminal 316 is a flat line equal to Vs 309 until time t2 is reached.

[0079] In FIG. 4, the example fifth graph 408 shows that the voltage on the A3 output 364 applied to the example Mpl gate terminal 318 is increasing until time t2. For example, as the current Iload 252 increases, the voltage of the A3 output 364 increases to keep the voltage of the Mpl drain terminal at the same value as Vs 309. The curve shown in the example fifth graph 408 continues to increase until time t2 is reached, which shows the maximum gate voltage (Vg(max)) of the example Mpl 312. For example, when the voltage of the A3 output 364 is increasing, there is a limit to how much the voltage can increase to, and such limit is the maximum voltage that the Mpl gate terminal 318 must undergo. In some examples, Vg(max) is defined by the transistor manufacturer to avoid damaging the transistor.

[0080] 4, when the current Iload 252 is increasing (first graph 400), the example amplifier A3 310 outputs an increasing voltage at the A3 output 364 (fifth graph 408) to keep the voltage at the example Mpl drain terminal 316 equal to Vs 309 (third graph 404) until the A3 output 364 voltage is equal to the Vg(max) of the example Mpl 312. When the example A3 output 364 voltage is equal to the Vg(max) of the example Mpl 312 at time t2, the example amplifier A3 310 stops increasing the A3 output 364 voltage and provides the Vg(max) voltage to the example Mpl gate terminal 318. Also, when the example A3 output 364 voltage stops increasing, the voltage at the example Mpl drain terminal 316 increases compared to the voltage Vs 309. For example, when amplifier A3 310 can no longer act to match Mpl drain terminal 316 to Vs 309 by adjusting its output 364 voltage, the voltage at Mpl drain terminal 316 begins to increase, as shown at time t2 in the third graph 404.

[0081] At time t1, when the current Iload 252 reaches the current limit, as shown in the example first graph 400, the example current limiting amplifier A2 350 reduces the voltage provided to the Mph gate terminal 306 (fourth graph 406). For example, the current limiting amplifier A2 350 imposes the current limit by controlling the switching characteristics of the Mph 302. When the example current limiting amplifier A2 350 reduces the output voltage to the Mph gate terminal 306, the current limiting amplifier A2 350 reduces the current conducted through the example Mph 302 by transitioning the example Mph 302 from a linear region to a saturation region. Thus, at time t1, the voltage at the example Mpl drain terminal 316 (third graph 404) stops increasing and becomes a flat signal because the Mpl drain terminal 316 voltage is now a function of the current Iload 252, which is also a flat signal. As used herein, the term flat is defined as a signal displayed on a graph that does not increase or decrease over time.

[0082] In this application, "comprising" (and all variations and tenses thereof) is used as an open-ended term. Therefore, whenever a claim uses any form of "comprising" (e.g., includes, includes, has, etc.) as a preamble or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used in this application, when the phrase "at least" is used as a transition term, for example in a claim preamble, it is open-ended in the same way that the term "comprising" is open-ended. The term "and / or," when used in the form A, B, and / or C, for example, refers to any combination or subset of A, B, and C, such as (1) A only, (2) B only, (3) C only, (4) A and B, (5) A and C, (6) B and C, and (7) A, B, and C. As used herein, in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein, in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein, in the context of describing the performance or execution of a process, instruction, act, activity, and / or step, the phrase "at least one of A and B" is intended to refer to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.Similarly, as used herein, in the context of describing the performance or execution of a process, instruction, act, activity, and / or step, the phrase “at least one of A or B” is intended to refer to implementations that include any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.

[0083] From the above, it will be appreciated that exemplary methods, apparatus, and articles of manufacture have been disclosed for sensing and limiting current in high voltage applications by cascoding a high voltage MOSFET with a low voltage MOSFET to improve the accuracy of the current sensing and therefore appropriately limit the current provided to an external load, such as a powered device. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of using computing devices by improving the accuracy of the current sensing techniques to effectively limit the current to the high voltage external load. Thus, the disclosed methods, apparatus, and articles of manufacture are directed to one or more improvements in the functionality of a computer.

[0084] Although example methods, apparatus, and articles of manufacture have been disclosed herein, the scope of application of this application is not limited thereto. Rather, this application covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this application.

Claims

1. An apparatus comprising: a first transistor having a first current terminal coupled to the output terminal, a second current terminal, and a first control terminal; a second transistor having a third current terminal coupled to the second current terminal, a fourth current terminal coupled to a ground terminal, and a second control terminal; a third transistor having a fifth current terminal, a sixth current terminal and a third control terminal coupled to the second control terminal; a fourth transistor having a seventh current terminal, an eighth current terminal coupled to the fifth current terminal, and a fourth control terminal; a fifth transistor having a ninth current terminal coupled to the seventh current terminal, a tenth current terminal, and a fifth control terminal coupled to the fourth control terminal; a first amplifier having a first inverting input coupled to the tenth current terminal and a first amplifier output coupled to the first control terminal; a second amplifier having a second amplifier output connected to the second control terminal and to the third control terminal; a third amplifier having a second inverting input coupled to the second current terminal, a non-inverting input coupled to the fifth current terminal, and a third amplifier output coupled to the fourth control terminal; 13. An apparatus comprising:

2. 2. The apparatus of claim 1, the first transistor, the second transistor and the third transistor being N-channel metal oxide semiconductor field effect transistors, and the fourth transistor being a P-channel metal oxide semiconductor field effect transistor.

3. 2. The apparatus of claim 1, The apparatus, wherein the first transistor is coupled to a power sourcing equipment (PSE) port via the output terminal.

4. 2. The apparatus of claim 1, The second transistor is cascoded with the first transistor.

5. 2. The apparatus of claim 1, the third transistor is coupled between the fourth transistor and the ground terminal.

6. An apparatus comprising: a cascoded circuit having an output terminal, the cascoded circuit including: a first transistor having a first current terminal coupled to the output terminal, a second current terminal and a first control terminal; and a second transistor having a third current terminal, a fourth current terminal and a second control terminal; a third transistor having a fifth current terminal, a sixth current terminal and a third control terminal, the third transistor configured to determine a current through the first transistor; a fourth transistor having a seventh current terminal, an eighth current terminal coupled to the fifth current terminal, and a fourth control terminal; a first amplifier coupled to the first control terminal, the first amplifier configured to input a voltage indicative of a current through the fourth transistor to control a current through the first transistor; a second amplifier coupled to the second control terminal and the third control terminal, the second amplifier configured to control a first voltage across the second transistor and a second voltage across the third transistor; 13. An apparatus comprising:

7. 7. The apparatus of claim 6, The apparatus further includes a sense amplifier having a sense amplifier inverting input coupled to the third current terminal, a sense amplifier non-inverting input coupled to the fifth current terminal, and a sense amplifier output coupled to the fourth control terminal.

8. 8. The apparatus of claim 7, the sense amplifier configured to match a second voltage across the third transistor to a first voltage across the second transistor.

9. 7. The apparatus of claim 6, further comprising: The apparatus further comprising a resistor configured to provide a voltage indicative of a current through the fourth transistor.

10. 10. The apparatus of claim 9, The apparatus, wherein the first amplifier is further configured to compare a voltage generated by the resistor to a current limit voltage and control a current through the first transistor based on the comparison.

11. 7. The apparatus of claim 6, An apparatus, wherein the output terminal is adapted to be coupled to an Ethernet cable via a port, the port being configured to provide power to the Ethernet cable.

12. 12. The apparatus of claim 11, The apparatus, wherein the first amplifier operating in cooperation with the first transistor is configured to control power provided to the Ethernet cable.

13. 1. A system comprising: A power sourcing equipment (PSE) circuit including an input terminal and an output terminal, a current limiting circuit coupled between the input terminal and the output terminal, a first transistor having a first current terminal coupled to the output terminal, a second current terminal, and a first control terminal; a second transistor having a third current terminal coupled to the second current terminal, a fourth current terminal coupled to a ground terminal, and a second control terminal; a third transistor having a fifth current terminal, a sixth current terminal and a third control terminal coupled to the second control terminal; a fourth transistor having a seventh current terminal, an eighth current terminal coupled to the fifth current terminal, and a fourth control terminal; a fifth transistor having a ninth current terminal coupled to the seventh current terminal, a tenth current terminal, and a fifth control terminal coupled to the fourth control terminal; a first amplifier having a first amplifier output coupled to the first control terminal and an inverting input coupled to the tenth current terminal; a second amplifier having a second amplifier output connected to the second control terminal and to the third control terminal; the PSE circuit including the current limiting circuit, a PSE port coupled to the output terminal; a power device circuit coupled to the PSE port; Including, the system.

14. 14. The system of claim 13, The current limiting circuit is configured to sense a current associated with the current limiting circuit by the fourth transistor.

15. 14. The system of claim 13, The first transistor has a first area and the second transistor has a second area, the first area being greater than the second area.

16. 16. The system of claim 15, The second transistor is configured to dissipate less heat than the first transistor.

17. 14. The system of claim 13, The system, wherein the output terminal is coupled to an Ethernet cable that provides power and data to the powered device circuitry, and the current limiting circuit is configured to limit power to the powered device circuitry when a current through the output terminal meets a threshold.

18. 20. The system of claim 17, The system, wherein the threshold value determines a value of current that the power device circuit or the current limiting circuit should conduct before the power device circuit or the current limiting circuit is damaged.

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