SYSTEMS AND METHODS FOR PROCESS CONDITION METROLOGY WAFER ASSEMBLY - Patent application

Abstract

To provide systems and methods capable of allowing high temperature measurement using an instrumented wafer to monitor conditions of a semiconductor device processing line.SOLUTION: In embodiments, a process condition measurement wafer assembly includes a bottom substrate and a top substrate. In an embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top and bottom substrates. In an embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom and top substrates. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse electric potentials across the bottom and top substrates.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates generally to monitoring wafers along a semiconductor process line, and more particularly to a system and method for process condition metrology wafer assembly. [Background technology]

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 62 / 727,633, filed September 6, 2018, entitled “PROCESS TEMPERATURE MEASUREMENT DEVICE FABRICATION TECHNIQUES AND METHODS OF CALIBRATION AND DATA INTERPOLATION OF THE SAME” by Farhat A. Quli, Andrew Nguyen and James Richard Bella, both of which are hereby incorporated by reference in their entirety.

[0003] As process condition tolerances in semiconductor device processing environments continue to tighten, the need for improved process monitoring systems continues to grow. Thermal uniformity within a processing system is one such condition. Current methods are unable to monitor temperature under extreme conditions (e.g., high temperatures) required by current processing technologies without contaminating the associated chamber. Previous process condition monitoring techniques involve the use of process condition metrology wafers. An example of a conventional process condition metrology wafer has a wireless data acquisition system that allows for measuring and recording process conditions, such as temperature. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 7,540,188 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional process condition metrology wafers often suffer from temperature inaccuracies due to internal configuration variations and may not be able to withstand the energy flux of current and future processing systems (e.g., epitaxy chambers, plasma etch chambers). Therefore, it would be desirable to provide a system and method capable of performing high temperature metrology using instrumented wafers to monitor the conditions of semiconductor device processing lines. [Means for solving the problem]

[0006] A process condition metrology wafer assembly is disclosed. According to some embodiments, the process condition metrology wafer assembly includes a lower substrate and an upper substrate. According to some embodiments, the process condition metrology wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and sandwiched between the upper substrate and the lower substrate. According to some embodiments, the process condition metrology wafer assembly includes one or more shielding layers formed between the lower substrate and the upper substrate. In some embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and to spread electrical potential across the lower substrate and the upper substrate.

[0007] A process condition metrology wafer assembly is disclosed. According to embodiments, the process condition metrology wafer assembly includes a lower substrate and an upper substrate. According to some embodiments, the process condition metrology wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and sandwiched between the upper substrate and the lower substrate. In some embodiments, at least one of the lower substrate and the upper substrate is configured to electromagnetically shield the one or more electronic components and to spread electrical potential across the lower substrate and the upper substrate.

[0008] A method is disclosed, according to embodiments, that includes obtaining, under isothermal conditions, a set of temperature measurements from a set of temperature sensors and a set of heat flux measurements from a set of heat flux sensors distributed throughout a process condition measurement wafer, calibrating the set of temperature measurements and the set of heat flux measurements obtained under isothermal conditions, applying a known heat flux to the process condition measurement wafer, and obtaining, during application of the known heat flux, a set of additional temperature measurements from the set of temperature sensors and a set of additional heat flux measurements from the set of heat flux sensors; identifying temperature variations observed across the set of temperature sensors during application of the known heat flux; identifying a heat flux vs. temperature variation relationship by correlating the known heat flux with the identified temperature variations at the set of temperature sensors; obtaining a set of trial temperature measurements from the set of temperature sensors and a set of trial heat flux measurements from the heat flux sensors under unknown heat flux conditions; and adjusting the set of trial temperature measurements based on the set of trial heat flux measurements and the identified heat flux vs. temperature variation relationship.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention.

[0010] The many advantages of the present disclosure can be better appreciated by those skilled in the art by reference to the following accompanying drawings, in which: [Brief description of the drawings]

[0011] [Figure 1A] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly according to one or more embodiments of the present disclosure. [Figure 1B] 1 is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. [Figure 1C]1 is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. [Figure 1D] 1 is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. [Figure 1E] 1 is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. [Figure 1F] 1 is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. [Figure 2A] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly according to one or more embodiments of the present disclosure. [Figure 2B] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly according to one or more embodiments of the present disclosure. [Diagram 3] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly according to one or more embodiments of the present disclosure. [Figure 4A] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present disclosure. [Figure 4B] FIG. 1 is a schematic block diagram of a process condition metrology wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present disclosure. [Diagram 5] 1 is a schematic cross-sectional view of a process condition metrology wafer assembly according to one or more embodiments of the present disclosure. [Figure 6] 1 is a flowchart of a method for calculating temperature throughout a process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0013] 1A-5, systems and methods for process condition metrology wafer assembly in accordance with one or more embodiments of the present disclosure are illustrated and described.

[0014] Conventional process condition metrology wafers have metrology electronics located between silicon wafers that are designed to shield the metrology electronics from the extreme conditions in the process chamber (e.g., strong RF, high heat flux, strong electromagnetic radiation). The silicon wafers in conventional process condition metrology wafers are typically joined by one or more discrete ohmic contacts between the individual silicon wafers. However, such ohmic contacts can result in high current densities in and around the contacts, creating strong potentials that can link to the process condition metrology wafer. Additionally, the internal configuration of conventional process condition metrology wafers is complex, which can result in temperature inaccuracies due to the internal configuration of the wafer itself.

[0015] Accordingly, embodiments of the present disclosure are directed to systems and methods that overcome one or more of the shortcomings of the prior approaches discussed above. Embodiments of the present disclosure are directed to a process condition metrology wafer assembly that improves the accuracy, precision, and configuration of wafer-based process condition metrology devices. Additional embodiments of the present disclosure are directed to a process condition metrology wafer assembly having one or more electromagnetic shielding layers disposed between an upper substrate and a lower substrate. Further embodiments of the present disclosure are directed to a process condition metrology wafer assembly having one or more thermal pillars configured to provide heat transfer throughout the apparatus.

[0016] Embodiments of the present disclosure are directed to a process condition metrology wafer assembly that can operate at high temperatures (e.g., 600° C. to 800° C.). Such a process condition metrology wafer assembly can be used with semiconductor processing chambers (e.g., epitaxy chambers, plasma etch chambers) that operate at high temperatures. In some embodiments, the process condition metrology wafer assembly of the present disclosure includes an upper substrate, a lower substrate, and one or more shielding layers, with on-board electronics (e.g., sensors, processors, memory, power supplies) and / or other sensing devices interposed between the upper substrate and the lower substrate and shielded by the one or more shielding layers. The use of instrumentation substrates is described in U.S. Patent Application Serial No. 15 / 277,753, filed September 27, 2016, which is incorporated herein by reference in its entirety. The instrumentation substrate is described in further detail in U.S. Patent Application No. 15 / 277,792, filed May 1, 2016, entitled "PROCESS CONDITION MEASURING DEVICE WITH SHIELDING," and U.S. patent application Ser. No. 15 / 277,792, filed Sep. 27, 2016, entitled "ENCAPSULATED INSTRUMENTED SUBSTRATE APPARATUS FOR ACQUIRING MEASUREMENT PARAMETERS IN HIGH TEMPERATURE PROCESS APPLICATIONS," both of which are incorporated herein by reference in their entireties.

[0017] 1A is a schematic cross-sectional view of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure. The process condition metrology wafer assembly 100 may include, but is not limited to, a top substrate 104 and a bottom substrate 102. The process condition metrology wafer assembly 100 may include one or more electronic components 106.

[0018] 1A, the upper substrate 104 can be mechanically coupled to the lower substrate 102. The upper substrate 104 and / or the lower substrate 102 of the process condition metrology wafer assembly 100 can be any substrate known in the art. According to some embodiments, the upper substrate 104 and / or the lower substrate 102 of the process condition metrology wafer assembly 100 can include a wafer. Examples of the upper substrate 104 and / or the lower substrate 102 may include, but are not limited to, a semiconductor substrate, a glass wafer (e.g., fused silica glass wafer, borosilicate glass wafer), a crystalline wafer (e.g., quartz wafer, silicon wafer), a wafer formed of one or more compounds (e.g., silicon carbide, silicon nitride), etc. For example, the substrate included in the process condition metrology wafer assembly 100 may be any substrate that causes negligible contamination in a semiconductor processing environment, such as, but not limited to, a wafer formed from one or more of silicon, silicon carbide, silicon nitride, gallium nitride, gallium arsenide, germanium, gallium, indium, and silicon dioxide (e.g., quartz).

[0019] According to one embodiment, one or more cavities 107 may be provided between the top substrate 104 and the bottom substrate 102 of the process condition metrology wafer assembly 100. For example, as shown in FIG. 1A, the cavity 107 may be provided in the bottom substrate 102 of the process condition metrology wafer assembly 100. It is noted that one or more cavities 107 may be provided in the process condition metrology wafer assembly 100 and may be provided in the top substrate 104 and / or the bottom substrate 102. For example, the cavity 107 may include a cavity 107 component in the top substrate 104 and a cavity 107 component in the bottom substrate 102.

[0020] Additionally, in some embodiments, the one or more electronic components 106 may be interposed between the upper substrate 104 and the lower substrate 102. For example, as shown in FIG. 1A, the one or more electronic components 106 may be disposed in the one or more cavities 107. In some embodiments, the one or more electronic components 106 may be disposed between the upper substrate 104 and the lower substrate 102 such that the one or more electronic components 106 are sealed (e.g., hermetically sealed) between the upper substrate 104 and the lower substrate 102. The one or more electronic components 106 may include any electronic component configured to monitor process conditions in a process system (e.g., an epitaxy chamber, a plasma etch chamber). In this case, the one or more electronic components 106 may include any electronic component known in the art, including, but not limited to, sensor devices (e.g., temperature sensors, pressure sensors, chemical sensors, radiation sensors, heat flux sensors, voltage sensors), power sources, one or more processors, memory, communication circuits, etc.

[0021] In some embodiments, a plurality of electronic components 106 may be communicatively coupled to one another within the process condition metrology wafer assembly 100. In some embodiments, the one or more electronic components 106 may be disposed on one or more printed circuit elements 105, which may be interposed between the upper substrate 104 and the lower substrate 102. In this case, the one or more electronic components 106 may be communicatively coupled to one another via the one or more printed circuit elements 105. The one or more printed circuit elements 105 may include any electronic component known in the art, including, but not limited to, a printed circuit board, a printed wiring board, and the like. Similarly, the one or more printed circuit elements 105 may be formed of any material known in the art, including, but not limited to, ceramics, silicon, inorganic materials, and the like.

[0022] FIG. 1B is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly 100 in accordance with one or more embodiments of the present disclosure.

[0023] As described herein, the upper substrate 104 and the lower substrate 102 may be mechanically coupled to each other. According to some embodiments, the process condition metrology wafer assembly 100 may also include one or more shielding layers 108. The one or more shielding layers 108 may be formed between the upper substrate 104 and the lower substrate 102. For example, the one or more shielding layers 108 may include one or more films disposed / deposited on the surfaces of the upper substrate 104 and / or the lower substrate 102. For example, as shown in FIG. 1B, the one or more shielding layers 108 may be disposed over at least a portion of the upper surface of the lower substrate 102 and / or over at least a portion of the lower surface of the upper substrate 104.

[0024] As contemplated herein, the one or more shielding layers 108 may include any layer / film configured to electromagnetically shield the one or more electronic components 106 and / or spread electrical potential across the top substrate 104 and / or bottom substrate 102, as known in the art. According to some embodiments, the one or more shielding layers 108 may be formed of a conductive material. According to additional and / or alternative embodiments, the one or more shielding layers 108 may include a light blocking film. Moreover, the one or more shielding layers 108 may include one or more opaque films. For example, the one or more shielding layers 108 may include, but are not limited to, a material that absorbs radiation traversing from the top substrate 104 to the bottom substrate 102.

[0025] The one or more shielding layers 108 may be better understood with reference to Figures 1C-1F.

[0026] 1C is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure. As shown in FIG. 1C, the one or more shielding layers 108 can include, but are not limited to, an adhesion layer 110 and a plurality of conductive particles 112.

[0027] In some embodiments, the shielding layer 108, which is formed between at least a portion of the lower substrate 102 and the upper substrate 104, can include an adhesive layer 110. The adhesive layer 110 can be formed of any adhesive material known in the art that is configured to mechanically bond the substrates together. In some embodiments, the shielding layer 108 can include conductive particles 112 disposed within the adhesive layer 110. For example, as shown in FIG. 1C, the shielding layer 108 can include a plurality of conductive particles 112 disposed within the adhesive layer 110. In some embodiments, the conductive particles 112 can be uniformly distributed throughout the adhesive layer 110. In some embodiments, the conductive particles 112 can be included within the shielding layer 108 to provide electrical contact between at least a portion of the upper substrate 104 and at least a portion of the lower substrate 102. Accordingly, the material used to form the conductive particles 112 may be any conductive material known in the art. Similarly, the adhesive layer 110 may be formed of a conductive material, which may facilitate the electrical contact between the upper substrate 104 and the lower substrate 102.

[0028] As contemplated herein, the inclusion of conductive particles 112 within the shielding layer 108 can provide electrical contact between the upper and lower substrates 104, 102 and / or between conductive layers deposited on the respective substrates. Such electrical contact can provide potential spreading across the process condition metrology wafer assembly 100 and / or between the upper and lower substrates 104, 102. Additionally, such electrical contact and conductive particles / layers can provide electrical and electromagnetic shielding for the electronic components 106 of the process condition metrology wafer assembly 100.

[0029] 1D is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure. As shown in FIG. 1D, the one or more shielding layers 108 can include, but are not limited to, an adhesion layer 110 and a plurality of conductive structures 114.

[0030] According to additional and / or alternative embodiments, electrical contact between portions of the upper substrate 104 and the lower substrate 102 can be achieved through the use of conductive structures 114. For example, as shown in FIG. 1D, a plurality of conductive structures 114 can be formed on a surface of at least one of the upper substrate 104 and the lower substrate 102, thereby electrically coupling at least a portion of the upper substrate 104 and at least a portion of the lower substrate 102. The plurality of conductive structures 114 can include any shape or type of conductive structure known in the art. For example, the plurality of conductive structures 114 can include a plurality of protrusions formed on a surface of at least one of the upper substrate 104 and the lower substrate 102. For example, the plurality of conductive structures 114 can include a plurality of cone-shaped portions (e.g., cones) and / or bumps formed on a surface of the upper substrate 104 and / or a surface of the lower substrate 102. The plurality of conductive structures 114 may be formed from any material known in the art, including, but not limited to, one or more conductive metals.

[0031] The conductive structures 114 may be formed / created on the surface of the upper substrate 104 and / or the lower substrate 102 by any technique known in the art, such as by depositing the conductive structures 114 on the surface of the upper substrate 104 and / or the lower substrate 102 through an electroplating process or a wire bond bumping process. In addition, according to an embodiment, an adhesion layer 110 may be formed around the conductive structures 114.

[0032] FIG. 1E is a schematic cross-sectional view of a portion of a process condition metrology wafer assembly 100 in accordance with one or more embodiments of the present disclosure.

[0033] According to some embodiments, the one or more shielding layers 108 are formed by direct wafer-to-wafer bonding. For example, as shown in FIG. 1E, the one or more shielding layers 108 can be formed by silicon-to-silicon adhesiveless bonding between the upper substrate 104 and the lower substrate 102. According to some embodiments, the upper substrate 104 and / or the lower substrate 102 can act as the one or more shielding layers 108. That is, the upper substrate 104 and / or the lower substrate 102 can be configured as the one or more shielding layers 108. In this case, the upper substrate 104 and / or the lower substrate 102 can electromagnetically shield the one or more electronic components 106 and diffuse electric potential in addition to or instead of the one or more shielding layers 108. For example, as shown in FIG. 1E, a top substrate 104 can include a doped silicon substrate that is bonded directly to the bottom substrate 102, thus acting as the shielding layer 108.

[0034] As contemplated herein, formation of the shielding layer 108 by direct wafer-to-wafer bonding (e.g., silicon-to-silicon bonding) can be accomplished by interposing one or more intermediate films 116 between the upper substrate 104 and the lower substrate 102.

[0035] In some embodiments, as shown in FIG. 1F, the one or more shielding layers 108 of the process condition metrology wafer assembly 100 include one or more intermediate films 116 and one or more metal contacts 118. As contemplated herein, the electrical coupling between the upper substrate 104 and the lower substrate 102 can be further achieved by direct metal-to-metal thermal compression bonding at discontinuous locations to improve electrical conductivity. Accordingly, electrical conductivity can be improved by incorporating one or more additional metal contacts 118 for silicon-to-silicon adhesiveless bonding. For example, as shown in FIG. 1F, the one or more intermediate films 116 sandwiched between the upper substrate 104 and the lower substrate 102 can include multiple metal contacts 118. For example, the one or more intermediate films 116 can include one or more metal film layers to improve electrical coupling between the upper substrate 104 and the lower substrate 102.

[0036] According to additional and / or alternative embodiments, the one or more shielding layers 108 may comprise one or more films deposited on at least one of the upper substrate 104 and the lower substrate 102 by a transient liquid phase bonding process. For example, metal films deposited on the surfaces of the upper substrate 104 and the lower substrate 102 may react with each other to form an alloy to form the one or more shielding layers 108 and bond the upper substrate 104 and the lower substrate 102.

[0037] 2A is a schematic cross-sectional view of a process condition metrology wafer assembly 100. The process condition metrology wafer assembly 100 may include, but is not limited to, a top substrate 104, a bottom substrate 102, one or more electronic components 106, one or more printed circuit elements 105, and one or more layers 208. It is noted that the one or more layers 208 may include one or more adhesion layers and / or one or more shielding layers 108, as discussed above in this application with reference to FIGS. 1B-1F.

[0038] As previously discussed herein, one of the problems associated with conventional process condition metrology wafers is poor thermal management and heat build-up, which can lead to failure of electronic components, adhesive layers, or both. For example, as shown in FIG. 2A, a process condition metrology wafer assembly 100 may be exposed to a strong heat flux 202. Although an effective heat transfer path may exist between the direct bond of the top substrate 104 and the bottom substrate 102, the heat transfer path may be substantially lost where the electronic components 106 and / or printed circuit elements 105 are interposed between the top substrate 104 and the bottom substrate 102. This loss of the heat transfer path may result in hot areas 203 and heat build-up, as shown in FIG. 2A.

[0039] Accordingly, some embodiments of the present disclosure are directed to improving the thermal robustness of the process condition metrology wafer assembly 100 by improving the thermal management configuration of the process condition metrology wafer assembly 100. This may be better understood with reference to FIG. 2B.

[0040] FIG. 2B is a schematic cross-sectional view of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure.

[0041] According to some embodiments, the process condition measurement wafer assembly 100 may include one or more thermal columnar structures 206a, 206b configured to provide an efficient heat transfer path between at least a portion of the upper substrate 104 and at least a portion of the lower substrate 102. For example, the one or more thermal columnar structures 206a, 206b may be machined into at least one of the upper substrate 104 and the lower substrate 102. For example, the one or more thermal columnar structures 206a, 206b may be plated with metal onto at least one of the upper substrate 104 and the lower substrate 102. According to embodiments, the one or more printed circuit elements 105 may include one or more ports, holes, or openings configured to receive the one or more columnar structures 206a, 206b. The one or more columnar structures 206a, 206b can thus be configured to provide an efficient heat transfer path from the top substrate 104 to the bottom substrate 102 through one or more ports (e.g., holes, openings, etc.) in the printed circuit element 105. The one or more columnar structures 206a, 206b can be formed of any material known in the art, including, but not limited to, semiconductor materials, metallic materials, etc. For example, the one or more columnar structures 206a, 206b can include silicon pillars, conductive metal pillars, etc.

[0042] 3 is a schematic cross-sectional view of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure. The process condition metrology wafer assembly 100 may include, but is not limited to, a top substrate 104, a bottom substrate 102, one or more electronic components 106, one or more printed circuit elements 105, and one or more layers 208. It is noted that the one or more layers 208 may include one or more adhesion layers and / or one or more shielding layers 108 as discussed above in this application with reference to FIGS. 1B-1F.

[0043] According to some embodiments, the one or more printed circuit elements 105 may be coupled to at least one of the top substrate 104 and the bottom substrate 102. For example, the one or more printed circuit elements 105 may be soldered and / or directly bonded to at least one of the top substrate 104 and the bottom substrate 102. As an example, the inorganic printed circuit element 105 may be directly bonded to the bottom substrate 102, as described herein above. It is noted that directly bonding the one or more printed circuit elements 105 to the top substrate 104 and / or the bottom substrate may improve thermal conductivity and thermal management of the process condition metrology wafer assembly 100.

[0044] Figure 4A is a schematic cross-sectional view of a process condition metrology wafer assembly 100 communicatively coupled to a remote data system 402 in accordance with one or more embodiments of the present disclosure. Figure 4B is a schematic block diagram of a process condition metrology wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present disclosure.

[0045] In some embodiments, the process condition metrology wafer assembly 100 includes one or more electronic components 106, such as one or more sensors, as described herein. According to some embodiments, the one or more electronic components 106 may be located at one or more locations on the printed circuit element 105 and communicatively coupled to one another via one or more wired and / or wireless connections. The one or more electronic components 106 may include, but are not limited to, communication circuitry 410, one or more processors 412, memory 414, one or more sensors 416, and a power source 418. According to some embodiments, the power source 418 may include any power source known in the art, such as, but not limited to, a battery, a wirelessly rechargeable battery, or the like.

[0046] For purposes of this disclosure, the term "processor" may be broadly defined to include any device having one or more processors (e.g., CPUs) or logic elements (e.g., ASICs) that execute instructions obtained from an internal or external memory 414. In this sense, the one or more processors 412 may include any microprocessor-type or logic device configured to execute algorithms and / or instructions. It should be recognized that the steps described throughout this disclosure may be performed by a single processor 412 or, alternatively, by multiple processors 412. Memory 414 may include read-only memory, random access memory, solid state drives, flash, EPROM, EEPROM, etc.

[0047] In various embodiments, the one or more processors 412 are configured to execute a set of program instructions stored in memory 414, which in turn are configured to cause the one or more processors 412 to perform and implement various steps / functions of the present disclosure. For example, the one or more processors 412 may be configured to generate one or more control signals to cause the one or more sensors 416 to acquire one or more measurement parameters, store the acquired measurement parameters in memory 414, calculate one or more values ​​based on the one or more measurement parameters, and transmit the one or more measurement parameters and / or the determined value or values ​​to the remote data system 402 via communication circuitry 410. Each of these steps will be discussed herein.

[0048] In one embodiment, one or more processors 412 in the process condition metrology wafer assembly 100 are configured to generate one or more control signals to cause one or more sensors 416 to acquire one or more measurement parameters, the one or more sensors 416 located at one or more locations in the process condition metrology wafer assembly 100 / printed circuit element 105 may be configured to acquire one or more measurement parameters (e.g., thermocouple voltage, resistance from a resistance temperature detector, voltage / signal from a pressure sensor, voltage / signal from a radiation sensor, voltage / signal from a chemical sensor, etc.) It is noted that depending on the configuration of the one or more sensors 416, the sensor(s) may acquire a measurement parameter associated with any parameter or characteristic to be monitored throughout a processing system (e.g., temperature, heat flux, pressure, etc.).

[0049] It is noted that the one or more sensors 416 can be formed to have any shape and can be distributed in any manner across the process condition metrology wafer assembly 100 (e.g., across the bottom substrate 102) such that the one or more sensors 416 can be selectively distributed across the process condition metrology wafer assembly 100 such that a metrology parameter is obtained at a selected location associated with each sensor 416. In accordance with further contemplated herein, the one or more sensors 416 can include discrete sensor devices and / or be integrated into the top substrate 104 and / or bottom substrate 102.

[0050] It is further noted that the one or more sensors 416 may include any measurement device known in the art. For example, the one or more sensors 416 may include, but are not limited to, heat / temperature sensors, pressure sensors, radiation sensors, chemical sensors, voltage sensors, heat flux sensors, etc. For example, for temperature measurements, the one or more sensors 416 may include, but are not limited to, one or more thermocouple (TC) devices (e.g., thermojunctions) and one or more resistance temperature detectors (RTDs) (e.g., thin film RTDs). For example, for pressure measurements, the one or more sensors 416 may include, but are not limited to, piezoelectric sensors, capacitive sensors, optical sensors, potentiometric sensors, etc. For alternative radiation measurements, the one or more sensors 416 may include, but are not limited to, one or more photodetectors (e.g., photovoltaic cells, photoresistors, etc.) or other radiation detectors (e.g., solid-state detectors). For alternative chemical sensors, the one or more sensors 416 may include, but are not limited to, one or more chemiresistors, gas sensors, pH sensors, etc.

[0051] Additionally, in one embodiment, one or more processors 412 included in the process condition metrology wafer assembly 100 are configured to store the acquired metrology parameters in memory 414 .

[0052] Also, in some embodiments, one or more processors 412 in the process condition metrology wafer assembly 100 are configured to calculate one or more values ​​based on the acquired metrology parameters. The one or more processors 412 may be configured to calculate any value known in the art based on the acquired metrology parameters. For example, in the case of temperature, the one or more sensors 416 may be configured to generate a thermocouple voltage (a metrology parameter) indicative of temperature, and the one or more processors 412 may be configured to calculate the temperature based on the thermocouple voltage.

[0053] Additionally, in some embodiments, one or more processors 412 on the process condition metrology wafer assembly 100 may be configured to transmit the one or more metrology parameters and / or the determined one or more values ​​to a remote data system 402 via communication circuitry 410. In this case, one or more electronic components 106 on the process condition metrology wafer assembly 100 may be communicatively coupled to the remote data system 402 via communication circuitry 410. One or more electronic components 106 on the process condition metrology wafer assembly 100 may be communicatively coupled to the remote data system 402 using any wired or wireless communication protocol known in the art.

[0054] According to embodiments, one or more electronic components 106 on the process condition metrology wafer assembly 100 may be wirelessly communicatively coupled to the remote data system 402. The one or more electronic components 106 may be wirelessly communicatively coupled to the remote data system 402 in any suitable manner. The communication circuitry 410 may include any communication circuitry and / or communication device known in the communications arts. For example, the communication circuitry 410 may include, but is not limited to, one or more communication antennas (e.g., communication coils).

[0055] In one embodiment, the communication circuitry 410 is configured to establish a communication link between the process condition metrology wafer assembly 100 and an off-substrate remote data system 402. The communication circuitry 410 may be communicatively coupled to one or more processors 412, memory 414, one or more sensors 416, and a power source 418. In this case, the one or more processors 412 may be configured to generate one or more control signals that cause the communication circuitry 410 to transmit the one or more metrology parameters and / or the determined value or values ​​to the remote data system 402.

[0056] In one embodiment, the remote data system 402 includes communications circuitry 404 suitable for establishing a communications link between the on-board communications circuitry 410 and the remote data system 402. For example, the communications circuitry 404 may establish a communications link between the on-board communications circuitry 410 and the remote data system 402 using radio frequency (RF) signals, 3G, 4G, 4G LTE, 5G, WiFi® protocols, Bluetooth® protocols, etc.

[0057] As discussed previously herein, one or more processors 412 in the process condition metrology wafer assembly 100 may be configured to determine values ​​associated with the acquired metrology parameters. According to additional and / or alternative embodiments, values ​​associated with the acquired metrology parameters may be determined / calculated by one or more processors 420 in the remote data system 402. For example, the communications circuitry 410 may transmit the acquired metrology parameters to the remote data system 402, where one or more processors 420 may calculate one or more values ​​based on the acquired metrology parameters acquired by the sensors 416.

[0058] Additionally, in accordance with an embodiment, the remote data system 402 may be configured to map (i.e., associate) one or more values ​​calculated by the processor 412 and / or the remote data system 402 based on one or more metrology parameters acquired by the sensor 416. The remote data system 402 may be configured to map (i.e., associate) the one or more values ​​to acquisition locations (e.g., “measurement locations”) on the process condition metrology wafer assembly 100. Additionally, in an embodiment, the remote data system 402 may communicate the mapped values ​​to a user interface. For example, the remote data system 402 may communicate the mapped values ​​to one or more of a desktop computer, a laptop, a tablet, a handheld device, a memory, and a server.

[0059] As discussed herein, certain conventional process condition metrology wafers are often subject to temperature inaccuracies due to internal configuration variations. For example, with a conventional process condition metrology wafer, temperature readings (e.g., metrology parameters) may be collected at 65 locations scattered across the wafer. When displaying these acquired temperature readings in the form of a 2D map, the wafer temperature may simply be interpolated between the locations on the sensor / measurement locations. Depending on the source and magnitude of temperature non-uniformity in the conventional process condition metrology wafer (e.g., chuck temperature, heat flux, wafer heat removal), the accuracy of the temperature interpolation may vary, leading to inaccurate temperature measurements.

[0060] Accordingly, some embodiments of the present disclosure are directed to techniques and process condition metrology wafer assemblies 100 that improve the accuracy of temperature readings by calibrating out condition variations, which may be better understood with reference to FIG.

[0061] FIG. 5 is a schematic cross-sectional view of a process condition metrology wafer assembly 100 according to one or more embodiments of the present disclosure.

[0062] 5, a first electronic component 106a (e.g., a first sensor 416a) can be disposed on a first printed circuit element 105a and disposed in a first cavity 107a between the upper substrate 104 and the lower substrate 102. Similarly, a second electronic component 106b (e.g., a second sensor 416b) can be disposed on a second printed circuit element 105b and disposed in a second cavity 107b between the upper substrate 104 and the lower substrate 102. By comparing the relative arrangement of the cavities 107a, 107b and the electronic components 106a, 106b, it can be seen that the first cavity 107a is larger than the second cavity 107b. In this case, the first electronic component 106a is set back / separated farther from the lower substrate 102, and thus is further separated from the lower substrate 102 by a larger thermal resistance than the second electronic component 106b.

[0063] In a completely isothermal environment, the first electronic component 106a (e.g., first sensor 416a) and the second electronic component 106a (e.g., second sensor 416b) would provide similar temperature measurements (e.g., measurement parameters). However, manufacturing processes are not typically performed in a completely isothermal environment. During a manufacturing process (e.g., an etching process), the lower substrate 102 may cool while the heat flux 202 is applied to the upper substrate 104. In this case, the first sensor 416a will read higher than the second sensor 416b because the first sensor is further back from the cooling lower substrate 102 and is more isolated from the heat removal.

[0064] That is, as can be appreciated, configurational variations (e.g., different sizes of cavities 107a, 107b) can result in errors / inconsistencies in the acquired measured parameters. Other configurational variations that can cause inconsistencies in the acquired measured parameters and / or calculated values ​​may include, but are not limited to, different sizes / shapes of electronic components 106, different bonding surfaces (e.g., bonded to top substrate 104, bonded to bottom substrate 102), different adhesive and / or conductive properties, etc. Furthermore, as temperature gradients and heat fluxes 202 increase, such configurational variations may lead to increased inconsistencies in the acquired measured parameters and / or calculated values.

[0065] Accordingly, some embodiments of the present disclosure are directed to quantifying and calibrating the effects of configuration variations on acquired metrology parameters and / or calculated values. By quantifying the effects of configuration variations on acquired metrology parameters and calibrating (e.g., removing) the found effects, the systems and methods disclosed herein can enable more efficient and accurate process monitoring.

[0066] According to various embodiments, one or more processors 420 in the remote data system 402 are configured to execute a set of program instructions stored in memory 422 that cause the one or more processors 420 to perform and implement various steps / functions of the present disclosure. For example, the one or more processors 420 may be configured to perform a program for acquiring, under isothermal conditions, a set of temperature measurements from a set of temperature sensors and a set of heat flux measurements from a set of heat flux sensors scattered throughout the process condition measurement wafer 100, calibrating the set of temperature measurements and the set of heat flux measurements acquired under isothermal conditions, applying a known heat flux to the process condition measurement wafer 100, and acquiring, during application of the known heat flux, a set of additional temperature measurements from the set of temperature sensors and a set of additional heat flux measurements from the set of heat flux sensors. the known heat flux, identify temperature variations observed across the set of temperature sensors during application of the known heat flux, identify a heat flux vs. temperature variation relationship by correlating the known heat flux with the identified temperature variations at the set of temperature sensors, obtain a set of trial temperature measurements from the set of temperature sensors and a set of trial heat flux measurements from the heat flux sensors under unknown heat flux conditions, and adjust the set of trial temperature measurements based on the set of trial heat flux measurements and the identified heat flux vs. temperature variation relationship. Each of these steps / functions is discussed in more detail herein.

[0067] According to one embodiment, the processor 420 can be configured to obtain a set of temperature measurements from a set of temperature sensors 416 and a set of heat flux measurements from a set of heat flux sensors 416 distributed throughout the process condition metrology wafer 100 under isothermal conditions. For example, the process condition metrology wafer assembly 100 can be created with multiple temperature sensors 416 and multiple heat flux sensors 416 distributed at various locations throughout the process condition metrology wafer assembly 100. The multiple temperature sensors 416 and multiple heat flux sensors 416 can be configured to obtain the set of temperature measurements and the set of heat flux measurements, respectively, under isothermal conditions. The processor 420 can then be configured to receive the measurements via the communication circuitry 404, 410.

[0068] Additionally, according to some embodiments, the processor 420 can be configured to calibrate a set of temperature measurements and a set of heat flux measurements acquired under isothermal conditions. For example, the processor 420 can be configured to calibrate measurements acquired under isothermal conditions. Baseline The measurement may be configured to set a threshold value against which subsequent measurements are compared and / or adjusted.

[0069] Additionally, in accordance with an embodiment, the processor 420 may be configured to generate one or more control signals that cause a heat source to apply a known heat flux to the process condition metrology wafer 100. For example, the processor 420 may be communicatively coupled to one or more heat sources (not shown) in the processing environment. The processor 420 may be configured to generate one or more control signals that cause the one or more heat sources to apply a known heat flux to the process condition metrology wafer assembly 100. Parameters / characteristics associated with the known heat flux may be stored in the memory 422 and retrieved by the processor 420.

[0070] According to an embodiment, the processor 420 can be configured to obtain a set of additional temperature measurements from the set of temperature sensors 416 and a set of additional heat flux measurements from the set of heat flux sensors 416 during application of the known heat flux. For example, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 can be configured to obtain a set of additional temperature measurements and a set of additional heat flux measurements, respectively, during application of the known heat flux. The processor 420 can then be configured to receive the measurements via the communication circuitry 404 and 410. The processor 420 can be configured to store the measurements in the memory 422.

[0071] Additionally, in some embodiments, the processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors during application of the known heat flux. For example, as described above with reference to FIG. 5, configuration variations (e.g., different sizes of cavities 107a, 107b, different sizes / shapes of electronic components 106, different bonding surfaces, different adhesive and / or conductive properties, etc.) may cause the readings obtained at the first temperature sensor 416a to differ from those obtained at the additional temperature sensor 416b. In this case, the processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors 416 during application of the known heat flux.

[0072] Additionally, according to some embodiments, the processor 420 can be configured to identify a heat flux vs. temperature variation relationship by correlating the known heat flux with an identification of temperature variations at the set of temperature sensors 416. For example, the processor 420 can be configured to identify a heat flux vs. temperature variation relationship by correlating the known heat flux with an identification of temperature variations. It is contemplated herein that the identification of a heat flux vs. temperature variation relationship may take any form known in the art, including, but not limited to, a relationship expressed as a mathematical equation(s), a list of associated heat flux values ​​and associated temperature variations, etc.

[0073] To more consistently model the variational relationship of heat flux versus temperature, the processor 420 can be configured to collect readings at a plurality of constant temperature conditions, as well as during a plurality of known varying heat flux conditions. By collecting measurements under the varying conditions, the processor 420 can be configured to generate a model that provides an identification of the variational relationship of heat flux versus temperature for the process condition metrology wafer assembly 100.

[0074] After the heat flux versus temperature variation relationship is identified, the process condition metrology wafer assembly 100 can be subsequently used in one or more processes (e.g., process in an epitaxy chamber, process in a plasma etch chamber). While the conditions in the individual chambers may be generally known, the exact temperature and heat flux conditions experienced by the process condition metrology wafer assembly 100 may be unknown. Thus, the processor 412 may be configured to obtain a set of trial temperature measurements and a set of trial heat flux measurements from the sensor 416.

[0075] For example, the set of temperature sensors 416 can be configured to obtain a set of trial temperature measurements under unknown heat flux conditions, and the set of heat flux sensors 416 can be configured to obtain a set of trial temperature measurements. A processor 420 can then be configured to receive the obtained measurements via communications circuits 404, 410. The processor 420 can be configured to store the obtained measurements in memory 422.

[0076] Additionally, according to some embodiments, the processor 420 may be configured to adjust the set of trial temperature measurements based on the set of trial heat flux measurements and the identification of the variational relationship between heat flux and temperature. For example, the processor 420 may be configured to identify that a subset of the temperature sensors 416 read higher temperatures under a particular set of heat flux conditions based on the variational relationship between heat flux and temperature. The processor 420 may then be configured to adjust (e.g., reduce) the temperature measurements collected by the subset of the temperature sensors 416 in the set of trial temperature measurements based on the variational relationship between heat flux and temperature. It is noted that the processor 420 may be configured to adjust the set of trial temperature measurements using any mathematical technique known in the art.

[0077] Additionally, according to one embodiment, the processor 420 may be configured to map the calibrated set of test temperature measurements to one or more measurement locations on the process condition metrology wafer assembly 100. For example, the location of each temperature sensor 416 on the process condition metrology wafer assembly 100 may be known and stored in the memory 422. These known locations of the temperature sensors 416 are locations where temperature measurements are obtained by the process condition metrology wafer assembly 100 and may be referred to as measurement locations. In this case, the processor 420 may be configured to map the calibrated set of test temperature measurements to the known individual locations (e.g., measurement locations) of each temperature sensor 416.

[0078] Also, according to some embodiments, processor 420 can be configured to interpolate a set of temperature values ​​at locations between the one or more measurement locations based on the adjusted set of test temperature measurements and relying on one or more interpolation functions. For example, processor 420 can be configured to map an adjusted first temperature value to the first measurement location and an adjusted second temperature value to the second measurement location. According to this example, processor 420 can be configured to interpolate between the first and second measurement locations. For example, processor 420 can be configured to assign one or more temperature values ​​to one or more locations between the first and second measurement locations.

[0079] Depending on the source and magnitude of temperature non-uniformity between the various measurement locations, the accuracy of the interpolated temperature values ​​may vary. To improve the accuracy of the interpolated temperature values ​​between the temperature sensors 416 (e.g., between the measurement locations), the processor 420 may be configured to model the effect of various types of compositional non-uniformities (e.g., differences in size of the cavities 107a, 107b, differences in size / shape of the electronic components 106, differences in bonding surfaces, differences in adhesive and / or conductive properties, etc.) on the acquired temperature values. For example, known compositional non-uniformities may be considered and incorporated into the heat flux vs. temperature variation relationship discussed above. In this case, the processor 420 may be configured to factor in the compositional non-uniformities in the process condition metrology wafer assembly 100 when generating its heat flux vs. temperature variation relationship model.

[0080] After the configuration non-uniformities are accounted for in the heat flux vs. temperature variational relationship model, the process condition metrology wafer assembly 100 can be used in the chamber under test. Process non-uniformities can then be identified using a number of techniques, including, but not limited to, pre-plasma chuck non-uniformities, measuring steady state temperature data (e.g., temperature measurements by temperature sensor 416), estimating heat flux and heat removal non-uniformities by taking the time derivative (dT / dt) of the measured temperature, simultaneously acquiring temperature and heat flux measurements, etc. According to some embodiments, the processor 420 can be configured to utilize the known effects of the configuration non-uniformities (e.g., the heat flux vs. temperature variational relationship model that at least partially accounts for the configuration non-uniformities) and the identified process non-uniformities to more accurately predict process temperature values ​​between measurement points (e.g., between temperature sensors 416).

[0081] According to additional and / or alternative embodiments, the metrology parameters and / or values ​​acquired by the process condition metrology wafer assembly 100 may be used in a feed-forward or feedback loop to adjust one or more upstream or downstream process tools. For example, the one or more processors 420 may be configured to receive the acquisition of metrology parameters within a semiconductor device process, receive the acquired metrology parameters and / or determined values, and generate one or more control signals configured to selectively adjust one or more characteristics of one or more process tools within the semiconductor device process. Process tools that may be adjusted may include, but are not limited to, lithography tools, deposition tools, etch tools, etc.

[0082] It is noted that one or more of the components of the process condition metrology wafer assembly 100 and associated systems may be communicatively coupled to various other components of the process condition metrology wafer assembly 100 and associated systems in any manner known in the art. For example, the communication circuits 410, 404 may be communicatively coupled to each other and to other components via wires (e.g., copper wire, fiber optic cable, etc.) or wireless connections (e.g., RF coupling, IR coupling, 3G, 4G, 4G LTE, 5G, WiFi, WiMax, Bluetooth, etc.).

[0083] According to some embodiments, the one or more processors 412, 420 may include one or more of any processing elements known in the art. In this sense, the one or more processors 412, 420 may include any microprocessor-based device configured to execute software algorithms and / or instructions. According to some embodiments, the one or more processors 412, 420 may be a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, or other computer system (e.g., a networked computer) configured to execute programs that cause the process condition metrology wafer assembly 100 and associated systems to operate as described elsewhere in this disclosure. It should be appreciated that the steps described elsewhere in this disclosure may be performed by a single computer system or, alternatively, by multiple computer systems. It should be further appreciated that the steps described elsewhere in this disclosure may be performed on any one or more of the one or more processors 412, 420. In general, the term "processor" may be broadly defined to encompass any device having one or more processing elements that execute program instructions obtained from memory 414, 422. Additionally, the various subsystems of the process condition metrology wafer assembly 100 and associated systems (e.g., sensor 416, remote data system 402) may include processors or logic elements suitable for performing at least a portion of the steps described elsewhere in this disclosure. Thus, the above description should be taken as merely illustrative and not as a limitation on the present disclosure.

[0084] The memory 414, 422 may include any storage medium known in the art suitable for storing program instructions executable by the associated processor(s) 412, 420 as well as data received from the process condition metrology wafer assembly 100 / sensor 416. For example, the memory 414, 422 may include a non-transitory storage medium. For example, the memory 414, 422 may include, but is not limited to, a read-only memory (ROM), a random access memory (RAM), a magnetic or optical storage device (e.g., disk), a magnetic tape, a solid-state drive, etc. It is further noted that the memory 414, 422 may be housed in a common controller housing with the processor(s) 412, 420. In some embodiments, the memory 414, 422 may be located remotely relative to the physical location of the processor(s) 412, 420. Moreover, in embodiments, program instructions retained by memory 414, 422 cause the one or more processors 412, 420 to perform various steps described throughout this disclosure.

[0085] FIG. 6 is a flow chart of a method 600 for calculating temperature at any point in a process condition metrology wafer assembly 100 in accordance with one or more embodiments of the present disclosure.

[0086] In step 602, a set of temperature measurements from a set of temperature sensors and a set of heat flux measurements from a set of heat flux sensors distributed throughout the process condition measurement wafer are obtained under isothermal conditions. For example, the process condition measurement wafer assembly 100 can be manufactured with a plurality of temperature sensors 416 and a plurality of heat flux sensors 416 distributed at various locations throughout the process condition measurement wafer assembly 100. The plurality of temperature sensors 416 and the plurality of heat flux sensors 416 can be configured to obtain the set of temperature measurements and the set of heat flux measurements, respectively, under isothermal conditions. The processor 420 can then be configured to receive the measurements via the communication circuitry 404, 410.

[0087] In step 604, the set of temperature measurements and the set of heat flux measurements acquired under isothermal conditions are calibrated. For example, processor 420 can be configured to calibrate the set of temperature measurements by adjusting one or more of the acquired temperature measurements. For example, processor 420 can be configured to calibrate the set of temperature measurements by adjusting one or more of the acquired temperature measurements. Baseline The measurement may be configured to set a threshold value against which subsequent measurements are compared and / or adjusted.

[0088] In step 606, a known heat flux is applied to the process condition metrology wafer. For example, the processor 420 may be communicatively coupled to one or more heat sources (not shown) in the processing environment. The processor 420 may be configured to generate one or more control signals that cause the one or more heat sources to apply a known heat flux to the process condition metrology wafer assembly 100.

[0089] In step 608, a set of additional temperature measurements is obtained from the set of temperature sensors and a set of additional heat flux measurements is obtained from the set of heat flux sensors during application of the known heat flux. For example, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 can be configured to obtain a set of additional temperature measurements and heat flux measurements, respectively, during application of the known heat flux. A processor 420 can then be configured to receive the measurements via communication circuitry 404, 410. The processor 420 can be configured to store the measurements in memory 422.

[0090] In step 610, temperature variations observed across the set of temperature sensors during application of the known heat flux are identified. For example, as described herein with reference to FIG. 5, configuration variations (e.g., different sizes of cavities 107a, 107b, different sizes / shapes of electronic components 106, different bonding surfaces, different adhesive and / or conductive properties, etc.) may cause a first temperature sensor 416a to obtain different readings than an additional temperature sensor 416b. In this case, processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors 416 during application of the known heat flux.

[0091] In step 612, a heat flux vs. temperature variation relationship is identified by associating the known heat flux with the identified temperature variations at the set of temperature sensors. For example, processor 420 may be configured to identify a heat flux vs. temperature variation relationship by associating the known heat flux with the identified temperature variations. It is contemplated herein that the identified heat flux vs. temperature variation relationship may take any form known in the art, including, but not limited to, a relationship expressed by a mathematical equation(s), a list of associated heat flux values ​​and associated temperature variations, etc.

[0092] In step 614, a set of trial temperature measurements is obtained from the set of temperature sensors and a set of trial heat flux measurements is obtained from the heat flux sensors under unknown heat flux conditions. For example, the set of temperature sensors 416 can be configured to obtain a set of trial temperature measurements and the set of heat flux sensors 416 can be configured to obtain a set of trial heat flux measurements under unknown heat flux conditions. A processor 420 can then be configured to receive the obtained measurements via communication circuits 404, 410. The processor 420 can be configured to store the obtained measurements in memory 422.

[0093] In step 616, the set of trial temperature measurements is adjusted based on the set of trial heat flux measurements and the identified variational relationship of heat flux versus temperature. For example, processor 420 may be configured to identify that a subset of temperature sensors 416 read higher temperatures under a particular set of heat flux conditions based on the variational relationship of heat flux versus temperature. In this case, processor 420 may be configured to adjust (e.g., reduce) the temperature measurements collected by the subset of temperature sensors 416 in the set of trial temperature measurements based on the variational relationship of heat flux versus temperature. It is noted that processor 420 may be configured to adjust the set of trial temperature measurements using any mathematical technique known in the art.

[0094] Any of the methods described herein may include storing results of one or more steps of the method embodiments in a memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any of the memories described herein or any other suitable storage medium known in the art. Once the results are stored, they may be placed in the memory and accessed, used in any of the method or system embodiments described herein, formatted for display to a user, used in another software module, method or system, etc. Additionally, the storage of the results may be "permanent," "semi-permanent," "transient," or for some period of time. For example, the memory may be random access memory (RAM), and the results may not necessarily reside in the memory permanently.

[0095] According to further considerations, each of the method embodiments described above may incorporate any other step(s) of any other method(s) described herein. Additionally, each of the method embodiments described above may be performed by any of the systems described herein.

[0096] The directional terms used herein, such as "top", "bottom", "up", "down", "upwards", "upwards", "downwards", "downwards", and the like, are intended to provide relative positions for descriptive purposes and are not intended to specify an absolute coordinate system. Those skilled in the art will recognize that various modifications can be made to the described embodiments, and the general principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the specific embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features of the present disclosure.

[0097] The subject matter described herein sometimes depicts various components embedded or connected to other components. As will be appreciated, the illustrated architectures are merely exemplary, and in fact many other architectures may be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieves the same functionality is substantially "associated" to achieve the desired functionality. Thus, any two components in this application that are combined to achieve a particular functionality may be considered to be "associated" with each other to achieve the desired functionality, regardless of the architecture or intervening components. Similarly, any two components so associated may also be viewed as being "connected" or "coupled" to each other to achieve the desired functionality, and any two components that can be so associated may also be viewed as being "combinable" with each other to achieve the desired functionality. Examples of "coupleable" include, but are not limited to, physically interactable and / or physically interacting components, and / or wirelessly interactable and / or wirelessly interacting components, and / or logically interacting and / or logically interacting components.

[0098] Further, as can be understood, the present invention is defined by the appended claims. As can be understood by those of ordinary skill in the art, generally, the terms used in this application, particularly in the appended claims (e.g., the body of the appended claims) are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including but not limited to," etc.). As can also be understood by those of ordinary skill in the art, if a specific number of claim-introducing features is intended, then that intent will be clearly stated in the claim, and the absence of such features indicates that no such intent exists. For example, as an aid to understanding, some of the appended claims below incorporate the introduction of claim features through the use of the introductory phrases "at least one" and "one or more." However, the use of the indefinite article "a" or "an" should not be interpreted as if it implies that the introduction of a claim-introducing feature with the indefinite article "a" or "an" implies that all individual claims containing the indefinite article are limited to inventions containing only one of the feature, even when the indefinite article "one or more" or "at least one" coexists with the indefinite article, e.g., "a" or "an" in the very claim (e.g., "a" and / or "an" should usually be interpreted as meaning "at least one" or "one or more"), and the same is true with respect to the introduction of a claim-introducing feature with the use of a definite article. In addition, even when a specific number of features is specified in a claim, the number should usually be interpreted as meaning at least the specified number, as would be recognized by a person skilled in the art (e.g., the bare expression "two features" without other modifiers usually means at least two features or more than two features).Furthermore, where a convention similar to "at least one of A, B, and C, etc." is used, such syntax is generally intended to be consistent with how a person of ordinary skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or systems having A, B, and C, etc.). Where a convention similar to "at least one of A, B, or C, etc." is used, such syntax is generally intended to be consistent with how a person of ordinary skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or systems having A, B, and C, etc.). As will also be appreciated by those of ordinary skill in the art, nearly all disjunctive conjunctions and / or phrases presenting two or more alternative terms, regardless of where they appear in the specification, claims, and drawings, should be understood to contemplate the possibility of including either term, either term, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0099] The present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes in the form, construction and arrangement of the parts may be made without departing from the disclosed subject matter or diminishing all of its essential advantages. The form described is merely illustrative, and it is the intent of the following claims to encompass and embrace all such modifications. Moreover, it is the appended claims which define the invention.

Claims

1. 1. A method comprising: obtaining a set of temperature measurements from a set of temperature sensors and a set of heat flux measurements from a set of heat flux sensors under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions; applying a known heat flux to a process condition measurement wafer; obtaining a set of additional temperature measurements from the set of temperature sensors and obtaining a set of additional heat flux measurements from the set of heat flux sensors during application of the known heat flux; identifying temperature variations observed across the set of temperature sensors during application of a known heat flux; identifying a heat flux-temperature change relationship by correlating known heat fluxes with identified temperature changes of the set of temperature sensors; obtaining a set of trial temperature measurements from the set of temperature sensors and a set of trial heat flux measurements from the set of heat flux sensors under unknown heat flux conditions; adjusting the set of trial temperature measurements based on the set of trial heat flux measurements and the identified heat flux-temperature variation relationship; A method for providing the above.

2. 2. The method of claim 1, wherein the set of temperature sensors is distributed across the process condition metrology wafer and the set of heat flux sensors is distributed across the process condition metrology wafer.

3. Mapping the adjusted set of test temperature measurements to one or more measurement locations on the process condition metrology wafer. The method of claim 1 further comprising:

4. Interpolating a set of temperature values ​​at locations between one or more measurement locations based on the adjusted set of trial temperature measurements and one or more interpolation functions. The method of claim 1 further comprising:

5. Calibrating the set of temperature measurements and the set of heat flux measurements taken under the isothermal conditions comprises: establishing the set of temperature measurements and the set of heat flux measurements taken under the isothermal conditions as a baseline; 2. The method of claim 1, comprising:

6. applying the known heat flux to the process condition measurement wafer, causing a heat source to apply the known heat flux to the process condition measurement wafer.

2. The method of claim 1, comprising:

7. 1. A system comprising: one or more processors communicatively coupled to a set of temperature sensors and a set of heat flux sensors of a process condition measurement wafer, the one or more processors comprising: obtaining a set of temperature measurements from the set of temperature sensors and a set of heat flux measurements from the set of heat flux sensors under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions; obtaining a set of additional temperature measurements from the set of temperature sensors and obtaining a set of additional heat flux measurements from the set of heat flux sensors during application of a known heat flux; identifying temperature variations across the set of temperature sensors during application of a known heat flux; identifying a heat flux-temperature variation relationship by correlating known heat fluxes with the identified temperature variations of the set of temperature sensors; obtaining a set of trial temperature measurements from the set of temperature sensors under unknown heat flux conditions; and obtaining a set of trial heat flux measurements from the set of heat flux sensors. Adjusting the set of trial temperature measurements based on the set of trial heat flux measurements and the identified heat flux-temperature variation relationship. The system is configured to execute a set of program instructions configured to:

8. 8. The system of claim 7, wherein the set of temperature sensors is distributed across the process condition metrology wafer and the set of heat flux sensors is distributed across the process condition metrology wafer.

9. The one or more processors: Mapping the adjusted set of test temperature measurements to one or more measurement locations on the process condition metrology wafer. The system according to claim 7 , configured to:

10. The one or more processors: Interpolating a set of temperature values ​​at locations between the one or more measurement locations based on the adjusted set of trial temperature measurements and one or more interpolation functions. The system according to claim 7 , configured to:

11. Calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions comprises: Establishing the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions as a baseline. The system of claim 7 , comprising:

12. a heat source configured to apply a known heat flux to the process condition measurement wafer; The system of claim 7 further comprising:

13. 1. A system comprising: a process condition measurement wafer including a set of temperature sensors and a set of heat flux sensors; one or more processors communicatively coupled to the set of temperature sensors and the set of heat flux sensors, obtaining a set of temperature measurements from the set of temperature sensors and a set of heat flux measurements from the set of heat flux sensors under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions; obtaining a set of additional temperature measurements from the set of temperature sensors and obtaining a set of additional heat flux measurements from the set of heat flux sensors during application of a known heat flux; identifying temperature variations across the set of temperature sensors during application of a known heat flux; identifying a heat flux-temperature variation relationship by correlating known heat fluxes with the identified temperature variations of the set of temperature sensors; obtaining a set of trial temperature measurements from the set of temperature sensors under unknown heat flux conditions; and obtaining a set of trial heat flux measurements from the set of heat flux sensors. adjusting the set of trial temperature measurements based on the set of trial heat flux measurements and the identified heat flux-temperature variation relationship. one or more processors configured to execute a set of program instructions configured to A system including:

14. 14. The system of claim 13, wherein the set of temperature sensors is distributed across the process condition metrology wafer and the set of heat flux sensors is distributed across the process condition metrology wafer.

15. The one or more processors: Mapping the adjusted set of test temperature measurements to one or more measurement locations on the process condition metrology wafer. The system of claim 13.

16. The one or more processors: Interpolating a set of temperature values ​​at locations between the one or more measurement locations based on the adjusted set of trial temperature measurements and one or more interpolation functions. The system of claim 13.

17. Calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions comprises: Establishing the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions as a baseline. The system of claim 13 , comprising:

18. a heat source configured to apply a known heat flux to the process condition measurement wafer; The system of claim 13 further comprising:

Images