Semiconductor Device

Abstract

To provide a memory device using a semiconductor that stores data by using a transistor with a low leakage current between a source and a drain in an off state as a write transistor.SOLUTION: In a matrix formed using a plurality of memory cells in which the drain of a write transistor WTr(n, m) is connected with the gate and the drain of a read transistor RTr(n, m) and one of electrodes of a capacitor C(n, m), the gate of the write transistor is connected to a write word line Qn, the source of the write transistor and the source of the read transistor are connected to a bit line Rm, and the drain of the read transistor is connected to a read bias line Sn. Here, the conductivity types of the write transistor and the read transistor are made different in order to increase the degree of integration, the bias line may be substituted by a read word line Pn in another row, or the memory cells may be connected in series to form a NAND structure, and the read word line and the write word line may be shared.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory device using a semiconductor. [Background technology]

[0002] There are many types of semiconductor memory devices. For example, dynamic random access memory (DRA) Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) , Electronically Erasable Programmable Read-Only Memory (EEPROM) and Flash Schmemorie et al.

[0003] DRAM stores data by storing electric charge in a capacitor in the memory cell. However, conventionally, transistors used for switching are in the off state. However, since a small amount of leakage current occurs between the source and drain, the data is stored for a relatively short time (long Therefore, data is lost in a certain period (generally every tens of milliseconds). It is necessary to write (refresh).

[0004] SRAM also retains data using the bistable state of flip-flop circuits. The flip-flop circuit of M usually uses a CMOS inverter, but Since six transistors are used per chip, the integration rate is lower than that of DRAM. If not, data will be lost.

[0005] On the other hand, EEPROM and flash memory use what is called a floating gate. The floating gate is placed between the channel and the gate, and stores electric charge to store data. The charge stored in the floating gate is retained when power to the transistor is removed. Since the information is retained after a period of time, these memories are called non-volatile memories. For this, see, for example, Patent Document 1.

[0006] In this specification, the present invention is particularly directed to a device having a floating gate, such as an EEPROM or a flash memory. The memory that uses this is called floating gate nonvolatile memory (FGNVM). In the , multi-level data can be stored in one memory cell, so the memory capacity can be increased. In addition, NAND flash memory can drastically reduce the number of contact holes, The degree of integration can be increased to a certain degree.

[0007] However, conventional FGNVMs have a problem when injecting or removing charge into the floating gate. High voltage is required, and because of this, deterioration of the gate insulating film is unavoidable and uncontrollable. It was not possible to repeatedly write or erase data. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0009] As described above, conventional semiconductor memory devices have both advantages and disadvantages. There was nothing that fully satisfied all the requirements. Low power consumption is required for memory devices. If the power consumption is large, the device that supplies the power must be large. In addition, the battery life is shortened. The characteristics may deteriorate, and even the circuit may be destroyed. It is preferable that there is no limit to the number of times it can be rewritten, and it is desirable that it can be rewritten more than 1 billion times. Of course, high integration is also necessary.

[0010] In this regard, DRAM consumes a lot of power because it constantly generates leakage current and is refreshed. On the other hand, SRAM has six transistors in one memory cell. Another problem is that the integration density cannot be increased due to the power consumption of the FGNVM. There were no problems with power or density, but the number of rewrites was less than 100,000.

[0011] In view of the above, it is desirable to reduce the power consumed by a memory cell for memory retention to less than that of a DRAM. The number of transistors used in the memory cell is 5 or less, and the number of rewrites is 1 million. The first challenge is to simultaneously meet these three conditions. Data should be retained for at least 10 hours, preferably at least 100 hours, without the application of force. and the number of rewrites must be more than one million. In this specification, the data retention time refers to the time period during which data is retained in a memory cell. This is defined as the time when the accumulated charge becomes 90% of the initial charge.

[0012] In addition to the above object, the present invention provides a novel semiconductor device, particularly a semiconductor memory device. Another object of the present invention is to provide a novel method for driving a semiconductor device, particularly a method for driving a semiconductor memory device. Further, it is an object of the present invention to provide a novel method for manufacturing a semiconductor device, particularly a method for manufacturing a semiconductor device. The present invention aims to provide a method for manufacturing a body memory device. This also solves the problem. [Means for solving the problem]

[0013] The present invention will be described below, but the terms used in this specification will be briefly explained. The source and drain of a transistor have the same or equivalent structure and function. Even if the structures are different, the potential and polarity applied to them must be constant. For these reasons, in this specification, when either one is referred to as a source, the other is referred to as a source for convenience. In this specification, the source and drain are referred to as the same. It is also possible to read what is written as drain.

[0014] In this specification, "orthogonal (in a matrix)" means intersecting at a right angle. In the simplest circuit diagram, not only in terms of meaning but also in terms of physics, "Parallel" means that two arrays are perpendicular to each other. Even if the lines are physically arranged to cross, they are parallel in the simplest circuit diagram. It means that it is a row.

[0015] One embodiment of the present invention is a transistor having a small leakage current between a source and a drain in an off state. is the write transistor, and another transistor (read transistor) and The conductivity type of the read transistor is the same as that of the write transistor. The conductivity type of the transistor is different from that of the write transistor. For example, if the write transistor is an N-channel type In this case, the readout transistor is a P-channel type. At least three types of wiring, namely, write word lines, bit lines, and read word lines, are used. Get it ready.

[0016] The drain of the write transistor is connected to the gate and capacitance of the read transistor. In addition, the gate of the write transistor is connected to the write word the source of the write transistor and the source of the read transistor to the bit line. , the other electrode of the capacitor is connected to a read word line.

[0017] Write transistor in off state (in the case of N-channel type, the gate potential is the same as the source and drain potential) The leakage current between the source and drain at the temperature (e.g., 1 × 10 at 25 °C) -20 A or less, preferably 1×10 -21 A or below, yes At 85°C, it is 1×10 -20 A or less is desirable. In normal silicon semiconductors, Although it is difficult to achieve such a low leakage current, oxide semiconductors are favorable conditions. This can be achieved in the transistor obtained by processing in the above manner. It is preferable to use an oxide semiconductor as the material for the capacitor. In silicon semiconductors and other semiconductors, it is possible to reduce the leakage current to the above value or less. If it is possible to do so, this does not preclude its use.

[0018] As the oxide semiconductor, various known materials can be used. Electron volts or more, preferably 3 electron volts or more and less than 3.6 electron volts. In addition, the electron affinity is 4 electron volts or more, preferably 4 electron volts or more and 4.9 electron volts or more. In particular, oxides containing gallium and indium are preferred for use in the present invention. In such a material, the donor or acceptor The carrier concentration derived from -14 cm -3 Less than 1 x 10 -11 c m -3 It is preferable that it is less than 100%.

[0019] As for the readout transistor, the leakage current between the source and drain in the off state is There is no limit to the leakage current, but it is preferable to have a smaller leakage current because it reduces power consumption. To increase the read speed, it is desirable to have a high-speed operation. It is preferable that the switching speed is 10 nsec or less. The gate leakage current (gate-source or gate-drain) of both the read transistor and the The capacitor must also have an extremely low internal leakage current ( The leakage current between the electrodes must be low. For example, 1 × 10 at 25°C -20 A or less, preferably 1×10 -21 A or below It is desirable to do so.

[0020] The potential of the gate of the read transistor changes according to the potential of the read word line. However, as a result, the gate capacitance of the read transistor may vary. The gate capacitance is larger when the read transistor is on than when it is off. If the gate capacitance variation is larger than the capacitance of the capacitor, the memory This creates problems in operating the cell.

[0021] Therefore, the capacitance of the capacitor is set to be equal to or larger than the gate capacitance of the read transistor, preferably It is advisable to set the capacitance to at least twice as large as the capacitance of the semiconductor memory device in order to operate the semiconductor memory device at high speed. It is desirable to keep the capacitance of the capacitor below 10 fF.

[0022] The write word lines, bit lines, and read word lines form a matrix. To drive the device, the write word line and the bit line are perpendicular to each other, and the write word line and the read The extended word lines are preferably parallel.

[0023] FIG. 1A shows an example of a memory cell having the above structure. We will explain this using a memory cell as an example. n and m can be natural numbers. In FIG. 1(A), Transistor WTr(n,m), read transistor RTr(n,m), and capacitor C A memory cell consisting of a write transistor WTr(n ,m) is connected to the gate of the read transistor RTr(n,m) and the capacitor C It is connected to one of the electrodes (n,m).

[0024] Furthermore, the gate of the write transistor WTr(n,m) is connected to the write word line Qn. The source of the write transistor WTr(n,m) and the read transistor RTr(n,m) The source of the capacitor C(n,m) is connected to the bit line Rm, and the other electrode of the capacitor C(n,m) is connected to the read word line P n, respectively.

[0025] In addition, the drain of the read transistor RTr(n,m) is connected to the bias line Sn. In FIG. 1A, a write word line Qn, a read word line Pn, and a bias line Sn are parallel to each other. The write word line Qn and the bit line Rm are perpendicular to each other.

[0026] FIG. 1(B) shows the periphery of the memory cell in the nth row and mth column (n and m are natural numbers greater than or equal to 2). As is clear from the figure, three wires are required per row and one wire per column. So, for a matrix with N rows and M columns, (3N+M) wires are required.

[0027] In the memory cell shown in FIG. 1(A), by applying an appropriate potential to the write word line Qn, Then, the write transistor WTr(n,m) is turned on. The potential injects charge into the drain of the write transistor WTr(n,m). The amount of charge injected at this time depends on the potential of the bit line Rm and the potential of the read transistor RTr(n,m). Since it is determined by the gate capacitance, the capacitance of the capacitor C(n,m), etc., This will result in almost the same results and less variation. do.

[0028] Next, the write transistor is turned on by applying another appropriate potential to the write word line Qn. In this case, the write transistor WTr(n,m) is in the off state. The charge on the drain of the nth and mth transistors is maintained as is. When reading, the read word line P n, bias line Sn, etc., the read transistor RTr(n,m) By monitoring whether the following conditions occur, you can know what data has been written: Cut.

[0029] In the above configuration, the bias line may be shared between adjacent rows. Here, the memory cell adjacent to the (2n-1)th row and mth column is shown. The memory cell in the 2nth row and mth column (n and m are natural numbers) will be described as an example.

[0030] In FIG. 5, a write transistor WTr(2n-1,m) and a read transistor RTr (2n-1,m) and capacitor C(2n-1,m) A memory cell, a write transistor WTr(2n,m) and a read transistor RTr(2 The memory cell in the 2nth row and mth column is shown, which consists of a 2n-th row, m-th column, and a capacitor C(2n,m). .

[0031] The drain of the write transistor WTr(2n-1,m) is connected to the read transistor RTr (2n-1,m) and one electrode of the capacitor C(2n-1,m) Similarly, the drain of the write transistor WTr(2n,m) is connected to the drain of the read transistor Connected to the gate of the transistor RTr(2n,m) and one electrode of the capacitor C(2n,m). It has been done.

[0032] Furthermore, the gate of the write transistor WTr(2n-1,m) is connected to the write word line Q2 n-1, the gate of the write transistor WTr(2n,m) is connected to the write word line Q2n The other electrode of the capacitor C(2n-1,m) is connected to the read word line P2n-1. The other electrode of the capacitor C(2n,m) is connected to the read word line P2n, and the other electrode of the read transistor The drain of RTr(2n-1,m) and the drain of the read transistor RTr(2n,m) The bias line Sn is connected to the source of the write transistor WTr(2n-1,m), The source of the read transistor WTr(2n,m), the source of the read transistor RTr(2n-1, The source of the read transistor RTr(2n,m) is connected to the bit line Rm, Each is connected.

[0033] As is clear from the above, five wires are required for every two rows and one wire for every column, so 2 A matrix of N rows and M columns requires (5N+M) wires. In this case, (6N+M) wires are required for the same size matrix. By sharing the bias line between the rows, the number of wirings can be reduced compared to the configuration in Figure 1. .

[0034] In addition, the bias line in the configuration of FIG. 1 may be replaced with an adjacent write word line. FIG. 6A shows an example of a memory cell having the above structure. (n, m are natural numbers) memory cell will be explained as an example. WTr(n,m), read transistor RTr(n,m), and capacitor C(n,m ) is shown.

[0035] The drain of the write transistor WTr(n,m) is connected to the drain of the read transistor RTr(n, m) and one electrode of the capacitor C(n,m). The gate of the write transistor WTr(n,m) is connected to the write word line Qn. The source of the read transistor WTr(n,m) and the source of the read transistor RTr(n,m) are The drain of the read transistor RTr(n,m) is connected to the bit line Rm. the other electrode of the capacitor C(n,m) is connected to the read word line Pn; Each is connected.

[0036] FIG. 6B illustrates the periphery of the memory cell in the nth row and mth column. Since two wires are required per row and one wire per column, the edges of the matrix are also Considering this, a matrix with N rows and M columns requires (2N+M+1) wires. As shown in FIG. 1, the bias line is replaced by the adjacent write word line. , the number of wirings can be further reduced compared to the configuration of FIG.

[0037] Another embodiment of the present invention is a write transistor, a read transistor, and a A semiconductor memory device consisting of a memory unit formed by using multiple transistors and capacitors. Here, the conductivity types of the write transistor and the read transistor are For example, if the write transistor is an N-channel type, the read The transistor is a P-channel type.

[0038] That is, the drain of the first write transistor is connected to one electrode of the first capacitor, and and the gate of the first read transistor, and the drain of the second write transistor. The input is connected to one electrode of the second capacitor and to the gate of the second readout transistor. To be continued.

[0039] The drain of the first write transistor is connected to the source of the second write transistor. The drain of the first readout transistor is connected to the source of the second readout transistor. Furthermore, the gate of the first write transistor is connected to the first write word line The gate of the second write transistor is connected to the second write word line via the first capacitor. The other electrode of the second capacitor is connected to the first read word line, and the other electrode of the second capacitor is connected to the first read word line. 2 and 3. The read word lines 111 and 112 are connected to the read word lines 111 and 113, respectively.

[0040] The source of the first write transistor and the source of the first read transistor are connected to a bipolar transistor. In addition, between the source of the first write transistor and the bit line, Alternatively, between the source of the first read transistor and the bit line, or One or more transistors may be inserted into both of the first and second inputs.

[0041] A first write word line, a second write word line, a first read word line, a second read The extension word lines are parallel to each other and perpendicular to the bit lines.

[0042] FIG. 16(A) illustrates an example of a storage unit having the above structure. The unit has one write transistor, one read transistor, and one capacitor. The memory cell has a plurality of unit memory cells. That is, the write transistor WTr1 and the read transistor WTr2 are A first memory cell consisting of a write transistor RTr1 and a capacitor C1. 2, a second memory cell consisting of a read transistor RTr2 and a capacitor C2, A third transistor WTr3, a read transistor RTr3, and a capacitor C3 A storage unit consisting of three storage cells, a storage cell, is shown.

[0043] The drain of the write transistor in each memory cell is connected to one electrode of a capacitor. and the gate of the read transistor. These transistors and capacitors The potential at the connection point is related to the on / off state of the read transistor, so These intersections are called nodes F1, F2, and F3.

[0044] The drain of the write transistor WTr1 is connected to the source of the write transistor WTr2. The drain of the read transistor RTr1 is connected to the source of the read transistor RTr2. In addition, the drain of the write transistor WTr2 is connected to the The drain of the read transistor RTr2 is connected to the source of the read transistor WTr3. Connect this pin to the source of transistor RTr3.

[0045] In this example, the drain of the read transistor RTr3 is connected to the bias line S. One or more transistors are placed between the drain of the readout transistor RTr3 and the bias line S. The source of the write transistor WTr1 and the source of the read transistor R The source of Tr1 is connected to the bit line R. The gates of WTr3 are connected to the write word lines Q1, Q2, and Q3, respectively. The other electrodes of the transistors C1, C2, and C3 are connected to read word lines P1, P2, and P3.

[0046] The write word lines Q1, Q2, and Q3 and the read word lines P1, P2, and P3 are parallel to each other. and is perpendicular to the bit line R. Note that the bias line S is always kept at a constant potential. If there is, it is not necessary to make it parallel or perpendicular to other wiring. From the viewpoint of increasing the efficiency, it is preferable that the gate line is perpendicular to the bit line.

[0047] In this way, the three memory cells share the contact between the bit line and the memory cell. By doing so, the area of ​​the contacts per unit memory cell can be reduced. In FIG. 16A, three memory cells are provided in the memory unit. However, one storage unit may be configured with more storage cells. For example, one storage unit may be made up of 16 or 32 storage cells.

[0048] This structure is similar to the NAND structure of flash memory. By connecting the memory cells in series like this, more memory cells can be connected to one bit line. The contact between the memory cell and the memory cell can be shared, and the surface area per unit memory cell can be reduced. For example, when the minimum processing line width is F, the unit The area per memory cell is 12F 2 , or even lower.

[0049] The circuit diagram shown in FIG. 16(A) is one memory unit used in a semiconductor memory device. However, a semiconductor memory device is obtained by arranging these storage units in a matrix. An example is shown in Figure 19. Here, the nth row, (m-1)th column, the nth row, mth column, the nth row, (m+ 1) Column, row n, column (m+2), row (n+1), column (m-1), row (n+1), column m , (n+1)th row, (m+1)th column, (n+1)th row, (m+2)th column, unit, 24 storage cells are shown.

[0050] The memory unit in the nth row and mth column is connected to write word lines Q1n, Q2n, and Q3n, and Word lines P1n, P2n, P3n, bias line Sn, and bit line Rm are provided. The same is true for the memory unit.

[0051] Another embodiment of the present invention is a write transistor, a read transistor, and a A memory unit formed by using a plurality of read transistors and a plurality of capacitors. That is, the drain of the first write transistor is connected to the first A second electrode is connected to one electrode of the capacitor and the gate of the first readout transistor. The drain of the write transistor is connected to one electrode of the second capacitor, and the drain of the second read transistor is connected to one electrode of the second capacitor. The drain of the third write transistor is connected to the gate of the third capacitor. The first electrode of the first read transistor is connected to one electrode of the second read transistor and to the gate of the third read transistor.

[0052] The drain of the first write transistor is connected to the source of the second write transistor. The drain of the first readout transistor is connected to the source of the second readout transistor. Similarly, the drain of the second write transistor is connected to the drain of the third write transistor. The drain of the second readout transistor is connected to the source of the third readout transistor. Connect to the source of the resistor.

[0053] Further, the gate of the first write transistor is connected to the first write word line. The other electrode of the capacitor and the gate of the second write transistor are connected to a second write word. The other electrode of the second capacitor and the gate of the third write transistor are connected to the line Connect to the write word line.

[0054] The source of the first write transistor and the source of the first read transistor are connected to a bipolar transistor. In addition, between the source of the first write transistor and the bit line, Alternatively, between the source of the first read transistor and the bit line, or One or more transistors may be inserted into both of the first and second inputs.

[0055] The first write word line, the second write word line, and the third write word line are mutually They are parallel and perpendicular to the bit lines.

[0056] FIG. 16B illustrates an example of a storage unit having the above structure. In FIG. The memory unit has one write transistor, one read transistor, and one capacitor. That is, the write transistor WTr1 and the read transistor WTr2 are A first memory cell consisting of a transistor RTr1 and a capacitor C1, a write transistor W A second memory cell is composed of a write transistor Tr2, a read transistor RTr2 and a capacitor C2. The third transistor is composed of a write transistor WTr3, a read transistor RTr3, and a capacitor C3. 3 storage cells, a storage unit consisting of three storage cells is shown.

[0057] The drain of the write transistor and one electrode of the capacitor in each memory cell The gates of the read transistors are connected together. The potential at the connection point is related to the on / off state of the read transistor, so These intersections are called nodes F1, F2, and F3.

[0058] The drain of the write transistor WTr1 is connected to the source of the write transistor WTr2. The drain of the read transistor RTr1 is connected to the source of the read transistor RTr2. In addition, the drain of the write transistor WTr2 is connected to the The drain of the read transistor RTr2 is connected to the source of the read transistor WTr3. Connect this pin to the source of transistor RTr3.

[0059] In this example, the drain of the read transistor RTr3 is connected to the bias line S. One or more transistors are placed between the drain of the readout transistor RTr3 and the bias line S. The source of the write transistor WTr1 and the source of the read transistor R The source of Tr1 is connected to the bit line R. The gates of WTr3 are connected to the write word lines Q1, Q2, and Q3, respectively. The other electrodes of the transistors C1 and C2 are also connected to the write word lines Q2 and Q3, respectively. In addition, the other electrode of the capacitor C3 is connected to a read word line P.

[0060] The write word lines Q1, Q2, Q3 and the read word line P are parallel to each other. If the bias line S is always kept at a constant potential, It is not necessary to make the wiring parallel or perpendicular to the wiring. However, in terms of increasing the integration density, It is preferable that the conductor be perpendicular to the dot line.

[0061] As in the memory unit shown in FIG. 16(A), there are three memory cells, and the bit lines and memory cells By sharing the contacts between the memory cells, The area of ​​the tact can be reduced, and the degree of integration can be improved. More memory The cells can share a contact between one bit line and the storage cell, The area per unit memory cell can be reduced.

[0062] In addition, the configuration shown in FIG. 16(B) does not require the readout required in the configuration shown in FIG. In addition, there is also an effect of reducing the area by substituting some of the word lines with write word lines. Due to such effects, for example, the area per unit memory cell in a semiconductor memory device can be reduced to 9 F 2 , or even lower.

[0063] Although several configurations have been shown above as means for solving the problem, this specification will not discuss other solutions. The present invention also discloses a method for manufacturing a semiconductor device using the above configuration and other solutions disclosed herein. The problem can be solved by making obvious modifications to the above. It is not limited to the three configurations. Effect of the Invention

[0064] By employing any one of the above configurations, at least one of the above problems can be solved. Regarding the number of rewrites, in the above configuration, all write operations are write transactions. Since the switching is performed by turning on and off the transistor, deterioration of the insulating film does not occur. The semiconductor memory device having the above configuration has virtually no restrictions on rewriting.

[0065] In addition, the semiconductor memory device having the above configuration has excellent characteristics with regard to the period during which data can be stored. The leakage current between the source and drain of the transistor in the off state and the gate By setting the above conditions for the internal leakage current of the capacitor, the charge is It is possible to maintain the temperature for 100 hours or more, preferably 100 hours or more. It can be retained for more than a month or a year.

[0066] If the charge is reduced due to leakage, it can be refreshed in the same way as with conventional DRAM. However, the interval is determined by the period during which the charge can be maintained. By retaining the charge for a certain period of time, the refresh interval can be set to, for example, once a month. Once a year, for example. Frequent refreshing, as was necessary with conventional DRAM, is no longer necessary. This results in a semiconductor memory device with lower power consumption.

[0067] In the semiconductor memory device having the above configuration, the data is erased by the data read operation. Conventionally, this feature has been realized with SRAM, but In the semiconductor memory device, the number of transistors used in one memory cell is smaller than that of the conventional SRA. It is less than M, 5 or less, typically 2. Furthermore, one of the transistors If a thin-film oxide semiconductor is used, it can be formed by stacking it on top of a conventional silicon semiconductor. This allows for greater integration density.

[0068] Regarding the degree of integration, in the semiconductor memory device having the above configuration, the absolute value of the capacity required for the memory cell is For example, in a DRAM, the capacitance of a memory cell is determined by the wiring capacitance. A capacitance of at least 30fF was required because operation would be impaired if the capacitance was not at least the same. However, since capacitance is proportional to area, increasing the degree of integration increases the area of ​​one memory cell. Therefore, DRAM requires special shapes and It was necessary to create a large volume using the material.

[0069] In contrast, in the semiconductor memory device having the above configuration, the capacitance of the capacitor is The capacitance can be determined by the relative ratio to the gate capacitance of the transistor. This means that the gate capacitance of the read transistor is small. The capacitance required for the capacitors also decreases by the same factor. Basically, a capacitor of the same structure can be used.

[0070] Furthermore, the semiconductor memory device having the above configuration is required for writing and erasing in the FGNVM. Among FGNVM, so-called flash memory (especially NA ND) had an advantage over SRAM and DRAM in terms of integration, but it was difficult to rewrite some of the data. To erase the data, it was necessary to use a high voltage to erase a certain area at once. In the semiconductor memory device having the above configuration, writing (rewriting) is performed row by row. , and can be completed with the minimum number of operations required.

[0071] In addition, in the FGNVM, the charge injection into the floating gate during writing is one-way. Since the charge transfer is performed in a non-equilibrium state, the charge amount varies widely. Depending on the amount of charge held by the gate, multiple levels of data can be stored. Considering the variation in load, about four stages (2 bits) were common. In order to store data, a higher voltage had to be used.

[0072] In contrast, in the configuration having the above structure, the accumulation of charge in the capacitor is reversible. For example, the threshold voltage of the read transistor due to the injection of electric charges is small. This allows the variation in the voltage to be reduced to less than 0.5 volts. More data can be stored in a single memory cell, resulting in a lower write and read voltage. For example, when writing or reading 4-bit (16-level) data, The voltage used can be 10 volts or less. [Brief description of the drawings]

[0073] [Figure 1] 1 is a diagram showing an example of a semiconductor memory device according to the present invention; [Diagram 2] 1 is a diagram for explaining an example of a driving method (writing) of a semiconductor memory device of the present invention. FIG. [Diagram 3] 1 is a diagram illustrating an example of a method for driving (reading) a semiconductor memory device according to the present invention. [Figure 4] 1A to 1C are diagrams illustrating an example of a method for driving a semiconductor memory device according to the present invention. [Diagram 5] 1 is a diagram showing an example of a semiconductor memory device according to the present invention; [Figure 6] 1 is a diagram showing an example of a semiconductor memory device according to the present invention; [Figure 7] 2 is a diagram showing an example of a wiring layout of a semiconductor memory device according to the present invention; FIG. [Figure 8] 1A to 1C are diagrams illustrating an example of a manufacturing process of a semiconductor memory device of the present invention. [Figure 9] 1A to 1C are diagrams illustrating an example of a manufacturing process of a semiconductor memory device of the present invention. [Figure 10] 2 is a diagram showing an example of a wiring layout of a semiconductor memory device according to the present invention; FIG. [Figure 11] 1A to 1C are diagrams illustrating an example of a method for driving a semiconductor memory device according to the present invention. [Figure 12] 1 is a diagram for explaining an example of a driving method (writing) of a semiconductor memory device of the present invention. FIG. [Figure 13] 1 is a diagram illustrating an example of a method for driving (reading) a semiconductor memory device according to the present invention. [Figure 14] 1 is a diagram for explaining an example of a driving method (writing) of a semiconductor memory device of the present invention. FIG. [Figure 15] 1 is a diagram for explaining an example of a method for driving (reading) a semiconductor memory device according to the present invention; [Figure 16] 1 is a diagram showing an example of a semiconductor memory device according to the present invention; [Figure 17] 1 is a diagram for explaining an example of a driving method (writing) of a semiconductor memory device of the present invention. FIG. [Figure 18] 1 is a diagram illustrating an example of a method for driving (reading) a semiconductor memory device according to the present invention. [Figure 19] 1 is a diagram showing an example of a semiconductor memory device according to the present invention; [Figure 20] 1 is a diagram for explaining an example of a driving method (writing) of a semiconductor memory device of the present invention. FIG. [Figure 21] 1 is a diagram illustrating an example of a method for driving (reading) a semiconductor memory device according to the present invention. [Figure 22] 2 is a diagram showing an example of a wiring layout of a semiconductor memory device according to the present invention; FIG. [Diagram 23] 2 is a diagram showing an example of a wiring layout of a semiconductor memory device according to the present invention; FIG. [Figure 24] 1A to 1C are diagrams illustrating an example of a manufacturing process of a semiconductor memory device of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0074] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0075] In addition, the structures, conditions, and other items disclosed in the following embodiments may also be used in other embodiments. In the configurations described below, the same things are indicated. The reference numerals in the drawings are the same, and the same parts or parts having similar functions are shown in the drawings. A detailed description of the above may be omitted.

[0076] In the following embodiments, for ease of understanding, the timing, width, height, etc. of the pulses are not necessarily specified. is written to be a constant value, but in the spirit of the present invention, it is not necessarily the case that the pulse It is easy to understand that the timing does not need to be perfectly synchronized or the width and height are constant. .

[0077] (Embodiment 1) In this embodiment, the operation of the semiconductor memory device shown in FIGS. 1(A) and 1(B) will be described with reference to FIG. An example of the operation will be described. Specific values ​​for the potential are given below, which are as follows: The purpose is to help understand the technical concepts. Needless to say, these values ​​are This can be changed depending on various characteristics of the capacitor, etc., or for the convenience of the implementer. The semiconductor memory device shown in FIG. 1 can also store data by methods other than the following method. It can be written or read.

[0078] Here, the write transistor WTr(n,m) is an N-channel type, and the read transistor The write transistor RTr(n,m) is a P-channel type. The write transistor WTr(n,m) is When the gate potential becomes 1V higher than either the source or drain potential, It is assumed that the transistor is turned on (current flows) and that the transistor is otherwise off (current does not flow). , the read transistor RTr(n,m) has a gate potential equal to the source or drain potential. When the potential of either of these is 1V or more lower, the transistor turns on (current flows). is off (does not pass current).

[0079] In addition, the gate capacitance of the read transistor RTr(n,m) is determined by the gate bias. The amount of fluctuation due to the change can be ignored compared to the capacitance of the capacitor C(n,m). , the parasitic capacitance of the write transistor WTr(n,m) and the parasitic capacitance of the read transistor RTr(n ,m) and other capacitances not shown in the figure, such as the parasitic capacitance between wiring, are all assumed to be 0. In Fig. 4, a circle is used to indicate a transistor that is in the on state, and a black circle is used to indicate a transistor that is in the off state. Transistors are represented by a cross over the transistor symbol. The items that are turned on may be separately indicated in the drawings.

[0080] In a write operation, as shown in FIG. 4A, the voltages of the read word line Pn and the bias line Sn are The potential of the bit line Rm is set to 0V, +1V, or , +2V, +3V. The potential of the write word line Qn is When the voltage is set to +4V, the write transistor WTr(n,m) turns on and the write transistor The drain potential of the transistor WTr(n,m) is the source potential of the write transistor (i.e. In this case, it is assumed that the potential of the bit line Rm approaches that of the bit line Rm. do.

[0081] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is It is equal to the drain potential of the read transistor WTr(n,m). The potential of the gate of the read transistor RTr(n,m) is 0V or higher. n, m) (i.e., the potential of bit line Rm).

[0082] Also, the drain of the read transistor RTr(n,m) (i.e., the bias line Sn) The potential at the gate of the read transistor RTr(n,m) is 0V. Since the potential is the same as or higher than the source and drain potentials, the read transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0083] In addition, the read transistor RTr(n,m) is turned off as much as possible, including during writing. The state is that the gate of the read transistor RTr(n,m) is connected to the source, or This is effective in reducing the leakage current from the gate to the drain. The peak current is increased in the on-state and is very low in the off-state.

[0084] Such leakage current is due to leakage of the charge stored in the capacitor C(n,m), so A large amount of data means a decrease in data retention time. The transistor RTr(n,m) is turned on only when reading data. It is excellent in terms of durability.

[0085] Next, when writing to a line other than the nth line, the writing is performed as shown in FIG. The potential of the read word line Qn is set to -3 V. The potential of the read word line Pn is set to +3 V. The potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm is set to It can take on four values: 0V, +1V, +2V, or +3V, depending on the data written to the line being written.

[0086] The drain potential of the write transistor WTr(n,m) is connected to the read word line Pn and the Since the connection is made via a capacitor C(n,m), the fluctuation in the potential of the read word line Pn ( That is, a rise of 3V occurs due to a rise from 0V in FIG. 4(A) to +3V in FIG. 4(B). That is, depending on the data written, it will be +3V, +4V, +5V, or +6V. value.

[0087] In this state, the source (bit line Rm) of the write transistor WTr(n,m) The potential of the drain of the write transistor WTr(n,m) (0 to +3V) The gate potential (-3V) of the write transistor WTr(n,m) is higher than the Since it is low, the write transistor WTr(n,m) is turned off.

[0088] Furthermore, the source of the read transistor RTr(n,m) (i.e., the bit line Rm) The potential (0 to +3V) and the drain (i.e. That is, the potential of the read transistor RTr(n,m) is higher than the potential (0V) of the bias line Sn. Because the gate potential (+3 to +6 V) is high, the read transistor RTr(n, m) is off. It becomes Hu.

[0089] Next, the read operation will be described. As shown in FIG. 4(C), the write word line Qn and The potential of the bias line Sn is set to −3 V. The potential of the read word line Pn is set to 0 V. In this state, the drain potential of the write transistor WTr(n,m) is Depending on the data input, the voltage of the bit line Rm can be 0V, +1V, +2V, or +3V. If the potential is between -3V and 0V, the write transistor WTr(n,m) The transistors RTr(n,m) are both off. That is, for the rows that are not read out, In this way, the write transistor and the read transistor are turned off.

[0090] On the other hand, for the row to be read, the potential of the read word line Pn is set to -3V. The potential of the gate of the read transistor RTr(n,m) is changed according to the written data. Depending on the bit line Rm, the potential is either -3V, -2V, -1V, or 0V. At this time, if the potential of the bias line Sn is -3V, the read transistor RTr(n,m) is off.

[0091] However, as shown in FIG. 4(D), when the potential of the bias line Sn becomes −2V, the read If the gate potential of the transistor RTr(n,m) is -3V, the read transistor R Tr(n,m) is in the on state.

[0092] When the read transistor RTr(n,m) is turned on, a voltage is applied to the bit line Rm. By detecting this current, the read transistor RTr(n,m) It can be seen that the terminal of the bit line Rm is in an on state. If so, the initial potential (-3V) approaches the potential of the bias line Sn, so again, It can be seen that the read transistor RTr(n,m) is in the on state.

[0093] Similarly, as shown in FIG. 4(E), when the potential of the bias line Sn becomes −1 V, the read When the gate potential of transistor RTr(n,m) is -3V and -2V, the read The transistor RTr(n,m) is turned on.

[0094] Also, as shown in FIG. 4(F), when the potential of the bias line Sn becomes 0V, the readout transistor When the gate potential of the transistor RTr(n,m) is -3V, -2V, and -1V, The output transistor RTr(n,m) is turned on.

[0095] Even if the potential of the bias line is set to 0V, the readout transistor RTr(n,m) remains off. In this case, the gate potential of the read transistor RTr(n,m) was 0V. It can be measured.

[0096] In this way, four levels of data (2 bits) can be written and read. In this way, more data, for example, 8-level data (3 bits), 16-level data, The 4-bit data can be written and read.

[0097] In the above explanation, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are The capacitance of the buffer C(n,m) was ignored, but in real memory cells, these are taken into account. It is necessary to determine the potential to be applied.

[0098] The gate capacitance of the read transistor RTr(n,m) changes significantly between the on and off states. Since the read transistor RTr(n,m) is driven by the The capacitance of the capacitor C(n,m) of the gate capacitance of the read transistor RTr(n,m) The larger the ratio to the capacitor C(n,m ) should be at least twice the gate capacitance of the read transistor RTr(n,m). .

[0099] In addition, by setting the charge amount held in the memory cell to multiple levels, multi-level data (multi-value In order to store the data, it is necessary that the variation in the amount of charge held is small. The semiconductor memory circuit and the semiconductor memory device shown in the embodiment are capable of increasing the amount of charge held. Since the fluctuation is small, it is suitable for this purpose.

[0100] (Embodiment 2) In this embodiment mode, the writing method and reading method for the semiconductor memory device shown in the first embodiment will be described. The timing of the signals given to the various wirings will be explained. The method will be explained with reference to FIG.

[0101] As described in the first embodiment, the bit lines ( , Rm-1, Rm, Rm+1, . . . ) A signal corresponding to the data is applied to the bit line. Here, the potential of the bit line is set to be higher than VRM and lower than VRH. In addition, the write word line (e.g., Qn) of a row of the memory cell to be written In the same row, a signal is sequentially applied to turn on the write transistor. The read word line (e.g., Pn) and bias line (e.g., Sn) of A signal is given so that the write word line potential becomes the appropriate potential. The potential of the read word line is VPM, and the potential of the bias line is VSM.

[0102] On the other hand, the write word lines of the other rows are connected to the write transistors so that the write transistors are turned off. A signal is applied, and the read word line and bias line are each at an appropriate potential. At this time, the potential of the write word line is VQL, and the potential of the read word line is VQL. The potential of the bias line is VPM, and the potential of the bias line is VSH.

[0103] Here, in order to turn off the read transistor, the potential VPH of the read word line is , (VPM+(VRH-VRM)) or more, and the bias line potential VSH is , (VRM+(VPH-VPM)) or less. For example, the potential of the bit line However, if you take the four values ​​of VRM, VRM+α, VRM+2α, and VRM+3α (α>0), Then, VRH=VRM+3α, so the potential VPH of the read word line is (VP M+3α) or more is preferred.

[0104] In the first embodiment, VRM=0[V], α=1[V], VPM=0[V], VSM=0[ V, VPH=+3[V], and VSH=0[V], and the above conditions are satisfied. In 1, the bias line potential (VSM, VSH) is always held at 0V during writing. (i.e. VSM=VSH=0), but data is written to the row and not written to the row. The amount of the charge may vary depending on whether the charge is in a normal state or not.

[0105] The timing chart of the signals considering the above is shown in Figure 2. n-1, Qn, Qn+1), bit lines (Rm-1, Rm, Rm+1), read word lines An example of a pulse applied to (Pn-1, Pn, Pn+1) is shown below. The pulse height and amplitude are The duration of the pulse is determined by considering the characteristics of the write transistor. It is enough to set it.

[0106] In the figure, the pulses applied to the write word lines (Qn-1, Qn, Qn+1) do not overlap. However, for example, the time when a pulse is applied to the write word line Qn-1 is Part of the time may overlap with the time when the pulse is applied to the write word line Qn. must be equal to or lower than the threshold voltage of the write transistor. In the first embodiment, VQH must be greater than or equal to the threshold voltage of the write transistor. In the first embodiment, it is set to +4 volts. However, it can take other values. It is possible.

[0107] The signal applied to the bit lines (Rm-1, Rm, Rm+1) consists of multiple pulses. The height can be various. Here, VRM, VRM+α, VRM+2α, These pulses are the pulses of the write word line. Instead of being perfectly synchronized with the write word line, the write word line pulse starts and runs for a fixed time (τ 1), and it is preferable to start after the write word line pulse has ended. Then, it is preferable to wait a certain time (τ2) and then terminate the process. Here, τ1<τ2. Alternatively, τ1>τ2 may be used, but in terms of circuit design, it is preferable to set τ1=τ2. I wish.

[0108] The pulses applied to the read word lines (Pn-1, Pn, Pn+1) are also the same as the pulses applied to the write word lines (Pn-1, Pn, Pn+1). The write transistor should be synchronized with the pulse applied to the write line or delayed slightly. In order to reliably set the potential of the drain of the transistor to the set value, the read word line (Pn- The pulse applied to the write word line of the same row (Pn, Pn+1) is the same as the pulse applied to the write word line of the same row. It is preferable that the process is terminated after a certain period of time has elapsed after the process is terminated.

[0109] In this manner, the drain potential of the write transistor of each memory cell is determined. The amount of charge generated at the drain of each write transistor is determined by the potential of , the charge amounts corresponding to the potentials VRL, VRL+α, VRL+2α, and VRL+3α, respectively. , Q0, Q1, Q2, Q3, the charge amount of each memory cell is as shown in Table 1. The transistors used are those with low leakage current between the source and drain in the off state. By this, these charges are released after the power supply to the semiconductor memory device is stopped. The temperature can also be maintained for a fairly long period of time (10 hours or more).

[0110] [Table 1]

[0111] Next, the read method will be described with reference to Figs. 3(A) and (B). As shown in FIG. 3B, the bit line At the end of Rm, a capacitor 13, a means 11 for measuring the potential of the electrodes of the capacitor 13, Means 12 for applying a potential to a capacitor 13 and a switch 14 are provided.

[0112] First, the switch 14 is turned on, and the means 12 for applying a potential to the capacitor 13 is operated as follows: The potential of the electrode (upper side of the figure) of the capacitor 13 on the memory cell side (i.e., the potential of the bit line Rm ) is set to a certain potential VRL. Then, the switch 14 is turned off. If the potential of the bit line Rm fluctuates for some reason, the potential of the capacitor electrode is measured. When the series of operations is completed, the bit line The potential of Rm is VRL.

[0113] In the row where reading is performed, the read transistor is turned on by the potential of the bias line. For example, as shown in FIG. 3A, the bias line Sn-1 , Sn, and Sn+1 are input with pulses of three different heights (VS1, VS2, VS3) in sequence.

[0114] As is apparent from the description of the first embodiment with reference to FIGS. Then, the read transistor is turned on according to the potential of the gate of the read transistor and the potential of the bias line. The transistor can be in the ON or OFF state. Here, a pulse of height VS1 When the charge held in the readout transistor is Q0, the readout transistor turns on and a pulse of height VS2 is generated. In this case, the read transistor is turned on when the charge stored in the memory cell is Q0 or Q1. In the case of a pulse with a height of VS3, the charges stored in the memory cells are Q0, Q1, and Q2. In this case, the read transistor is turned on.

[0115] When the read transistor is turned on, the potential of the bit line approaches the potential of the bias line. This change is measured by the means 1 for measuring the potential of the capacitor electrodes shown in FIG. By measuring at 1, it is possible to observe whether the read transistor is turned on or not.

[0116] For example, when three pulses with different heights are applied to the same memory cell, If the charge held by the capacitor is Q0, then the potential of the capacitor will rise in response to pulses of all heights. fluctuates. In other words, three pulses are observed.

[0117] However, if the charge held in that memory cell is Q1, it will not respond to the lowest pulse. Since the detector responds to the remaining two pulses, two pulses are observed. If the charge held in the cell is Q2, it will respond only to the highest pulse, so it will If a pulse is observed and the charge held in the memory cell is Q3, then for any pulse No response, no pulse observed.

[0118] In this way, by recording how many times a pulse occurs for each memory cell, For example, in FIG. 3(A), the (n+1)th line, The memory cells in the (m-1)th column generate a pulse three times in a series of readouts. This is because the charge held was Q0, and all the charges applied to the bias line Sn In response to the pulse, it is turned on, and the potential of the bit line Rm becomes the same as the potential of the bias line Sn. Or it was close to that value.

[0119] Conversely, the memory cell in the nth row and mth column did not generate a pulse even once. Since the charge of Q3 was the largest, it did not turn on even with the highest VS3 pulse. In this way, the pulses emitted by each memory cell are compiled as shown in Table 2. In this manner, the data stored in each memory cell can be read out. In the above example, we have shown how to read data row by row. It is also possible to read out only the data in a particular memory cell.

[0120] [Table 2]

[0121] In addition, the amount of charge held in the memory cell can be known by the number of pulses generated as described above. In addition, it is also possible to directly measure the voltage. For example, as shown in Figure 3(C), If the potential of the word line Pn is -3V and the potential of the write word line Qn is -3V, The transistor WTr(n,m) is in an off state, and the read transistor RTr(n,m The potential of the gate of the transistor 11 is between -3V and 0V.

[0122] The capacitor 13 shown in FIG. 3B is connected to the end of the bit line Rm. Assume that the potential is 0 V. Also, assume that the potential of the bias line Sn is initially 0 V. In this state, the gate potential of the read transistor RTr(n,m) is -3V, -2 If V, -1V, the read transistor RTr(n,m) is in the on state, but the source Since the potentials of the read transistor RTr and the drain are equal, no current flows. If the gate potential of (n,m) is 0V, the read transistor RTr(n,m) is off. It is in a non-operational state.

[0123] Next, when the potential of the bias line Sn is lowered to −3 V, the read transistor RTr(n, When the potential of the gate of the read transistor RTr(n,m) is other than 0V, However, since the bit line Rm is terminated at the capacitor 13, a current flows between the source and drain. Then, when the potential of the bit line Rm reaches a certain value, the current stops flowing.

[0124] For example, if the gate potential of the read transistor RTr(n,m) is −2V, When the potential of the bit line Rm becomes -1V, In the second stage, the gate potential (-2V) of the read transistor RTr(n,m) is Since the voltage is 1V lower than the potential (-1V), the read transistor RTr(n,m) is in the on state. However, when the potential of the bit line Rm further decreases, the read transistor RTr( n,m) gate potential (-2V) and source potential (less than -1V at the potential of bit line Rm) Since the difference between the bit line Rm and the bit line Rm is less than 1V, the bit line Rm is turned off. First, the potential of the bit line Rm remains substantially constant.

[0125] In this case, the potential of the bit line Rm is lower than -1V, but the read transaction is completed before it drops to -2V. Since the transistor RTr(n,m) is turned off, the potential of the bit line Rm is -2V or more and less than -1V. At this time, the potential of the bit line Rm is measured by the potential measuring means 11 shown in FIG. That is, if the potential of the bit line Rm is -2V or more and less than -1V, the read It can be inferred that the gate potential of the output transistor RTr(n,m) was -2V. From this, the data written in this memory cell can be known.

[0126] Similarly, if the gate potential of the read transistor RTr(n,m) is -3V or -1V, For example, the potential of the bit line Rm is −3 V or more and less than −2 V, and −1 V or more and less than 0 V. If the gate potential of the read transistor RTr(n,m) is 0V, Since the transistor RTr(n,m) remains in the off state, the potential of the bit line Rm does not change from 0V. Even in this way, the amount of charge at the time of writing can be known.

[0127] (Embodiment 3) In this embodiment mode, the shape and manufacturing method of the semiconductor memory device described in the first and second embodiments will be described. In this embodiment, the write transistor WTr is made of zinc and insulator. The read transistor RTr is a single-crystal silicon-containing oxide semiconductor. A silicon semiconductor is used. Therefore, the write transistor WTr is the read transistor It is laminated on top of the RTr.

[0128] That is, an insulated gate using a single crystal silicon semiconductor provided on a single crystal silicon substrate The type transistor is the readout transistor RTr, and a transistor using an oxide semiconductor is placed on top of it. A transistor is formed and used as the write transistor WTr. Although an example of forming a semiconductor memory device on a single crystal silicon substrate will be described below, other It is also possible to provide it on a substrate.

[0129] FIG. 7 shows an example of the layout of a memory cell in the semiconductor memory device of this embodiment. The main wiring and electrodes on a single crystal silicon substrate are shown. 02 is formed on the substrate. A conductive material or a conductive layer using doped silicon is formed on the substrate. Regions 106a and 106b are formed, a part of which is the source of the read transistor RTr, A part of the conductive region 106b serves as a bias line. 106b is separated by a read gate 110 of the read transistor RTr. A first connection electrode 111 is provided on the conductive region 106a.

[0130] FIG. 7B shows a transistor using an oxide semiconductor formed on the circuit in FIG. The main wiring and electrodes are shown in the center. The island-shaped oxide semiconductor region 112 and the first wiring 114 Here, the first wiring 114a is a write word line, and the first wiring 114b is a A part of the first wiring 114a is connected to the oxide semiconductor region 112. The oxide semiconductor region 1 is overlapped with the gate electrode of the write transistor WTr. The first wiring 114b is connected to the read gate 110 in the lower layer. A capacitor is formed in the overlapping portion with the oxide semiconductor region 110. 2 to an upper layer (e.g., a bit line). .

[0131] The read gate 110 is formed in ohmic contact with an oxide semiconductor to be formed later. Such a material is preferably a material having a work function W smaller than the electron affinity of the oxide semiconductor. Material with φ (energy difference between the lower limit of the conduction band of an oxide semiconductor and the vacuum level) that is approximately the same as or smaller than this In other words, the relationship W<φ+0.3 [electron volts] must be satisfied. For example, Examples include titanium, molybdenum, and titanium nitride.

[0132] When Figures 7(A) and (B) are superimposed, it becomes as shown in Figure 7(C). The layers are intentionally slightly offset so that the structure can be seen. Also shown is a second interconnect 118 (eg, a bit line) formed over the transistor.

[0133] In addition, points A and B in Figures 7(A) to 7(C) indicate the same position. The designer can choose the design rules as appropriate, but in terms of increasing the degree of integration, The channel width of the sta is 10 nm to 0.1 μm, and the channel length is 10 nm to 0.1 μm. It is preferable to set it as follows.

[0134] A method for manufacturing a semiconductor memory device having the above structure will be described below. 7 is a cross section connecting points A and B of the semiconductor device 7. In this embodiment, n-type single crystal silicon is used as the substrate. A p-type single crystal silicon substrate is used, but an n-type well is formed on the p-type single crystal silicon substrate, and the The manufacturing process will be described below according to the numbers in the drawings. do.

[0135] <Fig.8(A)> First, using a known semiconductor manufacturing technique, a semiconductor device as shown in FIG. As shown in FIG. 1, the element isolation region 102 is a conductive layer made of p-type doped silicon or the like. The insulating film 103 is a first insulating film made of a dummy gate 104. In FIG. 8A, two dummy gates 104 are shown. As is clear from FIG. 7, these are continuous.

[0136] A sidewall may be provided on the side surface of the dummy gate 104 as shown in FIG. The dummy gate 104 is preferably made of polycrystalline silicon. The thickness of 3 is preferably 10 nm or more in order to suppress leakage current. In order to make the gate capacitance smaller than the capacitance of the capacitor to be formed later, the first gate It is preferable to use a material having a relatively low dielectric constant, such as silicon oxide, as the dielectric material of the insulating film 103. It is.

[0137] The conductive regions 106a and 106b have silicide regions 105a and 105b formed on their surfaces. In addition, as described in relation to FIG. 7(A), The conductive region 106b becomes part of the bias line.

[0138] The first interlayer insulator 107 may be a single layer or a multilayer. The top layer may include a stress liner to provide a If the first interlayer insulating film 107 is made flat, it is advantageous in the subsequent steps. As a result, a silicon nitride film was formed by plasma CVD, and then a silicon nitride film was formed by spin coating. Alternatively, a multi-layer film having a flat silicon oxide film obtained by the above method may be used.

[0139] <Fig.8(B)> When the surface of the first interlayer insulator 107 is sufficiently flat, the first interlayer insulator 107 can be etched by dry etching. The first interlayer insulator 107 is etched, and when the top surface of the dummy gate 104 is exposed, the dry Stop etching. Use chemical mechanical polishing (CMP) instead of dry etching. Alternatively, the surface of the first interlayer insulator 107 may be planarized by a CMP method first, and then the surface may be planarized by a dry etching method. Alternatively, the etching may be further carried out by a dry etching method. After etching the interlayer insulating film to a certain extent, the film may be planarized by the CMP method. Thus, a first interlayer insulator 107a having a flat surface is obtained.

[0140] <Fig.8(C)> Next, the dummy gate 104 is selectively etched to form an opening 108. When polysilicon is used as the material for the gate 104, 2 to 40% is preferred. Alternatively, 20 to 25% TMAH (tetramethylammonium hydroxide) may be used. In addition, the first interlayer insulator 107a having a flat surface is etched to the silicide region 105a. An opening 109 is also formed.

[0141] <Fig.8(D)> A single layer or multiple layers of conductive material are deposited. The conductive material is the oxide that is subsequently formed. The conductive film is preferably made of a material that forms an ohmic contact with the semiconductor. Since it is also the gate electrode of a transistor (here, a P-channel type), it determines its threshold voltage. In terms of the material properties, it is preferable to use one that has appropriate physical properties such as work function. If the requirements cannot be met, a multi-layer film can be used to satisfy each of the requirements. For example, a multilayer film of titanium nitride and tantalum nitride may be used as the conductive material.

[0142] Next, the conductive material film is etched while being planarized by the CMP method. It is advisable to stop the process when the first interlayer insulator 107a having a surface appears. As shown in FIG. 1, a read gate 110 of the read transistor and a first connection electrode 111 are Thereafter, the first interlayer insulating film 107a having a flat surface is formed in the vicinity of the surface of the first interlayer insulating film 107a. To reduce hydrogen, the surface is treated with a fluorine-containing plasma. If the hydrogen concentration in the first interlayer insulator 107a is sufficiently low, this treatment is not necessary. Hydrogen concentration in a region 100 nm from the surface of the first interlayer insulator 107a having a flat surface is 1×10 18 cm -3 Less than 1 x 10 16 cm -3 It is advisable to set it to less than 100%.

[0143] <Fig.9(A)> An oxide semiconductor film having a thickness of 3 to 30 nm is formed by a sputtering method. The method for forming the oxide semiconductor may be other than the sputtering method. The oxide semiconductor preferably contains gallium and indium. In order to improve the reliability of the semiconductor memory device, the hydrogen concentration in the oxide semiconductor film is preferably 1×10 18 cm -3 Less than 1 x 10 16 cm -3 It is advisable to set it to less than 100%.

[0144] The oxide semiconductor film is etched to form an island-shaped oxide semiconductor region 112. In order to improve the characteristics, the oxide semiconductor region 112 may be subjected to heat treatment. The first gate 110, the oxide semiconductor region 112, the first connection electrode 111, and the oxide semiconductor region A structure in which 112 contacts is obtained.

[0145] Thereafter, the second gate insulating film 113 is formed by a known film forming method such as a sputtering method. In order to reduce the current, the thickness of the second gate insulating film 113 is preferably 10 nm or more. The hydrogen concentration in the gate insulating film is 1×10 -18 cm -3 Less than 1 x 10 16 cm -3 It is advisable to set it to less than 100%.

[0146] The gate insulating film may be made of silicon oxide, aluminum oxide, hafnium oxide, lanthanum oxide, It is preferable to use aluminum nitride, etc. Not only a single layer film but also a multilayer film of these may be used. The second gate insulating film 113 is a gate insulating film formed by the read gate 110 and the first wiring 114b. It is also the dielectric of the capacitor, and the capacitance of the capacitor is read out and calculated from the gate capacitance of the transistor. In order to increase the dielectric constant, it is preferable to use a material having a relative dielectric constant of 10 or more. After the formation, the oxide semiconductor region 112 may be subjected to heat treatment in order to improve characteristics of the oxide semiconductor region 112 .

[0147] <Fig.9(B)> The first wiring 114a (write word line) and the first wiring 114b (read A part of the first wiring 114a is a transistor using an oxide semiconductor. The first wirings 114a and 114b are made of a material having a work function of oxide. A material with an electron affinity 0.5 eV or higher than that of the semiconductor is preferred. For example, tungsten These include silicon, gold, platinum, and p-type silicon.

[0148] Between the read gate 110 and the first wiring 114b, a second gate insulating film 113 is provided as a dielectric. The capacitance of this capacitor is determined by the read gate 110 and the first wiring 114b, the area of ​​the overlap is 100 nm 2 More than 0.01 μm 2 It is preferable that:

[0149] In FIG. 9B, one end of the first connection electrode 111 and the gate electrode of the write transistor are One end of the first wiring 114a, and one end of the read gate 110 and the other end of the first wiring 114a The edges are shown to coincide exactly. However, in reality, the accuracy of the mask alignment is important. Depending on the angle, the first wiring 114a may be on the left side (first connection electrode 111 side) or the right side (reading In that case, the first distribution may be shifted toward the opposite side of the shifted side. The line 114a and either the first connection electrode 111 or the read gate 110 Since an offset state occurs between the transistor and the on-state transistor, the resistance of the transistor increases.

[0150] To prevent this, the width of the first wiring 114a is increased so that the wiring can overlap even with a slight misalignment. However, the first wiring 114a and the first connection electrode 111 and the read gate 11 This creates a parasitic capacitance with 0, which is disadvantageous for high-speed operation. Making it larger also goes against shrinking design rules.

[0151] In order to solve these problems, the oxide semiconductor region is masked with the first wiring 114a. It is sufficient to form an n-type region in a self-aligned manner. To do this, a known ion implantation method is used. In this case, ions of an element that is more easily oxidized than an oxide semiconductor are implanted. , titanium, zinc, magnesium, silicon, phosphorus, boron, etc. In general, boron and Phosphorus is readily available since it is used in conventional semiconductor processes, and is particularly useful for In order to implant such a thin second gate insulating film 113 and oxide semiconductor region 112, it is necessary to use ions other than boron. Phosphorus, which has a large atomic weight, is preferred.

[0152] It is desirable to have as few hydrogen atoms as possible in these ions. The hydrogen concentration is preferably 0.1% or less. Hydrogen acts as a donor for the oxide semiconductor. It is known that when hydrogen is contained in the ions, the hydrogen injected into the oxide semiconductor They migrate through the oxide semiconductor and reduce the reliability of the element.

[0153] In the oxide semiconductor, the injected ions combine with oxygen, causing oxygen vacancies and resulting in n-type The difference with silicon semiconductors is that silicon semiconductors are not implanted with ions. After that, heat treatment is required to restore the crystallinity. The advantage of this method is that it is possible to obtain high electrical conductivity without carrying out such heat treatment.

[0154] Thus, the oxide semiconductor region 112 includes regions 115a and 115b each exhibiting n-type conductivity. The carrier (electron) concentration in these regions is 1×10 -19 cm -3 That's all. It is preferable to set the ion implantation conditions so that the basic element structure is completed. do.

[0155] <Fig.9(C)> Thereafter, a second interlayer insulator 116 made of a single-layer or multi-layer thin film is formed. The surface of the semiconductor substrate is planarized to form a contact hole that reaches the region 115a exhibiting n-type conductivity. Then, the second connection electrode 117 is buried. After that, the second wiring 118 (bit line) is formed. Similar wiring may be formed in parallel to the first wirings 114a and 114b. As shown in FIG. 1C, a write transistor 119, a read transistor 120, A storage cell of a semiconductor memory device having a capacitor 121 is fabricated.

[0156] (Embodiment 4) In this embodiment, an example of the semiconductor memory device shown in FIG. 5 will be described with reference to FIG. In this embodiment, the write transistor WTr contains gallium and indium. The read transistor RTr is made of a single-crystal silicon semiconductor. Therefore, the write transistor WTr is stacked on top of the read transistor RTr. The layers are provided.

[0157] That is, an insulated gate using a single crystal silicon semiconductor provided on a single crystal silicon substrate The type transistor is the readout transistor RTr, and a transistor using an oxide semiconductor is placed on top of it. A transistor is formed and used as the write transistor WTr. Now, let us explain an example in which a single crystal silicon semiconductor is used as the read transistor RTr. However, other semiconductors can also be used.

[0158] FIG. 10 shows an example of the layout of memory cells in the semiconductor memory device of this embodiment. ) shows the main wiring, electrodes, etc. provided on the single crystal silicon substrate. In FIG. 10(A), The areas 200a and 200b enclosed by dotted lines are occupied by one memory cell each. For example, the area 200a is the occupancy of the memory cell in the (2n-1)th row and the mth column of FIG. 5. The region 200b corresponds to the region occupied by the memory cell in the 2nth row and the mth column of FIG. Correct.

[0159] An element isolation region 202 is formed on the substrate. In addition, a conductive material or a doped material is formed on the substrate. The etched silicon is used to form the conductive regions 206a, 206b. The drain and source of the transistor RTr are connected to the conductive region 206a. are bias lines (··, Sn, Sn+1,··). The conductive regions 206a and 206b are The conductive region 206b is separated by a read gate 210. A first connection electrode 211 is provided in the conductive region 206b. A wiring is provided to connect to the circuit on the upper layer.

[0160] FIG. 10B shows a transistor using an oxide semiconductor formed on the circuit of FIG. 10A. The figure shows the main wiring and electrodes, etc., centered on the oxide semiconductor region 212 and the conductive material. The material forms the first wiring 214. The first wiring 214 is, for example, line (··, Q2n-1, Q2n, Q2n+1,··), read word line (··, P2n -1, P2n, P2n+1, ··).

[0161] A part of the write word line overlaps with the oxide semiconductor region 212 to form a write transistor W The oxide semiconductor region 212 serves as the gate electrode of the transistor Tr. 0. The read word line is connected to the read gate 210 at the overlapping portion. Forms a capacitor.

[0162] The oxide semiconductor region 212 is connected to the read transistor RTr by the first connection electrode 211. The oxide semiconductor region 212 is connected to the source (conductive region 206b) of the A second connection electrode 217 is provided for connection to a bit line. is provided at the same position as the first connection electrode 211 that connects the lower layer and the oxide semiconductor region 212, This is preferable in terms of reducing the area of ​​the memory cell.

[0163] When Figures 10(A) and (B) are superimposed, it becomes as shown in Figure 10(C). Here, The overlapping is intentionally slightly shifted so that the overlapping can be seen. Also shown is a second interconnect 218 made of conductive material formed over the previously formed transistor. The second wiring 218 becomes the bit line (··, Rm−1, Rm, Rm+1, ··), and the second connection A connection electrode 217 is connected to the oxide semiconductor region 212 .

[0164] The semiconductor memory device having the above structure can be manufactured by using the method shown in the third embodiment. good.

[0165] (Embodiment 5) In this embodiment, the semiconductor device shown in FIGS. 1(A) and (B) is fabricated in a manner different from that of the first embodiment. An example of operating the whole memory circuit will be described with reference to FIG. 11. The specific values ​​are given below for the purpose of aiding understanding of the technical concept of the present invention. Needless to say, these values ​​depend on various characteristics of transistors, capacitors, etc. The schedule may be changed at the discretion of the project owner or the project implementer.

[0166] Here, the write transistor WTr(n,m) is an N-channel type, and the read transistor The write transistor RTr(n,m) is a P-channel type. The write transistor WTr(n,m) is When the gate potential becomes 1V higher than either the source or drain potential, The read transistor RTr(n ,m) The gate potential is 1 V or more higher than either the source or drain potential. When it is low it is on, otherwise it is off.

[0167] In addition, the gate capacitance of the read transistor RTr(n,m) is determined by the gate bias. The amount of fluctuation due to the change can be ignored compared to the capacitance of the capacitor C(n,m). , the parasitic capacitance of the write transistor WTr(n,m) and the parasitic capacitance of the read transistor RTr(n ,m) and other capacitances not shown in the figure, such as the parasitic capacitance between wiring, are all assumed to be 0. And think about it.

[0168] In addition, in FIG. 11, transistors in the on state are marked with a circle, and transistors in the off state are marked with a A switch is written with a cross over the symbol. Switches that turn on under certain conditions are listed separately. This may also be indicated in the drawings.

[0169] <Figure 11(A)> (Writing to the nth line) In the write operation, as shown in FIG. 11(A), the read word line Pn and the bias line Sn The potential of the bit line Rm is set to 0 V. The potential of the bit line Rm is set to 0 V, +1 The voltage of the write word line Qn is set to four levels: V, +2V, and +3V. When the potential is set to +4V, the write transistor WTr(n,m) turns on and the write The drain potential of the transistor WTr(n,m) is the source potential of the write transistor (i.e. In this case, the potential of the bit line Rm approaches that of the bit line Rm. Let us assume that.

[0170] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is It is equal to the drain potential of the read transistor WTr(n,m). The potential of the gate of the read transistor RTr(n,m) is 0V or higher. n, m) (i.e., the potential of bit line Rm).

[0171] Also, the drain of the read transistor RTr(n,m) (i.e., the bias line Sn) The potential at the gate of the read transistor RTr(n,m) is 0V. Since the potential is the same as or higher than the source and drain potentials, the read transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0172] <Figure 11(B)> (Writing on a line other than the nth line) Next, when writing to a line other than the nth line, the writing is performed as shown in FIG. The potential of the write word line Qn is set to 0 V. The potential of the read word line Pn is set to +3 V. The potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm is set to It can take on four values: 0V, +1V, +2V, or +3V, depending on the data written to the line being written.

[0173] The drain potential of the write transistor WTr(n,m) is connected to the read word line Pn and the Since the connection is made via a capacitor C(n,m), the fluctuation in the potential of the read word line Pn ( That is, the voltage rises by 3V from 0V in Figure 11(A) to +3V in Figure 11(B). That is, depending on the data written, it can be +3V, +4V, +5V, or +6V. The value will be:

[0174] In this state, the source (bit line Rm) of the write transistor WTr(n,m) The potential of the drain of the write transistor WTr(n,m) (0 to +3V) Since the potential of the gate of the write transistor WTr(n,m) is lower than The write transistor WTr(n,m) is turned off.

[0175] Furthermore, the potential (0 to +3V) and the potential of the drain (bias line Sn) of the read transistor RTr(n,m) Since the potential of the gate of the read transistor RTr(n,m) is higher than (0V), The read transistor RTr(n,m) is turned off.

[0176] <Figure 11(C)> (Reading) Next, the read operation will be described. As shown in FIG. 11C, the write word line Qn The potential of the read word line Pn and the bias line Sn is set to +3 V. In this state, the drain potential of the write transistor WTr(n,m) is Depending on the data written, the bit line will be +3V, +4V, +5V, or +6V. If the potential of Rm is between 0V and +3V, the write transistor WTr(n,m) The read transistors RTr(n,m) are both off. In this way, the write transistor and the read transistor are turned off.

[0177] <Figure 11(D)> (Reading) On the other hand, for the row to be read out, the potential of the bias line Sn is made higher than +3 volts. For example, as shown in FIG. 11(D), when the potential of the bias line Sn is +4V, If the gate potential of the read transistor RTr(n,m) is +3V, then the read transistor RT r(n,m) is turned on.

[0178] If the bit line potential is set to +3V in advance, a current will flow through the bit line Rm, By detecting this, it is possible to determine whether the read transistor RTr(n,m) is in an on state. Or, if the bit line Rm is terminated with a capacitor, Since the potential of the bias line Sn approaches the potential of the read transistor RTr(n,m), You can know that the device is in a down state.

[0179] <Figure 11(E)> (Reading) Similarly, as shown in FIG. 11(E), when the potential of the bias line Sn becomes +5V, If the gate potential of the transistor RTr(n,m) is +3V and +4V, the read transistor The transistor RTr(n,m) is turned on.

[0180] <Figure 11(F)> (Read) Also, as shown in FIG. 11(F), when the potential of the bias line Sn becomes +6V, the read If the gate potentials of transistors RTr(n,m) are +3V, +4V, and +5V, then the reading The output transistor RTr(n,m) is turned on.

[0181] Even if the potential of the bias line Sn is set to +6V, the read transistor RTr(n,m) remains off. If this is the case, the drain potential of the write transistor WTr(n,m) (=read It can be inferred that the gate potential of transistor RTr(n,m) was +6V.

[0182] In this way, four levels of data (2 bits) can be written and read. In this way, more data, for example, 8-level data (3 bits), 16-level data, In this embodiment, as described above, Writing and reading can be done using only positive potentials.

[0183] In the above explanation, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are The capacitance of the buffer C(n,m) was ignored, but in real memory cells, these are taken into account. The gate potential of the read transistor RTr(n,m) must be determined. Since the capacitance of the read transistor RTr(n The gate potential of the read transistor RTr(n,m) is affected. The greater the ratio of the port capacitance to the capacitance of the capacitor C(n,m), the greater the effect. Therefore, preferably, the capacitance of the capacitor C(n,m) is set to the capacitance of the read transistor RTr(n, m) or more.

[0184] (Embodiment 6) In this embodiment, an example of operating the semiconductor memory circuit shown in FIG. 5 will be described with reference to FIGS. This will be explained with reference to FIG. 13. Here, the write transistor WTr(2n-1,m) and and WTr(2n,m) are N-channel type, read transistors RTr(2n-1,m) and and RTr(2n,m) are P-channel types.

[0185] The write transistors WTr(2n-1,m) and WTr(2n,m) have a gate potential of When the potential of either the source or drain becomes 1 V or more higher, the transistor turns on. , otherwise it is off. Also, the read transistor RTr(2n-1,m), RTr(2n,m) is the gate potential that is either the source or the drain potential. It turns on when it is 1V or more lower than this, and it is off otherwise.

[0186] In addition, the gate capacitance of the read transistors RTr(2n-1,m) and RTr(2n,m) The amount that varies with the gate bias is insignificant compared to the capacitance of the capacitor C(n,m). In addition, the write transistors WTr(2n-1,m), WTr( 2n,m) and the parasitic capacitance of the read transistors RTr(2n-1,m) and RTr(2n, m) parasitic capacitance, other capacitances not shown in the figure, such as the parasitic capacitance between wiring, are all set to 0. I think.

[0187] In addition, in Fig. 12 and Fig. 13, transistors in the on state are marked with a circle, and transistors in the off state are marked with a circle. A transistor that is turned on under certain conditions is indicated by a cross over the symbol. may be described separately.

[0188] <Figure 12(A)> (Writing to the (2n-1)th line) When writing to the (2n-1)th row, as shown in FIG. 12(A), the read word line P 2n-1, the potential of the write word line Q2n, and the bias line Sn are set to 0V. The potential of the bit line P2n is set to +3V. The potential of the bit line Rm is set to The voltage can take four levels: 0V, +1V, +2V, and +3V. The drain potential of the write transistor WTr(2n,m) is set to +3V.

[0189] If the potential of the write word line Q2n-1 is set to +4V, the write transistor WTr(2n-1,m) turns on, and the write transistor WTr(2n-1,m) The potential of the drain is close to the potential of the source of the write transistor (i.e., bit line Rm). Here, it is assumed that the potential is equal to that of the bit line Rm.

[0190] On the other hand, at this stage, the potential of the gate of the read transistor RTr(2n-1,m) is The drain potential of the write transistor WTr(2n-1,m) is equal to the drain potential of the read transistor WTr(2n-1,m). The potential of the gate of the read-out transistor RTr(2n-1,m) is 0V or higher. The potential of the source of the transistor RTr(2n-1,m) (i.e., the bit line Rm) is the same as that of the be.

[0191] In addition, the drain of the read transistor RTr(2n-1,m) (i.e., the bias line Sn) is at 0V. Therefore, the potential of the read transistor RTr(2n-1,m) The gate potential of the read transistor R is equal to or higher than the source and drain potentials. Tr(2n-1,m) is in the off state.

[0192] Furthermore, the potential (0V) of the gate of the write transistor WTr(2n,m) is The potential of the drain (i.e., bit line Rm) (0V or more and +3V or less) and the potential of the drain (+3V ), the write transistor WTr(2n,m) is in the off state. The gate of the read transistor RTr(2n,m) (i.e., the gate of the write transistor W The potential (+3V) of the drain of Tr(2n,m) is m) (0V to +3V) and the drain potential (0V), so In this way, data can be written to the memory cells in the (2n-1)th row. can be done.

[0193] <Figure 12(B)> (Writing to the 2nth line) Next, when writing to the 2nth row, as shown in FIG. The potential of the read word line Q2n-1 and the read word line P2n is set to 0V. The potential of the word line P2n-1 is set to +3 V, and the potential of the bias line Sn is set to 0 V. The potential of the line Rm can be set to one of four values: 0V, +1V, +2V, or +3V, depending on the data to be written. Take.

[0194] The drain potential of the write transistor WTr(2n-1,m) is 2n-1 and capacitor C(2n-1,m) are connected, so the read word line The change in the potential of P2n-1 (i.e., from 0V in Figure 12(A) to +3V in Figure 12(B) This means that the voltage will rise by 3V, i.e. +3V, +4V depending on the data written. , +5V, or +6V.

[0195] If the potential of the write word line Q2n is set to +4V, the write transistor WT r(2n,m) turns on, and the drain voltage of the write transistor WTr(2n,m) The potential approaches that of the source of the write transistor (i.e., bit line Rm). is assumed to be equal to the potential of the bit line Rm.

[0196] On the other hand, at this stage, the potential of the gate of the read transistor RTr(2n,m) is The drain potential of the read transistor WTr(2n,m) is equal to the drain potential of the read transistor WTr(2n,m). The potential of the gate of the read transistor RTr(2n,m) is 0V or higher. This is the same as the potential of the source of Tr(2n,m) (that is, the bit line Rm).

[0197] In addition, the drain of the read transistor RTr(2n,m) (i.e., the bias line Sn ) is 0V. Therefore, the gate potential of the read transistor RTr(2n-1,m) The potential of the gate is the same as or higher than the potential of the source and drain, so the read transistor RTr (2n,m) is in the off state. Also, the write transistor WTr(2n-1,m), The read transistor RTr(2n-1,m) is also in an off state. Data can be written to n rows of memory cells.

[0198] <Figure 12(C)> (Writing on other lines) Next, when writing to a line other than the above, the write operation is performed as shown in FIG. 12(C). The potential of the read word lines Q2n-1 and Q2n is set to 0 V. 1. The potential of P2n is +3V, and the potential of the bias line Sn is 0V. On the other hand, The potential is set to 0V, +1V, +2V, or It has four values ​​from +3V to +3V.

[0199] The drain potential of the write transistor WTr(2n,m) is connected to the read word line P2n and the potential of the read word line P2n is (i.e., from 0V in Figure 12(B) to +3V in Figure 12(C)) V rises, i.e. +3V, +4V, +5V, +6V depending on the data written. The drain potential of the write transistor WTr(2n-1,m) is Similarly, the value can be +3V, +4V, +5V, or +6V.

[0200] In this state, the write transistors WTr(2n-1,m) and WTr(2n ,m) source (bit line Rm) potential (0 to +3V) and write transistor WTr( 2n-1,m) and WTr(2n,m) drain potential (+3 to +6V) Write transistor WTr(2n-1,m) and write transistor WTr(2n, m) has a low gate potential (0 V), so the write transistor WTr(2n-1, m) and WTr(2n,m) is turned off.

[0201] Furthermore, the sources of the read transistors RTr(2n-1,m) and RTr(2n,m) The potential (0 to +3V) of the bit line Rm and the read transistor RTr(2n-1,m ) and the drain of RTr(2n,m) (potential (0V) of bias line Sn), The potential of the gates of the read transistors RTr(2n-1,m) and RTr(2n,m) (+3 to +6V) is high, so the read transistor RTr(2n-1,m) and the read The output transistor RTr(2n,m) is turned off.

[0202] <Figure 13(A)> (Reading) Next, the read operation will be described. As shown in FIG. 13A, the read word line P2n The potentials of the write word lines Q2n-1, Q2n, and bias line Sn are set to 0V. The potential is set to -3 V. In this state, the read transistors RTr(2n-1,m) and R The gate potential of Tr(2n,m) is set to 0V, +1V, or +2V depending on the written data. It can be either +3V or +3V.

[0203] If the potential of the bit line Rm is between -3V and 0V, the write transistor WTr(2n -1,m), WTr(2n,m) readout transistor RTr(2n-1,m), RTr (2n,m) are both off. That is, for rows that are not to be read, The transistors in that row are turned off.

[0204] <Figure 13(B)> (Reading the 2nth row [1]) Next, the potential of the read word line P2n is set to -3 V, and the potential of the bit line Rm is set to -3 V. As a result, the potential of the gate of the read transistor RTr(2n,m) becomes equal to the Depending on the data, the voltage can be -3V, -2V, -1V, or 0V. Both the transistor WTr(2n,m) and the read transistor RTr(2n,m) are off. However, when the potential of the bias line Sn is changed, the read transistor RT r(2n,m) can be turned on. For example, as shown in FIG. When the potential of the bias line Sn becomes -2V, the gate of the read transistor RTr(2n,m) When the potential of the port is -3V, the read transistor RTr(2n,m) is turned on. do.

[0205] <Figure 13(C)> (Reading the 2nth row [2]) Similarly, as shown in FIG. 13(C), when the potential of the bias line Sn becomes −1 V, When the gate potential of the transistor RTr(2n,m) is -3V and -2V, the read The output transistor RTr(2n,m) turns on.

[0206] <Figure 13(D)> (Reading the 2nth row [3]) Also, as shown in FIG. 13(D), when the potential of the bias line Sn becomes 0V, the read When the gate potential of transistor RTr(2n,m) is -3V, -2V, and -1V, The read transistor RTr(2n,m) is turned on.

[0207] Even if the potential of the bias line Sn is set to 0V, the read transistor RTr(2n,m) is off. If this state remains the same, the potential of the gate of the read transistor RTr(2n,m) will be 0V. It can be inferred that this was the case.

[0208] Similarly, the data in the memory cell in the (2n-1)th row can be read out. We have shown an example of writing and reading four levels of data (2 bits), but in the same way, A lot of data, for example, 8-level data (3 bits), 16-level data (4 bits) In the above explanation, the parasitic capacitance and the read transistor RTr( The gate capacitance of the gate electrode (n,m) is ignored in relation to the capacitance of the capacitor C(n,m). In the memory cell, the potential to be applied must be determined taking these factors into consideration.

[0209] (Embodiment 7) In this embodiment, an example of operating the semiconductor memory circuit shown in FIGS. 6(A) and 6(B) will be described. The following will be described with reference to Figs. 14 and 15. The specific values ​​of the potential are as follows: The following are listed for the purpose of aiding understanding of the technical concept of the present invention. , their values ​​depend on various characteristics of transistors and capacitors, or on the implementer's It is subject to change according to circumstances.

[0210] Here, the write transistor WTr is an N-channel type, and the read transistor RTr is The write transistor WTr is a P-channel type. The gate potential is The transistor turns on when the potential on either side of the drain is 1V higher than the potential on the other side. The read transistor RTr is off. The gate potential is The transistor turns on when the potential of either the gate or drain is 1 V or more lower. is assumed to be off.

[0211] In addition, the gate capacitance of the read transistor RTr varies depending on the gate bias. The capacitance of the write transistor is negligible compared to the capacitance of the capacitor C. The parasitic capacitance of the WTr, the parasitic capacitance of the read transistor RTr, and other parasitic capacitances between wiring All capacities not shown in the figure, such as volume, are considered to be 0.

[0212] In addition, in Fig. 14 and Fig. 15, the transistors in the on state are marked with a circle, and the transistors in the off state are marked with a circle. A transistor that is turned on under certain conditions is indicated by a cross over the symbol. In the following description, the memory cell in the (n-1)th row and the mth column and the memory cell in the nth row and the mth column will be described separately. The description focuses on the storage cells of a column.

[0213] <Figure 14(A)> (Writing to the (n-1)th line) When writing to the memory cells in the (n-1)th row, as shown in FIG. The potential of the word line Pn-1 and the write word lines Qn and Qn+1 is set to 0V, and the potential of the read word line Pn The potential of Pn+1 is set to +4V. The potential of the bit line Rm is set to +4V according to the data to be written. The write trace can take four values: 0V, +1V, +2V, and +3V. The drain of the read transistor WTr(n,m) (i.e., the drain of the read transistor RTr(n,m) Assume that the potential of the gate of the transistor is initially between +4V and +7V.

[0214] If the potential of the write word line Qn-1 is set to +4V, the write transistor W Tr(n-1,m) turns on, and the drain of the write transistor WTr(n-1,m) The potential of the bit line approaches the potential of the source of the write transistor (ie, the bit line Rm). Here, it is assumed that the potential is equal to that of the bit line Rm.

[0215] On the other hand, at this stage, the gate potential of the read transistor RTr(n-1,m) is The drain potential of the read transistor WTr(n-1,m) is equal to the drain potential of the read transistor WTr(n-1,m). The gate potential of the read transistor RTr(n-1,m) is −1,m) (i.e., the potential of bit line Rm).

[0216] In addition, the drain of the read transistor RTr(n-1,m) (i.e., the write The potential of the read transistor RTr(n-1,m ) The gate potential is the same as or higher than the source and drain potentials, so the read transistor RTr(n-1,m) is in the off state.

[0217] The potential (0 V) of the gate of the write transistor WTr(n,m) is That is, the potential of the bit line Rm (0 to +3V) is the same as or lower than the drain (+4 to +7V). Therefore, the write transistor WTr(n,m) is in the off state, and the read transistor The potential (+4 to +7V) of the gate of RTr(n,m) is connected to its source (i.e., the bit line Rm) potential (0 to +3V), drain (i.e., write word line Qn+1) potential Since the voltage is higher than 0V, the read transistor RTr(n,m) is also in the off state. In this manner, data can be written to the memory cells in the (n-1)th row.

[0218] <Figure 14(B)> (Writing to the nth line) When writing to the memory cell in the nth row, as shown in FIG. 14(B), the read word line P n and the potential of the write word lines Qn-1 and Qn+1 are set to 0V, and the potential of the read word lines Pn-1 and P The potential of n+1 is set to +4 V. The potential of bit line Rm is set to the following according to the data to be written: It shall have four values: 0V, +1V, +2V, and +3V.

[0219] Since the potential of the read word line Pn-1 has increased by 4 V, the read transistor RTr(n -1,m) (i.e., the drain of the write transistor WTr(n-1,m) ) also rises in potential, going from +4V to +7V.

[0220] If the potential of the write word line Qn is set to +4V, the write transistor WTr (n,m) is turned on, and the drain potential of the write transistor WTr(n,m) becomes The potential of the bit line Rm approaches that of the source of the write transistor. The potential of the bit line Rm is assumed to be equal to that of the bit line Rm.

[0221] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is It is equal to the drain potential of the read transistor WTr(n,m). The potential of the gate of the read transistor RTr(n,m) is the source This potential is the same as the potential of the bit line (that is, bit line Rm).

[0222] In addition, the drain of the read transistor RTr(n,m) (i.e., the write word line Qn+1) is 0V. Therefore, the potential of the read transistor RTr(n,m) The gate potential (potential of bit line Rm) is the same as or higher than the source and drain potentials, so The read transistor RTr(n,m) is in the off state.

[0223] The gate potential (0V) of the write transistor WTr(n-1,m) is The potential of the drain (i.e., bit line Rm) is 0 to +3V, and the potential of the drain (+4 to +7V) is Since the write transistor WTr(n-1,m) is in the off state, the read transistor The potential (+4 to +7 V) of the gate of the transistor RTr(n-1,m) is That is, the potential (0 to +3V) of the bit line Rm, the drain (i.e., the write word line Qn In this way, the n-th row of memory cells is in the OFF state because the potential of the n-th row of memory cells is equal to or higher than the potential of the n-th row of memory cells (+4 V). You can write data to the file.

[0224] <Fig. 14(C)> (Writing in the (n+1)th row) When writing to the memory cells in the (n+1)th row, as shown in FIG. The potential of the word line Pn+1 and the write word lines Qn-1 and Qn is set to 0V, and the potential of the read word line Pn The potential of -1 and Pn is set to +4V. The potential of the bit line Rm is set to It has four possible values: 0V, +1V, +2V, and +3V.

[0225] Since the potential of the read word line Pn has increased by 4V, the read transistor RTr(n,m The potential of the gate of the write transistor WTr(n,m) (i.e., the drain of the write transistor WTr(n,m)) is also the same. The voltage rises steadily from +4V to +7V.

[0226] Then, the potential of the write word line Qn+1 is set to +4V, Data can be written to the storage cells of a row.

[0227] At this stage, the gate potential (0V) of the write transistor WTr(n,m) is The drain potential (+4 to +7V) and the source (i.e., bit line Rm) potential (0 to +3V ), the write transistor WTr(n,m) is in the off state.

[0228] In addition, the gate potential (+4 to +7 V) of the read transistor RTr(n, m) is The potential (+4V) of the drain (i.e., the write word line Qn+1) and the potential (+4V) of the source (i.e., The potential of the bit line Rm is equal to or higher than the potential (0 to +3V) of the read transistor RTr( n, m) are also in the off state.

[0229] Furthermore, the potential (0V) of the gate of the write transistor WTr(n-1,m) is The potential of the source (i.e., bit line Rm) is 0 to +3V, and the drain is +4 to +7V. Since the voltage is low, the write transistor WTr(n-1,m) is in the off state, and the read transistor The potential (+4 to +7 V) of the gate of the transistor RTr(n-1,m) is That is, the potential (0 to +3V) of the bit line Rm, the drain (i.e., the write word line Q n) is higher than the potential (0 V), so it is in the OFF state. Data can be written to the memory cells.

[0230] <Fig. 14(D)> (Writing on other lines) When writing to memory cells in rows other than the above, the write word is The potential of the read word lines Qn-1, Qn, and Qn+1 is set to 0V, and the potential of the read word lines Pn-1, Pn, and Pn+ The potential of bit line Rm is set to +4V. Depending on the data written, it can take on four values: 0V, +1V, +2V, and +3V.

[0231] In this state, the gate potential (0V) of the write transistor WTr(n,m) is The drain potential (+4 to +7V) and the source (i.e., bit line Rm) potential (0 to +3V ), the write transistor WTr(n,m) is in the off state.

[0232] In addition, the gate potential (+4 to +7 V) of the read transistor RTr(n, m) is The potential (0V) of the drain (i.e., the write word line Qn+1) and the potential (0V) of the source (i.e., the Since the potential of the bit line Rm is higher than the potential (0 to +3V), the read transistor RTr(n,m) is also in the off state.

[0233] Furthermore, the potential (0V) of the gate of the write transistor WTr(n-1,m) is The potential of the source (i.e., bit line Rm) is 0 to +3V, and the drain is +4 to +7V. Since the voltage is low, the write transistor WTr(n-1,m) is in the off state, and the read transistor The potential (+4 to +7 V) of the gate of the transistor RTr(n-1,m) is That is, the potential (0 to +3V) of the bit line Rm, the drain (i.e., the write word line Q n) is higher than the potential (0 V), so it is in the off state.

[0234] <Figure 15(A)> (Readout) Next, the reading will be described. The reading of the memory cell in the nth row will be described below. However, the readout of memory cells in other rows can be performed in the same manner. As shown in FIG. 15(A), the potentials of the write word lines Qn-1, Qn, and Qn+1 are set to 0V. The potential of the read word lines Pn-1, Pn, and Pn+1 is set to +3V.

[0235] In this state, the drain potential of the write transistor WTr(n,m) is Depending on the data input, the voltage will be +3V, +4V, +5V, or +6V. If the potential is between 0V and +3V, the write transistor WTr(n,m) The transistors RTr(n,m) are also off. Similarly, the write transistors WTr( n-1,m) and the read transistor RTr(n-1,m) are also off. For rows that do not include the write transistor and the read transistor, is turned off.

[0236] <Figure 15(B)> (Read) On the other hand, for the row to be read, the potential of the read word line Pn is set to be less than +3 volts. For example, as shown in FIG. 15B, when the potential of the bit line Rm is set to +3V, The potential of the read word line Pn is set to +2V. At this time, the read transistor RTr(n ,m) the gate potential is between +2V and +5V. In the case of +2V, Since the potential of the read transistor R Tr(n,m) is turned on.

[0237] When writing, four types of potential were given: 0V, +1V, +2V, and +3V. The transistor is turned on when a potential of 0V is applied during writing. The fact that the transistor RTr(n,m) is turned on can be detected in various ways, as in the other examples. You can find out by law.

[0238] <Figure 15(C)> (Read) Similarly, as shown in FIG. 15C, when the potential of the read word line Pn becomes +1V, The gate potential of the read transistor RTr(n,m) is between +1V and +4V. In the cases of +1V and +2V, the read transistor RTr(n,m) is on. Here, the on state is when a potential of 0V or +1V is applied during writing. This is the case.

[0239] <Figure 15(D)> (Read) Also, as shown in FIG. 15(D), when the potential of the read word line Pn becomes 0V, The gate potential of the output transistor RTr(n,m) is between 0V and +3V. In the cases of 0V, +1V, and +2V, the read transistor RTr(n,m) is on. Here, the on state is when a potential of 0V, +1V, or +2V is applied during writing. This is the case when

[0240] Even if the potential of the read word line Pn is set to 0V, the read transistor RTr(n,m) If it remains off, the gate potential of the read transistor RTr(n,m) will be +3V This is the case when a potential of +3V is applied during writing.

[0241] In the above process, the write transistors WTr(n,m), WTr(n-1,m), The read transistor RTr(n-1,m) remains in the off state. In this way, four stages You can write and read data (2 bits). Of course, you can write and read more data in the same way. Write data, for example, 8-level data (3 bits), 16-level data (4 bits) Can be read and written.

[0242] In the above explanation, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are The capacitance of the buffer C(n,m) was ignored, but in real memory cells, these are taken into account. It is necessary to determine the potential to be applied.

[0243] (Embodiment 8) In this embodiment, an example of the operation of the semiconductor memory circuit shown in FIG. The following will be explained with reference to FIG. 18. Specific values ​​for the potential are given below. The purpose of these values ​​is to help understand the technical concepts. This may be changed depending on the characteristics of the capacitors and / or the implementer. The semiconductor memory device shown in FIG. 16(A) can also be fabricated by a method other than the following method. , data can be written or read.

[0244] Here, the write transistors WTr1, WTr2, and WTr3 are N-channel types, and the read The transistors RTr1, RTr2, and RTr3 are P-channel types. In a transistor, the gate potential is 1 / 2 the lower of the source or drain potentials. When the voltage exceeds V, the readout transistor is turned on, otherwise it is turned off. The transistor is designed so that the gate potential is 1V or more higher than the source or drain potential. It is assumed that when the upper limit is low, it is on, and otherwise it is off.

[0245] In addition, the gate capacitance of the read transistor that varies with the gate bias is The capacitance of the capacitor C is negligible. Furthermore, the write transistor WT The parasitic capacitance of r, the parasitic capacitance of the read transistor RTr, and other parasitic capacitances between wiring, etc. All capacitances not shown in the figure are assumed to be 0. Also, in Figures 17 and 18, A circle indicates a transistor that is in the on state, and a cross indicates a transistor that is in the off state. These are written over the transistor symbol. Those that turn on under certain conditions are written in the diagram. In the following examples, the potential of the bias line S is always 0V.

[0246] First, we will explain writing to this storage unit. Writing is done in the rightmost storage cell. When writing data, the read word lines P1 and P2 are connected as shown in FIG. 2. The potential of P3 is set to 0V. The potential of the bit line R is set to 0 It has four values: V, +1V, +2V, and +3V.

[0247] Then, when the potential of the write word lines Q1, Q2, and Q3 is set to +4V, the write transistor The write transistors WTr1, WTr2, and WTr3 are turned on, and the drive of the write transistor WTr3 is turned on. The potential of the drain (i.e., the potential of the node F3) approaches the potential of the bit line R. It is assumed that the potential is equal to that of the bit line R.

[0248] On the other hand, at this stage, the read transistors RTr1, RTr2, and RTr3 are in the off state. 17B, ​​the potential of the write word line Q3 is set to 0V. Then, the write transistor WTr3 is turned off, and the previous bit In this way, data can be written to the rightmost memory cell. This can be done.

[0249] Next, data is written to the central memory cell. In the state of FIG. 17B, the potential of the node F2 becomes equal to the potential of the bit line R. Then, the potential of the write word line Q2 is set to 0V. (See FIG. 17C), the write transistor WTr2 is turned off, so that the node F2 In this way, the potential of the previous bit line R is maintained. can be written.

[0250] In this manner, data can be written to all the memory cells of the memory unit. If there is no need to write data to a storage unit other than the storage unit in question (if data is not written to a storage unit other than the storage unit in question), When writing data, the potential of the read word line P1 is set to +3V as shown in FIG. In this case, the potential of the node F1 is +3V or more and +6V or less. Since the potential of the read transistor RTr1 is between 0V and +3V, the read transistor RTr1 remains in the off state. It is possible to do so.

[0251] Next, the reading will be described with reference to FIG. 18. First, the reading of rows other than the memory unit in question When reading out, as shown in FIG. 18(A), the write word lines Q1, Q2, and Q The potential of read word lines P1, P2, and P3 is set to +4V. , the write transistors WTr1, WTr2, and WTr3 are turned off. Also, the node F1 The potential of F2 and F3 is +4V or more and +7V or less. As explained in , the voltage is between 0V and +4V, so the read transistors RTr1 and RT r2 and RTr3 can remain off.

[0252] To read the storage unit, the write word is The potentials of the read word lines Q1, Q2, and Q3 are set to 0V, and the potentials of the read word lines P1, P2, and P3 are set to 0V. The potential of the bit line is set to +4V. At this time, the write transistor WT r1, WTr2, and WTr3 are off, but the potentials of nodes F1, F2, and F3 are 0V or higher + The read transistors RTr1, RTr2, and RTr3 are turned on. Therefore, a current flows between the bit line R and the bias line S.

[0253] If the bit line R is terminated with a capacitor, a current flows between the bit line R and the bias line S. As the current flows, the initial potential (+4V) approaches the potential of the bias line S (0V). The final potential is determined by the minimum of the potentials of nodes F1, F2, and F3. The potential of bit line R fluctuates between 0V and +4V.

[0254] In the following, it is assumed that data is read from the central memory cell of the memory unit. As shown in (C), when the potential of the read word line P2 is raised to +1V, The potential will be +1V, +2V, +3V, or +4V depending on the data written. Here, if the potential of the node F2 is +4V, the read transistor RTr2 is turned off. Therefore, no current flows between the bit line R and the bias line S.

[0255] At this stage, the voltage of node F2 is +4V because the voltage of the bit line is + In other words, when the potential of the read word line P2 is +1V, If the read transistor RTr2 is off, the potential of the bit line R is +3 It turns out that it was V. In this way, the value of the stored data can be known.

[0256] Furthermore, when the potential of the read word line P2 is increased to +2 V as shown in FIG. The potential of node F2 is set to +2V, +3V, +4V, or +5V depending on the written data. Here, if the potential of node F2 is +4V or +5V, the read transistor Since the resistor RTr2 is turned off, no current flows between the bit line R and the bias line S. .

[0257] By detecting this, the value of the data can be known. The gate potential of the transistor RTr2 is +4V or +5V when writing. When the potential of the bit line R is +2V or +3V, When the potential was +1V (i.e., the state shown in FIG. 18(C)), the transistor was in the on state. However, when the potential was +2V, If the bit line R potential is +2V when writing, It is.

[0258] Similarly, when the potential of the read word line P2 is increased to +3 V as shown in FIG. The potential of node F2 is set to +3V, +4V, +5V, or +6V depending on the written data. Here, if the potential of node F2 is +4V, +5V, or +6V, the read However, the transistor RTr2 is turned off, so current flows between the bit line R and the bias line S. In other words, when writing, the bit line potential is +1V, +2V, or +3V. This is the case if:

[0259] If the potential of the bit line is 0V during writing, the potential of the read word line P2 is If +3V is applied, the potential of node F2 is +3V and it is still on. Even if the potential of the read word line P2 is +3V, a current flows between the bit line R and the bias line S. If this is the case, it is understood that the potential of the bit line was 0V at the time of writing.

[0260] The above is a method for finding the data value by gradually changing the potential of the read word line P2. However, the value of the data can also be known by measuring the potential. For example, in Figure 18(F As shown in Fig. 1, a capacitor is provided at the end of the bit line, and the potential on the memory cell side is set to 0V. .

[0261] In addition, the potentials of the write word lines Q1, Q2, and Q3 and the read word lines P1 and P3 are set to -3V. In this state, the potentials of both nodes F1 and F3 are between -3V and 0V. By setting the potential of the read transistors RTr1 and RTr2 to an appropriate level, 2. Turn on RTr3 to bring the potential of the bit line R closer to the potential of the bias line S (0V). For example, if node F2 is below 0V, the potential of the capacitor of bit line R is It is greater than 0V and less than +1V.

[0262] First, when the read word line P2 is set to +3V, the potential of the node F2 is +3V or more. V or less, the read transistor RTr2 is off at this stage. However, Next, when the potential of the read word line P2 is lowered to 0V, the potential of the node F2 is increased by +3V, which is higher than 0V. and the read transistor RTr2 is turned on.

[0263] As explained above, if the potential of the node F2 is 0V, the potential of the capacitor of the bit line R The potential of the node F2 is 0V or more and less than +1V. This is the case where the potential of the bit line is 0V.

[0264] Similarly, if the potential of node F2 is +1V, the potential of the capacitor of bit line R will be +1V or more. If the potential of node F2 is +2V, the potential of the capacitor of bit line R will be + If the potential of node F2 is +3V or more, the potential of the capacitor of bit line R is +3V. The bit level is between +3V and +4V. That is, by measuring the potential of the capacitor of the bit line R, Therefore, the potential of the node F2 can be known, and the potential of the bit line during writing can be calculated by You can find out.

[0265] In this way, four levels of data (2 bits) can be written and read. In this way, more data, for example, 8-level data (3 bits), 16-level data, The 4-bit data can be written and read.

[0266] In the above explanation, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are The capacitance of the buffer C(n,m) was ignored, but in real memory cells, these are taken into account. It is necessary to determine the potential to be applied.

[0267] The gate capacitance of the read transistor RTr(n,m) changes significantly between the on and off states. Since the read transistor RTr(n,m) is driven by the The capacitance of the capacitor C(n,m) of the gate capacitance of the read transistor RTr(n,m) The larger the ratio to the capacitor C(n,m ) should be at least twice the gate capacitance of the read transistor RTr(n,m). .

[0268] (Embodiment 9) In this embodiment mode, examples of the shape and manufacturing method of the semiconductor memory device described in Embodiment Mode 8 will be described. In this embodiment, the write transistor contains gallium and indium. An oxide semiconductor having a ferroelectric film is used as the read transistor, and a single crystal silicon semiconductor is used as the read transistor. Therefore, the write transistor is stacked on top of the read transistor. For details of the manufacturing method, etc., refer to the known semiconductor manufacturing technology or the third embodiment. It is recommended to refer to this.

[0269] FIG. 22 shows an example of the layout of the storage unit of the semiconductor memory device of this embodiment. In the embodiment, the unitary storage unit has four storage cells.

[0270] FIG. 22(A) shows the main wiring and electrodes provided on a single crystal silicon substrate. An element isolation region 302 is formed. A conductive material (silicide, etc.) or a doping material is formed on the substrate. A conductive region 306 is formed using the silicon that has been etched. A portion of the conductive region 306 is a read A portion of the conductive region 306 serves as a via. The conductive region 306 also becomes part of the read gate 31 of the read transistor. In some parts of the conductive region 306, a first connection electrode 311 is provided. can be done.

[0271] By forming bias lines S using the conductive regions 306, the integration density can be increased. In that case, however, the bias line S is parallel to the write word line and the read word line. It is preferable that the bit lines are aligned perpendicular to the bit lines. The bias line S is connected to the adjacent memory unit (the memory unit on the right side of the bias line S). By having such a structure, the degree of integration can be increased.

[0272] The materials for the read gate 310 and the first connection electrode 311 may be the same as those in the third embodiment (or FIG. 8) is used for the read gate 110 and the first connection electrode 111. That's good.

[0273] FIG. 22B shows a transistor using an oxide semiconductor formed on the circuit of FIG. 22A. The figure shows main wirings and electrodes, etc., with the oxide semiconductor regions 312 and the The first wiring 314 is connected to the write word lines Q1, Q2, Q3, Q4, or the read word lines P1, P2, P3, and P4.

[0274] A part of the first wiring 314 overlaps with the oxide semiconductor and serves as the gate electrode of the write transistor. The oxide semiconductor region 312 is in contact with the underlying read gate 310. A part of the wiring 314 overlaps with the read gate 310 to form a capacitor. A second contact for connection to an upper layer (e.g., bit line R) is provided in a portion of the nitride semiconductor region 312. A connecting electrode 317 is provided.

[0275] When Figures 22(A) and (B) are superimposed, it becomes as shown in Figure 22(C). Here, The overlapping is intentionally slightly shifted so that the overlapping can be seen. Also shown is a second wiring 318 formed on the transistor. The portion becomes the bit line R. Note that points A and B in FIGS. 22(A) to 22(C) indicate the same position. That is why.

[0276] In FIG. 22, the width of the conductive region 306 and the first wiring 314 are processed to a minimum processed line width F. That is, the line width and line spacing are F. In that case, the size of the unit memory cell is 12F 2 Since some memory units are shared by each memory cell, in reality, The area per floor is 12F. 2 The storage unit shown in FIG. 22 has four storage cells. However, by increasing the number of memory cells in the memory unit, the surface area per memory cell can be increased. The height is 12F 2 Approaching.

[0277] (Embodiment 10) In this embodiment, an example of the operation of the semiconductor memory circuit shown in FIG. The following will be explained with reference to FIG. 21. Specific values ​​for the potential are given below. The purpose of these values ​​is to help understand the technical concepts. This may be changed depending on the characteristics of the capacitors and / or the implementer. The semiconductor memory device shown in FIG. 16B can also be fabricated by a method other than the following method. , data can be written or read.

[0278] Here, the write transistors WTr1, WTr2, and WTr3 are N-channel types, and the read The transistors RTr1, RTr2, and RTr3 are P-channel types. In a transistor, the gate potential is 1V higher than either the source or drain potential. If the voltage is higher than this, the transistor is turned on, otherwise it is turned off. A transistor is one in which the gate potential is 1V or more lower than either the source or drain potential. When the threshold voltage Vcc is 1, the signal is turned on, otherwise the signal is turned off.

[0279] In addition, the gate capacitance of the read transistor that varies with the gate bias is The capacitance of the capacitor C is negligible. Furthermore, the write transistor WT The parasitic capacitance of r, the parasitic capacitance of the read transistor RTr, and other parasitic capacitances between wiring, etc. All capacitances not shown in the figure are assumed to be 0. Also, in Figures 20 and 21, A circle indicates a transistor that is in the on state, and a cross indicates a transistor that is in the off state. These are written over the transistor symbol. Those that turn on under certain conditions are written in the diagram. In the following examples, the potential of the bias line S is always 0V.

[0280] Writing starts from the rightmost memory cell. When writing, as shown in FIG. , the potential of the write word lines Q1, Q2, and Q3 is set to +4V, and the potential of the read word line P is set to -4 V. The potential of the bit line R is set to 0V, +1V, or +2V depending on the data to be written. It has four values: +3V, +4V, +5V, +6V, +7V, +8V, +10V, +12V, +14V, +16V, +20V, +3V.

[0281] In this state, the write transistors WTr1, WTr2, and WTr3 are on, The potential of the gate F3 approaches the potential of the bit line R. It shall be so.

[0282] On the other hand, at this stage, the read transistors RTr1, RTr2, and RTr3 are in the off state. Then, as shown in FIG. 20B, the potential of the write word line Q3 is set to −4 V. Then, the write transistor WTr3 is turned off, and the previous bit is In this way, data can be written to the rightmost memory cell. This can be done.

[0283] Next, data is written to the central memory cell. In the state of FIG. 20B, the potential of the node F2 is , the potential of the bit line R. Then, the potential of the write word line Q2 is set to -4V. (See FIG. 20C), the write transistor WTr2 is turned off, and at the node F2 The potential of the previous bit line R is maintained. In this way, data is written to the central memory cell. The data is written in the same manner until all memory cells have been written with data. You can get into it.

[0284] If there is no need to write data into the storage unit, as shown in FIG. The potential of the write word lines Q1, Q2, and Q3 is set to 0 V, and the potential of the read word line P is set to 0 V. At this time, the potential of the node F1 is +4V or more and +7V or less. Since the potential is between 0V and +3V, the read transistors RTr1, RTr2, and RTr 3 can remain off.

[0285] Next, the reading will be described with reference to FIG. 21. First, the reading of rows other than the memory unit in question When reading out, as shown in FIG. 21(A), the write word lines Q1, Q2, and Q The potential of the write word line 3 is set to 0V, and the potential of the read word line P is set to 0V. The transistors WTr1, WTr2, and WTr3 are turned off. Also, the voltages of the nodes F1, F2, and F3 are turned off. The potential of the bit line R is +4V or more and +7V or less. Since the voltage is between 0V and +4V, the read transistors RTr1, RTr2, and RTr3 are You can keep it off.

[0286] To read the storage unit, the write word is The potential of the read word line P is set to -4 V. The potential of the bit line is set to +4 V. At this time, the write transistors WTr1 and WT r2 and WTr3 are turned off. Also, when the potentials of nodes F1, F2, and F3 are greater than 0V and less than +3V, Since the read transistors RTr1, RTr2, and RTr3 are turned on, Therefore, a current flows between the bit line R and the bias line S.

[0287] If the bit line R is terminated with a capacitor, a current flows between the bit line R and the bias line S. As the current flows, the initial potential (+4V) approaches the potential of the bias line S (0V). The final potential is determined by the minimum of the potentials of nodes F1, F2, and F3. The potential of bit line R fluctuates between 0V and +4V.

[0288] In the following, it is assumed that data is read from the central memory cell of the memory unit. As shown in (C), when the potential of the write word line Q3 is raised to -3V, The potential will be +1V, +2V, +3V, or +4V depending on the data written. Here, if the potential of the node F2 is +4V, the read transistor RTr2 is turned off. Therefore, no current flows between the bit line R and the bias line S.

[0289] At this stage, the voltage of node F2 is +4V because the voltage of the bit line is + In other words, when the potential of the write word line Q3 is +1V, If the read transistor RTr2 is off, the potential of the bit line R is +3 We can see that it was V. In this way, we can know the value of the data.

[0290] Furthermore, when the potential of the write word line Q3 is increased to -2 V as shown in FIG. The potential of node F2 is set to +2V, +3V, +4V, or +5V depending on the written data. Here, if the potential of node F2 is +4V or +5V, the read transistor Since the resistor RTr2 is turned off, no current flows between the bit line R and the bias line S. The voltage at node F2 is +4V or +5V when the voltage at the bit line during writing is +2V or +3V.

[0291] Similarly, when the potential of the write word line Q3 is increased to -1 V as shown in FIG. The potential of node F2 is set to +3V, +4V, +5V, or +6V depending on the written data. Here, if the potential of node F2 is +4V, +5V, or +6V, the read However, the transistor RTr2 is turned off, so current flows between the bit line R and the bias line S. In other words, when writing, the bit line potential is +1V, +2V, or +3V. This is the case if:

[0292] If the potential of the bit line is 0V during writing, the potential of the write word line Q3 is If the potential of node F2 is set to -1V, the potential of node F2 is +3V and it is still on. That is, even if the potential of the write word line Q3 is -1V, no current flows between the bit line R and the bias line S. If this occurs, it is understood that the potential of the bit line R was 0V at the time of writing.

[0293] The potential is measured in the same manner as that described in the eighth embodiment with reference to FIG. Multi-value data can also be read out by this.

[0294] In this way, four levels of data (2 bits) can be written and read. In this way, more data, for example, 8-level data (3 bits), 16-level data, The 4-bit data can be written and read.

[0295] In the above explanation, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are The capacitance of the buffer C(n,m) was ignored, but in real memory cells, these are taken into account. It is necessary to determine the potential to be applied.

[0296] The gate capacitance of the read transistor RTr(n,m) changes significantly between the on and off states. Since the read transistor RTr(n,m) is driven by the The capacitance of the capacitor C(n,m) of the gate capacitance of the read transistor RTr(n,m) The larger the ratio to the capacitor C(n,m ) should be at least twice the gate capacitance of the read transistor RTr(n,m). .

[0297] (Embodiment 11) In this embodiment mode, examples of the shape and manufacturing method of the semiconductor memory device described in embodiment mode 10 will be described. FIG. 23 shows the layout of the storage unit of the semiconductor memory device of this embodiment. An example is shown below: In this embodiment, the unit storage unit has four storage cells.

[0298] FIG. 23(A) shows the main wiring, electrodes, etc., provided on a single crystal silicon substrate. An element isolation region 402 is formed. In addition, a conductive material or doped silicon is used. A conductive region 406 is formed, a part of which is connected to the source and drain of the read transistor. A part of the conductive area 406 becomes a part of the bias line S. The conductive area 406 is a read The conductive region 406 is separated by a read gate 410 of the transistor. A first connection electrode 411 is provided on a part of the first connection electrode 411. In this embodiment, the first connection electrode 411 is By sharing with adjacent memory units, the integration density can be increased. The material of the first connection electrode 411 may be the same as that of the read gate 310 or the first connection electrode 411 shown in the ninth embodiment. Any electrode that satisfies the conditions for one connection electrode 311 may be used.

[0299] FIG. 23B shows a transistor using an oxide semiconductor formed on the circuit of FIG. 23A. The figure shows main wirings and electrodes, etc., with the oxide semiconductor regions 412 and the The first wiring 414 is connected to the write word lines Q1, Q2, Q3, Q4, or the read word line P.

[0300] A part of the first wiring 414 overlaps with the oxide semiconductor and serves as the gate electrode of the write transistor. The oxide semiconductor region 412 is in contact with the underlying read gate 410. A part of the wiring 414 overlaps with the read gate 410 to form a capacitor. The nitride semiconductor region 412 has a second connection electrode for connection to an upper layer (e.g., a bit line R). 417 will be established.

[0301] When Figures 23(A) and (B) are superimposed, it becomes as shown in Figure 23(C). Here, The overlapping is intentionally slightly shifted so that the overlapping can be seen. Also shown is a second wiring 418 formed on the transistor. The portion becomes the bit line R.

[0302] Points A and B in Figures 23(A) to 23(C) indicate the same position. The width of the conductive region 406 is processed to a minimum processed line width F. That is, the line width and the line spacing are F. In that case, the size of the unit memory cell is 9F 2 In the memory unit, each memory cell In reality, the area per memory cell is 9F. 2 Become bigger. The memory unit shown in FIG. 23 has four memory cells. If you increase the number of memory cells, the area per memory cell becomes 9F. 2 Approaching.

[0303] A method for manufacturing a semiconductor memory device having the above structure will be described below. A process cross-sectional view connecting point A and point B. The manufacturing process will be explained below according to the numbers in the figure.

[0304] <Fig.24(A)> First, using a known semiconductor manufacturing technique, an element separation layer is formed on an n-type single crystal silicon substrate 401. Region 402, conductive region 406 made of a p-type doped silicon region, a first gate An insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. The side of the conductive region 404 may be provided with a sidewall as shown in the figure. A silicide region may be provided on the surface to increase the electrical conductivity.

[0305] <Fig.24(B)> Using the method described in the third embodiment, the read gate 410 of the read transistor, After the first connection electrode 411 is formed and embedded, the oxide semiconductor region 412 is formed. The thickness of the oxide semiconductor region is set to 30 to 50 nm, and the second gate insulating film 4 to be formed thereafter is set to 400 nm. In order to make the thickness several times larger than the 10 nm of 13, an oxide semiconductor was used to reduce the step. The end portion of the region 412 is processed to have a tapered shape. The taper angle at the end portion of the oxide semiconductor region is 30°. It is recommended to set the angle to 60 degrees.

[0306] <Fig.24(C)> A plurality of first wirings 414 are formed from a conductive material. The first wirings 414 are The write word lines Q1, Q2, Q3, etc. are made of oxide semiconductor. Further, a region 415 exhibiting n-type conductivity is formed as a gate electrode of a transistor using the above-mentioned A second interlayer insulator 416, a second connection electrode 417, and a second wiring 418 are formed. is the bit line R. Thus, as shown in FIG. 419a, 419b, a semiconductor memory device having a read transistor 420 and a capacitor 421. A storage cell of the memory device is fabricated.

[0307] As shown in the figure, the write word line Q2 is connected to the electrode of the capacitor 421 and the write It is formed as the gate electrode of the transistor 419b. That is, the oxide semiconductor region between the write word line Q2 and the read gate 410 Although 412 is not doped, its thickness is less than 50 nm, so more than half of the The portion acts as a weak n-type conductor. [Explanation of symbols]

[0308] 11 Means for measuring electric potential 12 Means for applying electric potential 13 Capacitor 14 Switch 101 Single crystal silicon substrate 102 Element isolation region 103 First gate insulating film 104 Dummy Gate 105a Silicide region 105b Silicide region 106a Conductive area 106b Conductive region 107 First interlayer insulator 107a: First interlayer insulator having a flat surface 108 Opening 109 Opening 110 Readout gate 111 First connection electrode 112 Oxide semiconductor region 113 Second gate insulating film 114a First Wiring 114b 1st wiring 115a Region showing n-type conductivity 115b Region showing n-type conductivity 116 Second interlayer insulator 117 Second connection electrode 118 2nd wiring 119 Write transistor 120 Readout transistor 121 Capacitor 200a Area of ​​unit memory cell 200b Area of ​​unit memory cell 202 Element isolation region 206a Conductive region 206b Conductive region 210 Readout gate 211 First connection electrode 212 Oxide semiconductor region 214 1st wiring 217 Second connection electrode 218 2nd wiring 302 Element isolation region 306 Conductive region 310 Readout Gate 311 First connecting electrode 312 Oxide semiconductor region 314 1st wiring 317 Second connecting electrode 318 2nd wiring 401 Single crystal silicon substrate 402 Element isolation region 403 First gate insulating film 404 Dummy Gate 406 Conductive region 407 First interlayer insulation 410 Readout Gate 411 First connecting electrode 412 Oxide semiconductor region 413 Second gate insulating film 414 1st wiring 415 Region showing n-type conductivity 416 Second interlayer insulation 417 Second connecting electrode 418 2nd wiring 419a Write transistor 419b Write transistor 420 Readout transistor 421 Capacitor P Read word line Q Write word line R bit line S bias wire WTr Write Transistor RTr Readout transistor C Capacitor

Claims

1. A semiconductor device having a first transistor and a second transistor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor; a second semiconductor having a channel formation region of the second transistor; a second insulating film having a region overlapping the second semiconductor; a second wiring having a region overlapping with a channel formation region of the second transistor; a third wiring having an area overlapping the second semiconductor; the second semiconductor is provided in a layer different from the first wiring; the second semiconductor includes an oxide semiconductor; the second semiconductor has a region on the first insulating film, the second semiconductor has a region in contact with the first wiring, The third wiring has a region in contact with the second semiconductor and a region in contact with one of a source or a drain of the first transistor.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor; a second semiconductor having a channel formation region of the second transistor; a second insulating film having a region overlapping the second semiconductor; a second wiring having a region overlapping with a channel formation region of the second transistor; a third wiring having an area overlapping the second semiconductor; the first wiring has a region that functions as an electrode of the capacitance element, the second semiconductor is provided in a layer different from the first wiring; the second semiconductor includes an oxide semiconductor; the second semiconductor has a region on the first insulating film, the second semiconductor has a region in contact with the first wiring, The third wiring has a region in contact with the second semiconductor and a region in contact with one of a source or a drain of the first transistor.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor contains zinc and indium.

4. A semiconductor device having a first transistor and a second transistor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor; a second semiconductor having a channel formation region of the second transistor; a second insulating film having a region overlapping the second semiconductor; a second wiring having a region overlapping with a channel formation region of the second transistor; a third wiring having an area overlapping the second semiconductor; the second semiconductor is provided in a layer different from the first wiring; the second semiconductor includes an oxide semiconductor; the oxide semiconductor contains indium; the second semiconductor has a region on the first insulating film, the second semiconductor has a region in contact with the first wiring, The third wiring has a region in contact with the second semiconductor and a region in contact with one of a source or a drain of the first transistor.

5. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor; a second semiconductor having a channel formation region of the second transistor; a second insulating film having a region overlapping the second semiconductor; a second wiring having a region overlapping with a channel formation region of the second transistor; a third wiring having an area overlapping the second semiconductor; the first wiring has a region that functions as an electrode of the capacitance element, the second semiconductor is provided in a layer different from the first wiring; the second semiconductor includes an oxide semiconductor; the oxide semiconductor contains indium; the second semiconductor has a region on the first insulating film, the second semiconductor has a region in contact with the first wiring, The third wiring has a region in contact with the second semiconductor and a region in contact with one of a source or a drain of the first transistor.

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