Ceramic electronic component, circuit board, and method for manufacturing ceramic electronic component

Abstract

To more effectively suppress the diffusion of hydrogen into an element.SOLUTION: A ceramic electronic component according to an embodiment includes an element body having a dielectric, and an internal electrode, and an external electrode formed on the element body, connected to the internal electrode, and having a conductive layer provided with a larger number of gaps on a side farther from the element body than on a side closer to the element body.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component, a circuit board, and a method for manufacturing a ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors are used in high-frequency communication systems, such as mobile phones, to remove noise, etc. As their applications expand to include in-vehicle applications, higher reliability is being demanded.

[0003] Patent Document 1 discloses a technology in which an element that forms a covalent hydride with hydrogen is contained between the outermost plating layer that constitutes the external electrode and the dielectric layer that constitutes the ceramic body, in order to reduce the effects of hydrogen generated in the plating process and prevent deterioration of insulation resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-58719 A Summary of the Invention [Problem to be solved by the invention]

[0005] The technique disclosed in Patent Document 1 may not be effective in preventing the diffusion of hydrogen from the plating layer to the ceramic body depending on the type of element.

[0006] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a ceramic electronic component, a circuit board, and a method for manufacturing a ceramic electronic component that are capable of more effectively suppressing the diffusion of hydrogen into the element body. [Means for solving the problem]

[0007] In order to solve the above problems, a ceramic electronic component according to one aspect of the present invention comprises a base body having a dielectric and an internal electrode, and an external electrode having a conductive layer formed on the base body, connected to the internal electrode, and having more voids on a side remote from the base body than on a side closer to the base body.

[0008] In the ceramic electronic component according to one aspect of the present invention, the external electrodes further include plating layers containing Ni and formed on the conductive layers.

[0009] In the ceramic electronic component according to one aspect of the present invention, the voids are located in a range of 0.1 μm to 3.0 μm in the thickness direction from the surface of the conductive layer farthest from the element body.

[0010] In the ceramic electronic component according to one aspect of the present invention, the length of the void in the planar direction of the conductive layer is longer than the length in the thickness direction of the conductive layer.

[0011] Furthermore, in a ceramic electronic component according to one embodiment of the present invention, a plurality of voids are provided in the conductive layer, and there are more voids whose planar length is longer than the thickness direction length of the conductive layer than there are voids whose planar length is shorter than the thickness direction length of the conductive layer.

[0012] In the ceramic electronic component according to one aspect of the present invention, the length of the void in the longitudinal direction is not less than 0.5 μm and not more than 6.5 μm.

[0013] Furthermore, in a ceramic electronic component according to one embodiment of the present invention, the conductive layer is provided with a plurality of voids, and voids whose planar length is four or more times the thickness direction length of the conductive layer are present at a frequency of 50% or more.

[0014] In addition, in the ceramic electronic component according to one aspect of the present invention, the conductive layer is provided on the inside of the void or in a position in contact with the void. Metals contained in the conductive layer It comprises an oxide.

[0015] In addition, in a ceramic electronic component according to one aspect of the present invention, the conductive layer comprises a base layer formed on the base body, connected to the internal electrode, and including a conductor, and an underlayer plating layer formed on the base layer and having more voids on its side remote from the base body than on its side closer to the base body.

[0016] In the ceramic electronic component according to one aspect of the present invention, the lower plating layer is mainly composed of a metal or alloy containing at least one selected from Cu, Fe, Zn, Sn, Pb, and Cr.

[0017] In the ceramic electronic component according to one aspect of the present invention, the lower plating layer contains Cu as a main component.

[0018] Furthermore, in a ceramic electronic component according to one aspect of the present invention, for the external electrode, the main component of the base layer is Ni, and the external electrode comprises a Ni plating layer formed on the underlayer plating layer, and a Sn plating layer formed on the Ni plating layer.

[0019] In addition, in a ceramic electronic component according to one aspect of the present invention, the conductive layer includes a base layer formed on the base body, connected to the internal electrode, and having more voids on a side farther from the base body than on a side closer to the base body.

[0020] Furthermore, in a ceramic electronic component according to one aspect of the present invention, the external electrode includes a base layer whose main component is Cu, and a Ni plating layer formed on the base layer, and a Sn plating layer formed on the Ni plating layer.

[0021] In the ceramic electronic component according to one aspect of the present invention, the external electrodes further include a conductive resin layer provided on the conductive layer.

[0022] In addition, in a ceramic electronic component according to one aspect of the present invention, the conductive layer comprises a base layer that is formed on the base body, is connected to the internal electrode, and contains Ni, and a Cu plating layer that is formed on the base layer and has more voids on its surface farther from the base body than on its surface closer to the base body, and the external electrode comprises a Ni plating layer formed on the conductive resin layer, and a Sn plating layer formed on the Ni plating layer.

[0023] In addition, in a ceramic electronic component according to one aspect of the present invention, the conductive layer comprises a base layer formed on the base body, connected to the internal electrode, and containing Cu with more voids on a side farther from the base body than on a side closer to the base body, and the external electrode comprises a Ni plating layer formed on the conductive resin layer and a Sn plating layer formed on the Ni plating layer.

[0024] Furthermore, according to a circuit board according to one aspect of the present invention, there is provided a circuit board on which any of the ceramic electronic components described above is mounted, wherein the ceramic electronic component is mounted via a solder layer attached to the external electrode.

[0025] Furthermore, a method for manufacturing a ceramic electronic component according to one aspect of the present invention includes the steps of: forming an element body having a dielectric and internal electrodes; forming a conductive layer on the element body, the conductive layer being connected to the internal electrodes and having more voids on a surface farther from the element body than on a surface closer to the element body; and forming a plating layer containing Ni on the conductive layer.

[0026] Furthermore, in a method for manufacturing a ceramic electronic component according to one aspect of the present invention, the step of forming the conductive layer on the base body includes the steps of applying a base material for an external electrode to multiple surfaces of the base body, firing the base material to form a base layer for the external electrode, oxidizing the surface side of the base layer while exposing it to an oxidizing atmosphere to form metal oxides that are more distributed on the surface side remote from the base body than on the surface side closer to the base body, and removing the metal oxides to form voids in the base layer. Effect of the Invention

[0027] According to one aspect of the present invention, the diffusion of hydrogen into the element body can be effectively suppressed, thereby making it possible to obtain a highly reliable ceramic electronic component. [Brief description of the drawings]

[0028] [Figure 1] 1 is a perspective view showing a configuration of a multilayer ceramic capacitor in accordance with a first embodiment. [Figure 2A] 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 taken in the longitudinal direction. [Figure 2B] 4 is a cross-sectional view showing another example of the configuration of the multilayer ceramic capacitor of FIG. 1 cut in the length direction. [Diagram 3] 4 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4A] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4B] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4C] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4D] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4E] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4F] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4G] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4H] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4I] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4J] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4K] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 4L] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Diagram 5] 6 is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor in accordance with a second embodiment is mounted. [Figure 6] 10 is a cross-sectional view of the multilayer ceramic capacitor in accordance with a third embodiment, cut in the length direction. FIG. [Figure 7] 10 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with a third embodiment. [Figure 8] 10 is a cross-sectional view of the multilayer ceramic capacitor in accordance with a fourth embodiment, cut in the length direction. FIG. [Figure 9] 10 is a cross-sectional view of the multilayer ceramic capacitor in accordance with a fifth embodiment, cut in the length direction. FIG. [Figure 10] FIG. 13 is a perspective view showing the configuration of a ceramic electronic component according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the embodiments of the present invention will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the present invention, and not all of the combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be appropriately modified or changed depending on the specifications of the device to which the present invention is applied and various conditions (usage conditions, usage environment, etc.). The technical scope of the present invention is determined by the claims, and is not limited by the individual embodiments below. Also, the drawings used in the following description may differ in scale and shape from the actual structure in order to make each configuration easier to understand.

[0030] (First embodiment) Fig. 1 is a perspective view showing the configuration of the multilayer ceramic capacitor in accordance with the first embodiment, and Fig. 2A is a cross-sectional view of the multilayer ceramic capacitor cut in the longitudinal direction of the capacitor in Fig. 1. Note that Fig. 1 shows an enlarged view of region R1 of the lower plating layer 9A. Fig. 2A shows an enlarged view of the configuration of region R2 of the external electrode 6A. In this embodiment, a multilayer ceramic capacitor is used as an example of a ceramic electronic component.

[0031] 1 and 2A, multilayer ceramic capacitor 1A comprises an element body 2 and external electrodes 6A, 6B. Element body 2 comprises a laminate 2A, a lower cover layer 5A and an upper cover layer 5B. Laminate 2A comprises internal electrode layers 3A, 3B and a dielectric layer 4.

[0032] A lower cover layer 5A is provided on the lower layer of the laminate 2A, and an upper cover layer 5B is provided on the upper layer of the laminate 2A. The internal electrode layers 3A, 3B are alternately laminated with a dielectric layer 4 interposed therebetween. Although an example in which a total of 11 internal electrode layers 3A, 3B are laminated is shown in Figs. 1 and 2A, the number of laminated internal electrode layers 3A, 3B is not particularly limited. In this case, the shapes of the element body 2 and the laminate 2A can be substantially rectangular parallelepiped shapes.

[0033] In the following description, the direction in which the side surfaces of the element body 2 face each other may be referred to as the length direction DL, the direction in which the front and rear surfaces of the element body 2 face each other as the width direction DW, and the direction in which the top and bottom surfaces of the element body 2 face each other as the stacking direction (height direction) DS. In this case, the bottom surface of the element body 2 may be disposed in a position facing the mounting surface of the circuit board on which the multilayer ceramic capacitor 1A is mounted. The element body 2 may be chamfered along the ridges of the element body 2. In this case, the element body 2 has curved surfaces R where the corners are chamfered.

[0034] The external electrodes 6A, 6B are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. Here, each of the external electrodes 6A, 6B is formed continuously from the lower surface side of the element body 2 via the side surfaces to the upper surface side of the element body 2. Furthermore, each of the external electrodes 6A, 6B may also be formed on the front and rear surfaces of the element body 2 that are perpendicular to both the lower surface and the side surfaces and face each other.

[0035] In the length direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions in the laminate 2A. In this case, the internal electrode layer 3A can be arranged on one side surface side of the element body 2 relative to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other side surface side of the element body 2 relative to the internal electrode layer 3A. Then, an end of the internal electrode layer 3A is drawn to an end of the dielectric layer 4 on one side surface side of the element body 2 in the length direction DL and connected to the external electrode 6A. An end of the internal electrode layer 3B is drawn to an end of the dielectric layer 4 on the other side surface side of the element body 2 in the length direction DL and connected to the external electrode 6B. On the other hand, in the width direction DW of the element body 2, the ends of the internal electrode layers 3A, 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the ends of the internal electrode layers 3A, 3B may be aligned.

[0036] The thickness of the internal electrode layers 3A, 3B and the dielectric layer 4 in the lamination direction DS can be within a range of 0.05 μm to 5 μm, for example, 0.3 μm. The material of the internal electrode layers 3A, 3B can be selected from metals such as Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or may be an alloy containing these metals.

[0037] The material of the dielectric layer 4 may be, for example, mainly composed of a ceramic material having a perovskite structure. The main component may be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 may be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanate zirconate, titanium oxide, etc.

[0038] The material of lower cover layer 5A and upper cover layer 5B may be mainly composed of a ceramic material, for example. In this case, the main component of the ceramic material of lower cover layer 5A and upper cover layer 5B may be the same as the main component of the ceramic material of dielectric layer 4. The thickness of lower cover layer 5A and upper cover layer 5B is preferably 5 μm or more and 30 μm or less.

[0039] Each of the external electrodes 6A, 6B is connected to each of the internal electrodes 3A, 3B, and includes a conductive layer 8 having more voids KJ on a surface M2 side farther from the element body 2 than on a surface M1 side closer to the element body 2 when viewed from the cross section of FIG. 2A, and a plating layer 9 containing Ni. The voids KJ can be distributed more biased toward the surface M2 side farther from the element body 2 than the surface M1 side closer to the element body 2 within a single layer of the conductive layer 8. The surface M1 can be located at the boundary between the conductive layer 8 and the element body 2, and the surface M2 can be located at the boundary between the conductive layer 8 and the plating layer 9. The plating layer 9 is formed on the conductive layer 8. The conductive layer 8 includes a base layer 7 and a lower plating layer 9A having more voids KJ on the surface M2 side. The plating layer 9 includes an upper plating layer 9B containing Ni and an exterior plating layer 9C that is solder wettable.

[0040] The underlayers 7 are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. At this time, the underlayers 7 are formed continuously from the lower surface side of the element body 2 through the side surfaces to the upper surface side for each of the external electrodes 6A, 6B. Note that the underlayers 7 may also be formed continuously from the lower surface side of the element body 2 to the front surface side and rear surface side for each of the external electrodes 6A, 6B.

[0041] The metal used as the conductive material of the underlayer 7 may be mainly composed of a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The underlayer 7 may contain a common material. The common material, when mixed in the underlayer 7, can reduce the difference in thermal expansion coefficient between the element body 2 and the underlayer 7 and relieve the stress applied to the underlayer 7. The main component of the common material is, for example, the same ceramic component as the main component of the dielectric layer 4. The underlayer 7 may contain a glass component. The glass component, when mixed in the underlayer 7, can densify the underlayer 7. The glass component is, for example, an oxide of Ba (barium), Ca (calcium), Zn, Al, Si (silicon), Mg (magnesium), or B (boron).

[0042] Here, the underlayer 7 is preferably made of a sintered body obtained by applying a metal paste and then firing the same. This allows the underlayer 7 to be made thicker while ensuring adhesion between the element body 2 and the underlayer 7, and ensures the strength of each of the external electrodes 6A, 6B while ensuring electrical continuity when connected to the internal electrode layers 3A, 3B. When the underlayer 7 is fired simultaneously with the element body 2, the main component of the underlayer 7 is preferably Ni. The underlayer 7 may also be formed by applying a metal paste to the element body 2 after firing, followed by firing the metal paste.

[0043] The lower plating layer 9A is formed on the base layer 7. A plurality of voids KJ are provided in the lower plating layer 9A and can be distributed over the entire surface direction of the lower plating layer 9A. As shown in FIG. 2A, the voids KJ are present in the lower plating layer 9A in a closed state when viewed from the cross section. The voids KJ may be distributed in layers over the entire surface direction on the surface M2 side. The voids KJ can be provided in the lower plating layer 9A present on different surfaces of the element body 2. For example, the voids KJ can be provided on a pair of surfaces in the stacking direction DS, a pair of surfaces in the length direction DL, and a pair of surfaces in the width direction DW in FIG. 1. The surface side of the lower plating layer 9A is the surface side on which the upper plating layer 9B is formed, and is the surface side farther from the element body 2. For example, the gap KJ may be provided not only on the surface side of the lower plating layer 9A having a normal in the length direction DL, but also on the surface side of the lower plating layer 9A having a normal in the width direction DW, or on the surface side of the lower plating layer 9A having a normal in the stacking direction DS. The surface side here refers to the side opposite the element body. The conductive layer 8 is provided on the inside of the gap KJ or in a position in contact with the gap KJ. Metals contained in The oxide may be provided.

[0044] At this time, before the upper plating layer 9B is formed on the surface side of the lower plating layer 9A, the metal contained in the lower plating layer 9A is oxidized non-uniformly while exposing the surface side of the lower plating layer 9A to an oxidizing atmosphere, and the oxide of the metal is removed, so that the voids KJ can be formed on the surface side of the lower plating layer 9A. Here, in order to oxidize the metal contained in the lower plating layer 9A non-uniformly, the surface side of the lower plating layer 9A can be rapidly oxidized. The voids KJ can be distributed in a spongy or porous manner on the surface side of the lower plating layer 9A. That is, there are more voids in the region on the surface side of the lower plating layer 9A than in other regions. At this time, the lower plating layer 9A can be mainly composed of a metal or alloy containing at least one selected from Cu, Fe, Zn, Sn, Pb, and Cr. The lower plating layer 9A is, for example, a Cu plating layer. By using a Cu plating layer as the lower plating layer 9A, good conductivity can be obtained while improving the adhesion between the lower plating layer 9A and the base layer 7, and a gap KJ can be formed on the surface M2 side of the lower plating layer 9A.

[0045] Here, the thickness of the lower plating layer 9A is preferably 2 μm or more and 15 μm or less. The voids KJ are preferably located in a range of 0.1 μm or more and 3.0 μm or less in the thickness direction from the surface of the lower plating layer 9A. The voids KJ are preferably longer in the planar direction than in the thickness direction of the lower plating layer 9A. It is preferable that there are more voids KJ whose planar length is longer than the thickness direction of the lower plating layer 9A than those whose planar length is shorter than the thickness direction of the lower plating layer 9A. The longitudinal length of the voids KJ is preferably 0.5 μm or more and 6.5 μm or less. It is preferable that voids KJ whose planar length is four times or more the thickness direction length of the lower plating layer 9A are present at a frequency of 50% or more of the total.

[0046] The upper plating layer 9B is formed on the lower plating layer 9A. The upper plating layer 9B is, for example, a Ni plating layer. By using a Ni plating layer as the upper plating layer 9B, the heat resistance of each of the external electrodes 6A, 6B during soldering can be improved.

[0047] The exterior plating layer 9C is formed on the upper plating layer 9A. The exterior plating layer 9C is, for example, a Sn plating layer. By using a Sn plating layer as the exterior plating layer 9C, the wettability of the solder can be improved.

[0048] Here, by providing the gap KJ on the surface side of the lower plating layer 9A, the gap KJ can prevent the diffusion of hydrogen generated when the upper plating layer 9B is formed on the lower plating layer 9A. The diffusion of hydrogen proceeds using the lower plating layer 9A as a medium, but the gap KJ hardly functions as a diffusion medium, so the diffusion of hydrogen hardly proceeds toward the element body 2. This makes it possible to prevent the diffusion of hydrogen generated when the upper plating layer 9B is formed on the lower plating layer 9A from diffusing into the element body 2, thereby suppressing hydrogen reduction of the dielectric layer 4 between the internal electrode layers 3A, 3B and suppressing deterioration of the insulation of the dielectric layer 4.

[0049] Furthermore, by arranging the voids KJ in a range of 0.1 μm to 3.0 μm in the thickness direction from the surface of the lower plating layer 9A, hydrogen diffusion can be effectively suppressed at the location of the voids KJ while suppressing an increase in the thickness of the external electrodes 6A, 6B. That is, more voids KJ are arranged in the region on the surface side of the lower plating layer 9A than in other regions. The concentration of hydrogen moving from the upper plating layer 9B side toward the element body 2 is higher on the surface side of the lower plating layer 9A and the diffusion rate is faster, so by arranging the voids KJ in such a range, hydrogen diffusion can be effectively suppressed.

[0050] Furthermore, by making the length of the gap KJ in the planar direction longer than the length of the gap KJ in the thickness direction of the lower plating layer 9A, the diffusion of hydrogen from the upper plating layer 9B side toward the base body can be effectively suppressed at the position of the gap KJ.

[0051] FIG. 2B is a cross-sectional view showing another example of the configuration of the multilayer ceramic capacitor of FIG. 1 cut in the length direction. In Fig. 2B, a multilayer ceramic capacitor 1Z has external electrodes 6ZA, 6ZB instead of the external electrodes 6A, 6B of the multilayer ceramic capacitor 1A in Fig. 2A. Each of the external electrodes 6ZA, 6ZB has a conductive layer 8Z instead of the conductive layer 8 in Fig. 2A. The conductive layer 8Z has an underlayer plating layer 9ZA instead of the underlayer plating layer 9A in Fig. 2A.

[0052] The lower plating layer 9ZA includes a void KZ and a metal oxide MZ. A plurality of voids KZ are provided in the lower plating layer 9ZA, and can be distributed over the entire surface of the lower plating layer 9ZA. As shown in FIG. 2B, the voids KZ are present in the lower plating layer 9ZA in a closed state when viewed from the cross section. The voids KZ may be distributed in layers over the entire surface of the surface M2. The voids KZ can be provided in the lower plating layer 9ZA present on different surfaces of the element 2. For example, the voids KZ can be provided in a pair of surfaces in the stacking direction DS, a pair of surfaces in the length direction DL, and a pair of surfaces in the width direction DW in FIG. 1.

[0053] The metal oxide MZ is an oxide of a metal contained in the lower plating layer 9ZA. For example, when the lower plating layer 9ZA is a Cu plating layer, the metal oxide MZ is CuO or Cu2O. The metal oxide MZ is present inside the void KZ or at a position in contact with the void KZ. Here, when the metal oxide MZ is present inside the void KZ or at a position in contact with the void KZ, the metal oxide MZ captures hydrogen, and can further suppress the diffusion of hydrogen into the element body 2.

[0054] Fig. 3 is a flow chart showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment, and Figs. 4A to 4L are cross-sectional views showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. Figs. 4C to 4L show an example in which three layers of internal electrode layers 3A and 3B are alternately laminated with dielectric layers 4 interposed therebetween. Figs. 4I to 4K show an enlarged view of the configuration of region R2' of the conductive layer 8. Fig. 4L shows an enlarged view of the configuration of region R2 of the external electrode 6A.

[0055] In S1 of FIG. 3, an organic binder and an organic solvent as a dispersant and a molding aid are added to a dielectric material powder, and the powder is pulverized and mixed to generate a mud-like slurry. The dielectric material powder includes, for example, a ceramic powder. The dielectric material powder may include an additive. The additive is, for example, an oxide or glass of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder is, for example, a polyvinyl butyral resin or a polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0056] Next, as shown in S2 of Fig. 3 and Fig. 3A, the slurry containing ceramic powder is applied in a sheet form onto a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry can be applied by a doctor blade method, a die coater method, a gravure coater method, or the like.

[0057] Next, as shown in S3 of FIG. 3 and FIG. 4B, the conductive paste for the internal electrodes is applied to the green sheets 24 of the layers forming the internal electrode layers 3A and 3B among the plurality of green sheets in a predetermined pattern to form the internal electrode patterns 23. At this time, a plurality of internal electrode patterns 23 separated in the longitudinal direction of the green sheets 24 can be formed on one green sheet 24. The conductive paste for the internal electrodes contains powder of the metal used as the material for the internal electrode layers 3A and 3B. For example, when the metal used as the material for the internal electrode layers 3A and 3B is Ni, the conductive paste for the internal electrodes contains Ni powder. The conductive paste for the internal electrodes also contains a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for the internal electrodes may contain a ceramic material, which is the main component of the dielectric layer 4, as a common material. The conductive paste for the internal electrodes can be applied by screen printing, inkjet printing, gravure printing, or the like.

[0058] Next, as shown in S4 of Fig. 3 and Fig. 4C, a laminated block is prepared by stacking a plurality of green sheets 24 on which the internal electrode pattern 23 is formed and green sheets 25A, 25B for outer layers on which the internal electrode pattern 23 is not formed, in a predetermined order. The thickness of the green sheets 25A, 25B for outer layers is greater than the thickness of the green sheet 24 on which the internal electrode pattern 23 is formed. At this time, the green sheets 24 adjacent in the stacking direction are stacked so that the internal electrode patterns 23A, 23B are alternately shifted in the longitudinal direction of the green sheets 24. Also, there are a portion where only the internal electrode pattern 23A is stacked in the stacking direction, a portion where the internal electrode patterns 23A, 23B are alternately stacked in the stacking direction, and a portion where only the internal electrode pattern 23B is stacked in the stacking direction.

[0059] Next, as shown in S5 of Fig. 3 and Fig. 4D, the laminated block obtained in the molding step S4 of Fig. 3 is pressed to pressure-bond the green sheets 24, 25A, and 25B. As a method for pressing the laminated block, for example, a method of isostatically pressing the laminated block can be used.

[0060] Next, as shown in S6 of Fig. 3 and Fig. 4E, the laminated block pressed in the pressure bonding step of S5 of Fig. 3 is cut and divided into rectangular parallelepiped elements. The laminated block is cut at a portion where only the internal electrode patterns 23A are stacked in the stacking direction and at a portion where only the internal electrode patterns 23B are stacked in the stacking direction. For example, a method such as blade dicing can be used to cut the laminated block.

[0061] At this time, as shown in Fig. 4F, the singulated element body 2' has internal electrode layers 3A, 3B alternately stacked with dielectric layers 4 interposed therebetween, and cover layers 5A, 5B are formed on the bottom and top layers. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 on one side surface of the element body 2', and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 on the other side surface of the element body 2'. Note that Fig. 4F shows one singulated element body of Fig. 4E enlarged in the length direction.

[0062] Next, as shown in S7 of Fig. 3 and Fig. 4G, the element body 2' is chamfered to form an element body 2 having curved surfaces R at its corners. The element body 2' can be chamfered by barrel polishing, for example.

[0063] Next, as shown in S8 of Fig. 3, the binder contained in the element body 2 chamfered in S7 of Fig. 3 is removed. In order to remove the binder, the element body 2 is heated in an N2 atmosphere at about 350°C, for example.

[0064] Next, as shown in S9 of FIG. 3, a conductive paste for the base layer is applied to both side surfaces of the element body 2 from which the binder has been removed in S8 of FIG. 3 and the four peripheral surfaces (upper, lower, front and rear surfaces) of each side surface, and then dried. For example, a dipping method can be used to apply the conductive paste for the base layer. The conductive paste for the base layer contains a powder or filler of a metal used as a conductive material for the base layer 7. For example, when the metal used as the conductive material for the base layer 7 is Ni, the conductive paste for the base layer contains a powder or filler of Ni. The conductive paste for the base layer also contains, as a common material, a ceramic component that is the main component of the dielectric layer 4. For example, the conductive paste for the base layer contains particles of an oxide ceramic mainly composed of barium titanate (for example, 0.8 μm to 4 μm in D50 particle size) as a common material. The conductive paste for the base layer also contains a binder and a solvent.

[0065] Next, as shown in S10 of FIG. 3 and FIG. 4H, the element body 2 coated with the conductive paste for the underlayer in S9 of FIG. 3 is fired to integrate the internal electrode layers 3A, 3B and the dielectric layer 4, and to form the underlayer 7 integrated with the element body 2. At this time, the underlayer 7 is electrically connected to the internal electrode layers 3A, 3B drawn out to the surface of the element body 2. The element body 2 and the conductive paste for the underlayer are fired, for example, in a firing furnace at 1000 to 1400° C. for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A, 3B, firing can be performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B.

[0066] Next, as shown in S11 of Fig. 3 and Fig. 4I, an underlayer plating layer 9A is formed on underlayer 7. At this time, element body 2 on which underlayer 7 has been formed is placed in a barrel together with a plating solution, and electricity is passed through the barrel while rotating, thereby forming underlayer plating layer 9A.

[0067] Next, as shown in S12 of FIG. 3 and FIG. 4J, the element body 2 having the lower plating layer 9A formed on the underlayer 7 is heated in a non-oxidizing atmosphere, then exposed to an oxidizing atmosphere while maintaining this temperature, and then cooled back to the non-oxidizing atmosphere. By such treatment, the surface side of the lower plating layer 9A is rapidly oxidized at high temperature, and the oxidation of the surface side of the lower plating layer 9A is stopped, so that a metal oxide MZ is formed on the surface side of the lower plating layer 9A. The time and temperature for exposing the lower plating layer 9A to the oxidizing atmosphere can be set so that the surface side of the lower plating layer 9A is non-uniformly oxidized, and the oxidation can be stopped before the oxidation of the surface side of the lower plating layer 9A becomes uniform. For example, in the oxidation treatment of the surface side of the lower plating layer 9A, the temperature is raised to 500° C. in an N2 atmosphere, and then the atmosphere is changed to air while maintaining this temperature, and this state is maintained for 2 minutes, and then the atmosphere is returned to the N2 atmosphere for cooling.

[0068] Next, as shown in S13 of FIG. 3 and FIG. 4K, the metal oxide MZ on the surface side of the lower plating layer 9A is removed by a method such as wet etching. For example, a dilute sulfuric acid solution can be used for wet etching of the metal oxide MZ. At this time, the metal oxide MZ is formed not only on the surface of the lower plating layer 9A but also in the thickness direction thereof, mixed with the metal contained in the lower plating layer 9A. Therefore, the metal oxide MZ is removed from the portion where the metal and the metal oxide MZ are mixed, and thus a void KJ is formed in the lower plating layer 9A. Note that the metal oxide MZ may not be entirely removed, but may be partially left. If the metal oxide MZ is present inside the void KJ or in a position in contact with the void KJ, the metal oxide MZ can capture hydrogen and further suppress diffusion.

[0069] The size of the void KJ may be 0.5 um or more and 6.5 um or less. The distance in the thickness direction from the surface of the lower plating layer 9A where the void KJ exists may be 0.1 um or more and 3.0 um or less. In this case, the porosity of the surface side of the lower plating layer 9A may be greater than the porosity of other regions of the lower plating layer 9A. The ratio of the length in the plane direction to the length in the thickness direction of the lower plating layer 9A may be 1 or more and 10 or less. In this case, more voids KJ whose length in the direction parallel to the plane of the lower plating layer 9A is longer than the length in the perpendicular direction are formed than voids KJ whose length in the direction parallel to the plane of the lower plating layer 9A is shorter than the length in the perpendicular direction.

[0070] Next, as shown in S14 of FIG. 3 and FIG. 4L, the upper plating layer 9B and the exterior plating layer 9C are sequentially formed on the lower plating layer 9A. At this time, the element 2 on which the lower plating layer 9A having the void KJ on the surface side is placed in a barrel together with a plating solution, and the barrel is rotated while current is applied, so that the upper plating layer 9B and the exterior plating layer 9C can be sequentially formed. Here, by providing the void KJ on the surface side of the lower plating layer 9A, it is possible to effectively suppress the diffusion of hydrogen generated when the upper plating layer 9B containing Ni is formed on the lower plating layer 9A toward the element 2 side, and the deterioration of the insulation property of the dielectric layer 4 can be suppressed. Such an effect of suppressing the diffusion of hydrogen is not only exhibited during the process of forming the upper plating layer 9B, but also has an effect of suppressing the diffusion of hydrogen remaining in the upper plating layer 9B toward the element 2 side over time. Note that the upper plating layer 9B may enter into a part of the void KJ, but this does not affect the basic characteristics of the part.

[0071] Second embodiment FIG. 5 is a cross-sectional view showing an example of the configuration of a circuit board on which the multilayer ceramic capacitor in accordance with the second embodiment is mounted. 5, land electrodes 12A, 12B are formed on a circuit board 11. The circuit board 11 may be a printed circuit board or a semiconductor substrate such as Si. The multilayer ceramic capacitor 1A is connected to the land electrodes 12A, 12B via the solder layers 13A, 13B attached to the exterior plating layers 9C of the external electrodes 6A, 6B.

[0072] Here, by providing the gap KJ in the lower plating layer 9A, the stress applied to the external electrodes 6A, 6B can be absorbed by the gap KJ. Therefore, even if stress is applied to the external electrodes 6A, 6B due to bending or expansion / contraction of the circuit board 11, the stress can be prevented from being transmitted to the element body 2 via the external electrodes 6A, 6B, and the occurrence of cracks in the element body 2 can be prevented.

[0073] Third embodiment Fig. 6 is a cross-sectional view taken along the length of the multilayer ceramic capacitor in accordance with the third embodiment, showing an enlarged view of the configuration of a region R3 of an external electrode 6A'. In FIG. 6, a multilayer ceramic capacitor 1B includes external electrodes 6A' and 6B' instead of the external electrodes 6A and 6B in FIG. 2A.

[0074] The external electrodes 6A', 6B' are formed on the element body 2 so as to face each other and be separated from each other in the longitudinal direction DL. Here, each of the external electrodes 6A', 6B' is formed continuously from the lower surface side of the element body 2 via the side surfaces to the upper surface side of the element body 2. Furthermore, each of the external electrodes 6A', 6B' may also be formed on the front and rear surfaces of the element body 2 that are perpendicular to both the lower surface and the side surfaces and face each other.

[0075] Each external electrode 6A', 6B' comprises an underlayer 7' connected to the respective internal electrode 3A, 3B and having more gaps KJ' on a surface M2' farther from the element body than on a surface M1' closer to the element body 2, a plating layer 9B' containing Ni, and a solder-wettable exterior plating layer 9C'. Note that surface M1' is located at the boundary between the underlayer 7' and the element body 2, and surface M2' can be located at the boundary between the underlayer 7' and plating layer 9B'.

[0076] The underlayers 7' are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. In this case, the underlayers 7' are formed continuously from the lower surface side of the element body 2 through the side surfaces to the upper surface side for each of the external electrodes 6A', 6B'. Note that the underlayers 7' may also be formed continuously from the lower surface side of the element body 2 to the front surface side and rear surface side for each of the external electrodes 6A', 6B'.

[0077] The voids KJ' can be provided in the underlayer 7' and distributed over the entire surface direction of the underlayer 7'. The voids KJ' may be distributed in a layered manner over the entire surface direction of the surface M2'. The underlayer 7' may contain a metal capable of forming an oxide corresponding to the shape of the voids KJ'. The voids KJ' can be provided over the entire surface side of the underlayer 7' present on different surfaces of the element body 2. The surface side of the underlayer 7' is the surface side on which the plating layer 9B' is formed. For example, the voids KJ' may be provided not only on the surface side of the underlayer 7' normalized in the length direction DL, but also on the surface side of the underlayer 7' normalized in the width direction DW, or on the surface side of the underlayer 7' normalized in the stacking direction DS.

[0078] At this time, before the plating layer 9B' is formed on the surface side of the underlayer 7', the metal contained in the underlayer 7' is non-uniformly oxidized while the surface side of the underlayer 7' is exposed to an oxidizing atmosphere, and the metal oxide is removed, so that voids KJ' can be formed on the surface side of the underlayer 7'. Here, in order to non-uniformly oxidize the metal contained in the underlayer 7', the surface side of the underlayer 7' can be rapidly oxidized. The voids KJ' can be distributed in a spongy or porous manner on the surface side of the underlayer 7'. That is, there are more voids in the region on the surface side of the underlayer 7' than in other regions.

[0079] In this case, the underlayer 7' may be mainly composed of a metal or alloy containing at least one selected from Cu, Fe, Zn, Sn, Pb, and Cr. By using Cu as the metal of the underlayer 7', the adhesion between the underlayer 7' and the plating layer 9B' can be improved while good electrical conductivity can be obtained, and gaps KJ' can be formed on the surface side of the underlayer 7'. The underlayer 7' may contain a common material in which a metal is mixed. The main component of the common material is, for example, a ceramic component that is the same as the main component of the dielectric layer 4. The underlayer 7' may contain a glass component. Here, the underlayer 7' is preferably composed of a sintered body obtained by applying a metal paste and then firing it.

[0080] The thickness of the underlayer 7' is preferably 2 um or more and 50 um or less. The voids KJ' are preferably located in a range of 0.1 μm or more and 3.0 μm or less from the surface of the underlayer 7' in the thickness direction. The voids KJ' are preferably longer in the plane direction than in the thickness direction of the underlayer 7'. It is preferable that there are more voids KJ' whose length in the plane direction is longer than the length in the thickness direction of the underlayer 7' than those whose length in the plane direction is shorter than the length in the thickness direction of the underlayer 7'. The longitudinal length of the voids KJ' is preferably 0.5 μm or more and 6.5 μm or less. It is preferable that voids KJ' whose length in the plane direction is four times or more the length in the thickness direction of the underlayer 7' are present at a frequency of 50% or more of the total.

[0081] The plating layer 9B' is formed on the underlayer 7'. The plating layer 9B' is, for example, a Ni plating layer. The exterior plating layer 9C' is formed on the plating layer 9B'. The exterior plating layer 9C' is, for example, a Sn plating layer.

[0082] Here, by providing the gap KJ' on the surface side of the underlayer 7', the diffusion of hydrogen generated when forming the plating layer 9B' on the underlayer 7' can be suppressed at the position of the gap KJ'. The diffusion of hydrogen proceeds using the underlayer 7' as a medium, but since the gap KJ' hardly functions as a diffusion medium, the diffusion of hydrogen hardly proceeds toward the element body 2. Therefore, it is possible to suppress the diffusion of hydrogen generated when forming the plating layer 9B' on the underlayer 7' into the element body 2, suppress the hydrogen reduction of the dielectric layer 4 between the internal electrode layers 3A, 3B, and suppress the deterioration of the insulation of the dielectric layer 4.

[0083] FIG. 7 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the third embodiment. In steps S21 to S28 in FIG. 7, an element body 2 from which the binder has been removed is produced by steps similar to those in steps S1 to S8 in FIG.

[0084] 7, the element body 2 from which the binder has been removed in S28 of Fig. 7 is fired to integrate the internal electrode layers 3A, 3B with the dielectric layer 4. The element body 2 is fired, for example, in a firing furnace at 1000 to 1350°C for 10 minutes to 2 hours.

[0085] Next, as shown in S30 of FIG. 7, a conductive paste for the base layer is applied to both end faces and the four peripheral faces of each end face of the element body 2 fired in S28 of FIG. 7, and then dried. The conductive paste for the base layer contains a powder or filler of a metal used as a conductive material for the base layer 7'. For example, when the metal used as the conductive material for the base layer 7' is Cu, the conductive paste for the base layer contains a powder or filler of Cu. The conductive paste for the base layer may also contain, for example, a ceramic component that is the main component of the dielectric layer 4 as a co-material. The conductive paste for the base layer also contains a binder and a solvent. Cu is preferable for the base layer 7' because it provides good conductivity.

[0086] Next, the conductive paste for the underlayer applied to the element body 2 is fired to form a underlayer 7' integrated with the element body 2. The conductive paste for the underlayer is fired, for example, in a firing furnace at 850° C. for 15 minutes or more.

[0087] Next, as shown in S31 of FIG. 7, the element body 2 on which the underlayer 7' is formed is heated in a non-oxidizing atmosphere, then exposed to an oxidizing atmosphere while maintaining this temperature, and then returned to the non-oxidizing atmosphere to cool. By such a treatment, the surface side of the underlayer 7' is rapidly oxidized at high temperature, and then the oxidation of the surface side of the underlayer 7' is stopped, so that a metal oxide is formed on the surface side of the underlayer 7'. The time and temperature for exposing the underlayer 7' to the oxidizing atmosphere can be set so that the surface side of the underlayer 7' is non-uniformly oxidized, and the oxidation can be stopped before the oxidation of the surface side of the underlayer 7' is uniformed. For example, in the oxidation treatment of the surface side of the underlayer 7', the temperature is raised to 500°C in an N2 atmosphere, and then the atmosphere is changed to air while maintaining this temperature, and this state is maintained for 2 minutes, and then the atmosphere is returned to the N2 atmosphere to cool.

[0088] Next, as shown in S32 of FIG. 7, the metal oxide on the surface side of the underlayer 7' is removed by a method such as wet etching. For example, a dilute sulfuric acid solution can be used for the wet etching of the metal oxide. At this time, the metal oxide is formed not only on the surface of the underlayer 7' but also in the thickness direction thereof, mixed with the metal contained in the underlayer 7'. Therefore, the metal oxide is removed from the portion where the metal and the metal oxide are mixed, and thus the void KJ' is formed in the underlayer 7'. Note that the metal oxide may not be entirely removed, but may be partially left. If the metal oxide is present inside the void KJ' or in a position in contact with the void KJ', the metal oxide can capture hydrogen and further suppress diffusion.

[0089] The size of the void KJ' can be 0.5 um or more and 6.5 um or less. The distance in the thickness direction from the surface of the underlayer 7' where the void KJ' exists can be 0.1 um or more and 3.0 um or less. In this case, the porosity on the surface side of the underlayer 7' can be made larger than the porosity in other regions of the underlayer 7'. The ratio of the length in the plane direction to the length in the thickness direction of the underlayer 7' can be 1 or more and 4 or less. In this case, more voids KJ' whose length in the direction parallel to the plane of the underlayer 7' is longer than the length in the perpendicular direction are formed than those whose length in the direction parallel to the plane of the underlayer 7' is shorter than the length in the perpendicular direction.

[0090] Next, as shown in S33 of Fig. 7, plating layer 9B' and exterior plating layer 9C' are successively formed on base layer 7'. At this time, the element body 2 on which base layer 7' having voids KJ' on the surface side is placed in a barrel together with a plating solution, and the barrel is rotated while current is applied, thereby successively forming plating layer 9B' and exterior plating layer 9C'. Plating layer 9B' is, for example, a Ni plating layer, and exterior plating layer 9C' is, for example, a Sn plating layer. Note that plating layer 9B' may enter part of voids KJ', but this does not affect the basic characteristics of the part.

[0091] (Fourth embodiment) Fig. 8 is a cross-sectional view taken along the length of the multilayer ceramic capacitor in accordance with the fourth embodiment, showing an enlarged view of the configuration of a region R4 of an external electrode 6JA. In FIG. 8, a multilayer ceramic capacitor 1C includes external electrodes 6JA and 6JB instead of the external electrodes 6A and 6B in FIG. 2A.

[0092] The external electrodes 6JA, 6JB are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. Here, each external electrode 6JA, 6JB is formed continuously from the lower surface side of the element body 2 via the side surface to the upper surface side of the element body 2. In addition, each external electrode 6JA, 6JB may also be formed on the front and rear surfaces of the element body 2 that are perpendicular to both the lower surface and the side surface and face each other.

[0093] Each of the external electrodes 6JA, 6JB includes a conductive layer 8J connected to each of the internal electrodes 3A, 3B and having more voids KJ on the surface MJ2 side farther from the element body 2 than on the surface MJ1 side closer to the element body 2, a conductive resin layer 9D, and a plating layer 9J containing Ni. The surface MJ1 can be located at the boundary between the conductive layer 8J and the element body 2, and the surface MJ2 can be located at the boundary between the conductive layer 8J and the conductive resin layer 9D. The conductive layer 8J is formed on the element body 2, the conductive resin layer 9D is formed on the conductive layer 8J, and the plating layer 9J is formed on the conductive resin layer 9D. The conductive layer 8J includes a base layer 7J provided on the element body 2, and a lower plating layer 9JA having voids KJ on the surface MJ2 side. The plating layer 9J includes an upper plating layer 9JB containing Ni, and an exterior plating layer 9JC that is solder wettable.

[0094] The undercoat layer 7J and undercoat layer 9JA can be configured similarly to the undercoat layer 7 and undercoat layer 9A in Fig. 2A, except that the undercoat layer 7J and undercoat layer 9JA extend from the side surface of the element body 2 to the lower, upper, front and rear surfaces.

[0095] When the underlayer 7J is a sintered layer mainly composed of Ni, the tip angle α can be adjusted by changing the viscosity of the Ni paste, the ratio of the co-material or the ratio of the additive, or by changing the temperature profile during sintering. Also, when the underlayer plating layer 9A is an electrolytic plating layer containing Cu, the tip angle β can be adjusted by changing conditions such as the pH of the plating solution, the temperature of the plating solution, the plating current density, or the plating time.

[0096] The conductive resin layer 9D is located between the conductive layer 8J and the plating layer 9J. The thickness of the conductive resin layer 9D is preferably 2 um or more and 40 um or less. The main component of the conductive resin layer 9D is, for example, a mixture of a thermosetting resin selected from epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc., and a conductive filler of a metal or alloy containing at least one selected from copper, tin, nickel, silver, gold, and zinc. The form of the conductive filler is spherical, flat, or fibrous, but is not particularly limited as long as the form can ensure conductivity. The conductive resin layer 9D can be formed by applying a conductive resin paste so that the lower plating layer 9JA is covered by a dipping method, a printing method, etc., and then thermally curing the paste. The material of the conductive filler preferably contains silver in terms of conductivity.

[0097] The upper plating layer 9JB is formed on the conductive resin layer 9D. The exterior plating layer 9JC is formed on the upper plating layer 9JB. The upper plating layer 9JB and the exterior plating layer 9JC can be configured similarly to the upper plating layer 9B and the exterior plating layer 9C in FIG. 2A. For example, the upper plating layer 9JB is a Ni plating layer, and the exterior plating layer 9JC is a Sn plating layer.

[0098] Here, by providing the gap KJ on the surface side of the lower plating layer 9JA, the diffusion of hydrogen generated when the upper plating layer 9JB is formed on the conductive resin layer 9D can be suppressed at the position of the gap KJ. The surface side of the lower plating layer 9JA is the surface side on which the conductive resin layer 9D is formed. The diffusion of hydrogen proceeds using the lower plating layer 9JA as a medium, but the gap KJ hardly functions as a diffusion medium, so that the diffusion of hydrogen hardly proceeds toward the element body 2 side. Therefore, the diffusion of hydrogen generated when the upper plating layer 9JB is formed on the conductive resin layer 9D can be suppressed from diffusing into the element body 2, and the hydrogen reduction of the dielectric layer 4 between the internal electrode layers 3A and 3B can be suppressed, and the deterioration of the insulation of the dielectric layer 4 can be suppressed. Other configuration examples and effects related to the gap KJ are the same as those described in the first embodiment.

[0099] Furthermore, by providing the conductive resin layer 9D between the conductive layer 8J and the upper plating layer 9J, the stress applied to the external electrodes 6JA, 6JB can be absorbed by the conductive resin layer 9D. Therefore, even if stress is applied to the external electrodes 6JA, 6JB due to bending or expansion / contraction of the circuit board on which the multilayer ceramic capacitor 1C is mounted, the stress can be prevented from being transmitted to the element body 2 via the external electrodes 6JA, 6JB, and the occurrence of cracks in the element body 2 can be prevented.

[0100] Fifth embodiment Fig. 9 is a cross-sectional view taken along the length of the multilayer ceramic capacitor in accordance with the fifth embodiment, showing an enlarged view of the configuration of a region R5 of an external electrode 6JA'. In FIG. 9, a multilayer ceramic capacitor 1D includes external electrodes 6JA' and 6JB' instead of the external electrodes 6A' and 6B' in FIG.

[0101] The external electrodes 6JA', 6JB' are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. Here, each external electrode 6JA', 6JB' is formed continuously from the lower surface side of the element body 2 via the side surface to the upper surface side of the element body 2. Furthermore, each external electrode 6JA', 6JB' may also be formed on the front and rear surfaces of the element body 2 that are perpendicular to both the lower surface and the side surface and face each other.

[0102] Each external electrode 6JA', 6JB' includes an underlayer 7J' connected to each internal electrode 3A, 3B and having more gaps KJ' on a surface MJ2' farther from the element body 2 than on a surface MJ1' closer to the element body 2, a conductive resin layer 9D', a plating layer 9JB' containing Ni, and a solder-wettable exterior plating layer 9JC'. The surface MJ1' can be located at the boundary between the underlayer 7J' and the element body 2, and the surface MJ2' can be located at the boundary between the underlayer 7J' and the conductive resin layer 9D'. The underlayer 7' is formed on the element body 2, the conductive resin layer 9D' is formed on the underlayer 7', and the plating layer 9JB' is formed on the conductive resin layer 9D'.

[0103] 6. However, the underlayer 7J' wraps around from the side surface of the element body 2 to the bottom, top, front and rear surfaces. In this case, the thickness of the underlayer 7J' is preferably 2 um or more and 40 um or less.

[0104] When the underlayer 7J' is a sintered layer containing Cu as a main component, the tip angle γ can be adjusted by changing the viscosity of the Cu paste, the ratio of the co-material or the ratio of the additive, as well as by changing the temperature profile during sintering.

[0105] The conductive resin layer 9D' is located between the underlayer 7J' and the plating layer 9JB'. The conductive resin layer 9D' can be configured in the same manner as the conductive resin layer 9D in FIG.

[0106] Plating layer 9JB' is formed on conductive resin layer 9D'. Exterior plating layer 9JC' is formed on plating layer 9JB'. Plating layer 9JB' and exterior plating layer 9JC' can be configured similarly to upper plating layer 9JB and exterior plating layer 9JC in FIG. 8. For example, plating layer 9JB' is a Ni plating layer, and exterior plating layer 9JC' is a Sn plating layer.

[0107] Here, by providing the gap KJ' on the surface side of the underlayer 7J', the diffusion of hydrogen generated when forming the plating layer 9JB' on the conductive resin layer 9D' can be suppressed at the position of the gap KJ'. The surface side of the underlayer 7J' is the surface side on which the conductive resin layer 9D' is formed. The diffusion of hydrogen proceeds using the underlayer 7J' as a medium, but the gap KJ' hardly functions as a diffusion medium, so the diffusion of hydrogen hardly proceeds toward the element body 2. Therefore, the diffusion of hydrogen generated when forming the plating layer 9JB' on the conductive resin layer 9D' can be suppressed from diffusing to the element body 2, and the hydrogen reduction of the dielectric layer 4 between the internal electrode layers 3A and 3B can be suppressed, and the deterioration of the insulation of the dielectric layer 4 can be suppressed. Other configuration examples and effects related to the gap KJ' are the same as those described in the third embodiment.

[0108] Furthermore, by providing the conductive resin layer 9D' between the underlayer 7J' and the plating layer 9JB', the stress applied to the external electrodes 6JA', 6JB' can be absorbed by the conductive resin layer 9D'. Therefore, even if stress is applied to the external electrodes 6JA', 6JB' due to bending or expansion / contraction of the circuit board on which the multilayer ceramic capacitor 1D is mounted, the stress can be prevented from being transmitted to the element body 2 via the external electrodes 6JA', 6JB', and the occurrence of cracks in the element body 2 can be prevented.

[0109] Sixth embodiment Fig. 10 is a perspective view showing an example of the configuration of a ceramic electronic component according to a sixth embodiment. In Fig. 10, a chip inductor is taken as an example of the ceramic electronic component. In Fig. 10, the chip inductor 21 comprises an element body 22 and external electrodes 26A, 26B. The element body 22 comprises a coil pattern 23, internal electrode layers 23A, 23B, and a magnetic material 24. The magnetic material 24 is also used as a dielectric to insulate the internal electrode layers 23A, 23B. The element body 22 may be shaped like a substantially rectangular parallelepiped. The external electrodes 26A, 26B are located on opposing side surfaces of the element body 22 and are separated from each other. Each of the external electrodes 26A, 26B is continuous from each side surface of the element body 22 to the front and rear surfaces and the top and bottom surfaces.

[0110] The coil pattern 23 and the internal electrode layers 23A, 23B are covered with a magnetic material 24. However, an end of the internal electrode layer 23A is exposed from the magnetic material 24 on one side surface of the element body 22 and is connected to an external electrode 26A. An end of the internal electrode layer 23B is exposed from the magnetic material 24 on the other side surface of the element body 22 and is connected to an external electrode 26B.

[0111] The material of the coil pattern 23 and the internal electrode layers 23A, 23B can be selected from metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or may be an alloy containing these metals. The magnetic material 24 is, for example, ferrite.

[0112] Each of the external electrodes 26A, 26B can be configured in the same manner as the external electrodes 6A, 6B in Fig. 1. That is, each of the external electrodes 26A, 26B includes a conductive layer connected to each of the internal electrodes 23A, 23B and having more voids on the side farther from the element body 22 than on the side closer to the element body 22, and a plating layer containing Ni. This makes it possible to suppress the diffusion of hydrogen generated when a plating layer is formed on the conductive layer at the positions of the voids, and to suppress the diffusion of hydrogen generated when a plating layer is formed on the conductive layer into the element body 22.

[0113] Each external electrode 26A, 26B may be configured similarly to external electrodes 6A', 6B' in FIG. 6, or may be configured similarly to external electrodes 6JA, 6JB in FIG. 8, or may be configured similarly to external electrodes 6JA', 6JB' in FIG.

[0114] In the above-described embodiment, a multilayer ceramic capacitor and a chip inductor are used as examples of electronic components, but a chip resistor or a sensor chip may be used. In addition, in the above-described embodiment, a component having two external electrodes is used as an example of an electronic component, but an electronic component having three or more external electrodes may be used.

[0115] In addition, the size, location, frequency, etc. of the voids described in each embodiment can be confirmed by measuring each item for, for example, 20 voids randomly selected from a portion of the cross-section of the external electrode, and using the average value.

[0116] (Example) A highly accelerated life test (HALT) was conducted at a high temperature and high electric field of 150°C and 40V / μm for the multilayer ceramic capacitors 1A to 1D (Examples 1 to 4) shown in Figures 2A, 6, 8, and 9 to measure the mean time to failure (MTTF). At this time, a Cu underlayer, a Ni plating layer, and a Sn plating layer were used as the underlayer 7', plating layer 9B', and exterior plating layer 9C' shown in Figure 6, and a comparative example was shown in which the Cu underlayer was not oxidized and the oxide was not removed.

[0117] The following results were obtained for the above Examples 1 to 4 and Comparative Example. Example 1 MTTF: 450 min MTTF of Example 2: 350 min MTTF of Example 3: 470 min MTTF of Example 4: 390 min Comparison example MTTF: 275min From the above results, it was found that in any of Examples 1 to 4, by providing a gap below the Ni-containing plating layer, the MTTF can be increased compared to a configuration (comparison example) in which there is no gap below the Ni-containing plating layer. [Explanation of symbols]

[0118] 1A Multilayer Ceramic Capacitor 2 Base 2A laminate 3A, 3B Internal electrode layer 4 Dielectric Layer 5A, 5B Cover Layer 6A, 6B external electrode 7 Base layer 8 Conductive Layer 9 Plating layer

Claims

1. An element body having a dielectric and an internal electrode; an external electrode formed on the element body, connected to the internal electrode, and having a conductive layer with more voids on a surface farther from the element body than on a surface closer to the element body; A ceramic electronic component, characterized in that the conductive layer includes an oxide of a metal contained in the conductive layer inside the void or at a position in contact with the void.

2. The ceramic electronic component according to claim 1 , wherein the external electrodes further comprise a plating layer containing Ni formed on the conductive layer.

3. 3. The ceramic electronic component according to claim 1, wherein the voids are located within a range of 0.1 μm to 3.0 μm in a thickness direction from the surface of the conductive layer farthest from the element body.

4. 4. The ceramic electronic component according to claim 1, wherein the length of the gap in the planar direction of the conductive layer is longer than the length in the thickness direction of the conductive layer.

5. The ceramic electronic component according to any one of claims 1 to 4, characterized in that a plurality of the voids are provided in the conductive layer, and there are more voids whose length in the planar direction is longer than the length in the thickness direction of the conductive layer than voids whose length in the planar direction is shorter than the length in the thickness direction of the conductive layer.

6. 6. The ceramic electronic component according to claim 1, wherein the length of the void in the longitudinal direction is 0.5 μm or more and 6.5 μm or less.

7. The ceramic electronic component according to any one of claims 1 to 6, characterized in that a plurality of voids are provided in the conductive layer, and voids whose length in the planar direction is four or more times the length in the thickness direction of the conductive layer are present at a frequency of 50% or more.

8. The conductive layer is a base layer formed on the element body, connected to the internal electrodes, and including a conductor; 8. The ceramic electronic component according to claim 1, further comprising an underlayer plating layer formed on the base layer and having more voids on a side farther from the element body than on a side closer to the element body.

9. 9. The ceramic electronic component according to claim 8, wherein the lower plating layer is mainly composed of a metal or an alloy containing at least one selected from the group consisting of Cu, Fe, Zn, Sn, Pb, and Cr.

10. 10. The ceramic electronic component according to claim 9, wherein the main component of the lower plating layer is Cu.

11. Regarding the external electrodes, The main component of the underlayer is Ni, a Ni plating layer formed on the underlayer plating layer; 11. The ceramic electronic component according to claim 10, further comprising a Sn plating layer formed on the Ni plating layer.

12. An element body having a dielectric and an internal electrode; an external electrode formed on the element body, connected to the internal electrode, and having a conductive layer with more voids on a surface farther from the element body than on a surface closer to the element body; a conductive layer provided on the base body, connected to the internal electrode, and having a larger number of voids on a surface farther from the base body than on a surface closer to the base body, the conductive layer comprising a base layer formed on the base body and connected to the internal electrode;

13. Regarding the external electrodes, The main component of the underlayer is Cu, A Ni plating layer formed on the underlayer; The ceramic electronic component according to claim 12, further comprising a Sn plating layer formed on the Ni plating layer.

14. The ceramic electronic component according to claim 1 , wherein the external electrodes further comprise a conductive resin layer provided on the conductive layer.

15. The conductive layer is a base layer formed on the element body, connected to the internal electrodes, and containing Ni; a Cu plating layer formed on the underlayer, the Cu plating layer having more voids on a surface side farther from the element body than on a surface side closer to the element body; The external electrode is A Ni plating layer formed on the conductive resin layer; The ceramic electronic component according to claim 14, further comprising a Sn plating layer formed on the Ni plating layer.

16. the conductive layer includes a base layer formed on the element body, connected to the internal electrode, and including a Cu base layer having more voids on a surface farther from the element body than on a surface closer to the element body; The external electrode is A Ni plating layer formed on the conductive resin layer; The ceramic electronic component according to claim 14, further comprising a Sn plating layer formed on the Ni plating layer.

17. A circuit board on which the ceramic electronic component according to any one of claims 1 to 16 is mounted, The ceramic electronic component is mounted on the circuit board via a solder layer attached to the external electrodes.

18. forming an element body provided with a dielectric and internal electrodes; forming a conductive layer on the element body, the conductive layer being connected to the internal electrodes and having more voids on a surface farther from the element body than on a surface closer to the element body; forming a plating layer containing Ni on the conductive layer; The step of forming the conductive layer on the body includes: applying a base material for external electrodes to a plurality of surfaces of the element body; firing the base material to form a base layer for the external electrodes; a step of oxidizing a surface side of the underlayer while exposing it to an oxidizing atmosphere to form a metal oxide that is distributed more on a surface side farther from the element body than on a surface side closer to the element body; and forming voids in the underlayer by removing the metal oxide.

19. A method for manufacturing a ceramic electronic component as described in claim 18, characterized in that in the step of forming the void, a portion of the metal oxide is left inside the void or in a position adjacent to the void.

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