Ceramic materials for capacitors

Abstract

The present invention relates to a ceramic material for capacitors using layer-by-layer technology, the ceramic material having a composition according to the following general formula: Pb (y-1,5a-0,5b+c+0,5d-0,5e-f) Ca a A b (Zr 1-x Ti x ) (1-c-d-e-f) E c Fe d Nb e W f O3, where: A is one or more of the group consisting of Na, K, and Ag; E is one or more of the group consisting of Cu, Ni, Hf, Si and Mn; 0 <a<0.14、 0.05≦x≦0.3, 0≦b≦0.12, 0 <c≦0.12、 0≦d≦0.12, 0≦e≦0.12, 0≦f≦0.12, 0.9≦y≦1.5, and 0.001 <b+c+d+e+f holds true. The present invention further includes a capacitor comprising the ceramic material described above.

Description

[Technical field]

[0001] The present invention relates to a ceramic material for a capacitor using a lamination technique. [Background technology]

[0002] A ceramic capacitor includes at least two electrical conductors with a dielectric ceramic layer disposed therebetween, and the performance of the ceramic capacitor is substantially determined by the polarization characteristics of the ceramic dielectric.

[0003] Certain materials exhibit spontaneous polarization in the absence of an electric field. If the direction of the spontaneous polarization can be changed by applying an electric field, the material is called ferroelectric. If, during the phase transition from the paraelectric phase, the ions of the ferroelectric material move antiparallel to each other rather than parallel to each other, the material is called antiferroelectric.

[0004] The ceramic materials that have been mainly used for piezoelectric elements so far are lead zirconate titanate (Pb(Zr x Ti 1-x )O3 or PZT). This system is a solid solution (fully mixed crystal system) of antiferroelectric lead zirconate (PbZrO3) and ferroelectric lead titanate (PbTiO3, PTO), and depending on the composition, can exhibit both ferroelectric and antiferroelectric properties.

[0005] The phase diagram (Figure 1) shows how the Curie temperature and crystal symmetry of the PZT system depend on its composition. FT and FR are ferroelectric tetragonal or rhombohedral phases. PC indicates the paraelectric cubic phase. AO and AT represent the antiferroelectric orthorhombic or tetragonal phases. HT represents the high temperature phase and LT the low temperature phase.

[0006] Starting from pure PTO, the Curie point increases with successive substitutions of titanium ions by zirconium ions from the initial 490°C (T c (PTO)) to 230°C (T c(PZO)), where the symmetry changes from FT through FR to AO at room temperature. c Above that, the PZT is paraelectric.

[0007] Below the Curie temperature, a distortion of the cubic structure occurs. This deformation depends on the Zr / Ti ratio: Ti-rich PZT alloys are ferroelectric and tetragonal at room temperature. In contrast, Zr-rich PZT alloys are antiferroelectric and orthorhombic (O phase) or ferroelectric and rhombohedral.

[0008] PZT materials have been used so far mainly in piezoelectric elements, e.g. in piezoelectric actuators. The necessary piezoelectric properties are particularly evident at the so-called morphotropic phase boundary (MPB) which separates the two FE phases (FT and FR). The two different crystal structures form only depending on a small change in the Zr / Ti ratio. The MPB is 0,6 Ti 0,4 O3 and PbZr 0,55 Ti 0,45 It is located between O3. Summary of the Invention [Problem to be solved by the invention]

[0009] It is an object of embodiments of the present invention to provide a ceramic material having improved properties suitable for capacitors using layer-by-layer technology. [Means for solving the problem]

[0010] This problem is solved by a ceramic material for capacitors using layer-by-layer technology, which has the following general formula: Pb (y-1,5a-0,5b+c+0,5d-0,5e-f) Ca a A b (Zr 1-x Ti x ) (1-c-d-e-f) E c Fe d Nb e W f O3, Where: A is one or more of the group consisting of Na, K and Ag; E is one or more of the group consisting of Cu, Ni, Hf, Si and Mn; 0 <a<0.14、 0.05≦x≦0.3, 0≦b≦0.12, 0 <c≦0.12、 0≦d≦0.12, 0≦e≦0.12, 0≦f≦0.12, 0.9≦y≦1.5, and 0.001 <b+c+d+e+f holds true.

[0011] The claimed ceramic material is lead calcium zirconate titanate (PCZT), which has improved properties compared to PZT.

[0012] According to the invention, a particularly Zr-rich PZT mixed crystal phase is selected from the phase diagram. The Ca doping allows for a relatively high percentage of titanium in the ceramic while maintaining the desired antiferroelectric crystal structure.

[0013] The phase boundary shift upon Ca doping occurs similarly to the shift upon La doping, which has already been thoroughly investigated in the literature.

[0014] The dependence of the phase boundary at room temperature on the La content is shown in the second phase diagram (Figure 2). The boundary is between the antiferroelectric orthorhombic phase and the ferroelectric rhombohedral phase in pure PZT crystals containing less than 10% titanate at room temperature.

[0015] When at least a portion of the lead is replaced by lanthanum, the phase boundary described above is initially shifted in the direction of larger titanate proportions. A maximum is reached at a lanthanum doping of about 10-15 mol %. Here, antiferroelectric phases containing up to 35 mol % titanate are possible.

[0016] As the La content is further increased, the phase boundary with the paraelectric cubic phase again shifts toward smaller titanate fractions, and the maximum titanate content in the antiferroelectric phase is reached near the triple point between the AO, PC, and FT phases.

[0017] Furthermore, the condition b+c+d+e+f>0 determines the inclusion of at least one further dopant in the ceramic material according to the invention.

[0018] At least one further doping element is selected from group A defined in the main claim, which comprises the alkali metals Na and K as well as Ag; and from group E, which comprises Cu, Ni, Hf, Si and Mn. Further possible dopants are one or more of Fe, Nb and W. This allows the sintering temperature of the ceramic material to be reduced, which allows the combination with other raw materials / materials that are not stable at higher temperatures already during the manufacturing process of the ceramic material.

[0019] For example, it is possible to sinter the ceramic material together with internal electrodes made of metals such as silver or copper (a "co-firing" process).

[0020] Furthermore, low sintering temperatures promote the formation of small grain sizes in the ceramic material, which favors the dielectric properties. More precisely, the dielectric properties of PZT ceramics are generally also determined by the domain size. A domain is understood as an area in the ceramic that has the same polarization. The domain size depends on the grain size. The number of domains per grain increases with increasing grain size. The altered domain size affects the material properties of the ceramic. It is therefore worthwhile to control the grain size or grain growth.

[0021] Typically, lead zirconate titanate ceramics doped according to the present invention comprise a perovskite lattice described by the general formula ABO3, where A represents the A sites and B represents the B sites of the perovskite lattice.

[0022] The perovskite lattice is characterized by a large tolerance to doping and vacancies.

[0023] The unit cell of the PZT crystal lattice can be described as a cube. The A site is Pb 2+ ion or Ca 2+ ions, which are located on the edges of the cube. At the center of each cube face is one O 2- The ions are located in the center of the cube. 4+ ion or Zr 4+ ions (B site). This structure has a large tolerance for substitution of metal ions by other metal ions and defects, making it suitable for doping.

[0024] Depending on the size difference between the ions introduced by doping and those replaced, distortion of the highly symmetric coordination polyhedra can result, which can change the center of symmetry of the crystal and affect the polarizability.

[0025] The various doping possibilities can be classified based on the valence of the doping ions: isovalent doping, i.e. the replacement of one ion by another with the same valence, does not affect the vacancies that may be present in the ceramic material.

[0026] Substitution of low valence cations (acceptors) with higher valence cations creates vacancies in the anion lattice. High valence cations (donors) cause vacancies in the cation lattice when they replace low valence cations. Acceptor and donor doping each result in characteristic changes in material properties. Acceptor doped ceramics are called "hard" ceramics and donor doped ceramics are called "soft" ceramics.

[0027] Nd not according to the present invention to the A site 3+or equivalent rare earth element doping, e.g. donor doping. Due to the ionic radius of neodymium, this is Pb 2+ The doping effect is a metric change of the lattice as well as a longer acting interaction between the unit cells.

[0028] Dopants according to the invention for the A sites in the PZT lattice comprise, in addition to calcium ions, substances from group A according to the main claim.

[0029] The calcium contained in the ceramic according to the main claim is, due to its ionic radius, Pb 2+ Therefore, calcium ions are more suitable for doping PZT ceramics than, for example, lanthanum ions. 2+ and Ca 2+ Due to the equivalent charges of the ions, no charge balancing is required with A-site or O-site vacancies.

[0030] Ag 2+ The doping of ions is equivalent to iso-doping.

[0031] K to A site + or a + The doping of Pb is acceptor doping. Due to the ionic radius of potassium or sodium, this is similar to Pb 2+ The charge balance is 2+ This is done by reducing vacancies (A vacancies) and / or creating corresponding oxygen vacancies. The effect of doping is the formation of oxygen vacancies which promotes grain growth and sintering densification, which is induced by K or Na acceptors at the sintering temperature.

[0032] Additional doping, for example with Cu, Ni, Hf, Si, Mn, Fe, Nb and W ions, contributes to the control of additional vacancies or metric changes in the lattice and to the effect of longer acting interactions between unit cells.

[0033] Due to their ionic radii, the ions mentioned in the previous paragraph are incorporated into the B-site of the PZT lattice.

[0034] Doping of, for example, Fe into the B-site is acceptor doping. Charge balance is achieved by a reduction in Pb 3+ vacancies (A-vacancies) and / or the formation of corresponding oxygen vacancies. The effect of doping is also, here, the promotion of sintering densification and the control of electrical properties. 2+ 2+

[0035] Further acceptor doping is doping with Cu 2+ or Ni 2+ Typical donor doping is doping with Nb 5+ or W 6+ ions.

[0036] In an appropriate combination of acceptor doping and donor doping, the formation of quasi-neutral defect pairs can occur. As a result, in the finished ceramic, there is no or very low lead or oxygen vacancy concentration.

[0037] Depending on the raw materials used, the ceramic can also contain ions of other elements.

[0038] Typically, for example, when zirconium is used, hafnium doping also occurs. This doping is due to the natural occurrence of Hf in the zirconium raw material.

[0039] Furthermore, doping with, for example, silicon or manganese also has advantages.

[0040] Regarding the Ca content a in the claimed ceramic material, in one embodiment 0.001 ≦ a < 0.14 holds. In a further embodiment, the Ca content is 0.01 ≦ a ≦ 0.14.

[0041] Due to the above-described advantages and properties of doping, in one embodiment of the present invention 0.001 < b < 0.12 holds.

[0042] Due to the above-described advantages and characteristics of doping, in a further embodiment of the present invention, 0.001 < c < 0.12 holds.

[0043] In a further embodiment of the present invention, 0.001 < d < 0.12 holds.

[0044] In a further embodiment of the present invention, 0.001 < e < 0.12 holds.

[0045] In a further embodiment of the present invention, 0.001 < f < 0.12 holds.

[0046] In a further embodiment of the present invention, 0.005 < b + c + d + e + f holds.

[0047] Doping the above-described elements can improve the stability and elasticity of the ceramic material and extend its service life.

[0048] In a further embodiment, the ceramic material is an antiferroelectric dielectric. For this reason, the base material PCZT is preferably selected from the antiferroelectric orthorhombic phase region (O phase).

[0049] The antiferroelectric arrangement is characterized by the superposition of a plurality of polarized sublattices, and their electric dipole moments cancel each other out. Therefore, an antiferroelectric crystal has no residual polarization but has special dielectric properties.

[0050] When an electric field is applied to an antiferroelectric, it first behaves like a linear dielectric. From a predetermined critical electric field strength, a discontinuous transition to the ferroelectric phase is induced, and the previously antiparallel dipoles reverse to a more energetically stable parallel direction.

[0051] In contrast, the reverse transition occurs at a smaller electric field. This results in the so-called double hysteresis loop. Figures 3 and 4 show the hysteresis loops at positive values of the electric field, respectively.

[0052] Antiferroelectric ceramic materials have a less pronounced polarization field strength hysteresis compared to ferroelectric ceramic materials, which results in less energy loss when used in capacitors, and for this reason the use of antiferroelectric ceramic materials is preferred in the present invention.

[0053] In one embodiment, the sintering temperature of the ceramic material is between 900°C and 1200°C.

[0054] Such low sintering temperatures can be achieved by the composition and appropriate doping of the ceramic according to the invention.

[0055] The low sintering temperature allows already during the manufacturing process of the ceramic material to be combined with other raw materials / materials that are not stable at higher temperatures.

[0056] For example, it is possible to sinter the ceramic material together with internal electrodes made of metals such as silver or copper (a "co-firing" process).

[0057] In a preferred embodiment, the sintering temperature of the ceramic material is between 980°C and 1080°C.

[0058] In a further embodiment, the sintering temperature of the ceramic material is below the melting point of copper, which is 1085°C.

[0059] In a further embodiment, the sintering temperature of the ceramic material is below the melting point of silver, which is 962°C.

[0060] For the production of pure and variously doped lead calcium zirconate titanate (PCZT) powders, a solvent-based method, also called the mixed oxide method or the sol-gel method, can be used.

[0061] The starting point is, for example, a solution of acetate or alcoholate of the constituent metals, which is converted into granulated xerogel, ceramic precursor through various drying processes. For drying, for example, spray drying and spray freeze granulation are used, followed by freeze drying. The precursor is then pyrolyzed into oxide. The powder thus produced can be deagglomerated with little effort and adapted for further processing.

[0062] The invention further relates to a capacitor comprising dielectric layers made of the ceramic material according to the invention and electrode layers arranged therebetween, the individual layers being arranged one on top of the other in a defined layer sequence, the electrode layers having at least a first and / or a second electrode.

[0063] Preferably, the capacitor has multiple first electrodes and multiple second electrodes, such a capacitor being called a stacked capacitor.

[0064] In one embodiment of the capacitor, the first and second electrodes at least partially overlap.

[0065] Thus, in their overlapping regions, the first and second electrodes form an active area.

[0066] In one embodiment, the first and second electrodes are formed in the same electrode layer but are separated from each other by a dielectric section.

[0067] In a further embodiment, the electrode layers each include only one first electrode or only one second electrode. The electrode layers having the two types of electrodes are stacked alternately in the capacitor.

[0068] In one embodiment, the electrodes include one or more of the group consisting of copper, silver, nickel, platinum and palladium. These metals are particularly suitable due to their high electrical conductivity.

[0069] For easy and cheap manufacture, it is preferable to sinter the entire capacitor in one step, as mentioned above, so the sintering process takes place after the individual layers have been stacked.

[0070] To enable such a process, the sintering temperature of the ceramic used for the dielectric layers must not exceed the melting temperature of the metal used for the electrodes.

[0071] This is accomplished by using a dielectric ceramic according to the present invention, which may be formed according to any one of the embodiments described above.

[0072] In one embodiment, the capacitor includes two segments, each of which includes a dielectric layer of ceramic material and an electrode layer disposed therebetween, the outermost dielectric layers of the two segments further forming a bonding region in which the segments are firmly bonded to each other parallel to the layer plane.

[0073] The bonded region further includes a stress relief region where the bonding of the segments is weakened or interrupted.

[0074] The stress relief regions keep the mechanical stresses within the capacitor low, thus helping to cushion the capacitor against mechanical deformations caused by an applied electric field.

[0075] The stress relief regions prevent the accumulation of mechanical stresses throughout the capacitor, where the thickness of the segments is preferably small enough that mechanical stresses within the segments do not lead to the initiation of cracks within the capacitor.

[0076] Preferably, this weakening is significant in the stacking direction, which corresponds to the electric field direction of the capacitor. The weakening can be achieved by forming gaps or by using a material with a different elastic modulus, preferably a material with a smaller elastic modulus value. Alternatively, the weakening can be achieved by inserting a harder or more brittle material compared to the ceramic. When a load is applied, this material can break.

[0077] In one embodiment, the capacitor comprises two separate external contacts for contacting the first and second electrodes, the external contacts being attached to the outer outlet faces of the capacitor, on which the electrodes exit the capacitor, the outlet faces of the first and second electrodes being two outer faces located on opposite sides of the capacitor.

[0078] External contacts are used to connect electrodes of the same kind to each other and to the outside world, for example, via a first external contact all first electrodes are electronically connected to each other, and via a second external contact all second electrodes are electronically connected to each other.

[0079] A possible third or further electrode, on the other hand, is not contacted by an external contact.

[0080] In one embodiment, the capacitor includes at least one third electrode that is not contacted by any of the external contacts. In one embodiment, the third electrode is not adjacent to any outer surface of the capacitor. The third electrode overlaps the first and second electrodes.

[0081] Such electrodes are also called "floating" electrodes.

[0082] Preferably, the capacitor has a number of first electrodes, a number of second electrodes and a number of third electrodes.

[0083] In one embodiment, the capacitor comprises at least one series connection of two capacitances, in particular a first capacitance formed by an overlap of at least one first electrode with at least one third electrode, and a second capacitance formed by an overlap of at least one second electrode with at least one third electrode.

[0084] In one embodiment, the capacitor includes an additional electrode that does not overlap any electrode of the opposite polarity.

[0085] Therefore, no electric field is generated between these electrodes, and such electrodes are called passive or dummy electrodes.

[0086] Such dummy electrodes reduce the mechanical stresses that typically occur within the capacitor between electroded and non-electroded areas.

[0087] Thus, the combined use of dummy electrodes and stress relief regions can minimize mechanical stresses within the stacked capacitor and improve the robustness of the capacitor, thereby optimizing the thermo-mechanical and electrical load capability of the stacked capacitor.

[0088] In a further embodiment, the external contact comprises multiple sputtered layers including layers of chromium, nickel, and at least one of silver or gold, the layers being deposited in that order on the exit face.

[0089] The chromium layer, which is applied directly onto the exit face, allows the sputtered layer to adhere well to the exit face. The layer made of silver or gold has a high electrical conductivity and therefore serves mainly for electrical contact between the electrodes. By means of the above-mentioned sputtered layer, all electrodes of one type can be electrically connected to each other and thus connected in parallel.

[0090] The nickel intermediate layer acts as a diffusion barrier.

[0091] For example, all of the first electrodes that all exit the capacitor on the same first side can be electrically connected to each other via a first sputtered layer, and all of the second electrodes that all exit on a second side can be electrically connected or connected in parallel via a further second sputtered layer, so that the entire stack including, for example, all of the first electrodes and all of the second electrodes forms a single stacked capacitor.

[0092] In one embodiment, the external contacts further include a fine copper grid mounted on top of the sputtered layer.

[0093] The copper grid covers the entire sputtered layer, and therefore can avoid the formation of cracks in the sputtered layer or even its flaking off in the event of mechanical deformation of the capacitor.

[0094] In one embodiment, the external contacts further comprise a metal sheet through which the capacitor element is contacted to the outside, the metal sheet being attached on top of the sputtered layer.

[0095] In one embodiment, the metal sheet is attached over the sputtered layer by a soldered connection.

[0096] In a further embodiment, the metal sheet is attached over the sputtered layer by a sintered silver layer.

[0097] The sputtered layers mentioned above usually have a thickness in the nanometer range, whereas the silver layer has a thickness in the micrometer range. Such a sintered silver layer covering the entire sputtered layer holds the sputtered layer together when the capacitor is deformed, and prevents, for example, the sputtered layer from peeling off.

[0098] The silver layer also fixes the metal sheet to the sputtered layer. Therefore, no further soldering connections are necessary. For this purpose, the silver is applied onto the sputtered layer and the metal sheet is placed directly on top of it. Only after the metal sheet has been placed is the silver layer sintered at the lowest possible pressure.

[0099] In at least one embodiment, the silver layer is sintered at a low pressure such that a residual porosity of about 35% is achieved.

[0100] Such porosity is small enough to only slightly reduce the electrical and thermal conductivity of silver. Due to its high electrical and thermal conductivity, the silver layer also allows a good electrical connection to the sputtered layer of the metal sheet. In addition, however, silver with the above-mentioned porosity has a sufficiently high ductility to ensure thermomechanical stress relaxation.

[0101] Furthermore, sintered silver layers exhibit less material fatigue when subjected to mechanical or thermomechanical loads compared to, for example, soldered layers.

[0102] The process temperatures during sintering are generally lower than in soldering, furthermore lower thermomechanical stresses are generated and the process is relatively easy and cheap to carry out.

[0103] The high melting point of the sintered silver, up to 962° C. for pure silver, ensures high temperature stability of the silver layer, which allows further process steps at high temperatures.

[0104] In one embodiment, the metal sheet includes two copper layers with an Invar layer disposed therebetween.

[0105] Copper has particularly good electrical and thermal conductivity.

[0106] An iron-nickel alloy with approximately 1 / 3 nickel and 2 / 3 iron is called Invar. This material has a particularly low coefficient of thermal expansion, which is in particular close to that of ceramics. In combination with copper, sufficient electrical conductivity of the connection contacts can be ensured, despite the low electrical conductivity of Invar.

[0107] Instead of Invar, another iron-nickel alloy or an iron-nickel-cobalt alloy may be used.

[0108] To manufacture the above mentioned metal sheets, for example, a copper layer is laid down on an Invar sheet.

[0109] The outer surface of the copper layer may be silver plated to improve the connection between the copper and the sintered silver layer. The silver plating is applied by electroplating in one embodiment.

[0110] In one embodiment, the metal sheet of the external contacts includes a copper layer having a serpentine geometry.

[0111] A copper layer is applied directly on the silver layer. The copper layer preferably has a serpentine lattice geometry. The copper layer can also be silver plated. The silver plating is preferably performed by electroplating. The copper layer can be sintered directly with the silver layer.

[0112] Copper is preferably used for the external contacts of the capacitor because of its excellent thermal and electrical conductivity.

[0113] In one embodiment, the capacitor comprises separable capacitor elements that can be optionally assembled and disassembled with contact surfaces, the contact surfaces being oriented perpendicular to the layer planes and the external contacts.

[0114] Therefore, any size of capacitor can be flexibly constructed. The capacitor units described above can be mass-produced in standard sizes and then assembled on demand.

[0115] The fixing of the individual capacitor units can be achieved, for example, via a sintered silver layer, which extends over the outer surfaces of all the capacitor units and thus binds them together.

[0116] For the production of ceramic capacitors according to the invention, thin ceramic sheets are drawn, for example, from a suspension of unsintered ceramic powder according to the invention with a suitable binder. These are printed with future electrodes by a silk-screen printing process using a metal paste, which can contain, for example, Cu or Ag or other metals with good electrical conductivity.

[0117] The printed sheets are stacked together in the number of layers required for the capacitor and pressed together to harden it. The number and thickness of the stacked layers, as well as the dielectric constant of the ceramic, determine the final capacitance value of the capacitor.

[0118] The printing and layering may be carried out in such a way that the electrodes in the stack are stacked one on top of the other with a slight alternation and offset, so that they can ultimately be connected to the connection surface on one side in a comb-like manner.

[0119] The layered and pressed laminate can then be subdivided into individual capacitors for a mass production process.

[0120] After cutting, the separated capacitors are first baked out of the binder (debinding), followed by a firing process in which the ceramic powder is sintered at temperatures between 900°C and 1200°C, preferably between 980°C and 1080°C, to obtain its final, mainly crystalline structure.

[0121] It is only through this firing process that the ceramic acquires its desired dielectric properties. The firing process is followed by a cleaning step and, in at least one embodiment, the attachment of external contacts.

[0122] In the following, the invention is explained in more detail on the basis of the drawings. [Brief description of the drawings]

[0123] [Figure 1] This is a phase diagram of the PbZrO3-PbTiO3 mixed crystal system when the temperature changes. [Diagram 2] Phase diagram of the PbZrO3-PbTiO3 mixed crystal system when doped with lanthanum at room temperature. [Diagram 3] Comparison of hysteresis curves at positive electric field values ​​for antiferroelectric ceramics with the following compositions: 1. Pb0,9Ca0,1Zr0,891Ti0,099Cu0,005W0,005O3 2. Pb0,9Ca0,1Zr0,8865Ti0,0985Cu0,005Nb0,01O3 3. Pb0,9Ca0,1Zr0,8865Ti0,0985Ni0,005Nb0,01O3 The thickness of each sample is 180 μm. The diameter of the measured surface is 5 mm. [Figure 4] 1 is a hysteresis loop of a positive electric field value of a ceramic multilayer capacitor including a ceramic having a composition Pb0,9Ca0,1Zr0,891Ti0,099Cu0,005W0,005O3 and an electrode made of copper. [Diagram 5] 1 is a side cross-sectional view of a first embodiment of a multilayer capacitor; [Figure 6] 1 is a top cross-sectional view of a first embodiment of a multilayer capacitor; [Figure 7] FIG. 4 is a side cross-sectional view of a second embodiment of the multilayer capacitor. [Figure 8] FIG. 4 is a top cross-sectional view of a second embodiment of the multilayer capacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0124] Figures 1 and 2 show the already previously introduced phase diagrams of the PbZrO3-PbTiO3 mixed crystal system at various temperatures (Figure 1) or at room temperature with La doping (Figure 2). FT and FR are ferroelectric tetragonal or rhombohedral phases. PC denotes the paraelectric cubic phase. AO and AT represent the antiferroelectric orthorhombic or tetragonal phases. HT corresponds to the high temperature phase and LT to the low temperature phase. MPB represents the morphotropic phase boundary.

[0125] Figure 3 shows the Ca 2+ Based on PZT ceramic doped with W 6+ Ion, Nb 5+ Ion, Cu 2+ ions and Ni 2+ Hysteresis measurements of sintered samples containing ion doping are shown. The samples are disk-shaped pellets that were debound in air at 150°C and sintered at 1150°C for 4 hours. The pellet diameter is 5 mm and the sample thickness is 180 μm.

[0126] The illustrated exemplary hysteresis measurements yield different values ​​for polarization at a defined electric field strength: in particular, the third measured composition Z3 is significantly less polarized at the same electric field strength than the two first compositions Z1 and Z2.

[0127] In general, a high polarizability of a ceramic upon application of an electric field is desirable because thus a higher capacitor charge can be achieved. The polarization is integrated with the electric field strength to obtain the energy stored in the ceramic.

[0128] Furthermore, the area enclosed by the hysteresis should be as small as possible since this is a measure of the energy loss during the charging and discharging process of the capacitor.

[0129] That these ceramics are also suitable for sintering below the melting point of copper could be shown on the basis of a multilayer capacitor with copper electrodes. Figure 4 shows the hysteresis curve of such a multilayer capacitor as an example of one of the materials of Figure 3.

[0130] The less pronounced polarization-field strength hysteresis indicates lower energy losses during the capacitor charging and discharging processes.

[0131] 5 and 6 exemplarily show a first embodiment of a multilayer capacitor 1 comprising a material according to the invention in two cross sections, from the side (FIG. 5) or from above (FIG. 6).

[0132] The capacitor has two segments 2A and 2B, which are arranged one above the other in the stacking direction.

[0133] Each segment comprises a stack including an electrode layer having a first electrode 3, an electrode layer having a second electrode 4 and a dielectric layer 6 arranged between said electrodes. The above mentioned layers are arranged one on top of the other in a defined stacking direction.

[0134] Ends of the first electrodes 3 and 4 are exposed at two opposing exit faces 3A and 4A of the multilayer capacitor 1 having a rectangular parallelepiped shape.

[0135] The electrodes 3 / 4 do not reach the opposite exit faces, resulting in two distinct regions in the stacked capacitor 1. In the central region of the capacitor, the first and second electrodes 3 / 4 overlap, these regions being referred to as the active area 7A.

[0136] In the areas adjacent to the exit faces 3A / 4A there is respectively only one type of electrode, namely only the first electrodes 3 or only the second electrodes 4. These areas are called passive areas 7B.

[0137] The segments are bonded at bond regions 8. Within the bond regions 8 there are stress relief regions 9.

[0138] Bonding region 8 comprises the same dielectric ceramic material as the dielectric layers in segments 2A and 2B.

[0139] The bonding region 8 includes the bottom dielectric layer of the first segment 2A and the top dielectric layer of the second segment 2B, which are arranged overlapping each other in the stacking direction. There are no electrodes inside the bonding region 8.

[0140] At the edge of bond region 8 is a continuous stress relief region 9 along the entire periphery of capacitor element 1. Stress relief region 9 is disposed between the bottom dielectric layer of first segment 2A and the top dielectric layer of second segment 2B.

[0141] The depth of the stress relief region 9, measured from the outer surface of the capacitor 1 to the innermost portion of the capacitor 1, preferably corresponds to the stack height of the segments.

[0142] It can therefore be ensured that mechanical stresses resulting from deformation of the ceramic in the electric field do not add up across segments and result in, for example, cracks in the material.

[0143] The stress relief region 9 includes all passive regions 7B of the multilayer capacitor 1. That is, the stress relief region 9 is arranged parallel to all sections in the segments that include only one type of electrode or no electrodes, inside the bonding region 8. Furthermore, the stress relief region 9 extends partially into the active region 7A.

[0144] When viewed from the lamination direction, the active region 7A has a rectangular shape, as shown in Fig. 6. The passive region 7B forms a rectangular frame surrounding the active region 7A. The stress relief region 9 forms a rectangular frame surrounding the passive region 7B and further partially overlaps with the active region 7A.

[0145] The stress relief regions 9 are regions where the stacked dielectric layers 6 are only partially, but not rigidly, bonded to one another.

[0146] The embodiment of the multilayer capacitor 1 shown in Figures 7 and 8 corresponds substantially to the first example multilayer capacitor 1 comprising the material according to the invention.

[0147] The multilayer capacitor 1 again comprises two segments 2A and 2B, each consisting of layer planes stacked in the same order.

[0148] In addition to the first and second electrodes 3 / 4, the segment also comprises a third electrode 5. The third electrode 5 is an internal, so-called floating electrode that is not contacted from the outside.

[0149] The first and second electrodes 3 / 4 are respectively arranged in the same layer plane but are separated by a dielectric section.

[0150] Between the layer planes containing the first and second electrodes 3 / 4 there is arranged a layer plane containing a third electrode 5. Between each electrode layer a respective dielectric layer 6 is arranged.

[0151] In this manner, a multilayer capacitor 1 is formed that includes two capacitors connected in series: a first capacitor 1A formed between the first and third electrodes, and a second capacitor 1B formed between the third and second electrodes.

[0152] Between the two active areas 7A of the capacitors 1A and 1B there is a passive area 7B in which only the third electrode 5 is present, so that there is no overlap of different types of electrodes in the passive area.

[0153] In the bonding region 8 the two outer dielectric layers of the segments 2A and 2B arranged in the stacking direction of the layers are firmly bonded together. The bond can be produced, for example, by sintering.

[0154] A stress relief region 9 is formed in the bond region 8. Here, the stress relief region 9 is a gap between the first and second segments.

[0155] Stress relief region 9 includes an outer section along the periphery of capacitor 1 and an inner section.

[0156] The additional inner section is formed such that the entire passive area 7B is covered by the stress relief region 9. Furthermore, the stress relief region 9 also extends to areas outside the two active areas 9A of the capacitors 1A and 1B.

[0157] The stress relief regions 9 contribute to stress relief of the capacitor during mechanical deformation due to an applied electric field, and prevent the accumulation of mechanical stresses across the stack height. [Explanation of symbols]

[0158] 1,1A,1B Capacitor 2A,2B Segment 3 First electrode 4 Second electrode 3A First electrode outlet surface 4A Second electrode outlet surface 5 Third electrode 6 Dielectric Layer 7A Active Area 7B Passive Area 8 Combined area 9 Stress relief area Z1, Z2, Z3 Ceramic Composition

Claims

1. A ceramic material for a capacitor using a lamination technique, represented by the following formula: Pb (y-1.5a+c-0.5e-f) Ca a (Zr 1-x Ti x ) (1-c-e-f) E c Nb e W f O 3, where: E is one or more of the group consisting of Cu and Ni; 0<a<0.14、 0.05≦x≦0.3、 0.001<c≦0.12、 0≦e≦0.12、 0≦f≦0.12、 0.9 ≦ y ≦ 1.5, and 0.001 < c + e + f holds.

2. The ceramic material according to Claim 1, wherein 0.001 < a < 0.

14.

3. The ceramic material according to Claim 1 or 2, wherein 0.001 < e < 0.

12.

4. The ceramic material according to any one of Claims 1 to 3, wherein 0.001 < f < 0.

12.

5. The ceramic material according to any one of Claims 1 to 4, wherein 0.005 < c + e + f.

6. The ceramic material according to any one of Claims 1 to 5, wherein the ceramic material is an antiferroelectric.

7. The ceramic material according to any one of Claims 1 to 6, wherein the sintering temperature of the ceramic material is 900°C to 1200°C.

8. The ceramic material according to Claim 7, wherein the sintering temperature of the ceramic material is 980°C to 1080°C.

9. The ceramic material according to Claim 7 or 8, wherein the sintering temperature of the ceramic material is lower than the melting point of copper.

10. The ceramic material according to Claim 9, wherein the sintering temperature of the ceramic material is lower than the melting point of silver.

11. A capacitor (1) including a dielectric layer (6) made of a ceramic material and electrode layers disposed between the dielectric layers (6) and overlapping in a certain layer order, wherein the electrode layer has at least first and / or second electrodes (3, 4), and the ceramic material has the following general formula: Pb (y-1.5a+c-0.5e-f) Ca a (Zr 1-x Ti x ) (1-c-e-f) E c Nb e W f O 3, where: E is one or more of the group consisting of Cu and Ni; 0<a<0.14、 0.05≦x≦0.3、 0.001<c≦0.12、 0≦e≦0.12、 0≦f≦0.12、 0.9 ≦ y ≦ 1.5, and 0.001 < c + e + f holds.

12. Including two segments (2A, 2B), each segment including a dielectric layer made of the ceramic material and an electrode layer disposed between the dielectric layers. The outermost dielectric layers of the two segments form a bonding region (8), and in the bonding region, the segments are fixed to each other parallel to the dielectric layer. The capacitor according to claim 11, wherein the bonding region includes a stress relaxation region (9), and in the stress relaxation region, the segments are not fixed to each other.

13. The capacitor according to claim 11 or 12, wherein two separate external contacts for contacting the first and second electrodes are mounted on the outer exit surface of the capacitor, and the electrodes exit from the capacitor on the exit surface.

14. The capacitor according to claim 13, including at least one third electrode (5) that is not in contact with any of the external contacts, and the third electrode overlaps with the first and second electrodes.

15. The laminated capacitor according to claim 13 or 14, wherein the external contacts include a multi-layer sputtered layer, the sputtered layer includes a layer composed of at least one of chromium, nickel, and silver or gold, and the layer composed of chromium, the layer composed of nickel, and the layer composed of at least one of silver or gold are coated on the exit surface in the order of the layer composed of chromium, the layer composed of nickel, and the layer composed of at least one of silver or gold.

16. The capacitor according to claim 15, wherein the external contacts include a metal sheet mounted on the sputtered layer by a sintered silver layer.

17. The capacitor according to claim 16, wherein the metal sheet includes two copper layers and an Invar layer disposed therebetween.

18. The capacitor includes a separable capacitor unit that can be arbitrarily assembled and disassembled on a contact surface. The capacitor according to any one of claims 13 to 17, wherein the contact surface is disposed perpendicular to the dielectric layer and the external contacts.

19. The capacitor according to any one of claims 11 to 14, including a further electrode that does not overlap with electrodes of different polarities.

20. The capacitor according to any one of claims 11 to 19, wherein 0.001 < a < 0.14 holds for the ceramic material.

21. The ceramic material according to any one of claims 11 to 20, wherein 0.001 < e < 0.12 holds for the ceramic material.

22. The ceramic material according to any one of claims 11 to 21, wherein 0.001 < f < 0.12 holds for the ceramic material.

23. The ceramic material according to any one of claims 11 to 22, wherein 0.005 < c + e + f holds for the ceramic material.

24. The ceramic material according to any one of claims 11 to 23, wherein the ceramic material is an antiferroelectric.

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