Semiconductor Device

Abstract

To provide a semiconductor device capable of suppressing a malfunction of a circuit connected to a passive element provided on a semiconductor substrate via an insulating film.SOLUTION: A semiconductor device includes a first conductive type semiconductor substrate (1,2), a first electrode 5 connected to the semiconductor substrate (1,2), a second conductive type first semiconductor region 3 provided on the upper part of the semiconductor substrate (1,2), a first conductive type second semiconductor region 4 provided on the first semiconductor region 3, a second electrode 7a electrically connected to the first semiconductor region 3, an insulating film 9 provided on the upper surface side of the second semiconductor region 4, and a passive element 6 provided on the upper surface side of the insulating film 9.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a passive element disposed on a semiconductor substrate via an insulating film. [Background technology]

[0002] A high-side power IC has been proposed in which power semiconductor elements such as vertical MOSFETs that serve as the output stage and a control circuit for controlling the power semiconductor elements are integrated (mixed) on the same semiconductor chip. High-side power ICs have various MOSFETs, various resistance elements, and various capacitance elements as semiconductor elements for the control circuit. One example of a capacitance element is a PIP (Polysilicon-Insulator-Polysilicon) type capacitance element. A PIP type capacitance element is composed of a layered structure of a polysilicon layer, an insulating film, and a polysilicon layer. Various devices are connected to the terminals composed of the upper and lower polysilicon layers to form a circuit. In a high-side power IC, the PIP type capacitance element is provided on a field oxide film (LOCOS film).

[0003] Patent Document 1 discloses a structure in which a MOSFET and a PIP-type capacitance element on an insulating film are formed on the same substrate. Patent Documents 2 and 3 disclose structures in which an insulating film is formed on various diffusion layers, and a polysilicon resistance element and a PIP-type capacitance element are arranged on the insulating film. Patent Document 4 discloses a structure in which a vertical MOSFET and a control circuit are integrated on the same substrate, and an integrated circuit is provided on a p-well. The source potential of the MOSFET is applied to the p-well, and a capacitor is provided on the p-well via an oxide film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-158779 A [Patent Document 2] Patent No. 6707917 [Patent Document 3] JP 2013-89764 A [Patent Document 4] JP 2003-264289 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor devices described in Patent Documents 1 to 4, a parasitic capacitance, which is a capacitance component unintended in circuit design, is formed by the polysilicon film below the PIP type capacitive element, the insulating film below the polysilicon film below the lower layer, and the semiconductor substrate below the insulating film. In a high-side power IC, since the semiconductor substrate is connected to a high-potential terminal (VCC terminal), the parasitic capacitance capacitively couples the high-potential terminal and the internal circuit in which the PIP type capacitive element is used, which causes a circuit malfunction. Since the PIP type capacitive element is composed of a polysilicon layer that is relatively larger than the polysilicon wiring and polysilicon resistance element, the parasitic capacitance has a relatively large capacitance value. In addition, as miniaturization progresses and the insulating film is made thinner to reduce steps, the parasitic capacitance value becomes even larger, increasing the risk of circuit malfunction.

[0006] In view of the above problems, the present invention aims to provide a semiconductor device that can reduce the parasitic capacitance connected to a passive element, such as a PIP type capacitance element provided on a semiconductor substrate via an insulating film, and can suppress malfunction of a circuit connected to the passive element. [Means for solving the problem]

[0007] One aspect of the present invention is a semiconductor device comprising: (a) a semiconductor substrate of a first conductivity type; (b) a first electrode electrically connected to the semiconductor substrate; (c) a first semiconductor region of a second conductivity type provided on an upper portion of the semiconductor substrate; (d) a second semiconductor region of the first conductivity type provided on an upper portion of the first semiconductor region; (e) a second electrode electrically connected to the first semiconductor region; (f) an insulating film provided on an upper surface side of the second semiconductor region; and (g) a passive element provided on an upper surface side of the insulating film. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor device capable of suppressing malfunction of a circuit connected to a passive element provided on a semiconductor substrate via an insulating film. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view of a semiconductor substrate of a semiconductor device according to a first embodiment. [Diagram 3] 2 is a cross-sectional view showing the expansion of a depletion layer in the semiconductor device according to the first embodiment. FIG. [Figure 4] 5 is another cross-sectional view showing the expansion of the depletion layer in the semiconductor device according to the first embodiment. FIG. [Diagram 5] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 7] FIG. 2 is a circuit diagram of a semiconductor device according to a first comparative example. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a second comparative example. [Figure 9] FIG. 11 is a circuit diagram of a semiconductor device according to a second comparative example. [Figure 10] 1 is a cross-sectional view of a semiconductor integrated circuit according to a first embodiment. [Figure 11] 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment. [Figure 12] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 13] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 14] FIG. 13 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 15] 15 is a cross-sectional view taken along the line BB in FIG. 14. [Figure 16] FIG. 13 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 17] 17 is a cross-sectional view taken along the line BB in FIG. 16. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0011] In the following description, the "first main electrode region" and the "second main electrode region" are main electrode regions of a semiconductor element into which a main current flows in or out. The "first main electrode region" means a semiconductor region that becomes either an emitter region or a collector region in the case of an insulated gate bipolar transistor (IGBT). The "first main electrode region" means a semiconductor region that becomes either a source region or a drain region in the case of a field effect transistor (FET) or a static induction transistor (SIT). The "second main electrode region" means a region that becomes either an emitter region or a collector region that is not the first main electrode region in the case of an IGBT. The "second main electrode region" means a semiconductor region that becomes either a source region or a drain region that is not the first main electrode region in the case of a FET or a SIT. The "second main electrode region" means a region that becomes either an anode region or a cathode region that is not the first main electrode region in the case of an SI thyristor or a GTO. That is, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region.

[0012] In the following description, the definitions of the directions such as up and down and left and right for "upper surface" and "lower surface" are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are of course read inverted.

[0013] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity concentration (in other words, a low or high resistivity) compared to a semiconductor region not attached with "+" or "-". However, in the representation of the drawings, even if the semiconductor regions are attached with the same "n" and "n", it does not mean that the impurity concentration (resistivity) of each semiconductor region is strictly the same.

[0014] (First embodiment) <Semiconductor device> The semiconductor device according to the first embodiment includes a first conductivity type (n-type) semiconductor substrate (1, 2) as shown in FIG. + A low resistivity layer 1 of a type, and a n-type semiconductor layer 2 of a type 3 of a type 4 of a type 5 of a type 6 of a type 7 of a type 8 of a type 9 of a type 10 of a type 11 of a type 12 of a type 13 of a type 14 of a type 15 of a type 16 of a type 17 of a type 19 ... - The semiconductor substrate (1, 2) is made of a n-type high resistivity layer 2. The low resistivity layer 1 is made of a semiconductor substrate (Si wafer) made of silicon (Si), for example. The high resistivity layer 2 is made of an epitaxially grown layer made of Si epitaxially grown on the low resistivity layer 1. The semiconductor substrate (1, 2) is made of a semiconductor material made of Si, for example, as a base material, but the base material is not limited to Si. Note that the n-type high resistivity layer 2 - On the bottom side of the semiconductor substrate (Si wafer), + The semiconductor substrate (1, 2) may be constructed by forming the low resistivity layer 1 made of a type of impurity-added layer by ion implantation or thermal diffusion.

[0015] When the low resistivity layer 1 is a semiconductor substrate, the impurity concentration of the low resistivity layer 1 is, for example, 2×10 18 cm -3 ~1×10 19 cm -3 In this case, the impurity concentration of the high resistivity layer 2 is, for example, 1×10 12 cm -3 ~1×10 16 cm -3 In this example, the value can be selected to be 1×10 15 cm -3 ~1×10 16 cm -3 n - A high resistivity layer 2 made of a type semiconductor substrate is provided on the lower surface of the n + When forming the low resistivity layer 1 with an impurity doped layer of the type, the impurity concentration of the low resistivity layer 1 is set to 5×10 18 cm -3 ~1×10 21 cm -3 The impurity concentration of the low resistivity layer 1 does not have to be constant. 21 cm -3 The low resistivity layer 1 may have an impurity profile with a high impurity concentration of, for example, 5×10 18 cm -3 ~2×10 19 cm -3 The upper layer is about 3×10 19 cm -3 ~1×10 21 cm -3 It may be constructed of a composite structure with a lower layer of about

[0016] A lower electrode (rear electrode) 5 serving as a first electrode is provided on the lower surface side of the low resistivity layer 1. A first potential terminal (VCC terminal) 71 on the high potential side is connected to the lower electrode 5. A first potential is applied to the low resistivity layer 1 from the first potential terminal 71 via the lower electrode 5. For example, a power supply potential (VCC potential) of about 15 V of a high-side power IC is applied as the first potential.

[0017] The upper part of the high resistivity layer 2 is a second conductive type (p -A first semiconductor region 3 having a p-type impurity is selectively provided in the high resistivity layer 2. The first semiconductor region 3 is, for example, a diffusion layer formed by ion-implanting a p-type impurity into the high resistivity layer 2 and performing a heat treatment. The impurity concentration of the first semiconductor region 3 is, for example, 6×10 15 cm -3 The impurity concentration of the first semiconductor region 3 may be about, but is not particularly limited to, the same as the impurity concentration of the high resistivity layer 2, or may be higher than the impurity concentration of the high resistivity layer 2, or may be lower than the impurity concentration of the high resistivity layer 2. The impurity concentration, position and depth of the first semiconductor region 3 are adjusted so that the region below the passive element 6 can be depleted during operation of the semiconductor device according to the first embodiment, as will be described in detail later.

[0018] The upper portion of the first semiconductor region 3 is - A second semiconductor region 4 of a n-type is selectively provided. The second semiconductor region 4 is composed of a diffusion layer formed by, for example, ion-implanting n-type impurities into the high resistivity layer 2 and performing heat treatment. A part of the second semiconductor region 4 extends to the outside of the first semiconductor region 3 and contacts the high resistivity layer 2. Therefore, the second semiconductor region 4 has the same potential (VCC potential) as the high resistivity layer 2. The impurity concentration of the second semiconductor region 4 is, for example, 6×10 15 cm -3 The impurity concentration, position and depth of the second semiconductor region 4 are adjusted so that the region below the passive element 6 can be depleted during operation of the semiconductor device according to the first embodiment, as will be described in detail later.

[0019] An insulating film 9 is provided on the upper surface side of the first semiconductor region 3 and the second semiconductor region 4. The insulating film 9 is made of a field oxide film such as a local insulating film (LOCOS film) selectively (locally) formed by the local oxidation of silicon (LOCOS) method. Note that the insulating film 9 may be made of an insulating film other than a field oxide film.

[0020] An opening is provided in the insulating film 9. When the insulating film 9 is a LOCOS film, the opening may be selectively formed when the insulating film 9 is formed, or may be formed by dry etching or the like after the insulating film 9 is formed. The opening in the insulating film 9 is formed by arranging a p + The contact region 7 of the p-type is exposed. In the opening of the insulating film 9, an electrode 7a as a second electrode is formed. + The first semiconductor region 3 is provided so as to be in contact with a contact region 7 of a lower potential type. The first semiconductor region 3 is electrically connected to a second potential terminal (GND terminal) 72 on the low potential side via the contact region 7. To the second potential terminal 72, for example, a ground potential (GND potential) is applied as a second potential that is lower than the first potential (VCC) applied to the first potential terminal 71.

[0021] A passive element 6, which is a PIP type capacitance element, is disposed on the upper surface of the insulating film 9. The passive element 6 is configured with a laminated structure of a first conductive layer (lower electrode) 61 provided on the upper surface of the insulating film 9, a dielectric layer 62 provided on the upper surface of the first conductive layer 61, and a second conductive layer (upper electrode) 63 provided on the upper surface of the dielectric layer 62. Note that FIG. 1 illustrates a case in which the right end of the dielectric layer 62 contacts the upper surface of the insulating film 9, but the dielectric layer 62 may be provided only on the upper surface of the first conductive layer 61. Also, a case in which the right end of the second conductive layer 63 has a step portion and contacts the upper surface of the insulating film 9 is illustrated, but the second conductive layer 63 may be provided only on the upper surface of the dielectric layer 62.

[0022] The first conductive layer 61 and the second conductive layer 63 are made of, for example, polysilicon to which impurities are added at a high concentration. The impurity concentrations of the first conductive layer 61 and the second conductive layer 63 may be the same or different. The dielectric layer 62 is made of, for example, an insulating film such as a high-temperature oxide film (HTO). A first terminal 81 is connected to the first conductive layer 61, and a second terminal 82 is connected to the second conductive layer 63. The first terminal 81 and the second terminal 82 are connected to predetermined locations of an internal circuit so that a desired circuit specification can be realized.

[0023] Both ends of the second semiconductor region 4 and the first semiconductor region 3 below the passive element 6 are provided at positions outside of both ends of the first conductive layer 61 and the second conductive layer 63 of the passive element 6. Note that both ends of the second semiconductor region 4 and the first semiconductor region 3 may be provided at positions inside of both ends of the first conductive layer 61 and the second conductive layer 63 of the passive element 6.

[0024] FIG. 2 shows an example of a planar layout of the semiconductor substrate (1, 2) viewed from the top side. In FIG. 2, the position of the passive element 6 arranged on the second semiconductor region 4 via the insulating film 9 is shown by a dashed line. Each of the first semiconductor region 3 and the second semiconductor region 4 has a rectangular planar pattern, but is not limited to this. Each of the first semiconductor region 3 and the second semiconductor region 4 is provided so as to overlap the passive element 6 in the planar pattern and cover the entire passive element 6. Note that each of the first semiconductor region 3 and the second semiconductor region 4 may be provided so as to cover only a part of the passive element 6 without covering the entire passive element 6 in the planar pattern.

[0025] 3 is a schematic diagram showing the spread of depletion layers D1, D2, and D3 when a voltage (e.g., about 5V) lower than the VCC potential during normal operation and higher than the GND potential is applied to the first potential terminal 71 as the first potential, and a GND potential is applied to the second potential terminal 72 as the second potential in the semiconductor device according to the first embodiment. As shown in FIG. 3, the depletion layer D1 extends from the pn junction between the high resistivity layer 2 and the first semiconductor region 3 to both the high resistivity layer 2 side and the first semiconductor region 3 side. In addition, the first semiconductor region 3 also has a high potential because it is in contact with the high resistivity layer 2, and the depletion layer D2 extends from the pn junction between the first semiconductor region 3 and the high resistivity layer 2 to both the first semiconductor region 3 side and the second semiconductor region 4 side. In addition, the depletion layer D3 extends from the junction between the first semiconductor region 3 and the insulating film 9 to the first semiconductor region 3 side.

[0026] 4 shows a schematic diagram of the spread of the depletion layer D4 when a VCC potential (e.g., about 13 V) during normal operation is applied as a first potential to a first potential terminal 71 and a GND potential is applied as a second potential to a second potential terminal 72 in the semiconductor device according to the first embodiment. In FIG. 4, a capacitance C1 formed by a passive element 6 which is a PIP type capacitance element and a parasitic capacitance C2 connected to the passive element 6 are shown by circuit symbols.

[0027] As shown in FIG. 4, the depletion layers D1, D2, and D3 shown in FIG. 3 are further expanded and connected to form a depletion layer D4, so that the portions directly below the passive element 6 in the second semiconductor region 4 and the first semiconductor region 3 can be substantially or completely depleted. By adjusting the positions, junction depths, and impurity concentrations of the semiconductor substrates (1, 2), the first semiconductor region 3, and the second semiconductor region 4, when a predetermined first potential and a predetermined second potential are applied, the portions directly below the passive element 6 in the first semiconductor region 3 and the second semiconductor region 4 can be substantially or completely depleted as shown in FIG. 4. As a result, the parasitic capacitance connected to the passive element 6 can be reduced, and circuit malfunctions can be suppressed. Note that the portions directly below the passive element 6 in the first semiconductor region 3 and the second semiconductor region 4 do not necessarily have to be completely depleted, and even in that case, the effect of reducing the parasitic capacitance can be achieved.

[0028] For example, the high resistivity layer 2, the first semiconductor region 3, and the second semiconductor region 4 each have an average concentration of 6×10 15 cm -3 Assuming that the high resistivity layer 2 has a flat concentration profile, the width of the depletion layer extending from each junction of the high resistivity layer 2, the first semiconductor region 3, and the second semiconductor region 4 is about 1.2 μm when 13 V, which is a standard battery voltage for an automobile, is applied as the voltage between the first potential terminal 71 and the second potential terminal 72. Therefore, complete depletion can be realized by forming the first semiconductor region 3 and the second semiconductor region 4 so that the depth of the second semiconductor region 4 is less than 1.2 μm and the width of the first semiconductor region 3 sandwiched between the high resistivity layer 2 and the second semiconductor region 4 is less than 2.4 μm.

[0029] 5 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. As shown in FIG. 5, an oxide film capacitance Co formed by an insulating film 9 is connected to a capacitance C1 of a passive element 6. A depletion layer capacitance Ca is connected between the oxide film capacitance Co and the VCC potential, and a depletion layer capacitance Cb is connected between the oxide film capacitance Co and the GND potential. The parasitic capacitance Cvcc connected to the VCC potential and the parasitic capacitance Cgnd connected to the GND potential are as follows: Cvcc ≒ Ca / (Co+Ca) × Co ( <Co) ...(1) Cgnd ≒ Cb / (Co+Ca) × Co ( <Co) ...(2)

[0030] In the semiconductor device according to the first embodiment, the depletion layer capacitances Ca and Cb are connected in series to the oxide film capacitance Co, so that the combined parasitic capacitances Cvcc and Cgnd can be reduced to be less than the oxide film capacitance Co. When the thickness of the insulating film 9 is 0.3 μm, the oxide film capacitance Co is 0.11 fF / μm. 2 The average impurity concentration is 6×10 15 cm -3 and the second semiconductor region 4 having an average impurity concentration of 6×10 15 cm -3 When 13 V is applied to the junction of the first semiconductor region 3, the depletion layer capacitance Ca, Cb is 0.04 fF / μm 2 In the structure of the semiconductor device according to the first embodiment, the depletion layer extends more than in a simple pn junction, so the depletion layer capacitances Ca and Cb are 0.04 fF / μm 2 From the above, it can be estimated that the combined series capacitances Cvcc and Cgnd of the oxide film capacitance Co and the depletion layer capacitances Ca and Cb will be at least 1 / 4 of the oxide film capacitance Co alone. In reality, the planar distance to the terminals is also included, so the depletion layer capacitances Ca and Cb are likely to be even lower than the above.

[0031] <First Comparative Example> Next, a semiconductor device according to a first comparative example will be described. As shown in Fig. 6, the semiconductor device according to the first comparative example differs from the semiconductor device according to the embodiment shown in Fig. 1 in that the first semiconductor region 3 and the second semiconductor region 4 shown in Fig. 1 are not provided on the upper part of the high resistivity layer 2. A passive element 6 is provided on the upper surface side of the high resistivity layer 2 via an insulating film 9.

[0032] 6, there are diagrammatically shown a capacitance C1 of the passive element 6, a parasitic capacitance C3 connected to the passive element 6, and a depletion layer D5 formed when a first potential (VCC potential) is applied to a first potential terminal 71. The parasitic capacitance C3 is composed of a high resistivity layer 2, a depletion layer D5, an insulating film 9, and a first conductive layer 61. As shown in FIG 7, the parasitic capacitance C3 is connected between a first terminal 81 of the passive element 6 and the VCC potential, and causes a circuit malfunction.

[0033] <Second Comparative Example> Next, a semiconductor device according to a second comparative example will be described. As shown in FIG. 8, the semiconductor device according to the second comparative example has a p - 1 in that only a type semiconductor region 11 is provided. A second potential terminal 72 is connected to the semiconductor region 11. A passive element 6 is provided on the upper surface side of the semiconductor region 11 with an insulating film 9 interposed therebetween.

[0034] 8, there are diagrammatically shown a capacitance C1 of the passive element 6, a parasitic capacitance C4 connected to the passive element 6, and depletion layers D6 and D7 formed when a VCC potential is applied to the first potential terminal 71 and a GND potential is applied to the second potential terminal 72. The parasitic capacitance C4 is composed of the semiconductor region 11, the depletion layers D6 and D7, the insulating film 9, and the first conductive layer 61.

[0035] In the semiconductor device according to the second comparative example, n - The p-type high resistivity layer 2 is the opposite conductivity type. -By providing a semiconductor region 11 having a GND potential, the semiconductor region 11 is electrically isolated from the high resistivity layer 2 having the VCC potential. However, as shown in Fig. 9, a parasitic capacitance C4 is connected between the first terminal 81 of the passive element 6 and the GND potential, which causes a circuit malfunction.

[0036] In the semiconductor device according to the second comparative example, - It is possible to consider a case where the second potential terminal 72 is not connected to the semiconductor region 11 of the semiconductor device, and the semiconductor region 11 is set to a floating potential. In this case, since the potential of the semiconductor region 11 is easily affected by the charge in the insulating film 9 and the charge in the package, there is a risk that the characteristics will fluctuate due to the mobile charge that moves due to the application of voltage for a long period of time, and reliability will decrease.

[0037] In contrast to the first and second comparative examples, the semiconductor device according to the first embodiment has a p - The first semiconductor region 3 and the n - By arranging multiple second semiconductor regions 4 of the same type and applying a first potential, which is a high potential, to the second semiconductor region 4 and a second potential, which is a low potential, to the first semiconductor region 3, the depletion layer capacitance can be reduced by promoting depletion of the first semiconductor region 3 and the second semiconductor region 4. As a result, the parasitic capacitance connected to the passive element 6 can be reduced, and malfunction of the circuit connected to the passive element 6 can be suppressed.

[0038] <Semiconductor integrated circuits> A high-side power IC will be described as an example of a semiconductor integrated circuit to which the semiconductor device according to the first embodiment is applied. The semiconductor integrated circuit according to the first embodiment is a power IC in which an output section 100 and a circuit section 200 are monolithically integrated on the same semiconductor chip, as shown in FIG.

[0039] As shown on the right side of FIG. 10, a vertical trench-gate n-channel MOSFET is exemplified as an output stage element 101, which is a power semiconductor element integrated in the output section 100. A part of the low resistivity layer 1 functions as a first main electrode region (drain region) of the output stage element 101, and a part of the high resistivity layer 2 located on this first main electrode region functions as a drift layer of the output stage element 101. A bottom electrode 5, which serves as a drain electrode, is disposed on the bottom side of the low resistivity layer 1. The bottom electrode 5 is connected to a first potential terminal 71, which is a power supply terminal. A power supply potential (VCC potential) of, for example, about 13 V is applied as a first potential to the first potential terminal 71.

[0040] A body region (base region) 13 of a second conductivity type (p type) is disposed in a part of the upper portion of the high resistivity layer 2 located on the output section 100 side. + The body region 13 is provided with p-type second main electrode regions (source regions) 15a and 15b in contact with the source regions 15a and 15b. + A mold base contact region 16 is optionally provided.

[0041] Focusing on the unit cell in Fig. 10, a pair of opposing trenches 17a, 17b are provided, which are dug from the upper surface of the body region 13. At least a portion of the side surface of the trenches 17a, 17b contacts the body region 13, and the trenches 17a, 17b are provided deeper than the body region 13. In the cross-sectional view of Fig. 10, a pair of trenches 17a, 17b is illustrated as an example, but in reality, the trenches may be a single trench having a circular planar shape that is continuous in the front-to-rear direction of the paper surface of Fig. 10. In addition, a p-type well region (p-well) 23 is provided in a portion of the upper part of the high resistivity layer 2 so as to contact the trench 17a.

[0042] A gate insulating film 18 is provided along the inner surface of the trenches 17a and 17b. Gate electrodes 19a and 19b are embedded in the trenches 17a and 17b through the gate insulating film 18, forming trench-type control electrode structures (18, 19a), (18, 19b).

[0043] As the gate insulating film 18, for example, a silicon oxide film (SiO2 film) can be used, but in addition to the SiO2 film, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, or an aluminum oxide (Al2O3) film can also be used. Alternatively, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a bismuth oxide (Bi2O3) film may be used. Furthermore, a composite film in which some of these single layer films are selected and stacked can also be used.

[0044] The material of the gate electrodes 19a and 19b may be, for example, polysilicon to which n-type or p-type impurities are highly doped (doped polysilicon), but other than doped polysilicon (DOPOS), it may also be possible to use high-melting-point metals such as tungsten (W), molybdenum (Mo), titanium (Ti), or silicides of high-melting-point metals and polysilicon. Furthermore, the material of the gate electrodes 19a and 19b may be polycide, which is a composite film of polysilicon and silicide of a high-melting-point metal.

[0045] The gate electrodes 19a, 19b electrostatically control the surface potential of the side surface portions of the trenches 17a, 17b in the body region 13 via the gate insulating film 18, thereby forming an inversion channel on the side surface of the trenches 17a, 17b in the body region 13. In the output stage element 101, a main current flows through the inversion channel between the source regions 15a, 15b on the upper surface side and a drain region constituted by a part of the low resistivity layer 1 on the lower surface side facing the source regions 15a, 15b.

[0046] 10, the circuit section 200 includes circuit elements 201 and 202 that control the output stage element 101. For example, a complementary MOS (CMOS) can be used in which the circuit element 201 is a lateral n-channel MOSFET and the circuit element 202 is a lateral p-channel MOSFET. The circuit element 201 is provided in a p-type well (p-well) 22 provided on the high resistivity layer 2. The impurity concentrations of the p-wells 22 and 23 are, for example, 1×10 16 cm -3 That's about it.

[0047] The circuit element 201 is provided with an n-type + A first main electrode region (source region) 25 and a second main electrode region (drain region) 26 of the same type are opposed to each other. The source region 25 and the drain region 26 are selectively provided spaced apart from each other and have a higher impurity concentration than the high resistivity layer 2.

[0048] A planar control electrode structure (27, 28) extends laterally on the p-well 22. The control electrode structure (27, 28) includes a gate insulating film 27 provided on the p-well 22 between the source region 25 and the drain region 26, and a gate electrode 28 disposed on the gate insulating film 27. The gate electrode 28 electrostatically controls the surface potential of the p-well 22 via the gate insulating film 27, thereby forming an inversion channel in the surface layer of the p-well 22.

[0049] The circuit element 202 is provided on the p-well 22 and is provided in an n-type well (n-well) 24. The impurity concentration of the n-well 24 is, for example, 1×10 17 cm -3 The impurity concentration of the n-well 24 may be lower than the impurity concentration of the high resistivity layer 2. The circuit element 202 is formed by forming a p + A first main electrode region (source region) 29 and a second main electrode region (drain region) 30 of the same type are opposed to each other. The source region 29 and the drain region 30 are selectively provided spaced apart from each other, and have a higher impurity concentration than the p-well 22.

[0050] A planar control electrode structure (31, 32) extends laterally on the n-well 24. The control electrode structure (31, 32) includes a gate insulating film 31 provided on the n-well 24 between the source region 29 and the drain region 30, and a gate electrode 32 arranged on the gate insulating film 31. The gate electrode 32 electrostatically controls the surface potential of the n-well 24 via the gate insulating film 31 to form an inversion channel in the surface layer of the n-well 24. An insulating film 9, which is a field oxide film such as a local insulating film (LOCOS film), is selectively provided between the circuit elements 201, 202, and the output stage element 101 on the upper surface of the high resistivity layer 2.

[0051] 10, the circuit section 200 includes a structure of a semiconductor device 203 according to the first embodiment. The semiconductor device 203 includes a p - A first semiconductor region 3 of a type and an n-type semiconductor region selectively provided on the upper portion of the first semiconductor region 3. - The first semiconductor region 3 may have the same depth and impurity concentration as, for example, the body region 13 of the output section 100, the p-well region 23, or the p-well 22 of the circuit section 200, and may be formed in the same process as the body region 13 of the output section 100, the p-well region 23, or the p-well 22 of the circuit section 200. The second semiconductor region 4 may have the same depth and impurity concentration as, for example, the n-well 24 of the circuit section 200, and may be formed in the same process as the n-well 24 of the circuit section 200.

[0052] An insulating film 9 is formed on the upper surface side of the first semiconductor region 3 and the second semiconductor region 4. The opening of the insulating film 9 is p + The second potential terminal 72 is electrically connected to a second potential terminal (GND terminal) 72 via a contact region 7 of the mold. A second potential (GND potential) is applied to the second potential terminal.

[0053] A passive element 6, which is a PIP type capacitive element, is disposed on the upper surface of the insulating film 9. The passive element 6 has a laminated structure including a first conductive layer 61 provided on the upper surface of the insulating film 9, a dielectric layer 62 provided on the upper surface of the first conductive layer 61, and a second conductive layer 63 provided on the upper surface of the dielectric layer 62. A first terminal 81 is connected to the first conductive layer 61, and a second terminal 82 is connected to the second conductive layer 63.

[0054] FIG. 11 shows an equivalent circuit diagram of the semiconductor integrated circuit according to the first embodiment. As shown in FIG. 11, the semiconductor integrated circuit according to the first embodiment includes an output section 100 and a circuit section 200. The circuit elements 201 and 202 shown in FIG. 10 correspond to the MOS transistors T1 and T2 included in the circuit section 200 shown in FIG. 11. The MOS transistors T1 and T2 correspond to, for example, a part of a control circuit that controls the output section 100. The output stage element 101 shown in FIG. 10 corresponds to the MOS transistor T0 of the output section 100 shown in FIG. 11. A freewheel diode D0 is connected to the MOS transistor T0. The source terminal of the MOS transistor T0 is connected to the output terminal OUT, and the drain terminal of the MOS transistor T0 is connected to a first potential terminal (power supply terminal) VCC. Although not shown in FIG. 11, the semiconductor device 203 shown in FIG. 10 is included in the circuit section 200.

[0055] According to the semiconductor integrated circuit of the first embodiment, by applying the structure of the semiconductor device 203 to a power IC in which the output section 100 and the circuit section 200 are mounted together, the parasitic capacitance of the passive element 6 of the semiconductor device 203 can be reduced, and therefore, malfunction of the circuit section 200 connected to the passive element 6 can be suppressed. - The first semiconductor region 3 and the n - By forming the second semiconductor region 4 of the mold in the same process as other semiconductor regions of the output section 100 or the circuit section 200, an increase in the number of steps can be suppressed.

[0056] Second embodiment As shown in FIG. 12, the semiconductor device according to the second embodiment has n -A part of the second semiconductor region 4 of the p - 1 in that the second semiconductor region 4 does not extend outside the n-type first semiconductor region 3, and the left side surface of the second semiconductor region 4 substantially coincides with the left side surface of the first semiconductor region 3. - The second embodiment is in contact with the high resistivity layer 2 of the mold. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, so that a duplicated description will be omitted.

[0057] According to the semiconductor device of the second embodiment, n - A part of the second semiconductor region 4 of the p - Even if the n-type first semiconductor region 3 does not extend outside the n-type first semiconductor region 3, - A part of the second semiconductor region 4 of the n-type - If it is in contact with the high resistivity layer 2 of the mold, the same effects as those of the semiconductor device according to the first embodiment can be obtained.

[0058] Third embodiment As shown in FIG. 13, the semiconductor device according to the third embodiment has n - The second semiconductor region 4 is of p - 1 in that it is provided inside the first semiconductor region 3 of the n-type. + A contact area 10 of the n-type is provided. + An electrode 10a serving as a third electrode provided within an opening in an insulating film 9 is in contact with the contact region 10 of the mold. A third potential terminal 73 is connected to the electrode 10a. A potential higher than the second potential is applied to the third potential terminal 73 as a third potential. The third potential may be, for example, a VCC potential that is the same as the first potential applied to the first potential terminal 71. Other configurations of the semiconductor device according to the third embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0059] According to the semiconductor device of the third embodiment, n - The second semiconductor region 4 is of p -When the second semiconductor region 4 is provided inside the first semiconductor region 3 of the type, the second semiconductor region 4 can be set to the same potential as the semiconductor body (1, 2) by applying a VCC potential to the second semiconductor region 4 via the third potential terminal 73. Therefore, the same effects as those of the semiconductor device according to the first embodiment can be achieved.

[0060] (Fourth embodiment) 14, the semiconductor device according to the fourth embodiment differs from the planar layout of the semiconductor device according to the first embodiment shown in Fig. 2 in that the second semiconductor region 4 has a comb-tooth-shaped planar pattern. Stripe-shaped planar patterns (stripe portions) corresponding to the teeth of the comb-tooth shape formed by the second semiconductor region 4 extend parallel to the first semiconductor region 3 so as to overlap with each other.

[0061] The cross section seen from the AA direction passing through the teeth of the comb-tooth shape of the second semiconductor region 4 in Fig. 14 corresponds to Fig. 1. The cross section seen from the BB direction not passing through the teeth of the comb-tooth shape of the second semiconductor region 4 in Fig. 14 corresponds to Fig. 15. Other configurations of the semiconductor device according to the fourth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0062] In the semiconductor device of the fourth embodiment, the second semiconductor region 4 has a comb-tooth planar pattern, which increases the junction area between the second semiconductor region 4 and the first semiconductor region 3, making it easier to completely deplete the region directly below the passive element 6.

[0063] Fifth embodiment As shown in Fig. 16, the semiconductor device according to the fifth embodiment has a planar pattern of the second semiconductor region 4 that is different from the planar layout of the semiconductor device according to the fourth embodiment shown in Fig. 14. The second semiconductor region 4 has a striped planar pattern extending parallel to the first semiconductor region 3 so as to overlap with the second semiconductor region 4.

[0064] The cross section seen from the AA direction passing through the stripe portion of the second semiconductor region 4 in Fig. 16 corresponds to Fig. 1. The cross section seen from the BB direction not passing through the stripe portion of the second semiconductor region 4 in Fig. 16 corresponds to Fig. 17. Other configurations of the semiconductor device according to the fifth embodiment are similar to those of the semiconductor device according to the fourth embodiment, and therefore repeated explanations will be omitted.

[0065] According to the semiconductor device of the fifth embodiment, similarly to the semiconductor device of the fourth embodiment, the second semiconductor region 4 has a striped planar pattern, which increases the junction area between the second semiconductor region 4 and the first semiconductor region 3, making it easier to completely deplete the region directly below the passive element 6.

[0066] (Other embodiments) As described above, the present invention has been described by the first to fifth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art from this disclosure.

[0067] For example, in the first to fifth embodiments, the passive element 6 is exemplified as a PIP type capacitive element, but the passive element is not limited to a PIP type capacitive element. For example, as the passive element, other capacitive elements such as MIM (Metal-Insulator-Metal) type capacitive elements in which the first conductive layer 61 and the second conductive layer 63 are made of metal may be used. Furthermore, as the passive element, resistive elements, wiring, etc. may be used in addition to capacitive elements. When the passive element is a resistive element, a resistive element made of a polysilicon layer or the like may be provided on the insulating film 9, and terminals may be connected to both ends of the resistive element. When the passive element is a wiring, a wiring made of a metal or the like may be provided on the insulating film 9, and terminals may be connected to both ends of the wiring.

[0068] In the first embodiment, a trench-gate MOS transistor is exemplified as the output stage element 101, but the present invention is not limited to this. For example, the output stage element 101 may be a trench-gate IGBT. When the output stage element 101 is an IGBT, for example, +The low resistivity layer 1 of the p + Moreover, although a high-side power IC has been described as an example of a semiconductor integrated circuit to which the semiconductor device according to the first embodiment is applied, the present invention is also applicable to semiconductor integrated circuits other than high-side power ICs.

[0069] In the first to fifth embodiments, the semiconductor substrate (1, 2) is formed of Si. However, the present invention can be applied to a semiconductor substrate having a wider band gap than Si (wide band gap semiconductor), such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN).

[0070] In addition, the configurations disclosed in the first to fifth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0071] 1...Low resistivity layer 2...High resistivity layer 3...First semiconductor region 4...Second semiconductor region 5...Bottom electrode (back electrode) 6... Passive elements 7,10...Contact area 7a,10a...electrode 9...Insulating film 11...Semiconductor area 13...Body region (base region) 15a, 15b, 25, 29...Source region 16...Base contact area 17a, 17b...Trench 18, 27, 31...Gate insulating film 19a, 19b, 28, 32...gate electrodes 22,23,24...well 26,30...Drain area 61...First conductive layer (lower electrode) 62...Dielectric layer 63...Second conductive layer (upper electrode) 100...Output section 101...Output stage element 200...Circuit section 201, 202...Circuit elements 203...Semiconductor device

Claims

1. A semiconductor substrate of a first conductivity type; A first electrode electrically connected to the semiconductor substrate; a first semiconductor region of a second conductivity type provided on an upper portion of the semiconductor substrate; a second semiconductor region of a first conductivity type provided on an upper portion of the first semiconductor region; A second electrode electrically connected to the first semiconductor region; an insulating film provided on an upper surface side of the second semiconductor region; a passive element provided on an upper surface side of the insulating film; Equipped with The second semiconductor region has a striped planar pattern.

2. A semiconductor substrate of a first conductivity type; A first electrode electrically connected to the semiconductor substrate; a first semiconductor region of a second conductivity type provided on an upper portion of the semiconductor substrate; a second semiconductor region of a first conductivity type provided on an upper portion of the first semiconductor region; A second electrode electrically connected to the first semiconductor region; an insulating film provided on an upper surface side of the second semiconductor region; a passive element provided on an upper surface side of the insulating film; Equipped with A semiconductor device, characterized in that the second semiconductor region has a comb-tooth planar pattern, and stripe portions corresponding to the teeth of the comb shape overlap the first semiconductor region.

3. 3. The semiconductor device according to claim 1, wherein a portion of the second semiconductor region is in contact with the semiconductor substrate.

4. 4. The semiconductor device according to claim 1, wherein a portion of the second semiconductor region extends to an outside of the first semiconductor region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that when a first potential is applied to the first electrode and a second potential is applied to the second electrode, portions of the first semiconductor region and the second semiconductor region located directly below the passive element are depleted by a depletion layer extending from a junction between the semiconductor substrate and the first semiconductor region toward the first semiconductor region, and a depletion layer extending from a junction between the first semiconductor region and the second semiconductor region toward the first semiconductor region and the second semiconductor region.

6. the first conductivity type is n-type, A first potential is applied to the first electrode; A second potential lower than the first potential is applied to the second electrode.

5. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

7. the second semiconductor region is provided inside the first semiconductor region, a third electrode electrically connected to the second semiconductor region; 3. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

8. 8. The semiconductor device according to claim 7, wherein when a first potential is applied to the first electrode, a second potential is applied to the second electrode, and a third potential is applied to the third electrode, portions of the first semiconductor region and the second semiconductor region located directly below the passive element are depleted by a depletion layer extending from a junction between the semiconductor body and the first semiconductor region toward the first semiconductor region, and a depletion layer extending from a junction between the first semiconductor region and the second semiconductor region toward the first semiconductor region and the second semiconductor region.

9. the first conductivity type is n-type, A first potential is applied to the first electrode; A second potential lower than the first potential is applied to the second electrode; A third potential higher than the second potential is applied to the third electrode.

8. The semiconductor device according to claim 7,

10. 10. The semiconductor device according to claim 1, wherein the passive element constitutes a capacitance element, a resistance element, or a wiring.

11. the passive element is a capacitive element, a first conductive layer provided on an upper surface side of the insulating film; a dielectric film provided on an upper surface side of the first conductive layer; a second conductive layer provided on an upper surface side of the dielectric film; The semiconductor device according to claim 10 , further comprising:

12. 12. The semiconductor device according to claim 11, wherein the first conductive layer and the second conductive layer are made of polysilicon.

13. 13. The semiconductor device according to claim 1, wherein an output stage element and a circuit element for controlling the output stage element are provided on the semiconductor substrate.

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