Semiconductor Device

Abstract

To provide a semiconductor device capable of shortening a manufacturing time, reducing the manufacturing cost, and improving a breakdown voltage, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device includes an active portion 101, and an outer peripheral portion 102 having a second conductivity type guard ring 6a provided on a first conductivity type semiconductor layer 2 arranged around the active portion 101 and extending from the active portion 101. In the outer peripheral portion 102, isolation regions 17 are provided in a concentric ring shape so as to be adjacent to both adjacent guard rings 6a. The isolation region 17 contains both the first conductivity type first impurity and a second conductivity type second impurity.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique for reducing electric field concentration in a breakdown voltage structure region of a semiconductor device. [Background technology]

[0002] Conventionally, silicon (Si) semiconductors have been used in power semiconductor devices that are mainly used in power conversion devices and the like. In recent years, silicon carbide (SiC), a wide-gap semiconductor, has been expected to replace Si as a semiconductor material. Compared to conventional Si power semiconductor devices, SiC power semiconductor devices have advantages such as high voltage resistance, low loss, high-speed operation, and stable operation in high-temperature environments. This is due to the characteristics of the material itself, that is, compared to Si, SiC has a band gap about three times larger, a dielectric breakdown field strength about ten times higher, a saturated drift velocity about two times larger, and a thermal conductivity about three times larger.

[0003] Commercially available power semiconductor devices include Schottky barrier diodes (SBDs), field effect transistors (FETs), static induction transistors (SITs), and insulated gate bipolar transistors (IGBTs). Trench MOSFETs are three-dimensional semiconductor devices that form trenches in a SiC semiconductor substrate and use the sides of the trenches as channels. Therefore, when comparing devices with the same on-resistance, trench MOSFETs can overwhelmingly reduce the device area compared to planar vertical MOSFETs, making them a particularly promising semiconductor device structure.

[0004] In a high-voltage semiconductor device, a high electric field is likely to occur in the termination region on the periphery of the semiconductor device, and a voltage-resistant structure that alleviates electric field concentration is important. If a voltage-resistant structure is not provided, an electric field will concentrate in the termination region of the semiconductor device, and the semiconductor device will be destroyed at a low voltage. For this reason, a voltage-resistant structure such as a guard ring is provided in the termination region. In addition to the voltage-resistant structure in the termination region, a trench-type MOSFET also requires a structure that alleviates electric field concentration at the bottom of the gate trench to prevent destruction of the gate insulating film.

[0005] A guard ring as a voltage-resistant structure is generally formed by processing techniques such as photolithography and ion implantation. For example, in the case of a MOSFET, a mask for ion implantation is created by photolithography or the like using a photomask for the guard ring, and the guard ring is formed by ion implantation of p-type impurities on the upper surface of the n-type drift layer. Therefore, at least a photomask for the guard ring, an ion implantation process, and a mesa groove formation process are required, which increases the manufacturing time and cost.

[0006] In Patent Document 1, a base bottom buried region and a guard ring are simultaneously formed by ion implantation through a trench and burying and growing the trench. In Patent Document 2, ions are implanted deep inside from the upper surface of the drift layer to selectively form a guard ring together with the base bottom buried region. In the semiconductor devices described in Patent Documents 1 and 2, an electric field relaxation structure is not provided at the bottom of the gate trench. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2016-225455 A [Patent Document 2] JP 2019-054087 A Summary of the Invention [Problem to be solved by the invention]

[0008] In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can shorten the manufacturing time and reduce the manufacturing cost and improve the breakdown voltage. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device having (a) an active portion through which a main current flows and an outer periphery surrounding the active portion, (b) a semiconductor layer of a first conductivity type made of a wide band gap semiconductor, (c) a plurality of guard rings of a second conductivity type provided in the outer periphery inside the semiconductor layer so as to surround the active portion, and (d) an isolation region provided in the outer periphery in a concentric ring shape so as to be adjacent to both of the adjacent guard rings, wherein the isolation region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type.

[0010] Another aspect of the present invention is summarized as a method for manufacturing a semiconductor device having an active portion through which a main current flows and an outer periphery surrounding the active portion in a semiconductor layer of a first conductivity type made of a wide band gap semiconductor, the method including: (b) forming a semiconductor region of a second conductivity type on a surface of the semiconductor layer from the active portion to the outer periphery; and (c) forming concentric ring-shaped isolation regions and a guard ring sandwiched between the isolation regions by injecting impurities of the first conductivity type into the semiconductor region in the outer periphery so as to reach the semiconductor layer. Effect of the Invention

[0011] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the manufacturing time and manufacturing costs and improve the breakdown voltage. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view taken along the line AA in FIG. 1. [Diagram 3] 1A to 1C are cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4] 4 is a cross-sectional view illustrating an example of a step subsequent to FIG. 3 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Diagram 5] 5 is a cross-sectional view illustrating an example of a step subsequent to FIG. 4 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 6] 6 is a cross-sectional view illustrating an example of a step subsequent to FIG. 5 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 7] 7 is a cross-sectional view illustrating an example of a step subsequent to FIG. 6 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 8] 8 is a cross-sectional view illustrating an example of a step subsequent to FIG. 7 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 9] 9 is a cross-sectional view illustrating an example of a step subsequent to FIG. 8 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 10] 10 is a cross-sectional view illustrating an example of a step subsequent to FIG. 9 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 11] 11 is a cross-sectional view illustrating an example of a step subsequent to FIG. 10 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 12] 12 is a cross-sectional view illustrating an example of a step subsequent to FIG. 11 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 13] 13 is a cross-sectional view illustrating an example of a step subsequent to FIG. 12 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 14] 14 is a cross-sectional view illustrating an example of a step subsequent to FIG. 13 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 15] 5A to 5C are cross-sectional views illustrating another example of a process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 16] 16 is a cross-sectional view illustrating another example of a step subsequent to FIG. 15 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 17] 17 is a cross-sectional view illustrating another example of a step subsequent to FIG. 16 in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 18] FIG. 4 is a cross-sectional view of a semiconductor device according to a first modified example of the first embodiment of the present invention. [Figure 19] 10A to 10C are cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to a first modified example of the first embodiment of the present invention. [Figure 20] 20 is a cross-sectional view illustrating an example of a step subsequent to FIG. 19 in the method for manufacturing a semiconductor device according to a first modified example of the first embodiment of the present invention. FIG. [Figure 21] 21 is a cross-sectional view illustrating an example of a step subsequent to that in FIG. 20 in the method for manufacturing a semiconductor device according to the first modified example of the first embodiment of the present invention. FIG. [Figure 22] 22 is a cross-sectional view illustrating an example of a step subsequent to that in FIG. 21 in the method for manufacturing a semiconductor device according to a first modified example of the first embodiment of the present invention. FIG. [Diagram 23] 23 is a cross-sectional view illustrating an example of a step subsequent to that in FIG. 22 in the method for manufacturing a semiconductor device according to the first modified example of the first embodiment of the present invention. FIG. [Figure 24] FIG. 11 is a cross-sectional view of a semiconductor device according to a second modified example of the first embodiment of the present invention. [Diagram 25] 10A to 10C are cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to a second modified example of the first embodiment of the present invention. [Figure 26] 26 is a cross-sectional view illustrating an example of a step subsequent to FIG. 25 in the method for manufacturing a semiconductor device according to a second modified example of the first embodiment of the present invention. FIG. [Figure 27] 27 is a cross-sectional view illustrating an example of a step subsequent to FIG. 26 in the method for manufacturing a semiconductor device according to a second modified example of the first embodiment of the present invention. FIG. [Figure 28] 27 in a method for manufacturing a semiconductor device according to a second modified example of the first embodiment of the present invention. FIG. [Figure 29] 29 is a cross-sectional view illustrating an example of a step subsequent to FIG. 28 in the method for manufacturing a semiconductor device according to a second modified example of the first embodiment of the present invention. FIG. [Diagram 30] FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. [Diagram 31]6A to 6C are cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Diagram 32] 31 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 33] 33 is a cross-sectional view illustrating an example of a step subsequent to that in FIG. 32 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 34] 34 is a cross-sectional view illustrating an example of a step subsequent to FIG. 33 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 35] 35 is a cross-sectional view illustrating an example of a step subsequent to FIG. 34 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 36] 36 is a cross-sectional view illustrating an example of a step subsequent to FIG. 35 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Figure 37] 37 is a cross-sectional view illustrating an example of a step subsequent to FIG. 36 in the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. [Figure 38] 11 is a cross-sectional view showing another example of the voltage-resistant structure of the semiconductor device according to the second embodiment of the present invention. FIG. [Figure 39] 11 is a cross-sectional view showing another example of the voltage-resistant structure of the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 40] 11 is a cross-sectional view showing another example of the voltage-resistant structure of the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 41] 11 is a cross-sectional view showing another example of the voltage-resistant structure of the semiconductor device according to the second embodiment of the present invention. FIG. [Diagram 42] 13 is a diagram showing an example of an impurity concentration distribution by ion implantation in a voltage-resistant structure of a semiconductor device according to a second embodiment of the present invention. FIG. [Diagram 43] 43 is a cross-sectional view showing an example of a voltage-resistant structure having the impurity concentration distribution shown in FIG. 42. [Diagram 44] FIG. 11 is a plan view showing an example of a semiconductor substrate used in manufacturing a semiconductor device according to a third embodiment of the present invention. [Diagram 45]45 is a cross-sectional view taken along the line BB shown in FIG. 44. [Figure 46] FIG. 11 is a cross-sectional view showing an example of a voltage-resistant structure of a semiconductor device according to a third embodiment of the present invention. [Figure 47] FIG. 11 is a cross-sectional view showing another example of the voltage-resistant structure of the semiconductor device according to the third embodiment of the present invention. [Figure 48] FIG. 11 is a cross-sectional view showing an example of a voltage-resistant structure of a semiconductor device according to another embodiment of the present invention. [Figure 49] FIG. 11 is a cross-sectional view showing another example of a voltage-resistant structure of a semiconductor device according to another embodiment of the present invention. [Figure 50] FIG. 11 is a cross-sectional view showing another example of a voltage-resistant structure of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0014] In this specification, the source region of a MOS transistor is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is p-type and the opposite second conductivity type is n-type will be described as an example. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + and -. However, even if the same n and n are added to the semiconductor region, it does not mean that the impurity concentration of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

[0016] (First embodiment) <Structure of Semiconductor Device> As shown in FIG. 1, a SiC semiconductor device (semiconductor chip) 100 according to a first embodiment of the present invention is made up of an active portion 101 and an outer peripheral portion 102. For example, the active portion 101 has a rectangular planar shape, and the outer peripheral portion 102 is disposed around the active portion 101. FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. 1. As shown in FIG. 2, the active portion 101 includes an active element, and the outer peripheral portion 102 includes a termination structure. In FIG. 2, a first conductivity type (n - 1 shows an example in which a MOSFET with a trench gate structure provided on top of a drift layer 2 of a gate-type MOSFET includes a plurality of electric field relaxation regions (guard rings) 6a as a termination structure.

[0017] As shown in Fig. 2, a base region 6 of a second conductivity type (p type) is disposed on the upper surface of the drift layer 2. The drift layer 2 and the base region 6 are each composed of an epitaxially grown layer (hereinafter abbreviated as "epitaxial layer") made of SiC. + An n-type base contact region 8 is selectively provided on the upper portion of the base region 6. The n-type base contact region 8 is in contact with the base contact region 8 and has a higher impurity concentration than the drift layer 2. + A first main region (source region) 7 of the type is optionally provided.

[0018] For example, the impurity concentration of the drift layer 2 is 1×10 14 cm -3 More than 1×10 16 cm -3 Hereinafter, the impurity concentration of the base region 6 is 1×10 17 cm -3 More than 1×10 18 cm -3 The impurity concentration of the base contact region 8 is 5×10 18 cm -3 5×10 or more 20 cm -3 Hereinafter, the impurity concentration of the source region 7 is 5×10 18 cm -3 5×10 or more 20 cm -3 The following is the result.

[0019] A trench 9 having a width of 1 μm or less is provided from the upper surface of the source region 7 and the base region 6 through the base region 6. That is, the source region 7 and the base region 6 are in contact with the side surface of the trench 9. A gate insulating film 11 is provided on the bottom surface and side surface of the trench 9. A gate electrode 12 is embedded in the trench 9 via the gate insulating film 11 to form an insulated gate electrode structure (11, 12). As the gate insulating film 11, in addition to a silicon dioxide (SiO2) film, any one of a single layer film of a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, or a composite film obtained by stacking a plurality of these films can be used. As the material for the gate electrode 12, for example, a polysilicon layer (doped polysilicon layer) doped with impurities such as phosphorus (P) or boron (B) at a high impurity concentration can be used.

[0020] The upper part of the drift layer 2 is made of n-type semiconductor material having a higher impurity concentration than the drift layer 2. + A p-type current spreading layer (CSL) 3 is selectively provided. The bottom of the trench 9 reaches the current spreading layer 3. The current spreading layer 3 is not necessarily provided. If the current spreading layer 3 is not provided, the bottom of the trench 9 reaches the drift layer 2. Inside the current spreading layer 3, a p + A gate bottom protection region 4b of a shaped type is provided. Inside the current spreading layer 3, a first base bottom buried region 4a is provided below the base contact region 8 at a depth approximately the same as that of the gate bottom protection region 4b and spaced apart from the gate bottom protection region 4b. A second base bottom buried region 5 is provided above the current spreading layer 3 so as to contact an upper surface of the first base bottom buried region 4a and a lower surface of the base region 6. The second base bottom buried region 5 is also provided below the base contact region 8.

[0021] An interlayer insulating film 13 is disposed on the upper surface of the gate electrode 12. A silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used as the interlayer insulating film 13. However, the interlayer insulating film 13 may be a silicon oxide film (PSG) doped with phosphorus (P), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG) doped with boron (B), a Si3N4 film, or the like. A laminate film of these may also be used.

[0022] A source contact layer 14 is provided so as to be in physical contact with the source region 7 and base contact region 8 exposed between the interlayer insulating film 13. A first main electrode (source electrode) 15 is provided so as to cover the interlayer insulating film 13 and the source contact layer 14. A barrier metal layer (not shown) may be provided between the interlayer insulating film 13 and the source contact layer 14 and the first main electrode (source electrode) 15. The first main electrode (source electrode) 15 is electrically connected to the source region 7 and base contact region 8 via the barrier metal layer and the source contact layer 14. For example, if the source contact layer 14 is made of nickel silicide (NiSi x The field insulating film 10 is formed of a gate electrode pad (not shown) disposed on the upper surface of the field insulating film 10, and the source electrode 15 is formed of an aluminum (Al) film or an aluminum-silicon (Al-Si) film. The source electrode 15 is disposed separately from the gate surface electrode (not shown). Although not shown, a gate electrode pad (not shown) disposed on the upper surface of the field insulating film 10 is electrically connected to the gate electrode 12.

[0023] The bottom surface of the drift layer 2 is +A second main region (drain region) 1 of a type is disposed on the bottom surface of the drain region 1. A second main electrode (drain electrode) 16 is disposed on the bottom surface of the drain region 1. As the drain electrode 16, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Ti, nickel (Ni) and Au can be used, and further a metal film of molybdenum (Mo), tungsten (W) or the like may be laminated on the bottom layer. In addition, a drain contact layer may be provided between the drain region 1 and the drain electrode 16. The drain contact layer is, for example, nickel silicide (NiSi x ) membrane.

[0024] The impurity concentration of the current diffusion layer 3 is 5×10 16 cm -3 More than 3×10 18 cm -3 The impurity concentration of the first base bottom buried region 4a and the gate bottom protection region 4b is 1×10 18 cm -3 More than 1×10 19 cm -3 The impurity concentration of the second base bottom buried region 5 is 1×10 18 cm -3 More than 1×10 19 cm -3 The impurity concentration of the drain region 1 is 1×10 18 cm -3 More than 1×10 19 cm -3 The following is the result.

[0025] In the semiconductor device according to the first embodiment, the drain region 1 is made of a semiconductor substrate (SiC substrate) made of SiC, and the drift layer 2 is made of an epitaxial layer (SiC layer) made of SiC. The semiconductor region constituting the semiconductor device according to the first embodiment including the drain region 1 and the drift layer 2 is not limited to SiC. In addition to SiC, for example, hexagonal semiconductor materials such as gallium nitride (GaN), lonsdaleite (hexagonal diamond), and aluminum nitride (AlN) having a wider bandgap than that of Si (1.1 eV) can be used. The bandgap at room temperature has been reported to be 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. In the present invention, a semiconductor having a bandgap wider than that of silicon is defined as a wide bandgap semiconductor.

[0026] During operation of the semiconductor device according to the first embodiment, when the source electrode 15 is set to earth potential, a positive voltage is applied to the drain electrode 16, and a positive voltage equal to or greater than a threshold is applied to the gate electrode 12, an inversion layer (channel) is formed on the side of the trench 9 in the base region 6, resulting in an ON state. The inversion layer is formed on the surface of the base region 6 exposed on the side of the trench 9, which is the interface between the base region 6 and the gate insulating film 11 sandwiched at a position where the base region 6 faces the gate electrode 12. In the ON state, a current flows from the drain electrode 16 to the source electrode 15 via the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layer of the base region 6, and the source region 7. On the other hand, when the voltage applied to the gate electrode 12 is less than the threshold, no inversion layer is formed in the base region 6, resulting in an OFF state, and no current flows from the drain electrode 16 to the source electrode 15.

[0027] As shown in FIG. 2, in the peripheral portion 102, an n-type junction is formed through the p-type base region 6 extending from the active portion 101. -A plurality of n-type isolation regions 17 are provided, which reach the n-type drift layer 2. The isolation regions 17 are provided in a concentric ring shape so as to surround the active section 101. The p-type base region 6 sandwiched between the isolation regions 17 constitute a plurality of p-type electric field relaxation regions (guard rings) 6a. Therefore, the guard rings 6a and the isolation regions 17 are provided alternately in contact with each other. The impurity concentration of the second conductive type impurity contained in the p-type base region 6, the guard rings 6a, and the isolation regions 17 is the same. The p-type electric field relaxation regions (guard rings) 6a are provided in a concentric ring shape, spaced apart from each other by the isolation regions 17. The p-type impurity concentration of each of the guard rings 6a is 1×10 17 cm -3 More than 1×10 18 cm -3 Each of the isolation regions 17 is a co-doped region in which an n-type impurity is added to the base region 6 containing a p-type impurity, and the p-type impurity concentration is 1×10 17 cm -3 More than 1×10 18 cm -3 Below, the n-type impurity concentration is 1×10 17 cm -3 More than 3×10 18 cm -3 2 illustrates an n-type isolation region 17, but the isolation region 17 may be p-type. If there is a difference in p-type impurity concentration between the guard ring 6a and the isolation region 17, it is possible to alleviate electric field concentration. An interlayer insulating film 13 extending from the active section 101 is provided on the upper surfaces of the guard ring 6a and the isolation region 17 with a field insulating film 10 interposed therebetween.

[0028] At the outer end of the outer periphery 102, n + The channel stoppers may be arranged in concentric rings. + Instead of a channel stopper of type p + A molded channel stopper may be provided.

[0029] In the semiconductor device according to the first embodiment, a p-type base region 6 extending from the active portion 101 to the outer peripheral portion 102 is selectively doped with n-type impurities to provide a plurality of concentric ring-shaped isolation regions 17. The base region 6 (p-type epitaxial layer) remaining in the portion sandwiched between the plurality of isolation regions 17 becomes a plurality of concentric ring-shaped p-type guard rings 6a. In the semiconductor device according to the first embodiment, a mesa groove forming process is not required, and the guard rings 6a can be provided by forming the isolation regions 17 by ion implantation of n-type impurities. In this way, the semiconductor device according to the first embodiment has a simple configuration, and the manufacturing process can be simplified. Ion implantation of p-type impurities requires high-temperature ion implantation to increase the injection efficiency, and a photoresist film cannot be used as a mask for ion implantation, and a mask material such as an oxide film is required. On the other hand, ion implantation of n-type impurities can be performed even at room temperature, so a photoresist film can be used as an ion implantation mask. In this way, deposition of an oxide film or the like is not required, and the guard ring forming process can be shortened. In addition, photolithography technology allows the pattern of the photoresist film to be finely patterned. Furthermore, since the active portion 101 and the peripheral portion 102 are flat, the pattern of the photoresist film can be made finer, and the pattern of the multiple guard rings 6a formed in the peripheral portion 102 can be reduced. This makes it possible to increase the area of ​​the active portion, increase the current capacity, and reduce the dimensions of the semiconductor chip. In this way, the number of steps in the guard ring formation process and the mesa groove formation process can be reduced, making it possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[0030] <Method of Manufacturing Semiconductor Device> Next, the method for manufacturing the SiC semiconductor device according to the first embodiment will be described using the process cross-sectional views of Figures 3 to 14 as an example of a trench-gate MOSFET. Note that the method for manufacturing the trench-gate MOSFET described below is only an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit of the claims.

[0031] First, n-type impurities such as nitrogen (N) are added. + A type SiC semiconductor substrate (substrate) 1p is prepared. As shown in FIG. 3, an n - A n-type drift layer 2p is epitaxially grown. Next, a photoresist film is applied to the upper surface of the drift layer 2p, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the active portion 101 of the drift layer 2 from the upper surface side of the drift layer 2p. In this manner, an n-ion implanted layer 3p is formed on the upper portion of the drift layer 2p in the active portion 101.

[0032] An oxide film made of SiO2 is deposited on the upper surface of the n ion implantation layer 3p and the drift layer 2p by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film 40 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the n ion implantation layer 3p. As a result, as shown in FIG. 4, a first base bottom buried region 4a and a gate bottom protection region 4b are selectively formed on the upper portion of the n ion implantation layer 3p.

[0033] After removing the oxide film 40, an n ion implantation layer 3p, a first base bottom buried region 4a, a gate bottom protection region 4b, and an upper surface of the drift layer 2p are implanted with n -A type epitaxial layer 55 is grown. A photoresist film is applied to the surface of the epitaxial layer 55, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper part of the epitaxial layer 55 from the upper surface side of the epitaxial layer 55. As a result, as shown in FIG. 5, an n-ion implantation layer 5p is formed on the n-ion implantation layer 3p, the first base bottom buried region 4a, and the gate bottom protection region 4b. As will be described later, the n-ion implantation layer 3p and the n-ion implantation layer 5p constitute the current spreading layer 3, and it is desirable that the impurity concentration of the n-ion implantation layer 5p is higher than that of the n-ion implantation layer 3p.

[0034] Next, an oxide film made of SiO2 is deposited on the upper surface of the n ion implantation layer 5p and the epitaxial layer 55 by CVD or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography and dry etching or the like. Using the patterned oxide film 60 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the n ion implantation layer 5p. As a result, as shown in FIG. 6, the second base bottom buried region 5 is selectively formed on the first base bottom buried region 4a. Also, a drift layer 2 made of the drift layer 2p and the epitaxial layer 55 is formed.

[0035] After removing the oxide film 60, a p-type base region 6p is epitaxially grown on the upper surface of the second base bottom buried region 5, the n ion implantation layer 5p, and the drift layer 2. An oxide film made of SiO2 is deposited on the surface of the base region 6p by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the base region 6p in multiple stages from the upper surface side of the base region 6p. As a result, as shown in FIG. 7, a base contact region 8 is formed on the upper surface of the base region 6p above the second base bottom buried region 5 and the n ion implantation layer 5p.

[0036] After removing the oxide film used as the ion implantation mask, an oxide film made of SiO2 is deposited on the upper surface of the base contact region 8 and the base region 6p by CVD or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography and dry etching or the like. Using the patterned oxide film 70 as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted into the base region 6p in multiple stages from the upper surface side of the base region 6p. As a result, as shown in FIG. 8, a source region 7 is formed on the upper surface of the base region 6p above the n ion implantation layer 5p.

[0037] After removing the oxide film 70 used as an ion implantation mask, a photoresist film is applied to the upper surfaces of the base contact region 8, the source region 7, and the base region 6p, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 80 as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages from the upper surface side of the base region 6p so as to penetrate the base region 6p and reach the drift layer 2. As a result, as shown in FIG. 9, a plurality of n-type isolation regions 17 are provided in the base region 6p of the outer periphery 102. In addition, the base region 6p sandwiched between the plurality of isolation regions 17 becomes a plurality of p-type guard rings 6a, which are formed in a concentric ring shape spaced apart from each other. That is, the plurality of guard rings 6a and the plurality of isolation regions 17 are alternately provided in contact with each other. In addition, the base region 6p in the active portion 101 becomes the base region 6. Therefore, the impurity concentrations of the second conductivity type impurities contained in the p-type base region 6, the guard ring 6a, and the isolation region 17 are the same.

[0038] After removing the photoresist film 80 used as an ion implantation mask, an oxide film made of SiO2 is deposited on the upper surfaces of the base contact region 8, the source region 7, and the base region 6p by CVD or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography and dry etching techniques. Using the patterned oxide film 90 as an etching mask, a trench 9 is selectively formed by dry etching techniques such as ICP-RIE. The trench 9 penetrates the source region 7, the base region 6, and the n-ion implantation layer 5p to reach the gate bottom protection region 4b. After removing the oxide film 90, a carbon (C) film is formed on the upper surface of the trench 9 by carbon sputtering or the like.

[0039] Thereafter, a heat treatment is performed to simultaneously activate the implanted n-type impurity ions and p-type impurity ions. As a result, as shown in FIG. 10, a n-type ion implanted layer 3p and a n-type ion implanted layer 5p are formed. + A p-type current spreading layer 3 is formed on the upper surface of the drift layer 2.+ The first base bottom buried region 4a of the p type is sandwiched between the first base bottom buried region 4a and the base region 6. + The bottom of the trench 9 is provided with a p + A gate bottom protection region 4b of the n-type is formed on the upper surface of the base region 6 so as to contact the trench 9. + A p-type source region 7 and a p-type ... + In addition, a plurality of p-type base contact regions 8 are formed in the outer periphery 102. Furthermore, a plurality of p-type guard rings 6a are formed in the shape of concentric rings spaced apart from each other with a plurality of n-type isolation regions 17 interposed therebetween.

[0040] After removing the carbon film, a field oxide film is deposited on the exposed surface by CVD or the like. A photoresist film is applied to the upper surface of the field oxide film, and the photoresist film is patterned by photolithography and dry etching or the like. The patterned photoresist film is used as an etching mask to selectively remove the field oxide film. As a result, as shown in FIG. 11, a field insulating film 10 is formed on the upper surfaces of the guard ring 6a and the isolation region 17.

[0041] 12, a gate insulating film 11p such as a SiO2 film is formed on the bottom and side surfaces of the trench 9 and on the upper surfaces of the source region 7 and the base contact region 8 by thermal oxidation or chemical vapor deposition (CVD) technology. Next, a polysilicon layer (doped polysilicon layer) 12p doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD technology or the like so as to fill the trench 9. As shown in FIG. 12, the polysilicon layer 12p extends so as to cover the upper surface of the field insulating film 10 in the outer periphery 102.

[0042] Then, a part of the polysilicon layer 12p and a part of the gate insulating film 11p are selectively removed by photolithography and dry etching. As shown in FIG. 13, a pattern of the gate electrode 12 consisting of the gate insulating film 11 and the polysilicon layer is formed to form an insulated gate electrode structure (11, 12). Next, an insulating film is deposited on the upper surface of the insulated gate electrode structure (11, 12) consisting of the gate electrode 12 and the gate insulating film 11 by CVD or the like. As this insulating film, boron phosphorus glass (BPSG), NSG, or the like is used. Then, a part of the deposited insulating film is selectively removed by photolithography and dry etching or the like. As a result, a source electrode contact hole is opened in the interlayer insulating film 13 as shown in FIG. 13. Although not shown, a gate contact hole is also opened in the interlayer insulating film 13 at a location different from the source electrode contact hole so that a part of the gate surface electrode connected to the gate electrode 12 is exposed.

[0043] A metal layer such as a Ni film is deposited by sputtering or vapor deposition, and the metal layer is patterned by photolithography and RIE. Then, rapid thermal annealing (RTA), for example, at about 1000°C, is performed to form NiSi x Then, the unreacted Ni film is removed to form a source contact layer 14 on the upper surfaces of the source region 7 and the base contact region 8 (FIG. 14). Next, a barrier metal layer (not shown) such as a Ti film or a TiN film and a metal layer such as an Al film are deposited by sputtering or the like, and the barrier metal layer and the metal layer are patterned by photolithography and RIE or the like. As a result, a laminated structure of the barrier metal layer and the source electrode 15 is formed so as to cover the source contact layer 14 and the interlayer insulating film 13. In addition, the patterns of the source electrode 15 and the gate surface electrode are separated, and the gate surface electrode is electrically connected to the gate electrode 12a via a wiring layer (not shown) provided on the field insulating film 10.

[0044] Furthermore, the bottom surface of the substrate 1p is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Thereafter, a drain electrode 16 made of Ti, Ni, Au or the like is formed on the entire bottom surface of the drain region 1 by a sputtering method or a deposition method or the like. In this manner, the trench gate type semiconductor device shown in FIG. 2 is completed.

[0045] In the manufacturing method of the semiconductor device according to the first embodiment, a plurality of isolation regions 17 are formed by ion-implanting n-type impurities into the base region 6 extending to the outer periphery 102, and a plurality of p-type guard rings 6a are formed in a concentric ring shape by isolating them from one another. In a conventional trench-gate type semiconductor device, a mesa groove is provided in the outer periphery 102 to remove the base region, and a guard ring is formed by ion-implanting p-type impurities into the exposed drift layer. In the semiconductor device according to the first embodiment, the mesa groove formation process is unnecessary, and the manufacturing process can be shortened. In addition, the guard ring 6a can be provided by forming the isolation region 17 by ion-implanting n-type impurities. The ion implantation of p-type impurities requires high-temperature ion implantation to increase the injection efficiency, and a photoresist film cannot be used as a mask for ion implantation, and a mask material such as an oxide film is required. On the other hand, the ion implantation of n-type impurities can be performed even at room temperature, so a photoresist film can be used as an ion implantation mask. In this way, deposition of an oxide film or the like is not necessary, and the guard ring formation process can be shortened. In addition, the photolithography technology allows the pattern of the photoresist film to be finely formed. Furthermore, since the active portion 101 and the peripheral portion 102 are flat, the pattern of the photoresist film can be made finer, and the pattern of the multiple guard rings 6a formed in the peripheral portion 102 can be reduced. This makes it possible to increase the current capacity of the semiconductor chip and reduce the dimensions of the semiconductor chip. In this way, the number of steps in the guard ring formation process and the mesa groove formation process can be reduced, making it possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[0046] In the above description, in order to form the multiple guard rings 6a, the multiple isolation regions 17 are formed by ion implantation, penetrating the base region 6 and reaching the drift layer 2. If the capacity of the ion implantation device is insufficient and ions cannot be implanted through the base region 6, the base region 6 may be formed multiple times, for example, in two separate steps.

[0047] For example, as shown in FIG. 6, the second base bottom buried region 5 is selectively formed on the first base bottom buried region 4a. Then, as shown in FIG. 15, the p-type first base region 6pa is epitaxially grown on the upper surface of the second base bottom buried region 5, the n ion implantation layer 5p, and the drift layer 2. A photoresist film is applied to the upper surface of the first base region 6pa, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages from the upper surface side of the first base region 6pa so as to penetrate the first base region 6pa and reach the drift layer 2. As a result, as shown in FIG. 15, a plurality of n-type first isolation regions 17a are provided in the first base region 6pa of the outer periphery 102, and a plurality of p-type first guard rings 6aa are formed in a concentric ring shape spaced apart from each other.

[0048] After removing the photoresist film used as the ion implantation mask, the p-type second base region 6pb is epitaxially grown on the upper surfaces of the first base region 6pa, the first guard ring 6aa, and the first isolation region 17a. A photoresist film is applied to the upper surface of the first base region 6pb, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 72 as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages from the upper surface side of the second base region 6pb so as to penetrate the second base region 6pb and reach the first isolation region 17a. As a result, as shown in FIG. 16, a plurality of n-type second isolation regions 17b are provided in the second base region 6pb of the outer periphery 102 in contact with the plurality of first isolation regions 17a. A plurality of p-type second guard rings 6ab are formed in contact with the first guard ring 6aa and spaced apart from each other in a concentric ring shape.

[0049] After removing the photoresist film 72, the base region 6p consisting of the first and second base regions 6pa, 6pb, the guard ring 6a consisting of the first and second guard rings 6aa, 6ab, and the isolation region 17 consisting of the first and second isolation regions 17a, 17b are formed. An oxide film consisting of SiO2 is deposited on the surfaces of the base region 6p, the guard ring 6a, and the isolation region 17 by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the base region 6p in multiple stages from the upper surface side of the base region 6p. As a result, a base contact region 8 is formed on the upper surface of the base region 6p above the second base bottom buried region 5 and the n ion implantation layer 5p.

[0050] After removing the oxide film used as the ion implantation mask, an oxide film made of SiO2 is deposited on the upper surface of the base contact region 8 and the base region 6p by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted into the base region 6p in multiple stages from the upper surface side of the base region 6p. As a result, as shown in FIG. 17, the source region 7 is formed on the upper surface of the base region 6p above the n ion implantation layer 5p. The subsequent steps are the same as those shown in FIG. 10 to FIG. 14, so repeated explanations will be omitted. Here, when a channel stopper is formed at the outer end of the outer periphery 102, ions may be implanted into the outer end during the steps of forming the base contact region 8 and the source region 7.

[0051] (First Modification of the First Embodiment) As shown in FIG. 18, the semiconductor device according to the first modification of the first embodiment has a p + The n-type semiconductor layer 66 is formed by passing through the n-type base contact region 8a. + The present embodiment differs from the first embodiment in that multiple isolation regions 7b of a type are provided. The semiconductor layer 66 is provided in the outer periphery 102 at the depth of the base region 6b, and is provided on the upper surface of the drift layer 2, and is in contact with the side surface of the base region 6b of the active part 101, the lower surface of the multiple isolation regions 7b, and the lower surface of the guard ring 8b. An n-type semiconductor layer having a higher impurity concentration than the drift layer 2 is provided on the upper part of the base region 6b so as to be in contact with the base contact region 8a. + A source region 7a of the semiconductor device according to the second embodiment is selectively provided. The other configuration is the same as that of the semiconductor device according to the first embodiment, so a duplicated description will be omitted.

[0052] As shown in FIG. 6, the second base bottom buried region 5 is selectively formed on the first base bottom buried region 4a, and then, as shown in FIG. 19, an n-type semiconductor layer 66 is epitaxially grown on the upper surface of the second base bottom buried region 5, the n ion implantation layer 5p, and the drift layer 2. An oxide film made of SiO2 is deposited on the surface of the semiconductor layer 66 by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the semiconductor layer 66 in multiple stages from the upper surface side of the semiconductor layer 66. As a result, as shown in FIG. 20, a base region 6bp is formed on the upper surface of the second base bottom buried region 5 and the n ion implantation layer 5p.

[0053] After removing the oxide film used as the ion implantation mask, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the base region 6bp and the semiconductor layer 66 from the upper surface side of the base region 6bp and the semiconductor layer 66. As a result, as shown in FIG. 21, a base contact region 8p is formed on the base region 6bp and the semiconductor layer 66.

[0054] Thereafter, a photoresist film is applied to the upper surface of the base contact region 8p, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted in multiple stages into the base contact region 8p from the upper surface side of the base contact region 8p. As a result, as shown in FIG. 22, n-type impurity ions such as phosphorus (P) are implanted in the base contact region 8a above the base region 6b. + A n-type source region 7a is formed. Also, a n-type ... + In this way, a plurality of isolation regions 7b of the p +A plurality of n-type guard rings 8b are formed in a concentric ring shape spaced apart from each other. Each of the plurality of isolation regions 7b contains not only n-type impurities ion-implanted, but also p-type impurities contained in the base contact region 8a. + Since the impurity concentration of the n-type source region 7a is at least one order of magnitude higher than the impurity concentrations of the semiconductor layer 66 and the base region 6b, the depth of the base contact region 8a and the depth of the guard ring 8b are the same. The depth of the isolation region 7b is the same as the depth of the source region 7a. Although the isolation region 7b has been described as an n-type semiconductor layer, it may be a p-type semiconductor layer. Also, after the base region 6b is formed over the entire surface by p-type epitaxial growth, the semiconductor layer 66 may be formed by injecting n-type impurities.

[0055] Then, a trench 9 is formed by CVD, photolithography, dry etching, etc., penetrating the source region 7a, base region 6b, and n-ion implantation layer 5p to reach the gate bottom protection region 4b. A carbon (C) film is formed on the upper surface of the trench 9 by carbon sputtering, etc. The implanted n-type impurity ions and p-type impurity ions are activated simultaneously by activation heat treatment, etc. On the exposed surface after removing the carbon film, a field insulating film 10 is selectively formed on the upper surface of the guard ring 8b and the isolation region 7b by CVD, photolithography, dry etching, etc. A gate insulating film 11p such as a SiO2 film is formed on the bottom and side surfaces of the trench 9 and on the upper surfaces of the source region 7a and base contact region 8a by thermal oxidation or CVD, etc., as shown in FIG. 23. Next, a polysilicon layer 12p to which impurities such as phosphorus (P) and boron (B) are added at a high concentration is deposited by CVD, etc., so as to fill the trench 9. 23, the polysilicon layer 12p extends so as to cover the upper surface of the field insulating film 10 in the outer periphery 102. The subsequent steps are similar to those shown in FIGS.

[0056] In the first modification of the first embodiment, in the outer peripheral portion 102, p+ The n-type semiconductor layer 66 is formed by passing through the n-type base contact region 8a. + A plurality of p-type isolation regions 7b are formed. A plurality of p-type guard rings 8b are separated from each other and formed in a concentric ring shape. In the first modification of the first embodiment, the mesa groove forming process is unnecessary, and the manufacturing process can be shortened. In addition, the guard ring 8b is provided by forming the isolation region 7b by ion implantation of n-type impurities. Since ion implantation of n-type impurities is possible even at room temperature, a photoresist film can be used as an ion implantation mask. In this way, deposition of an oxide film or the like is unnecessary, and the guard ring forming process can be shortened. In addition, the photolithography technique allows the pattern of the photoresist film to be finer. Furthermore, since the active portion 101 and the outer peripheral portion 102 are flat, the pattern of the photoresist film can be further finer, and the pattern of the plurality of guard rings 8b formed in the outer peripheral portion 102 can be reduced, and the dimensions of the semiconductor chip can be reduced. In this way, in the first modification of the first embodiment, the number of steps in the guard ring forming process and the mesa groove forming process can be reduced, and it is possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[0057] (Second Modification of the First Embodiment) 24, the semiconductor device according to the second modification of the first embodiment is different from the first modification of the first embodiment in that a mesa groove 9b is provided at the boundary between the active portion 101 and the peripheral portion 102. In addition, the p-type base region 6c in the active portion 101 is provided on the upper surface of the p-type base region 6c. + A base contact region 8c extends through the mesa groove 9b onto the upper surface of the drift layer 2 in the outer circumferential portion 102. An n-type dopant layer having a higher impurity concentration than the drift layer 2 is disposed on the upper portion of the base region 6c so as to contact the base contact region 8c. + A source region 7c of the semiconductor device according to the first modification of the first embodiment is selectively provided. Since the other configurations are similar to those of the semiconductor device according to the first modification of the first embodiment, a duplicated description will be omitted.

[0058] As shown in FIG. 6, the second base bottom buried region 5 is selectively formed on the first base bottom buried region 4a, and then, as shown in FIG. 25, a p-type base region 6cp is epitaxially grown on the second base bottom buried region 5, the n ion implantation layer 5p, and the upper surface of the drift layer 2. An oxide film made of SiO2 is deposited on the surface of the base region 6cp by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology, or the like. As shown in FIG. 26, the base region 6cp is partially etched by dry etching technology or the like using the patterned oxide film 71 as an etching mask to form a mesa groove 9b. In the outer periphery 102, the base region 6cp is left on the upper surface of the drift layer 2.

[0059] After removing the oxide film 71 used as the etching mask, p-type impurity ions such as aluminum (Al) are implanted into the entire surface of the base region 6cp from the upper surface side of the base region 6cp in multiple stages. As a result, as shown in FIG. 27, a base contact region 8cp is formed on the upper surface of the base region 6c and the drift layer 2.

[0060] Thereafter, a photoresist film is applied to the upper surface of the base contact region 8cp, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 81 as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted in multiple stages into the base contact region 8cp from the upper surface side of the base contact region 8cp. As a result, as shown in FIG. 28, n-type impurity ions such as phosphorus (P) are implanted in the base contact region 8c above the base region 6c. + A n-type source region 7c is formed. In addition, an n-type source region 7c is formed by penetrating the base contact region 8c extending on the upper surface of the drift layer 2 and reaching the drift layer 2. + A plurality of isolation regions 7d of the p-type are formed. At this time, the base contact region 8cp remaining in the active portion 101 becomes the base contact region 8c. In addition, the base contact region 8cp sandwiched between the plurality of isolation regions 7d becomes the p +The isolation regions 7d are each formed into a plurality of guard rings 8d of a second conductivity type, which are spaced apart from each other and are formed in a concentric ring shape. Each of the isolation regions 7d contains not only n-type impurities ion-implanted, but also p-type impurities contained in the base contact region 8c. The guard rings 8d and the isolation regions 7d are alternately provided in contact with each other. The impurity concentration of the second conductivity type impurity in the guard rings 8d is the same as the impurity concentration of the second conductivity type impurity in the base contact region 8c. The impurity concentration of the first conductivity type impurity in the isolation regions 7d is the same as the impurity concentration of the first conductivity type impurity in the source region 7c. Although the isolation regions 7d have been described as an n-type semiconductor layer, they may be a p-type semiconductor layer.

[0061] Then, a trench 9 is formed by CVD, photolithography, dry etching, etc., penetrating the source region 7c, base region 6c, and n-ion implantation layer 5p to reach the gate bottom protection region 4b. A carbon (C) film is formed on the upper surface of the trench 9 by carbon sputtering, etc. The implanted n-type impurity ions and p-type impurity ions are activated simultaneously by activation heat treatment, etc. On the exposed surface after removing the carbon film, a field insulating film 10 is selectively formed on the upper surface of the guard ring 8d and the isolation region 7d by CVD, photolithography, dry etching, etc. As shown in FIG. 29, a gate insulating film 11p such as a SiO2 film is formed on the bottom and side surfaces of the trench 9 and on the upper surfaces of the source region 7c and base contact region 8c by thermal oxidation or CVD, etc. Next, a polysilicon layer 12p to which impurities such as phosphorus (P) and boron (B) are added at a high concentration is deposited so as to fill the trench 9 by CVD, etc. 29, the polysilicon layer 12p extends so as to cover the upper surface of the field insulating film 10 in the outer periphery 102. The subsequent steps are similar to those shown in FIGS.

[0062] In the second modification of the first embodiment, a mesa groove 9b is provided at the boundary between the active section 101 and the peripheral section 102, and a p+ The n-type base contact region 8c is penetrated to reach the n-type drift layer 2. + A plurality of p-type isolation regions 7d are formed. A plurality of p-type guard rings 8d are separated from each other and formed in a concentric ring shape. In the second modification of the first embodiment, a mesa groove forming process is introduced, but the base contact region 8c is formed by full-surface ion implantation, so the number of photomasks and the high constant can be reduced. In addition, the guard ring 8d is provided by forming the isolation region 7d by ion implantation of n-type impurities. Since ion implantation of n-type impurities is possible even at room temperature, the photoresist film 81 can be used as an ion implantation mask. In this way, deposition of an oxide film or the like is not required, and the guard ring forming process can be shortened. In addition, in the photolithography technique, the pattern of the photoresist film can be made fine, and the pattern of the plurality of guard rings 8d formed in the outer periphery 102 can be reduced, and the dimensions of the semiconductor chip can be reduced. In this way, in the second modification of the first embodiment, the number of steps in the base contact region forming process and the guard ring forming process can be reduced, and it is possible to shorten the manufacturing time and the manufacturing cost of the semiconductor device.

[0063] Second embodiment <Structure of Semiconductor Device> As shown in FIG. 30, the semiconductor device according to the second embodiment of the present invention has a mesa groove 9c penetrating the base region 6d in the outer periphery 102, and a p + A plurality of guard rings (4c, 5a) of type and + The difference from the first embodiment is that a plurality of isolation regions 5n of the p-type are provided. + The first region 4c and p +The guard ring (4c, 5a) is composed of a second region 5a of a type having a gate-type impurity concentration higher than that of the drift layer 2. The second regions 5a of the guard ring (4c, 5a) and the isolation regions 5n are alternately provided in contact with each other. The first region 4c is at the same level as the first base bottom buried region 4a and the gate bottom protection region 4b, and the second region 5a is at the same level as the second base bottom buried region 5. An n-type impurity concentration higher than that of the drift layer 2 is provided at the top of the base region 6d so as to contact the base contact region 8e. + A source region 7e of a type is selectively provided. A field insulating film 10b and an interlayer insulating film 13b extend from near the boundary between the active portion 101 and the outer peripheral portion 102 to the bottom of the mesa groove 9c. The other configuration is the same as that of the semiconductor device according to the first embodiment, so a duplicated description will be omitted.

[0064] In the semiconductor device according to the second embodiment, the guard ring (4c, 5a) is composed of a first region 4c and a second region 5a. The first region 4c can be formed by ion-implanting p-type impurities into the first base bottom buried region 4a and the gate bottom protection region 4b at the same level. Similarly, the second region 5a can be formed by ion-implanting p-type impurities into the second base bottom buried region 5 at the same level. In this way, in the second embodiment, the guard ring (4c, 5a) can be formed in the process of forming the first base bottom buried region 4a and the gate bottom protection region 4b and the process of forming the second base bottom buried region 5. A dedicated photomask for forming the guard ring and a guard ring forming process are not required, and it is possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[0065] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a SiC semiconductor device according to the second embodiment will be described using the process cross-sectional views of Figures 31 to 37, taking a trench-gate MOSFET as an example. Note that the method for manufacturing a trench-gate MOSFET described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0066] First, n-type impurities such as nitrogen (N) are added.+ A type SiC semiconductor substrate (substrate) 1p is prepared. n epitaxially grown on the top surface of the substrate 1p. - A photoresist film is applied to the upper surface of the drift layer 2 of the mold, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the active portion 101 of the drift layer 2 from the upper surface side of the drift layer 2. In this way, n-type impurity ions such as nitrogen (N) are implanted in the upper portion of the drift layer 2 in the active portion 101. + Thus, an n-type ion-implanted layer 3p is formed.

[0067] An oxide film made of SiO2 is deposited on the n ion implantation layer 3p and the upper surface of the drift layer 2 by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the n ion implantation layer 3p. As a result, as shown in FIG. 31, in the active portion 101, p-type impurity ions such as aluminum (Al) are formed on the upper part of the drift layer 2 so as to contact the n ion implantation layer 3p. + The first base bottom buried region 4a and p + In the outer peripheral portion 102, a p-type gate bottom protection region 4b is selectively formed on the top of the drift layer 2. + A first region 4c of the mold is formed.

[0068] After removing the oxide film used as a mask for ion implantation, n ions are implanted into the n ion implantation layer 3p, the first base bottom buried region 4a, the gate bottom protection region 4b, the first region 4c, and the upper surface of the drift layer 2. - Then, p-type epitaxial layer is grown. Then, p-type impurity ions are implanted on the entire surface to form p +A p-type ion implantation layer 55a is formed (FIG. 32). A photoresist film is applied to the surface of the p ion implantation layer 55a, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 50 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper part of the p ion implantation layer 55a from the upper surface side of the p ion implantation layer 55a. As a result, as shown in FIG. 33, in the active portion 101, n-type impurity ions such as nitrogen (N) are formed on the n ion implantation layer 3p and the gate bottom protection region 4b. + A type n ion implanted layer 5p is formed. Also, a p ion implanted layer 55a in a portion where ions are not implanted becomes the second base bottom buried region 5, and is formed on the first base bottom buried region 4a. As will be described later, the n ion implanted layer 3p and the n ion implanted layer 5p form the current spreading layer 3, and it is desirable that the impurity concentration of the n ion implanted layer 5p is higher than that of the n ion implanted layer 3p.

[0069] In the outer peripheral portion 102, n is formed on the drift layer 2 sandwiched between the first regions 4c. + The p-type isolation region 5n is formed. Then, the p-type ion-implanted layer 55a remaining in the portion sandwiched between the isolation regions 5n is p + The second region 5a is a n-type second region 5a, which is formed on the first region 4c. The guard rings (4c, 5a) consisting of the first region 4c and the second region 5a are formed in a concentric ring shape, spaced apart from each other. Therefore, the second regions 5a of the guard ring (4c, 5a) and the separation regions 5n are alternately provided in contact with each other. The separation region 5n contains both n-type (first conductivity type) impurities and p-type (second conductivity type) impurities, and the impurity concentration of the p-type (second conductivity type) impurities is the same as the impurity concentration of the p-type (second conductivity type) impurities in the second region 5a. The impurity concentration of the p-type (second conductivity type) impurities in the second region 5a is the same as the impurity concentration of the p-type (second conductivity type) impurities in the second base bottom buried region 5. The impurity concentration of the n-type (first conductivity type) impurity in the isolation region 5n is the same as the impurity concentration of the n-type (first conductivity type) impurity in the current spreading layer 3 (n ion-implanted layer 5p).

[0070] After removing the photoresist film 50 used as a mask for ion implantation, a p-type base region 6dp is epitaxially grown on the upper surfaces of the second base bottom buried region 5, the n ion implantation layer 5p, the guard ring (4c, 5a) and the isolation region 5n, as shown in FIG. 34. An oxide film made of SiO2 is deposited on the surface of the base region 6dp by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as an etching mask, the base region 6dp is selectively etched by dry etching technology or the like to form a mesa groove 9c, as shown in FIG. 35. The base region 6d remains in the active portion 101, and in the outer peripheral portion 102, the upper surface of the second region 5a of the guard ring (4c, 5a) and the upper surface of the isolation region 5n are exposed at the bottom surface of the mesa groove 9c.

[0071] After removing the etching mask, an oxide film made of SiO2 is deposited on the upper surface of the base region 6d and on the bottom surface of the mesa groove 9c by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the base region 6d from the upper surface side of the base region 6d. As a result, p-type impurity ions such as aluminum (Al) are implanted into the upper surface of the base region 6d above the second base bottom buried region 5 and the n ion implantation layer 5p. + A mold base contact region 8e is formed.

[0072] After removing the oxide film used as a mask for ion implantation, an oxide film made of SiO2 is deposited on the upper surfaces of the base contact region 8e and base region 6d and on the bottom surface of the mesa groove 9c by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted in multiple stages into the base region 6d from the upper surface side of the base region 6d. As a result, as shown in FIG. 36, n-type impurity ions such as phosphorus (P) are implanted into the upper surface of the base region 6d above the n-ion implantation layer 5p. + A source region 7e of the type is formed.

[0073] An oxide film made of SiO2 is deposited on the upper surfaces of the base contact region 8e and the source region 7e, and on the bottom surface of the mesa groove 9c by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology, or the like. Using the patterned oxide film as an etching mask, a trench 9 is selectively formed by dry etching technology. The trench 9 penetrates the source region 7e, the base region 6d, and the n-ion implantation layer 5p to reach the gate bottom protection region 4b. After removing the oxide film used as the etching mask, a field insulating film 10b is deposited on the exposed surfaces of the trench 9 and the mesa groove 9c by CVD technology or the like. A photoresist film is applied to the upper surface of this field insulating film 10b, and the photoresist film is patterned by photolithography technology, dry etching technology, or the like. Using the patterned photoresist film as an etching mask, a part of the field insulating film 10b is selectively removed.

[0074] A gate insulating film 11 such as a SiO2 film is formed on the bottom and side surfaces of the trench 9 and on the upper surfaces of the source region 7e and the base contact region 8e by thermal oxidation or chemical vapor deposition (CVD) technology, as shown in Fig. 37. Next, a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD technology, so as to fill the trench 9.

[0075] Then, a part of the polysilicon layer and a part of the gate insulating film 11 are selectively removed by photolithography and dry etching. As shown in FIG. 37, a pattern of the gate electrode 12 made of the gate insulating film 11 and the polysilicon layer is formed to form an insulated gate electrode structure (11, 12). Next, an insulating film is deposited on the upper surface of the insulated gate electrode structure (11, 12) made of the gate electrode 12 and the gate insulating film 11 by CVD or the like. As this insulating film, boron phosphorus glass (BPSG), NSG, or the like is used. Then, a part of the deposited insulating film is selectively removed by photolithography and dry etching or the like. As a result, as shown in FIG. 37, a source electrode contact hole is opened in the interlayer insulating film 13. Although not shown, a gate contact hole is also opened in the interlayer insulating film 13 at a location different from the source electrode contact hole so that a part of the gate surface electrode connected to the gate electrode 12 is exposed.

[0076] A metal layer such as a Ni film is deposited by sputtering or vapor deposition, and the metal layer is patterned by photolithography and RIE. Then, a rapid thermal annealing (RTA), for example, is performed at about 1000° C., to form a source contact layer 14 on the upper surface of the source region 7e and the base contact region 8e, as shown in FIG. 37. Next, a barrier metal layer (not shown) such as a Ti film or TiN film and a metal layer such as an Al film are deposited by sputtering, and the barrier metal layer and the metal layer are patterned by photolithography and RIE. As a result, as shown in FIG. 30, a laminated structure of a barrier metal layer (not shown) and a source electrode 15 is formed so as to cover the source contact layer 14 and the interlayer insulating film 13. The patterns of the source electrode 15 and the gate surface electrode are separated, and the gate surface electrode is electrically connected to the gate electrode 12 via a wiring layer (not shown) provided on the field insulating film 10b.

[0077] Furthermore, the lower surface of the substrate 1p is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Thereafter, a drain electrode 16 made of Ti, Ni, Au or the like is formed on the entire lower surface of the drain region 1 by a sputtering method or a deposition method or the like. In this manner, the trench gate type semiconductor device shown in FIG. 30 is completed.

[0078] In the second embodiment, a mesa groove 9c penetrating the base region 6d is formed in the peripheral portion 102, and p + A plurality of guard rings (4c, 5a) of a type are provided. The guard rings (4c, 5a) are formed from a first region 4c and a second region 5a provided so as to contact the upper surface of the first region 4c. The second regions 5a of the guard rings (4c, 5a) and the isolation regions 5n are alternately formed so as to contact each other. The first region 4c is formed by ion-implanting p-type impurities simultaneously with the first base bottom buried region 4a and the gate bottom protection region 4b at the same level. Similarly, the second region 5a is formed by ion-implanting p-type impurities simultaneously with the second base bottom buried region 5 at the same level. Thus, in the second embodiment, the guard rings (4c, 5a) are formed in the process of forming the first base bottom buried region 4a and the gate bottom protection region 4b and the process of forming the second base bottom buried region 5. Therefore, a dedicated photomask for forming the guard rings and a guard ring forming process are not required, and it is possible to shorten the manufacturing time and reduce the manufacturing cost of the semiconductor device.

[0079] In the above description, the first region 4c and the second region 5a of the guard ring (4c, 5a) have approximately the same width. In a photolithography process, a mask pattern for the second region 5a is formed according to the pattern for the first region 4c formed earlier. There may be a positional shift between the pattern for the first region 4c and the mask pattern for the second region 5a. If the positional shift between the patterns is large, the electric field concentration relaxation deteriorates, making it difficult to maintain the breakdown voltage of the semiconductor device.

[0080] In order to suppress the misalignment between the patterns, for example, as shown in FIG. 38, the width of the second region 5b may be narrowed by a width d×2 with respect to the first region 4d. For example, the maximum misalignment width of an exposure tool used in a photolithography process may be used as the width d. When the mask pattern of the second region 5a is aligned with the pattern of the first region 4d using an exposure tool, even if the alignment reaches the maximum misalignment width of the exposure tool, the second region 5a can be formed without protruding from the upper surface of the first region 4d. Also, as shown in FIG. 39, the width of the second region 5a may be widened by a width d×2 with respect to the first region 4c. In order to maintain the breakdown voltage of the semiconductor device, it is preferable to alleviate the electric field concentration at a position deep from the upper surface of the drift layer 2. Therefore, the guard ring (4d, 5b) shown in FIG. 38 in which the first region 4d is wider than the second region 5b is preferable.

[0081] As a measure against misalignment of the mask, the first region 4e may be formed as a continuous, integrated pattern, and the second regions 5b may be provided at a distance from each other, as shown in FIG. 40. In this case, even if the mask alignment of the patterns of the second regions 5b is misaligned, the second regions 5b will be in contact with the upper surface of the first region 4e, and the effect on the relaxation of electric field concentration will be suppressed. Also, as shown in FIG. 41, the first regions 4c may be formed at a distance from each other, and the second regions 5c may be formed as a continuous, integrated pattern. In this case, the effect on the relaxation of electric field concentration caused by the pattern misalignment is suppressed, and the breakdown voltage of the semiconductor device can be maintained.

[0082] Furthermore, for example, in the guard ring (4d, 5b) shown in Fig. 38, the ion-implanted p-type impurities are distributed in the depth direction as shown in Fig. 42. In Fig. 42, CB1 shown by a dotted line corresponds to the impurity concentration distribution in the first region 4d, and CB2 shown by a solid line corresponds to the impurity concentration distribution in the second region 5b. As shown in Fig. 42, even if the portion in the second region 5b where the impurity concentration is flat is removed, a tail of the impurity concentration distribution where the impurity concentration originating from the second region 5b decreases remains in the first region 4d.

[0083] FIG. 43 shows a case where the tail of the impurity concentration distribution of p-type impurities ion-implanted on the first region 4c is used as the second region 5t. In this case, in the process of forming the mesa groove 9c, dry etching is performed to a depth that removes the part of the second region 5t where the impurity concentration is flat. As shown in FIG. 43, the second region 5t is narrower than the first region 4c by a width d×2. Therefore, even if the mask alignment is misaligned, the second region 5t is formed above the first region 4c, and the effect on the relaxation of electric field concentration is suppressed, making it possible to maintain the breakdown voltage of the semiconductor device.

[0084] Third embodiment As shown in FIG. 44, the semiconductor device according to the third embodiment is fabricated based on a semiconductor substrate 110 made of SiC and having a (0001) surface orientation. An orientation flat OF indicating the crystal orientation of the semiconductor substrate 110 is provided on the outer periphery of the semiconductor substrate 110. The semiconductor substrate 110 is sliced ​​along a direction that forms a surface inclined by a certain offset angle (off angle) with respect to a specific crystal orientation, and the position of the orientation flat OF is determined by the crystal orientation. Instead of the orientation flat OF, a notch may be provided on the outer periphery of the semiconductor substrate 110. The X direction in FIG. 44 is the <11-20> direction, and the Y direction is the <1-100> direction. On the upper surface of the semiconductor substrate 110, trenches of the semiconductor device extend in a stripe shape along the <11-20> direction, i.e., the X direction.

[0085] As shown in FIG. 45, in the X direction, the upper surface of the semiconductor substrate 110 <0001> The off-angle h is greater than 0° and about 10° or less in the <11-20> direction with respect to the (c-axis) direction. The off-angle h is the angle between a plane (basal plane) perpendicular to the c-axis, which is the (0001) Si plane or the (000-1) C plane, and the upper surface of the semiconductor substrate 110. For example, when an epitaxial layer is grown on the upper surface of the semiconductor substrate 110 on which a concave-convex pattern such as an alignment mark is drawn, the concave-convex pattern observed on the upper surface of the epitaxial layer is shifted by a certain distance in parallel to the main surface of the semiconductor substrate 110 in the X direction, as shown by the arrow in FIG. 45. This is because the epitaxial layer grows in the c-axis direction, and the amount of shift is a value proportional to the film thickness of the epitaxial layer. Moreover, such a position shift does not occur in a direction (Y direction) where no off-angle is provided. For example, if the off angle h is 4°, then when the thickness of the epitaxial layer is 1.6 μm, a positional deviation of approximately 0.112 μm occurs in the X direction.

[0086] Therefore, when an epitaxial layer is grown on the drift layer 2 on which the first region 4c is formed, and the second region 5d is formed by ion implantation from the upper surface of the epitaxial layer, it is desirable to design the pattern in anticipation of the width of misalignment based on the thickness of the epitaxial layer. Furthermore, it is desirable to design the width of the second region 5d relative to the first region 4c, taking into consideration the width of misalignment of the mask in photolithography.

[0087] Specifically, as shown in Fig. 46, in the X direction having an off angle, the width dx between the side of the first region 4c and the side of the second region 5d is determined taking into consideration the misalignment due to the thickness of the epitaxial layer and the misalignment of the mask in photolithography. Also, as shown in Fig. 47, in the Y direction not having an off angle, the width dy between the side of the first region 4c and the side of the second region 5d is determined taking into consideration only the misalignment of the mask in photolithography. In this way, by making the width dx in the X direction larger than the width dy in the Y direction, the influence of the misalignment can be minimized.

[0088] (Other embodiments) As described above, the semiconductor device according to the first to third embodiments of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0089] In the semiconductor device according to the second embodiment, the guard ring (4c, 5a) of the outer periphery 102 shown in FIG. + Alternatively, multiple guard rings 4f of the same type may be used. In this case, p-type impurities are ion-implanted into the first base bottom buried region 4a and the gate bottom protection region 4b shown in FIG. 31 at the same time to form a continuous, integrated p-type ion-implanted layer. Then, n-type impurities are ion-implanted into the p-ion-implanted layer at the same time as the n-ion-implanted layer 3p to form an n-type ion-implanted layer. + In this manner, a plurality of concentric guard rings 4f can be formed at intervals. Alternatively, as shown in FIG. 49, p + A second region 5f of a type may be provided. In this case, p-type impurities are selectively ion-implanted into the p ion-implanted layer simultaneously with the second base bottom buried region 5 to form the second regions 5f spaced apart from each other in the p ion-implanted layer. Then, n-type impurities are ion-implanted into the p ion-implanted layer simultaneously with the n ion-implanted layer 5p to selectively form the isolation region 3n. In this manner, a plurality of concentric guard rings (4f, 5f) spaced apart from each other can be formed. Also, as shown in FIG. 50, the widths of the first region 4c and the second region 5e may be made different in the guard rings (4c, 5e) of the outer periphery 102. Also, the widths may be changed in the X / Y directions.

[0090] In the first to third embodiments, a MISFET having a trench structure is exemplified, but the present invention is not limited thereto, and the present invention is applicable to semiconductor devices having various trench structures, such as an IGBT having a trench structure. As a trench gate type IGBT, the n-type MISFET shown in FIG. 2, FIG. 18, and FIG. 30 may be used. + The n-type source region 7 is the emitter region, + Instead of the drain region 1 of the p+ The present invention can be applied to diodes such as SBDs.

[0091] Although the first to third embodiments have been described by way of example with respect to a semiconductor device using SiC, the present invention can also be applied to a semiconductor device using other hexagonal wide band gap semiconductors such as gallium nitride (GaN) or diamond.

[0092] Thus, the present invention naturally includes various embodiments not described here, such as configurations in which the configurations described in the above embodiments and modifications are applied in any way. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0093] 1...Drain region (second main region) 1p,110...SiC semiconductor substrate (substrate) 2, 2p...Drift layer 3...Current spreading layer 3n, 5n, 7b, 7d, 17...separation area 3p, 5p...n ion implanted layers 4a...First base bottom buried region 4b...Gate bottom protection area 4c, 4d, 4e...first area 4f, 6a, 8b, 8d... Field relaxation area (guard ring) 5...Second base bottom buried region 5a, 5b, 5c, 5d, 5e, 5f, 5t...Second area 6, 6b, 6bp, 6c, 6cp, 6d, 6dp, 6p...base region 7, 7a, 7c, 7e, 7p... source area 8, 8a, 8c, 8cp, 8e, 8p...base contact area 9. Trench 9b, 9c...Mesa groove 9c...Mesa groove 10, 10b... Field insulating film 11, 11p...Gate insulating film 12, 12a...gate electrode 12p...Polysilicon layer (doped polysilicon layer) 13, 13b...Interlayer insulating film 14...Source contact layer 15...Source electrode 16...Drain electrode 40, 60, 70, 71, 90...Oxide film 55...Epitaxial layer 66...Semiconductor layer 72, 80, 81...Photoresist film 100...SiC semiconductor device (semiconductor chip) 101...active part 102...Outer periphery

Claims

1. A semiconductor device having an active portion through which a main current flows and an outer periphery surrounding the active portion, a first conductivity type semiconductor layer made of a wide band gap semiconductor; a plurality of second conductivity type guard rings provided in the outer periphery of the semiconductor layer so as to surround the active portion; an isolation region provided in the outer periphery in a concentric ring shape so as to be adjacent to both of the guard rings adjacent to each other; Equipped with the isolation region includes a first impurity of a first conductivity type and a second impurity of a second conductivity type; The active portion is a second conductivity type base region provided within the semiconductor layer; a first conductivity type source region selectively provided on an upper portion of the base region; a second conductive type base contact region selectively provided on an upper portion of the base region; a trench extending through the base region and reaching the semiconductor layer; an insulated gate electrode structure provided within the trench; a second conductivity type gate bottom protection region provided on a bottom surface of the trench; a second conductivity type base bottom buried region provided within the semiconductor layer and in contact with a lower surface of the base region; Further equipped with 4. A semiconductor device comprising: a first insulating layer formed on said first insulating film and a second insulating layer formed on said second insulating film; a second insulating layer formed on said first insulating film and a second insulating layer formed on said second insulating film;

2. A semiconductor device having an active portion through which a main current flows and an outer periphery surrounding the active portion, a first conductivity type semiconductor layer made of a wide band gap semiconductor; a plurality of second conductivity type guard rings provided in the outer periphery of the semiconductor layer so as to surround the active portion; an isolation region provided in the outer periphery in a concentric ring shape so as to be adjacent to both of the guard rings adjacent to each other; Equipped with the isolation region includes a first impurity of a first conductivity type and a second impurity of a second conductivity type; The active portion is a second conductivity type base region provided within the semiconductor layer; a first conductivity type source region selectively provided on an upper portion of the base region; a second conductive type base contact region selectively provided on an upper portion of the base region; a trench extending through the base region and reaching the semiconductor layer; an insulated gate electrode structure provided within the trench; a second conductivity type gate bottom protection region provided on a bottom surface of the trench; a second conductivity type base bottom buried region provided within the semiconductor layer and in contact with a lower surface of the base region; Further equipped with a first conductivity type impurity concentration in the isolation region is the same as a first conductivity type impurity concentration in the source region, and a second conductivity type impurity concentration in the guard ring is the same as a second conductivity type impurity concentration in the base contact region, and a first conductivity type impurity concentration in the isolation region is the same as a first conductivity type impurity concentration in the source region.

3. 3. The semiconductor device according to claim 1, wherein at a depth where the guard ring and the isolation region are adjacent to each other, an impurity concentration of the second impurity in the isolation region is the same as an impurity concentration of the second conductivity type impurity contained in the guard ring.

4. 4. The semiconductor device according to claim 1, wherein the isolation region is a semiconductor region of a first conductivity type.

5. 4. The semiconductor device according to claim 1, wherein the isolation region is a semiconductor region of a second conductivity type.

6. 6. The semiconductor device according to claim 1, wherein an upper surface of the semiconductor layer has an off angle in a range of more than 0° and not more than 10° in a <11-20> direction with respect to a <0001> direction.

7. 7. The semiconductor device according to claim 1, wherein a mesa groove is provided in the outer periphery.

8. 3. The semiconductor device according to claim 1, wherein the guard ring has a first region and a second region in contact with a lower surface of the first region and having a width different from that of the first region.

9. 9. The semiconductor device according to claim 1, wherein the wide band gap semiconductor is any one of silicon carbide, gallium nitride, and aluminum nitride.

10. A method for manufacturing a semiconductor device having an active portion through which a main current flows and an outer periphery surrounding the active portion, the method comprising the steps of: forming a semiconductor region of a second conductivity type on a surface of the semiconductor layer from the active portion to the outer periphery; forming a concentric ring-shaped isolation region and a guard ring sandwiched between the isolation regions by implanting an impurity of a first conductivity type into the semiconductor region in the outer periphery so as to reach the semiconductor layer; Including, forming a second conductivity type base region inside the semiconductor layer in the active portion; selectively forming a source region of a first conductivity type above the base region; selectively forming a base contact region of a second conductivity type on an upper portion of the base region; forming a trench extending through the base region and reaching the semiconductor layer; forming an insulated gate electrode structure within the trench; forming a gate bottom protection region of a second conductivity type on a bottom surface of the trench; forming a second conductivity type base bottom buried region in the semiconductor layer so as to be in contact with a lower surface of the base region; Further comprising:

4. A method for manufacturing a semiconductor device, comprising forming the guard ring so that its depth is the same as that of the base contact region, and forming the isolation region so that its depth is the same as that of the source region.

11. A method for manufacturing a semiconductor device having an active portion through which a main current flows and an outer periphery surrounding the active portion, in a first conductivity type semiconductor layer made of a wide band gap semiconductor, comprising: forming a semiconductor region of a second conductivity type on a surface of the semiconductor layer from the active portion to the outer periphery; forming a concentric ring-shaped isolation region and a guard ring sandwiched between the isolation regions by implanting an impurity of a first conductivity type into the semiconductor region in the outer periphery so as to reach the semiconductor layer; Including, forming a second conductivity type base region inside the semiconductor layer in the active portion; selectively forming a source region of a first conductivity type above the base region; selectively forming a base contact region of a second conductivity type on an upper portion of the base region; forming a trench extending through the base region and reaching the semiconductor layer; forming an insulated gate electrode structure within the trench; forming a gate bottom protection region of a second conductivity type on a bottom surface of the trench; forming a second conductivity type base bottom buried region in the semiconductor layer so as to be in contact with a lower surface of the base region; Further comprising: forming said guard ring so that an impurity concentration of a second conductivity type impurity is the same as an impurity concentration of a second conductivity type impurity included in said base contact region, and forming said isolation region so that an impurity concentration of a first conductivity type impurity is the same as an impurity concentration of a first conductivity type impurity included in said source region.

12. 12. The method for manufacturing a semiconductor device according to claim 10, wherein at a depth where the guard ring and the isolation region are adjacent to each other, an impurity concentration of the second conductivity type impurity in the isolation region is formed to be the same as an impurity concentration of the second conductivity type impurity contained in the guard ring.

13. 12. The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming the base region is a step of forming an epitaxial layer of a second conductivity type, and the semiconductor region is the epitaxial layer.

14. 12. The method for manufacturing a semiconductor device according to claim 10, wherein the guard ring has a first region and a second region in contact with a lower surface of the first region, and the second region is formed to have a width different from that of the first region.

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