Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of securing a proof pressure while suppressing increase of a chip size.SOLUTION: A semiconductor device comprises: a semiconductor layer 1 of a first conductivity type; a well region 2 of a second conductivity type, provided onto an upper part of the semiconductor layer 1; base regions 4a and 4b of the second conductivity type, provided onto the upper part of the well region 2; carrier supply regions 6a and 6b of the first conductivity type, provided onto the upper part of the base regions 4a and 4b; a drift region 3 of the first conductivity type, provided onto the top part of the well region 2 and provided so as to be separated from the base regions 4a and 4b; a carrier acceptance region 5 of the first conductivity type, provided onto the top part of the drift region 3; gate electrodes 11a and 11b provided via a gate insulator 12 onto an upper surface of the well region 2 nipped between the base regions 4a and 4b and the drift region 3; and punch-through prevention regions 9a and 9b of the second conductivity type of an impurity density, provided onto the upper part of the well region 2 and different from the base regions 4a and 4b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A laterally diffused metal-oxide-semiconductor (LDMOS) transistor is one of the semiconductor devices commonly used for high-voltage applications. LDMOS achieves high voltage resistance by mitigating the electric field strength when a high voltage is applied by using a drift region with a relatively low impurity concentration provided between the source and drain regions (see Patent Document 1).

[0003] When the LDMOS is a p-channel type, an n-type well region is formed for element isolation. The n-type well region is formed deep in the p-type semiconductor substrate to ensure sufficient isolation voltage resistance. The impurity concentration of the n-type well region is appropriately adjusted according to the voltage resistance and on-resistance of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4645861 specification Summary of the Invention [Problem to be solved by the invention]

[0005] As the breakdown voltage of LDMOS elements increases, the impurity concentration in the n-type well region tends to decrease. When the impurity concentration in the n-type well region decreases, the depletion layer between the drain region and the semiconductor substrate tends to spread, causing punch-through, which may lead to a decrease in the breakdown voltage between the drain region and the semiconductor substrate. For this reason, if an attempt is made to ensure a sufficient distance between the drain region and the semiconductor substrate, the device size increases, which in turn increases the chip size, leading to increased costs.

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device that can ensure a sufficient breakdown voltage while suppressing an increase in chip size, and a method for manufacturing the same. [Means for solving the problem]

[0007] One aspect of the present invention is a semiconductor device including: (a) a semiconductor layer of a first conductivity type; (b) a well region of a second conductivity type provided on an upper portion of the semiconductor layer; (c) a base region of the second conductivity type provided on an upper portion of the well region and having a higher impurity concentration than the well region; (d) a carrier supply region of the first conductivity type provided on an upper portion of the base region; (e) a drift region of the first conductivity type provided on an upper portion of the well region and spaced apart from the base region; (f) a carrier receiving region of the first conductivity type provided on an upper portion of the drift region and having a higher impurity concentration than the drift region; (g) a gate electrode provided via a gate insulating film on an upper surface of the well region sandwiched between the base region and the drift region; and (h) a punch-through prevention region of the second conductivity type provided on an upper portion of the well region, having a higher impurity concentration than the well region and a different impurity concentration than the base region.

[0008] Another aspect of the present invention is summarized as a method for manufacturing a semiconductor device, including the steps of: (a) forming a well region of a second conductivity type on an upper portion of a semiconductor layer of a first conductivity type; (b) forming a base region of the second conductivity type on the upper portion of the well region, the base region having an impurity concentration higher than that of the well region; (c) forming a punch-through prevention region of the second conductivity type on the upper portion of the well region, the punch-through prevention region having an impurity concentration higher than that of the well region and different from that of the base region; (d) forming a drift region of the first conductivity type on the upper portion of the well region and spaced apart from the base region; (e) forming a carrier supply region of the first conductivity type on the upper portion of the base region; (f) forming a carrier receiving region of the first conductivity type on the upper portion of the drift region, the carrier receiving region having an impurity concentration higher than that of the drift region; and (g) forming a gate electrode via a gate insulating film on an upper surface of the well region sandwiched between the base region and the drift region. Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can ensure a sufficient breakdown voltage while suppressing an increase in chip size. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along the line BB in FIG. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 5A] 3A to 3C are process cross-sectional views corresponding to FIG. 2 for explaining a method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 5B] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention, the cross-sectional views corresponding to FIG. [Figure 6A] 5B is a cross-sectional view illustrating a process subsequent to FIG. 5A for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 6B] 5B to 5C are cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7A] 6B is a cross-sectional view illustrating a process of the semiconductor device according to the embodiment of the present invention, continuing from FIG. 6A. FIG. [Figure 7B] 6B to 6C are cross-sectional views illustrating the steps of a method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 8A] 7A and 7B for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 8B] 8B is a cross-sectional view taken along the line AA in FIG. 8A. [Figure 8C] 8B is a cross-sectional view taken along the line BB in FIG. 8A. [Figure 8D] 8B is a cross-sectional view taken along the CC direction in FIG. 8A. [Figure 9A]8B for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention. FIG. [Figure 9B] 8D are cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, continuing from FIG. 8C. [Figure 10A] 9B is a cross-sectional view illustrating a process of the semiconductor device according to the embodiment of the present invention, continuing from FIG. 9A. FIG. [Figure 10B] 9B for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention. FIG. [Figure 11A] 10B is a cross-sectional view illustrating a process following FIG. 10A for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 11B] 10B for explaining a process of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 12A] 11B is a cross-sectional view illustrating a process following FIG. 11A for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 12B] 11B for explaining a process of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 13] FIG. 2 is a plan view showing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 14] FIG. 11 is a plan view illustrating a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 15] FIG. 11 is a plan view illustrating a method for manufacturing a semiconductor device according to a second modified example of the embodiment of the present invention. [Figure 16] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 17] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Figure 18] 10A to 10C are cross-sectional views illustrating steps of a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Figure 19] FIG. 13 is a plan view showing a semiconductor device according to a fifth modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments and each modified example of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, the drawings may include parts with different dimensional relationships and ratios. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0012] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers (majority carriers) that become the main current, such as the source region of a metal-insulated field-effect transistor (MISFET) or a metal-insulated static induction transistor (MISSIT), the emitter region of an insulated gate bipolar transistor (IGBT), or the anode region of a metal-insulated static induction thyristor (MIS-controlled SI thyristor). The term "carrier receiving region" refers to a semiconductor region that receives majority carriers that become the main current, such as the drain region of a MISFET or a MISSIT, the collector region of an IGBT, or the cathode region of a MIS-controlled SI thyristor. In semiconductor devices that operate as bipolar types, such as an IGBT or a MIS-controlled SI thyristor, carriers (carriers) of the opposite conductivity type to the majority carriers are injected from the carrier receiving region.

[0013] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0014] In the following description, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. The + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions have the same n and n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0015] (Embodiment) <Structure of Semiconductor Device> FIG. 1 shows a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 corresponds to a cross-sectional view seen from the AA direction in FIG. 1. FIG. 3 corresponds to a cross-sectional view seen from the BB direction in FIG. 1. For convenience, FIG. 1 omits the illustration of the element isolation insulating film 10, gate insulating film 12, gate electrodes 11a and 11b, interlayer insulating film 13, drain electrode 14, source electrodes 15 and 16, and substrate contact electrodes 17 and 18 on the upper side of the semiconductor layer 1 shown in FIG. 2 and FIG. 3, and corresponds to a plan view of the semiconductor layer 1. For convenience, FIG. 1 shows the gate electrodes 11a and 11b shown in FIG. 2 in a schematic manner by broken lines.

[0016] As shown in FIGS. 1 to 3, a semiconductor device according to an embodiment of the present invention includes a first conductive type (p-type) semiconductor layer 1 and a second conductive type (n-type) semiconductor layer provided on the upper portion of the semiconductor layer 1. - The well region 2 is of the type described above.

[0017] A semiconductor substrate such as a silicon (Si) substrate can be used as the semiconductor layer 1. A semiconductor substrate made of a semiconductor (wide band gap semiconductor) having a wider band gap than silicon, such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN), can also be used as the semiconductor layer 1. The semiconductor layer 1 may be a p-type semiconductor region provided on an upper portion of a p-type or n-type semiconductor substrate.

[0018] As shown on the left side of FIG. 1 and FIG. 2, the upper portion of the well region 2 is provided with n-type GaN layers having a higher impurity concentration than the well region 2.- A p-type base region (channel forming region) 4a is provided on the upper portion of the base region 4a. + A n-type carrier supply region (source region) 6a is provided on the upper portion of the base region 4a so as to contact the source region 6a. + A contact region 7a is provided on the source region 6a. As shown in Fig. 1, the source region 6a and the contact region 7a have a striped planar pattern and extend in the vertical direction of Fig. 1. As shown in Fig. 2, a source electrode 15 is connected to the upper surfaces of the source region 6a and the contact region 7a.

[0019] As shown on the right side of FIG. 1 and FIG. 2, an n-type semiconductor layer having a higher impurity concentration than the well region 2 is provided above the well region 2. - A base region 4b of a type is provided. The upper portion of the base region 4b is provided with a p + An n-type source region 6b is provided on the upper portion of the base region 4b so as to contact the source region 6b. + A contact region 7b is provided on the source region 6b. As shown in Fig. 1, the source region 6b and the contact region 7b have a striped planar pattern and extend in the vertical direction of Fig. 1. As shown in Fig. 2, a source electrode 16 is connected to the upper surfaces of the source region 6b and the contact region 7b.

[0020] As shown in the center of the left-right direction in FIGS. 1 to 3, the upper part of the well region 2 is provided with p - A carrier transport region (drift region) 3 of the type is provided. Above the drift region 3, a p +The well region 2 has a rectangular planar pattern. The drain region 5 has a striped planar pattern and extends in the vertical direction of FIG. 1. The drain region 5 faces the source regions 6a and 6b in the horizontal direction of FIG. 1, sandwiching the well region 2 and the drift region 3. That is, the semiconductor device according to the embodiment of the present invention has two p-channel LDMOSs symmetrically provided, and the two LDMOSs share the drain region 5. In addition to the two LDMOSs, various semiconductor elements such as transistors may be mixed in the semiconductor layer 1. As shown in FIG. 2, a drain electrode 14 is connected to the upper surface of the drain region 5.

[0021] 2 and 3, an element isolation insulating film 10 is provided on the upper surface of the semiconductor layer 1. The element isolation insulating film 10 is made of a field oxide film such as a local insulating film (LOCOS film) selectively (locally) formed by the local oxidation of silicon (LOCOS) method.

[0022] 1 and 2, a gate electrode 11a is provided on the upper surfaces of the base region 4a and well region 2 sandwiched between the source region 6a and drift region 3, with a gate insulating film 12 interposed therebetween. As shown on the right side of Fig. 1 and 2, a gate electrode 11b is provided on the upper surfaces of the base region 4b and well region 2 sandwiched between the source region 6b and drift region 3, with a gate insulating film 12 interposed therebetween.

[0023] The gate insulating film 12 may be, for example, a silicon oxide film (SiO2 film), or a single layer film of any one of a silicon oxynitride film (SiON film), a strontium oxide film (SrO film), a silicon nitride film (Si3N4 film), an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgO film), an yttrium oxide film (Y2O3 film), a hafnium oxide film (HfO2 film), a zirconium oxide film (ZrO2 film), a tantalum oxide film (Ta2O5 film), and a bismuth oxide film (Bi2O3 film), or a composite film formed by stacking a plurality of these films.

[0024] The gate electrodes 11a and 11b may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type impurities such as boron (B) or n-type impurities such as phosphorus (P), or a high melting point metal.

[0025] An interlayer insulating film 13 is disposed on the gate electrodes 11a and 11b. A non-doped silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), known as "NSG," can be used as the interlayer insulating film 13. The interlayer insulating film 13 may also be a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with boron and phosphorus (BPSG film), a silicon nitride film (Si3N4 film), or a laminate film of these.

[0026] As shown in FIGS. 1 to 3, the semiconductor layer 1 is provided with p + A molded substrate contact region 8 is provided. As shown in Fig. 1, the substrate contact region 8 has, for example, a ring-shaped planar pattern. As shown in Fig. 2, substrate contact electrodes 17 and 18 are connected to the upper surface of the substrate contact region 8. A substrate potential (for example, a ground potential) is applied to the substrate contact region 8 via the substrate contact electrodes 17 and 18, and the semiconductor layer 1 is fixed to the substrate potential.

[0027] As shown in FIG. 1 and FIG. 3, an n-type semiconductor layer having a higher impurity concentration than the well region 2 is provided above the well region 2. -The punch-through prevention regions 9a and 9b are provided in a shape similar to that of the drain region 5. The punch-through prevention regions 9a and 9b have a function of preventing punch-through between the drain region 5 and the semiconductor layer 1. In Figs. 1 and 3, the punch-through prevention regions 9a and 9b are separated from the drift region 3, but the punch-through prevention regions 9a and 9b may be in contact with the drift region 3. As shown in Fig. 1, the punch-through prevention regions 9a and 9b are provided in a region where the drain region 5 and the semiconductor layer 1 face each other in the vertical direction of Fig. 1. The punch-through prevention regions 9a and 9b are provided so as to sandwich the drain region 5 and the drift region 3. In the horizontal direction of Fig. 1, the width W0 of the punch-through prevention regions 9a and 9b is wider than the width of the drain region 5.

[0028] The impurity concentration of the punch-through prevention regions 9a, 9b is higher than that of the well region 2 and lower than that of the base regions 4a, 4b. In the embodiment of the present invention, the depth D2 of the punch-through prevention regions 9a, 9b is equal to the depth D1 of the base regions 4a, 4b. The depth D2 of the punch-through prevention regions 9a, 9b may be shallower than the depth D1 of the base regions 4a, 4b. As will be described later, the punch-through prevention regions 9a, 9b and the base regions 4a, 4b are simultaneously formed by the same ion implantation process and heat treatment process.

[0029] The depth D2 of the punch-through prevention regions 9a and 9b is equal to the depth D3 of the drift region 3. The depth D2 of the punch-through prevention regions 9a and 9b may be deeper than the depth D3 of the drift region 3 or may be shallower than the depth D3 of the drift region 3.

[0030] <First Comparative Example> Here, a semiconductor device according to a first comparative example will be described. Fig. 4 shows a cross section of the semiconductor device according to the first comparative example, which corresponds to Fig. 3 of the semiconductor device according to the embodiment of the present invention. As shown in Fig. 4, the semiconductor device according to the first comparative example differs from the semiconductor device according to the embodiment of the present invention in that no punch-through prevention region is provided above the well region 2.

[0031] In the semiconductor device according to the first comparative example, when the impurity concentration of the well region 2 is low, p - Drift region of type 3 to n - The depletion layer spreads toward the drain well region 2 and reaches the p-type semiconductor layer 1, causing punch-through between the drain region 5 and the semiconductor layer 1, resulting in a drop in the breakdown voltage. To prevent punch-through, it is necessary to ensure a sufficient distance D0 for the well region 2, but this increases the device area and the cost due to the increased chip area.

[0032] In contrast, according to the semiconductor device of the embodiment of the present invention, as shown in Figures 1 and 3, punch-through prevention regions 9a, 9b are provided above the well region 2, so that punch-through between the drain region 5 and the semiconductor layer 1 can be prevented, and an increase in the device area, and therefore the chip area, can be suppressed, making it possible to manufacture the device at low cost. <Second Comparative Example> Next, a semiconductor device according to a second comparative example will be described. The semiconductor device according to the second comparative example has the same structure as the semiconductor device according to the embodiment of the present invention shown in Figs. 1 to 3, but is different in that the impurity concentration of the punch-through prevention regions 9a, 9b is equal to that of the base regions 4a, 4b. In the semiconductor device according to the second comparative example, in the ion implantation process for forming the base regions 4a, 4b, ions are also simultaneously implanted into the punch-through prevention regions 9a, 9b, and the base regions 4a, 4b and the punch-through prevention regions 9a, 9b are simultaneously formed by subsequent heat treatment. However, in the ion implantation process for forming the base regions 4a, 4b, implantation conditions suitable for the impurity concentration of the base regions 4a, 4b are used, so that the impurity concentration may not be suitable for the punch-through prevention regions 9a, 9b.

[0033] In contrast, according to a semiconductor device of an embodiment of the present invention, the impurity concentration of the punch-through prevention regions 9a, 9b is made different from the impurity concentration of the base regions 4a, 4b within the same device, so that the impurity concentration of the punch-through prevention regions 9a, 9b can be adjusted to an impurity concentration suitable for preventing punch-through.

[0034] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 5A to 12B. Here, the description will be focused mainly on the cross-sections of the semiconductor device shown in Figures 2 and 3. Note that the method for manufacturing a semiconductor device described below is one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit of the claims.

[0035] First, a semiconductor layer 1 such as a p-type Si substrate is prepared. Next, a photoresist film 20 is applied to the upper surface of the semiconductor layer 1, and the photoresist film 20 is patterned using photolithography technology. As shown in FIGS. 5A and 5B, n-type impurity ions such as phosphorus (P) are implanted using the patterned photoresist film 20 as a mask. After removing the photoresist film 20, a heat treatment is performed to activate the n-type impurity ions. As a result, n-type impurity ions are formed on the upper part of the semiconductor layer 1, as shown in FIGS. 6A and 6B. - A mold well region 2 is selectively formed.

[0036] Next, a photoresist film 21 is applied to the upper surfaces of the semiconductor layer 1 and the well region 2, and the photoresist film 21 is patterned using a photolithography technique. As shown in Figures 7A and 7B, the patterned photoresist film 21 is used as a mask to implant p-type impurity ions such as boron (B). After removing the photoresist film 21, a new photoresist film 22 is applied to the upper surfaces of the semiconductor layer 1 and the well region 2, and the photoresist film 22 is patterned using a photolithography technique, as shown in Figure 8A.

[0037] A cross section seen from the AA direction in Fig. 8A is shown in Fig. 8B, a cross section seen from the BB direction in Fig. 8A is shown in Fig. 8C, and a cross section seen from the CC direction in Fig. 8A is shown in Fig. 8D. As shown in Fig. 8A, the resist pattern of the photoresist film 22 has slit-shaped (striped) openings 22a and 22b corresponding to the punch-through prevention regions 9a and 9b, and rectangular openings 22c and 22d that are fully open corresponding to the base regions 4a and 4b. The slits of the openings 22a and 22b extend in the vertical direction in Fig. 8A, and a plurality of openings are provided side by side in the left-right direction in Fig. 8A.

[0038] As shown in FIGS. 8B to 8D, the patterned photoresist film 22 is used as a mask for ion implantation to implant n-type impurity ions such as phosphorus (P). The ion implantation conditions at this time are set to implantation conditions suitable for the base regions 4a and 4b. For this reason, as shown in FIG. 8B, the openings 22c and 22d for forming the base regions 4a and 4b are entirely opened for ion implantation. On the other hand, as shown in FIGS. 8C and 8D, the openings 22a and 22b for forming the punch-through prevention regions 9a and 9b are slit-shaped, thereby limiting the amount of ion implantation and making the impurity concentration of the punch-through prevention regions 9a and 9b a concentration suitable for preventing punch-through.

[0039] As shown in FIG. 8A, the impurity concentration of the punch-through prevention regions 9a, 9b can be adjusted to a concentration suitable for preventing punch-through by adjusting the density (shielding rate) of the slits of the openings 22a, 22b, the slit width (non-opening width) W1 of the openings 22a, 22b, the slit interval (opening width) S1, the ratio S1 / W1 of the slit interval S1 to the slit width W1, etc. The higher the shielding rate of the slits of the openings 22a, 22b is, the lower the impurity concentration of the punch-through prevention regions 9a, 9b becomes, and the depth of the punch-through prevention regions 9a, 9b becomes shallower. For example, when the shielding rate of the openings 22a, 22b is adjusted to about 50%, the slit width W1 is about 0.5 μm, the slit interval S1 is about 0.5 μm, and the ratio S1 / W1 of the slit interval S1 to the slit width W1 is about 1, the impurity concentration of the punch-through prevention regions 9a, 9b can be adjusted to about 1 / 2 of the impurity concentration of the base regions 4a, 4b. After the n-type impurity ions are implanted as shown in FIGS. 8B to 8D, the photoresist film 22 is removed.

[0040] Next, the p-type impurity ions and the n-type impurity ions are activated by performing a heat treatment. As a result, p - A n-type drift region 3 is selectively formed on the top of the well region 2. - Punch-through prevention regions 9a, 9b and n - The n-type base regions 4a, 4b are selectively formed. The punch-through prevention regions 9a, 9b are integrated regions with a uniform impurity concentration, where n-type impurities injected through the slits of the openings 22a, 22b are diffused laterally. The impurity concentration of the punch-through prevention regions 9a, 9b is different from that of the base regions 4a, 4b, and is lower than that of the base regions 4a, 4b. - A heat treatment for forming a drift region 3 of the n type; - Punch-through prevention regions 9a, 9b and n - The heat treatment for forming the base regions 4a and 4b of the mold may be carried out individually instead of all at once.

[0041] Next, as shown in FIGS. 10A and 10B, an element isolation insulating film 10 is formed on the upper surface of the semiconductor layer 1 by a LOCOS method or the like. Next, a gate insulating film 12 is formed on the upper surface of the semiconductor layer 1 by a thermal oxidation method, a chemical vapor deposition (CVD) method or the like. Furthermore, a polysilicon layer (doped polysilicon layer) to which n-type impurities or p-type impurities are highly doped is deposited by a CVD method or the like using a dopant gas. Thereafter, a portion of the doped polysilicon layer and the gate insulating film 12 are selectively removed by photolithography and dry etching. As a result, as shown in FIGS. 11A and 11B, a pattern of the gate insulating film 12 and gate electrodes 11a and 11b made of the doped polysilicon layer is formed.

[0042] Next, a photoresist film is applied to the upper surfaces of the semiconductor layer 1 and the gate electrodes 11a and 11b, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as a mask, p-type impurity ions such as boron (B) are implanted. After removing the photoresist film, a new photoresist film is applied to the upper surfaces of the semiconductor layer 1 and the gate electrodes 11a and 11b, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as a mask, n-type impurity ions such as phosphorus (P) are implanted. After removing the photoresist film, a heat treatment is performed to activate the p-type impurity ions and n-type impurity ions. As a result, p-type impurity ions are formed in the upper part of the base region 4a, as shown in FIGS. 12A and 12B. + Type source regions 6a and n + A p-type contact region 7a is formed on the upper portion of the base region 4b. + Type source regions 6b and n + A p-type contact region 7b is formed on the top of the drift region 3. + A p-type drain region 5 is selectively formed on the upper portion of the semiconductor layer 1. + A mold substrate contact region 8 is selectively formed.

[0043] Next, the interlayer insulating film 13 is deposited by a CVD method or the like so as to cover the gate electrodes 11a and 11b. Then, a part of the interlayer insulating film 13 is selectively removed by a photolithography technique, a dry etching technique, or the like to form contact holes exposing the upper surfaces of the source regions 6a and 6b, the drain region 5, the contact regions 7a and 7b, and the substrate contact region 8. Furthermore, the contact holes are filled with a metal film by a sputtering method, a photolithography technique, a dry etching technique, or the like to form a drain electrode 14 connected to the drain region 5, source electrodes 15 and 16 connected to the source regions 6a and 6b and the contact regions 7a and 7b, and substrate contact electrodes 17 and 18 connected to the substrate contact region 8. In this manner, the semiconductor device according to the embodiment of the present invention shown in FIGS. 1 to 3 is completed.

[0044] According to the manufacturing method of the semiconductor device of the embodiment of the present invention, punch-through prevention regions 9a, 9b are formed on the upper part of the well region 2, thereby preventing punch-through between the drain region 5 and the semiconductor layer 1, suppressing an increase in the device area and therefore the chip area, and enabling inexpensive manufacturing.

[0045] Furthermore, in the ion implantation process for forming the base regions 4a, 4b, ion implantation for forming the punch-through prevention regions 9a, 9b is also performed at the same time, and when the punch-through prevention regions 9a, 9b having the same impurity concentration as the base regions 4a, 4b are formed at the same time as the base regions 4a, 4b, the ion implantation conditions are suitable for the base regions 4a, 4b, and may not be suitable for the impurity concentration of the punch-through prevention regions 9a, 9b. On the other hand, adding a dedicated photolithography process and ion implantation process to set the impurity concentration of the punch-through prevention regions 9a, 9b to a concentration suitable for preventing punch-through will lead to an increase in costs.

[0046] In contrast, according to the manufacturing method of the semiconductor device according to the embodiment of the present invention, in the ion implantation step for forming the base regions 4a, 4b, the openings 22a, 22b for forming the punch-through prevention regions 9a, 9b are slit-shaped, so that the punch-through prevention regions 9a, 9b having an impurity concentration different from that of the base regions 4a, 4b can be formed at the same time as the base regions 4a, 4b are formed. Therefore, the impurity concentration of the punch-through prevention regions 9a, 9b can be set to a concentration suitable for preventing punch-through, and the punch-through prevention regions 9a, 9b can be manufactured at low cost without adding a dedicated photolithography step and ion implantation step for forming the punch-through prevention regions 9a, 9b.

[0047] (First Modification) The semiconductor device according to the first modification of the embodiment of the present invention is different from the semiconductor device according to the embodiment of the present invention in that the width W2 of the punch-through prevention regions 9a and 9b in the left-right direction of FIG. 13 is enlarged. The width W2 of the punch-through prevention regions 9a and 9b in the left-right direction of FIG. - The width of the semiconductor device according to the first modification of the embodiment of the present invention is otherwise wider than the width of the drift region 3 of the mold. Since the other configurations of the semiconductor device according to the first modification of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, a duplicated description will be omitted.

[0048] According to the semiconductor device of the first modification of the embodiment of the present invention, even if the width W2 of the punch-through prevention regions 9a, 9b is increased, the same effects as those of the semiconductor device of the embodiment of the present invention are achieved.

[0049] When manufacturing a semiconductor device according to the first modified embodiment of the present invention, as shown in FIG. 14, when forming a resist pattern of a photoresist film 22, the areas of the slit-shaped openings 22a, 22b for forming the punch-through prevention regions 9a, 9b can be expanded to match the width W2 of the punch-through prevention regions 9a, 9b.

[0050] (Second Modification) The method for manufacturing a semiconductor device according to the second modified example of the embodiment of the present invention differs from the method for manufacturing a semiconductor device according to the embodiment of the present invention in that the orientation of the slits of the openings 22a, 22b corresponding to the punch-through prevention regions 9a, 9b is different when forming a resist pattern of the photoresist film 22, as shown in Fig. 15. The slits of the openings 22a, 22b extend in the left-right direction of Fig. 15, and a plurality of slits are provided side by side in the up-down direction of Fig. 15. Other steps of the method for manufacturing a semiconductor device according to the second modified example of the embodiment of the present invention are similar to those of the method for manufacturing a semiconductor device according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0051] According to the manufacturing method of a semiconductor device according to the second modified embodiment of the present invention, the same effects as those of the manufacturing method of a semiconductor device according to the embodiment of the present invention can be achieved even if the slits of the openings 22a, 22b corresponding to the punch-through prevention regions 9a, 9b of the photoresist film 22 are different. Note that the shape of the slits of the openings 22a, 22b is not particularly limited, and may be, for example, an oblique slit or a lattice pattern formed by combining slits perpendicular to each other.

[0052] (Third Modification) The semiconductor device according to the third modification of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention in that the depth D2 of the punch-through prevention regions 9a, 9b is shallow, as shown in Fig. 16. The depth D2 of the punch-through prevention regions 9a, 9b is shallower than the depth D3 of the drift region 3, and is shallower than the depth D1 of the base regions 4a, 4b shown in Fig. 2. Other configurations of the semiconductor device according to the third modification of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0053] According to the semiconductor device of the third modified example of the embodiment of the present invention, even if the depth D2 of the punch-through prevention regions 9a, 9b is shallow, the same effects as those of the semiconductor device of the embodiment of the present invention can be achieved.

[0054] When manufacturing a semiconductor device according to the third modified embodiment of the present invention, the depth D2 of the punch-through prevention regions 9a, 9b can be made shallow by adjusting the density of the slits of the openings 22a, 22b corresponding to the punch-through prevention regions 9a, 9b.

[0055] (Fourth Modification) The semiconductor device according to the fourth modification of the embodiment of the present invention is different from the semiconductor device according to the embodiment of the present invention in that the impurity concentration of the base regions 4a, 4b is lower than the impurity concentration of the punch-through prevention regions 9a, 9b shown in FIG. 3, as shown in FIG. 17. As shown in FIG. 17, the depth D1 of the base regions 4a, 4b is shallower than the depth D3 of the drift region 3 and shallower than the depth D2 of the punch-through prevention regions 9a, 9b shown in FIG. 3. The depth D1 of the base regions 4a, 4b may be equal to the depth D3 of the drift region 3 or may be equal to the depth D2 of the punch-through prevention regions 9a, 9b shown in FIG. 3. The other configurations of the semiconductor device according to the fourth modification of the embodiment of the present invention are the same as those of the semiconductor device according to the embodiment of the present invention, so that the overlapping description will be omitted.

[0056] According to the semiconductor device of the fourth modified example of the embodiment of the present invention, even if the impurity concentration of the base regions 4a, 4b is different from the impurity concentration of the punch-through prevention regions 9a, 9b shown in Figure 3 and is lower than the impurity concentration of the punch-through prevention regions 9a, 9b, the same effect as the semiconductor device of the embodiment of the present invention is achieved.

[0057] 18, when forming a resist pattern of a photoresist film 22, the openings 22a and 22b corresponding to the punch-through prevention regions 9a and 9b are formed into a rectangular pattern rather than a slit pattern, while the openings 22c and 22d corresponding to the base regions 4a and 4b are formed into a slit pattern.

[0058] When n-type impurity ions are implanted using the resist pattern of the photoresist film 22 shown in Fig. 18 as a mask, implantation conditions suitable for forming the punch-through prevention regions 9a, 9b are set. The impurity concentration and depth of the base regions 4a, 4b can be adjusted by adjusting the density of the slits of the openings 22c, 22d. This makes it possible to form the base regions 4a, 4b and the punch-through prevention regions 9a, 9b such that the impurity concentration of the base regions 4a, 4b is lower than the impurity concentration of the punch-through prevention regions 9a, 9b, and the depth D1 of the base regions 4a, 4b is shallower than the depth D2 of the punch-through prevention regions 9a, 9b.

[0059] (Fifth Modification) The semiconductor device according to the fifth modification of the embodiment of the present invention is different from the semiconductor device according to the embodiment of the present invention in that it has one LDMOS, as shown in Fig. 19. The one LDMOS shown in Fig. 19 corresponds to the left LDMOS of the two LDMOSs shown in Fig. 1. The punch-through prevention region 9a has a C-shaped planar pattern, and - The second insulating layer 14 is provided so as to surround the periphery of the drift region 3 of the mold. Other configurations of the semiconductor device according to the fifth modified example of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, and therefore a duplicated description will be omitted.

[0060] According to the semiconductor device of the fifth modification of the embodiment of the present invention, even if it has one LDMOS, it has the same effects as the semiconductor device of the embodiment of the present invention.

[0061] In manufacturing the semiconductor device according to the fifth modification of the embodiment of the present invention, when forming the resist pattern of the photoresist film 22, a C-shaped pattern may be formed as a slit for the opening corresponding to the punch-through prevention region 9a.

[0062] (Other embodiments) As described above, the present invention has been described by the embodiment and each modification, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure. For example, the configurations disclosed in the embodiment and each modification of the present invention can be appropriately combined within the scope of not causing contradiction. [Explanation of symbols]

[0063] 1...Semiconductor layer 2. Well area 3. Drift region 4a, 4b...Base region 5…Drain region 6a, 6b…Source region 7a, 7b...Contact area 8…Substrate contact area 9a, 9b...Punch-through prevention area 10...Element isolation insulating film 11a, 11b...gate electrode 12...Gate insulating film 13...Interlayer insulating film 14...Drain electrode 15,16...Source electrode 17, 18...Substrate contact electrodes 20, 21, 22...Photoresist film 22a, 22b, 22c, 22d...opening

Claims

1. A semiconductor layer of a first conductivity type; a second conductivity type well region provided on an upper portion of the semiconductor layer; a second conductivity type base region provided above the well region and having a higher impurity concentration than the well region; a first conductive type carrier supply region provided above the base region; a first conductivity type drift region provided above the well region and spaced apart from the base region; a carrier receiving region of a first conductivity type provided above the drift region and having a higher impurity concentration than the drift region; a gate electrode provided on an upper surface of the well region sandwiched between the base region and the drift region via a gate insulating film; a second conductive type punch-through prevention region provided above the well region and having a higher impurity concentration than the well region and a different impurity concentration than the base region; Equipped with A semiconductor device characterized in that the punch-through prevention region is provided in a region where the carrier receiving region and the well region face each other in a plane pattern in a direction perpendicular to the direction in which the carrier receiving region and the carrier supply region face each other.

2. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the punch-through prevention region is lower than the impurity concentration of the base region.

3. A semiconductor layer of a first conductivity type; a second conductivity type well region provided on an upper portion of the semiconductor layer; a second conductivity type base region provided above the well region and having a higher impurity concentration than the well region; a first conductive type carrier supply region provided above the base region; a first conductivity type drift region provided above the well region and spaced apart from the base region; a carrier receiving region of a first conductivity type provided above the drift region and having a higher impurity concentration than the drift region; a gate electrode provided on an upper surface of the well region sandwiched between the base region and the drift region via a gate insulating film; a second conductive type punch-through prevention region provided above the well region and having a higher impurity concentration than the well region and a different impurity concentration than the base region; Equipped with 4. A semiconductor device comprising: a first insulating layer formed on said first insulating film and a second insulating layer formed on said second insulating film;

4. A semiconductor layer of a first conductivity type; a second conductivity type well region provided on an upper portion of the semiconductor layer; a second conductivity type base region provided above the well region and having a higher impurity concentration than the well region; a first conductive type carrier supply region provided above the base region; a first conductivity type drift region provided above the well region and spaced apart from the base region; a carrier receiving region of a first conductivity type provided above the drift region and having a higher impurity concentration than the drift region; a gate electrode provided on an upper surface of the well region sandwiched between the base region and the drift region via a gate insulating film; a second conductive type punch-through prevention region provided above the well region and having a higher impurity concentration than the well region and a different impurity concentration than the base region; Equipped with a first impurity concentration in the punch-through prevention region being higher than a first impurity concentration in the base region;

5. 5. The semiconductor device according to claim 1, wherein the depth of the punch-through prevention region is deeper than the depth of the base region.

6. 2. The semiconductor device according to claim 1, wherein the punch-through prevention region is provided in a region where the drift region and the well region face each other in the perpendicular direction on a plane pattern.

7. forming a well region of a second conductivity type on an upper portion of a semiconductor layer of a first conductivity type; forming a second conductivity type base region having a higher impurity concentration than the well region above the well region; forming a second conductivity type punch-through prevention region having an impurity concentration higher than that of the well region and different from that of the base region, above the well region; forming a drift region of a first conductivity type above the well region and spaced apart from the base region; forming a carrier supply region of a first conductivity type above the base region; forming a carrier receiving region of a first conductivity type above the drift region and having a higher impurity concentration than the drift region; forming a gate electrode on an upper surface of the well region sandwiched between the base region and the drift region via a gate insulating film; Including, The steps of forming the base region and forming the punch-through prevention region include: forming a resist pattern having a first opening for forming the base region and a slit-shaped second opening for forming the punch-through prevention region; implanting impurity ions exhibiting a second conductivity type using the resist pattern as a mask; The base region and the punch-through prevention region having a lower impurity concentration than the base region are simultaneously formed by heat treatment. A method for manufacturing a semiconductor device comprising the steps of:

8. A step of forming a well region of a second conductivity type on an upper portion of a semiconductor layer of a first conductivity type; forming a second conductivity type base region having a higher impurity concentration than the well region above the well region; forming a second conductivity type punch-through prevention region having an impurity concentration higher than that of the well region and different from that of the base region, above the well region; forming a drift region of a first conductivity type above the well region and spaced apart from the base region; forming a carrier supply region of a first conductivity type above the base region; forming a carrier receiving region of a first conductivity type above the drift region and having a higher impurity concentration than the drift region; forming a gate electrode on an upper surface of the well region sandwiched between the base region and the drift region via a gate insulating film; Including, The steps of forming the base region and forming the punch-through prevention region include: forming a resist pattern having a slit-shaped first opening for forming the base region and a second opening for forming the punch-through prevention region; implanting impurity ions exhibiting a second conductivity type using the resist pattern as a mask; The base region and the punch-through prevention region having a higher impurity concentration than the base region are simultaneously formed by heat treatment. A method for manufacturing a semiconductor device comprising the steps of:

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