Semiconductor Device

Abstract

To provide a semiconductor device with high reliability, in which the insulation breakdown of a gate insulating film can be prevented.SOLUTION: A semiconductor device includes an n-type drift layer 2, an n-type current diffusion layer (3, 6) provided on an upper surface thereof and having higher impurity concentration than the drift layer 2, a p-type base region 8 provided on an upper surface thereof, a p-type gate bottom part protection region 5 provided inside the current diffusion layer and having a first lower end part including a curved surface, a p-type base bottom part embedded region (4, 7) provided inside the current diffusion layer apart from the gate bottom part protection region 5 in contact with a lower surface of the base region 8 and having a second lower end part including a curved surface on a side surface facing the gate bottom part protection region 5, and an insulated gate electrode structure provided inside a trench 11a reaching the gate bottom part protection region 5 while penetrating the base region 8. A bottom surface of the base bottom part embedded region is deeper than a bottom surface of the gate bottom part protection region 5. A minimum value of the radius of curvature of the first lower end part is larger than a minimum value of the radius of curvature of the second lower end part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a highly reliable trench type semiconductor device. [Background technology]

[0002] Conventionally, silicon (Si) semiconductors have been used in power semiconductor devices that are primarily used in power conversion devices and the like. In recent years, silicon carbide (SiC), a wide-gap semiconductor, has been expected to replace Si as a semiconductor material. Compared to conventional semiconductor elements that use Si as a material, SiC semiconductors have the advantages of being able to reduce the resistance of elements in the on-state to one-hundredth of that of conventional semiconductor elements that use Si as a material, and being usable in higher temperature environments (e.g., 200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of SiC is about three times larger than that of Si, and that the dielectric breakdown field strength is about ten times larger than that of Si.

[0003] As power semiconductor devices, Schottky barrier diodes (SBD), field effect transistors (FET), static induction transistors (SIT), insulated gate bipolar transistors (IGBT), etc. are commercially available. Trench MOSFETs are semiconductor devices with a three-dimensional structure in which a trench is formed in a SiC semiconductor substrate and the sidewall of the trench is used as a channel. Therefore, when comparing elements with the same on-resistance, trench MOSFETs can overwhelmingly reduce the element area compared to planar vertical MOSFETs, and are considered to be a particularly promising semiconductor element structure.

[0004] In conventional trench MOSFETs, a channel is formed vertically along the sidewall of a trench in a SiC semiconductor layer, resulting in a structure in which the entire inner wall of the trench is covered with a gate insulating film. Since the dielectric breakdown field strength of SiC is about 10 times greater than that of Si, the SiC semiconductor layer does not break down when a high voltage is applied, and a high electric field is also applied to the gate insulating film on the inner wall of the trench. In particular, the electric field is likely to concentrate at the bottom of the trench facing the drain electrode, and dielectric breakdown of the gate insulating film easily occurs. In order to improve the reliability of trench MOSFETs, an electric field relaxation structure is required that relieves the electric field concentration at the bottom of the trench and prevents breakdown of the gate insulating film. Conventionally, the electric field relaxation structure has been a p-type MOSFET adjacent to the base region. + The p-type base bottom buried region and the p-type base bottom buried region are in contact with the bottom of the trench. + The gate bottom protection region of the mold is selectively provided at the same level.

[0005] Patent Document 1 describes a structure in which the base bottom buried region is formed deeper toward the drain region than the gate bottom protection region. In the structure of Patent Document 1, the pn junction on the side of the base bottom buried region has a higher electric field strength than the pn junction on the side of the gate bottom protection region. This causes avalanche breakdown to occur on the side of the base bottom buried region, preventing carrier injection into the gate insulating film.

[0006] Patent Document 2 describes providing an n-type buried layer with a higher impurity concentration than the n-type impurity doped layer immediately below the gate bottom protection region so as to contact the bottom surface of the base bottom buried region. The electric field strength applied to the pn junction between the highly impurity-concentrated n-type buried layer and the base bottom buried region is higher than that of the pn junction between the n-type impurity doped layer and the gate bottom protection region. Therefore, avalanche breakdown is more likely to occur on the base bottom buried region side rather than on the gate bottom protection region side, preventing the avalanche current from flowing through the gate insulating film.

[0007] However, in Patent Documents 1 and 2, the base bottom buried region and the gate bottom protection region are formed in the same shape, so that the electric field is likely to concentrate at the corners of the base bottom buried region and the gate bottom protection region. Therefore, at the corners of the gate bottom protection region, the electric field strength may reach a level sufficient to cause avalanche breakdown. If avalanche breakdown occurs at the pn junction on the gate bottom protection region side, carriers may be injected into the gate insulating film inside the trench, causing dielectric breakdown of the gate insulating film. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2017 / 064949 [Patent Document 2] Patent No. 6617657 Summary of the Invention [Problem to be solved by the invention]

[0009] SUMMARY OF THE PRESENT EMBODIMENT In view of the above problems, an object of the present invention is to provide a highly reliable semiconductor device capable of preventing dielectric breakdown of a gate insulating film. [Means for solving the problem]

[0010] In order to achieve the above object, one aspect of the present invention includes: (a) a first conductivity type drift layer made of a hexagonal semiconductor having a band gap wider than that of silicon; (b) a first conductivity type current diffusion layer provided on an upper surface of the drift layer and having a higher impurity concentration than the drift layer; (c) a second conductivity type base region provided on an upper surface of the current diffusion layer; (d) a second conductivity type gate bottom protection region provided inside the current diffusion layer and having a first lower end portion formed of a curved surface; and (e) a second conductivity type gate bottom protection region provided inside the current diffusion layer and spaced apart from the gate bottom protection region, the second conductivity type base region having a lower end portion formed of a curved surface. and (f) an insulated gate type electrode structure provided inside a stripe-shaped trench that penetrates the base region and reaches the gate bottom protection region, wherein, in a cross section taken perpendicular to the extension direction of the trench, the bottom surface of the base bottom buried region is located deeper than the bottom surface of the gate bottom protection region, and the minimum value of the radius of curvature of the first bottom end is greater than the minimum value of the radius of curvature of the second bottom end. Effect of the Invention

[0011] According to the present invention, it is possible to provide a highly reliable semiconductor device capable of preventing dielectric breakdown of the gate insulating film. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 2 is a schematic cross-sectional view taken along line AA in FIG. 1. [Diagram 3] FIG. 3 is an enlarged view of part B in FIG. [Figure 4] 4 is a schematic cross-sectional view illustrating an example of a method for reducing the radius of curvature of the bottom corner of the base bottom buried region shown in FIG. 3. [Diagram 5] 11 is a diagram showing the relationship between the impurity concentration of the guard ring and the breakdown voltage of the termination portion. [Figure 6] 1A to 1C are schematic cross-sectional views for explaining an example of a process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7]7 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 6 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 8] 8 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 7 in the method for manufacturing a semiconductor device according to the embodiment of the present invention. [Figure 9] 9 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 8 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. [Figure 10] 10 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 9 in the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 11 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 10 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 12] 12 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 11 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 13] 13 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 12 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 14] 14 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 13 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 15] 15 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 14 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 16] 16 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 15 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 17] 17 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 16 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. [Figure 18] 18 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 17 in the method for manufacturing the semiconductor device according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0014] In this specification, the source region of a MOS transistor is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is n-type and the opposite second conductivity type is p-type will be described as an example. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + and -. However, even if the semiconductor regions have the same n and n added, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0016] <Structure of Semiconductor Device> As shown in Fig. 1, a SiC semiconductor device (semiconductor chip) 100 according to an embodiment of the present invention is made up of an active section 101 and an outer peripheral section 102. For example, the active section 101 has a rectangular planar shape, and the outer peripheral section 102 is disposed around the active section 101. Fig. 2 is a cross-sectional view taken along the line AA shown in Fig. 1. As shown in Fig. 2, the active section 101 includes an active element, and the outer peripheral section 102 includes a termination structure. In Fig. 2, a first conductivity type (n - 1 shows an example in which a MOSFET with a trench gate structure provided on top of a MOSFET-type (type) drift layer 2 includes, as a termination structure, a plurality of electric field relaxation regions (guard rings) 44. Stripe-shaped trenches 11a extend in a direction perpendicular to the paper surface.

[0017] As shown in Fig. 2, a base region 8 of a second conductivity type (p type) is disposed on the upper surface of the drift layer 2. The drift layer 2 and the base region 8 are each composed of an epitaxially grown layer (hereinafter abbreviated as "epitaxial layer") made of SiC. + An n-type base contact region 10 is selectively provided on the upper portion of the base region 8. The n-type base contact region 10 is in contact with the base contact region 10 and has a higher impurity concentration than the drift layer 2. + A first main region (source region) 9 of the type is optionally provided.

[0018] A stripe-shaped trench 11a having a width of 1 μm or less is provided from the upper surfaces of the source region 9 and base region 8 through the base region 8. The source region 9 and base region 8 are in contact with the side surfaces of the trench 11a. A gate insulating film 13 is provided on the bottom and side surfaces of the trench 11a. A gate electrode 14a is buried in the trench 11a with the gate insulating film 13 interposed therebetween, forming an insulated gate electrode structure (13, 14a). As the gate insulating film 13, in addition to a silicon dioxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a bismuth oxide (Bi2O3) film may be used as a single layer film or a composite film in which a plurality of these films are laminated. As the material for the gate electrode 14a, for example, a polysilicon layer (doped polysilicon layer) in which impurities such as phosphorus (P) or boron (B) are added at a high impurity concentration may be used.

[0019] The upper part of the drift layer 2 is made of n-type semiconductor material having a higher impurity concentration than the drift layer 2. + A p-type current diffusion layer (CSL) (3, 6) is selectively provided. The current diffusion layer (3, 6) is composed of a first diffusion layer 3 whose lower surface is in contact with the drift layer 2, and a second diffusion layer 6 that is in contact with the upper surface of the first diffusion layer 3 and the lower surface of the base region 8 and is in contact with the side surface of the trench 11a. The bottom of the trench 11a reaches the first diffusion layer 3. It is not essential to provide the current diffusion layer (3, 6). If the current diffusion layer (3, 6) is not provided, the bottom of the trench 11a reaches the drift layer 2. Inside the first diffusion layer 3, a p + A p-type gate bottom protection region 5 is provided inside the first diffusion layer 3 below the base contact region 10. The p-type gate bottom protection region 5 is located deeper than the gate bottom protection region 5 and is spaced apart from the gate bottom protection region 5. + A p-type first buried region 4 is provided inside the second diffusion layer 6 below the base contact region 10 so as to contact the upper surface of the first buried region 4 and the lower surface of the base region 8.+ A second buried region 7 of a type is provided. The first buried region 4 and the second buried region 7 constitute a base bottom buried region (4, 7). The gate bottom protection region 5 has a higher impurity concentration than the first buried region 4 of the base bottom buried region (4, 7).

[0020] 2, an interlayer insulating film 15 is disposed on the upper surface of the gate electrode 14a. A silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used as the interlayer insulating film 15. However, the interlayer insulating film 15 may be a silicon oxide film (PSG) doped with phosphorus (P), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG) doped with boron (B), a silicon nitride (Si3N4) film, or the like. A laminate film of these may also be used.

[0021] 2, a source contact layer 16 is provided so as to be in physical contact with the source region 9 and the base contact region 10 exposed between the interlayer insulating film 15. A barrier metal layer 17 is provided so as to cover the interlayer insulating film 15 and the source contact layer 16. A first main electrode (source electrode) 18a is electrically connected to the source region 9 and the base contact region 10 via the barrier metal layer 17 and the source contact layer 16. For example, if the source contact layer 16 is made of nickel silicide (NiSi x The barrier metal layer 17 can be made of a titanium nitride (TiN) film or a titanium (Ti) film, and the source electrode 18a can be made of an aluminum (Al) film or an aluminum-silicon (Al-Si) film. The source electrode 18a is disposed separately from the gate surface electrode (not shown).

[0022] In the active portion 101 near the outer periphery 102, as shown in FIG. 2, a base contact region 10a is provided above the base region 8. A wiring layer 14b is disposed on the upper surface of the base contact region 10a via a field oxide film 12, and a gate electrode pad 18b is disposed on the upper surface of the wiring layer 14b via a barrier metal layer 17b. Although not shown, the gate electrode pad 18b is electrically connected to the gate electrode 14a via the wiring layer 14b. The interlayer insulating film 15 and the field oxide film 12 extend from near the boundary between the active portion 101 and the outer periphery 102 to the bottom of the mesa groove 11b in the outer periphery 102. In addition, a base bottom buried region (4a, 7a) is provided in the active portion 101 near the outer periphery 102 so as to contact the lower surface of the base region 8. The base bottom buried region (4a, 7a) is composed of a second buried region 7a in contact with the lower surface of the base region 8, and a first buried region 4a whose lower surface is in contact with the partial current diffusion layer 22a.

[0023] As shown in FIG. 2, in the outer peripheral portion 102, a plurality of p + A type-type guard ring 44 is provided. The multiple guard rings 44 function as electric field relaxation regions, and are provided in the shape of concentric rings spaced apart from one another so as to surround the active section 101. In the drift layer 2, the bottom surface of each of the multiple guard rings 44 is at the same level as the bottom surface of the first buried region 4 of the base bottom buried region (4a, 7a), and is provided with the same impurity concentration as the first buried region 4. The bottom surface of each of the multiple guard rings 44 has an n + A plurality of partial current spreading layers 42a of the same type are provided. Each of the plurality of partial current spreading layers 42a is at the same level as the partial current spreading layers 22, 22a and has the same impurity concentration.

[0024] At the outer end of the outer periphery 102, n + The channel stoppers 33 are arranged in a concentric ring shape. + Instead of the channel stopper 33 of the type, + A molded channel stopper may be provided.

[0025] The bottom surface of the drift layer 2 is + A second main region (drain region) 1 of a type is disposed on the bottom surface of the drain region 1. A second main electrode (drain electrode) 19 is disposed on the bottom surface of the drain region 1. As the drain electrode 19, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Ti, nickel (Ni) and Au can be used, and further a metal film of molybdenum (Mo), tungsten (W) or the like may be laminated on the bottom layer. In addition, a drain contact layer may be provided between the drain region 1 and the drain electrode 19. The drain contact layer is, for example, nickel silicide (NiSi x ) membrane.

[0026] For example, the impurity concentration of the drift layer 2 is 2×10 15 cm -3 More than 2×10 16 cm -3 Hereinafter, the impurity concentration of the base region 8 is 1×10 17 cm -3 More than 1×10 18 cm -3 The impurity concentration of the base contact region 10 is 5×10 18 cm -3 5×10 or more 20 cm -3 Hereinafter, the impurity concentration of the source region 9 is 5×10 18 cm -3 5×10 or more 20 cm -3 The impurity concentration of the current spreading layer (3, 6) is 5×10 16 cm -3 5×10 or more 17 cm -3 In the following, the impurity concentration of the partial current spreading layer 22 is 5×10 17 cm -3 5×10 or more 18 cm -3 The gate bottom protection region 5 has a higher impurity concentration than the first buried region 4 of the base bottom buried region (4, 7), and is 1×10 17 cm -3 Larger, 1×10 19 cm -3 Less than 3×10 18 cm -3More than 1×10 19 cm -3 The impurity concentration of the first buried region 4 and the guard ring 44 of the base bottom buried region (4, 7) is the same, and is 1×10 17 cm -3 More than 3×10 18 cm -3 The impurity concentration of the second buried region 7 of the base bottom buried region (4, 7) is approximately the same as that of the first buried region 4, but may be higher than that of the first buried region 4. The impurity concentration of the drain region 1 is 1×10 18 cm -3 More than 1×10 19 cm -3 The following is the result.

[0027] In the semiconductor device according to the embodiment, the drain region 1 is made of a semiconductor substrate (SiC substrate) made of SiC, and the drift layer 2 is made of an epitaxial layer (SiC layer) made of SiC. The semiconductor region constituting the semiconductor device according to the embodiment including the drain region 1 and the drift layer 2 is not limited to SiC. In addition to SiC, for example, hexagonal semiconductor materials such as gallium nitride (GaN), lonsdaleite (hexagonal diamond), and aluminum nitride (AlN) having a wider bandgap than that of Si (1.1 eV) can be used. The bandgap at room temperature has been reported to be 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. In the present invention, a semiconductor having a bandgap wider than that of silicon is defined as a wide bandgap semiconductor.

[0028] During operation of the semiconductor device according to the embodiment, when the source electrode 18a is set to earth potential, a positive voltage is applied to the drain electrode 19, and a positive voltage equal to or greater than a threshold is applied to the gate electrode 14a, an inversion layer (channel) is formed on the side of the trench 11a in the base region 8, resulting in an ON state. The inversion layer is formed on the surface of the base region 8 exposed on the side of the trench 11a, which is the interface between the base region 8 and the gate insulating film 13 sandwiched at a position where the base region 8 faces the gate electrode 14a. In the ON state, a current flows from the drain electrode 19 to the source electrode 18a via the drain region 1, the drift layer 2, the current diffusion layers (3, 6), the inversion layer of the base region 8, and the source region 9. On the other hand, when the voltage applied to the gate electrode 14a is less than the threshold, an inversion layer is not formed in the base region 8, resulting in an OFF state, and no current flows from the drain electrode 19 to the source electrode 18a.

[0029] FIG. 3 is an enlarged view of the B portion in FIG. 1. As shown in FIG. 3, the gate bottom protection region 5 is provided inside the first diffusion layer 3 of the current diffusion layer (3, 6). The lower end (first lower end) 5r and the upper end 5s of the gate bottom protection region 5 each have a curved surface. The lower end (second lower end) 4r of the first buried region 4 of the base bottom buried region (4, 7) also has a curved surface. In a cross section cut perpendicular to the extension direction of the trench 11a, the circle having the smallest radius of curvature among the arcs approximating the curved surface of the lower end 5r of the gate bottom protection region 5 is defined as the curvature circle Da, and the circle having the smallest radius of curvature among the arcs approximating the curved surface of the upper end 5s of the gate bottom protection region 5 is defined as the curvature circle Dc. Similarly, the circle having the smallest radius of curvature among the arcs approximating the curved surface of the lower end 4r of the base bottom buried region (4, 7) is defined as the curvature circle Db. The minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5 is larger than the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the first buried region 4 of the base bottom buried region (4,7). Therefore, the electric field is likely to concentrate on the lower end 4r of the base bottom buried region (4,7). Therefore, the avalanche breakdown is likely to occur on the base bottom buried region (4,7) side rather than on the gate bottom protection region 5 side, and it is possible to prevent the avalanche current from flowing into the gate insulating film 13 inside the trench 11a. In addition, it is desirable to make the minimum value of the radius of curvature of the circle of curvature Dc of the upper end 5s of the gate bottom protection region 5 larger than the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the base bottom buried region (4,7). As a result, the electric field concentration near the gate bottom protection region 5 can be further alleviated, and it is possible to prevent the avalanche breakdown from occurring near the gate bottom protection region 5.

[0030] The gate bottom protection region 5 and the first buried region 4 of the base bottom buried region (4, 7) are formed by injecting p-type impurity ions into the n-type current diffusion layer (3, 6) using an ion implantation technique, as described below. The impurity diffusion coefficient in SiC is very small, so the impurity concentration distribution can be controlled accurately and reproducibly. The penetration depth of the implanted ions is determined by the acceleration energy and the loss of momentum due to collision and scattering with the crystal lattice of the semiconductor layer, and varies according to a Gaussian distribution. In general, the greater the ion implantation depth, the greater the variation in the depth distribution of the implanted ions. FIG. 4 is a schematic cross-sectional view illustrating an example of forming the gate bottom protection region 5 and the first buried region 4 of the base bottom buried region (4, 7) by injecting p-type impurity ions into the first diffusion layer 3 of the current diffusion layer (3, 6). The implantation region 4x shown in FIG. 4 is a region in which p-type impurity ions, which are implanted from the surface of the first diffusion layer 3 aiming at the level of the bottom surface of the first buried region 4, are distributed in a scattered manner further downward from the bottom surface of the first buried region 4. As shown in FIG. 3, the level of the bottom surface of the first buried region 4 is deeper than the bottom surface of the gate bottom protection region 5 by a depth t, and the distribution of the implanted ions in the implantation region 4x becomes more uneven. Therefore, the minimum value of the radius of curvature of the circle of curvature Dx of the lower end 4xr of the implantation region 4x becomes larger than the minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5. Therefore, before forming the first buried region 4, n-type impurity ions are implanted at a position overlapping with the implantation region 4x to form an n-type impurity ion having a higher impurity concentration than the implantation region 4x. + As a result, the p-type impurity of the implantation region 4x is compensated for by the n-type impurity of the partial current diffusion layer 22, and the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the first buried region 4 can be made smaller than the minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5. Note that after forming the first buried region 4 and the implantation region 4x, an n-type impurity having a higher impurity concentration than the implantation region 4x is formed so as to overlap the implantation region 4x. + A partial current spreading layer 22 of the same type may be provided.

[0031] 3, the bottom surface of the first buried region 4 of the base bottom buried region (4,7) is provided at a level that is deeper than the bottom surface of the gate bottom protection region 5 by a depth t. Therefore, during operation of the semiconductor device according to the embodiment, the electric field is more likely to concentrate on the base bottom buried region (4,7) side, and it is possible to alleviate the electric field concentration on the gate bottom protection region 5. Here, the depth t may be zero, that is, the bottom surfaces of the first buried region 4 and the gate bottom protection region 5 may be the same depth. Here, the same depth is a concept that includes manufacturing variations and may include variations of about ±100 nm. Even in this case, the electric field is concentrated on the first buried region 4, which has a smaller radius of curvature, so the same effect can be obtained.

[0032] In the semiconductor device according to the embodiment shown in FIG. 2, if the p-type impurity concentration in the gate bottom protection region 5 is low, the effect of mitigating electric field concentration is reduced, making it difficult to prevent dielectric breakdown of the gate insulating film 13. Furthermore, if the p-type impurity concentration in the guard ring 44 is too high, the breakdown voltage in the outer periphery 102 is reduced. FIG. 5 is a diagram showing the relationship between the breakdown voltage of a pn diode corresponding to the pn junction between the guard ring 44 and the drift layer 2, for example, and the p-type impurity concentration in the semiconductor layer corresponding to the guard ring 44. As shown in FIG. 5, when the p-type impurity concentration is 3×10 18 cm -3 If the p-type impurity concentration is less than 3×10, the diode breakdown voltage can be maintained at 1800V or more. 18 cm -3 If the voltage exceeds this limit, the breakdown voltage of the diode will be reduced to approximately 1660 V or less. Therefore, in order to alleviate the electric field concentration in the vicinity of the trench 11a, the p-type impurity concentration of the gate bottom protection region 5 is set to 3×10 18 cm -3 More than 1×10 19 cm -3 In order to suppress a decrease in the breakdown voltage in the outer peripheral portion 102, the impurity concentration of the first buried region 4 and the guard ring 44 in the base bottom buried region (4, 7) is set to 1×10 17 cm -3 More than 3×10 18 cm -3 Less than.

[0033] In this manner, in the embodiment, the minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5 is set to be larger than the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the first buried region 4 of the base bottom buried region (4,7). In addition, the bottom surface of the first buried region 4 is provided at a level that is deeper than the bottom surface of the gate bottom protection region 5 by a depth t. As a result, the electric field is concentrated on the base bottom buried region (4,7) side, thereby alleviating the electric field concentration on the gate bottom protection region 5, and it becomes possible to prevent avalanche breakdown from occurring in the vicinity of the gate bottom protection region 5.

[0034] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a SiC semiconductor device according to an embodiment will be described using a trench MOSFET as an example, with reference to the process cross-sectional views of Figures 6 to 18. Note that the method for manufacturing a trench MOSFET described below is only an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0035] First, n-type impurities such as nitrogen (N) are added. + A type SiC semiconductor substrate (substrate) 1p is prepared. - Next, using a photoresist film 130 formed on the upper surface of the epitaxial layer as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted into the epitaxial layer in multiple stages from the upper surface side of the epitaxial layer. In this way, as shown in FIG. 6, n-type impurity ions are implanted in the upper part of drift layer 2 made of an epitaxial layer in active portion 101 of semiconductor chip 100 shown in FIG. + A n-type implantation layer 3p is formed in the outer periphery 102. + A mold channel stopper 33 is formed.

[0036] An oxide film made of SiO2 is deposited on the upper surfaces of the implantation layer 3p and the channel stopper 33 by CVD technology or the like. The oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film 140 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages so as to reach the upper part of the drift layer 2 below the implantation layer 3p. Subsequently, using the oxide film 140 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the implantation layer 3p so as to connect to the upper part of the drift layer 2 into which the n-type impurities have been implanted. As shown in FIG. 7, in the active portion 101, n-type impurity ions are implanted in the upper part of the drift layer 2. + The partial current diffusion layers 22 and 22a are selectively formed, and the first diffusion layer 3 is provided with a p + In the peripheral portion 102, the n-type first buried regions 4, 4a are selectively formed on the upper portion of the drift layer 2. + A plurality of partial current spreading layers 42a of the type are selectively formed, and p + A plurality of guard rings 44 of the mold are selectively formed.

[0037] After removing the oxide film 140, a new oxide film is deposited on the upper surfaces of the first diffusion layer 3, the first buried regions 4, 4a, the guard ring 44, and the channel stopper 33, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film 150 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the first diffusion layer 3 so as to separate it from the first buried region 4. As a result, as shown in FIG. 8, p-type impurity ions having a higher impurity concentration than the first buried region 4 are formed between the first buried regions 4. +A gate bottom protection region 5 having a p-type impurity concentration higher than that of the p-type impurity distributed in the implantation region 4x is selectively formed. In the vicinity of the boundary between the active portion 101 and the peripheral portion 102, the gate bottom protection region 5 is formed in contact with the first buried region 4a. As shown in FIG. 3 and FIG. 4, in the first diffusion layer 3, the first buried region 4 is formed at a deeper level of p-type impurity ions than the gate bottom protection region 5. Therefore, an n-type impurity having a higher impurity concentration than the p-type impurity distributed in the implantation region 4x is formed so as to overlap with the implantation region 4x formed beyond the bottom surface of the first buried region 4. + As a result, the p-type impurities distributed in the implantation region 4x are compensated for by the n-type impurities of the partial current diffusion layer 22, and the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the first buried region 4 can be made smaller than the minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5. Note that after forming the first buried region 4 and the implantation region 4x, an n-type impurity having a higher impurity concentration than the implantation region 4x is formed so as to overlap the implantation region 4x. + A partial current spreading layer 22 of the same type may be formed.

[0038] After removing the oxide film 150, an n-type epitaxial layer 6p is grown on the upper surfaces of the first diffusion layer 3, the first buried regions 4, 4a, the gate bottom protection region 5, the guard ring 44, the drift layer 2, and the channel stopper 33, as shown in FIG. 9. A photoresist film is applied to the upper surface of the epitaxial layer 6p, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 160 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper part of the epitaxial layer 6p from the upper surface side of the epitaxial layer 6p. As a result, as shown in FIG. 10, n-type impurity ions such as nitrogen (N) are grown on the first diffusion layer 3, the first buried region 4, and the gate bottom protection region 5. + A mold implantation layer 6a is formed.

[0039] After removing the photoresist film 160, an oxide film is deposited on the upper surfaces of the implantation layer 6a and the epitaxial layer 6p, and the oxide film is patterned using photolithography and dry etching techniques. Using the patterned oxide film 170 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the implantation layer 6a and the epitaxial layer 6p. As a result, p-type impurity ions such as aluminum (Al) are formed on the first buried region 4 as shown in FIG. + The second buried region 7 of the n type + The first buried region 4a and the second buried region 7 are selectively formed so as to sandwich the second diffusion layer 6 of the p-type. A base bottom buried region (4, 7) consisting of the first buried region 4 and the second buried region 7 is formed. Also, a p + A second buried region 7a of the mold is selectively formed.

[0040] After removing the oxide film 170, a p-type epitaxial layer 8p is grown on the upper surfaces of the second buried regions 7, 7a, the second diffusion layer 6, and the epitaxial layer 6p, as shown in Fig. 12. From the upper surface side of the epitaxial layer 8p, n-type impurity ions such as phosphorus (P) are implanted into the epitaxial layer 8p in multiple stages to form n-type ions in the upper part of the epitaxial layer 8p. + A mold injection layer is formed. An oxide film is deposited on the upper surface of the injection layer formed on the upper part of the epitaxial layer 8p by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as an etching mask, the injection layer on the upper part of the epitaxial layer 8p, the epitaxial layer 8p and the epitaxial layer 6p are selectively etched by dry etching technology or the like. As a result, a mesa groove 11b is formed as shown in FIG. 13. In the active part 101 shown in FIG. 1, the injection layer 9p, the base region 8 and the second buried region 7a remain, and in the outer peripheral part 102, the upper surfaces of the multiple guard rings 44 are exposed at the bottom surface of the mesa groove 11b.

[0041] After removing the etching mask, an oxide film is deposited on the upper surface of the implantation layer 9p and on the bottom surface of the mesa groove 11b by CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the implantation layer 9p in multiple stages from the upper surface side of the implantation layer 9p. As a result, as shown in FIG. 14, a source region 9 is formed above the gate bottom protection region 5, and a p-type impurity ion in contact with the source region 9 is formed above the second buried regions 7, 7a. + Mold base contact regions 10, 10a are formed.

[0042] After removing the oxide film used as a mask for ion implantation, an oxide film is deposited on the upper surfaces of the base contact regions 10, 10a and source region 9, and on the bottom surface of the mesa groove 11b, by CVD or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography and dry etching techniques. Using the patterned oxide film as an etching mask, a trench 11a is selectively formed by dry etching. As shown in FIG. 15, the trench 11a penetrates the source region 9, base region 8, and second diffusion layer 6 to reach the gate bottom protection region 5 formed in the first diffusion layer 3. A n-type diffusion layer 11a is formed by the first diffusion layer 3 and the second diffusion layer 6. + A current spreading layer (3, 6) of the type is formed on the upper surface of the drift layer 2.

[0043] After removing the etching mask, a carbon (C) film is formed on the upper surface of the trench 11a by carbon sputtering or the like. Then, a heat treatment is performed to simultaneously activate the implanted n-type impurity ions and p-type impurity ions. A field oxide film is deposited on the exposed surface after removing the carbon film by CVD or the like. A photoresist film is applied to the upper surface of the field oxide film, and the photoresist film is patterned by photolithography or the like. The patterned photoresist film is used as an etching mask to selectively remove the field oxide film. As a result, as shown in FIG. 16, a field oxide film 12 is formed that extends from the bottom and side surfaces of the mesa groove 11b to the upper surface of the base contact region 10a.

[0044] A gate insulating film 13p such as a SiO2 film is formed on the bottom and side surfaces of the trench 11a and on the upper surfaces of the source region 9 and the base contact region 10 by thermal oxidation or chemical vapor deposition (CVD) technology. Next, as shown in Fig. 17, a polysilicon layer (doped polysilicon layer) 14p doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD technology or the like so as to fill the trench 11a.

[0045] Then, a part of the polysilicon layer 14p and a part of the gate insulating film 13p are selectively removed by photolithography and dry etching. As shown in FIG. 18, a pattern of the gate electrode 14a made of the gate insulating film 13 and the polysilicon layer is formed to form an insulated gate electrode structure (13, 14a). Next, an insulating film is deposited on the upper surface of the insulated gate electrode structure (13, 14a) made of the gate electrode 14a and the gate insulating film 13 by CVD or the like. As the insulating film, boron phosphorus glass (BPSG), NSG, or the like is used. Then, a part of the deposited insulating film is selectively removed by photolithography and dry etching or the like. As a result, a source electrode contact hole is opened in the interlayer insulating film 15 as shown in FIG. 18. Although not shown, a gate contact hole is also opened in the interlayer insulating film 15 at a location different from the source electrode contact hole so that a part of the gate surface electrode connected to the gate electrode 14a is exposed.

[0046] A metal layer such as a Ni film is deposited by sputtering or vapor deposition, and the metal layer is patterned by photolithography and RIE. Then, rapid thermal annealing (RTA), for example, at about 1000°C, is performed to form NiSi xThen, the unreacted Ni film is removed to form a source contact layer 16 on the upper surface of the source region 9 and the base contact region 10, as shown in FIG. 18. Next, a barrier metal layer (not shown) such as a Ti film or a TiN film and a metal layer such as an Al film are deposited by sputtering or the like. The barrier metal layer and the metal layer are patterned by photolithography and RIE techniques to form a pattern of a source electrode 18a, a gate electrode pad 18b, and a gate surface electrode (not shown) as shown in FIG. 2. As a result, a laminated structure of the barrier metal layer 17 and the source electrode 18a is formed so as to cover the source contact layer 16 and the interlayer insulating film 15. The patterns of the source electrode 18a and the gate surface electrode are separated, and the gate electrode pad 18b, which forms a laminated structure with the barrier metal layer 17b, is electrically connected to the gate electrode 14a via the wiring layer 14b provided on the field oxide film 12.

[0047] Furthermore, the bottom surface of the substrate 1p is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Thereafter, a drain electrode 19 made of Ti, Ni, Au or the like is formed on the entire bottom surface of the drain region 1 by a sputtering method or a deposition method or the like. In this manner, the trench gate type semiconductor device shown in FIG. 2 is completed.

[0048] 3 and 4, in the embodiment, the minimum value of the radius of curvature of the circle of curvature Da of the lower end 5r of the gate bottom protection region 5 is set to be larger than the minimum value of the radius of curvature of the circle of curvature Db of the lower end 4r of the first buried region 4 of the base bottom buried region (4,7). In addition, the bottom surface of the first buried region 4 is formed at a level that is deeper than the bottom surface of the gate bottom protection region 5 by a depth t. As a result, the electric field is concentrated on the base bottom buried region (4,7) side, thereby alleviating the electric field concentration on the gate bottom protection region 5, and it becomes possible to prevent avalanche breakdown from occurring in the vicinity of the gate bottom protection region 5.

[0049] (Other embodiments) As described above, the insulated gate semiconductor device according to the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0050] In the embodiment, a semiconductor device using SiC has been exemplified, but the present invention can also be applied to a semiconductor device using other hexagonal wide band gap semiconductors such as gallium nitride (GaN) or diamond.

[0051] Thus, the present invention naturally includes various embodiments not described here, such as configurations in which the configurations described in the above embodiments and modifications are applied in any way. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0052] 1...Drain region (second main region) 1p...Semiconductor substrate (substrate) 2. Drift layer 3…First diffusion layer (3,6)…Current spreading layer 4, 4a...First buried region (4,7)…Base bottom buried region 4r…Lower end (second lower end) 4x…Injection area 4xr…lower end 5…Gate bottom protection area 5r…Lower end (first lower end) 5s…Top end 6…Second diffusion layer 7, 7a...Second buried region 8…Base area 9...Source region (first main region) 10...Base contact region 11a…Trench (11a, 14a)…Insulated gate electrode structure 11b...Mesa groove 12...Field oxide film 13...Gate insulating film 14a...gate electrode 15...Interlayer insulating film 16…Source contact layer 17...Barrier metal layer 18a...Source electrode (first main electrode) 19...Drain electrode (second main electrode) 22, 22a, 42a...partial current diffusion layer 33...Channel stopper 44...Electric field relaxation region (guard ring)

Claims

1. a first conductivity type drift layer made of a hexagonal semiconductor having a band gap wider than that of silicon; a current diffusion layer of a first conductivity type provided on an upper surface of the drift layer and having a higher impurity concentration than the drift layer; a second conductivity type base region provided on an upper surface of the current spreading layer; a second conductivity type gate bottom protection region provided within the current spreading layer and having a first lower end portion formed of a curved surface; a second conductivity type base bottom buried region that is disposed inside the current spreading layer and is spaced apart from the gate bottom protection region, contacts a lower surface of the base region, and has a second lower end portion formed of a curved surface on a side surface facing the gate bottom protection region; an insulated gate electrode structure provided inside a stripe-shaped trench that penetrates the base region and reaches the gate bottom protection region; Equipped with In a cross section taken perpendicular to the extension direction of the trench, a bottom surface of the base bottom buried region is located deeper than a bottom surface of the gate bottom protection region; A semiconductor device, wherein a minimum value of the radius of curvature of the first bottom end is greater than a minimum value of the radius of curvature of the second bottom end.

2. 2. The semiconductor device according to claim 1, wherein the gate bottom protection region has a higher impurity concentration than the base bottom buried region.

3. The impurity concentration of the gate bottom protection region is 3×10 18 cm -3 Above 1 x 10 19 cm -3 3. The semiconductor device according to claim 1, wherein the thickness of the semiconductor device is less than 100 nm.

4. The impurity concentration of the base bottom buried region is 1×10 17 cm -3 Above 3 x 10 18 cm -3 3. The semiconductor device according to claim 1, wherein the thickness of the semiconductor device is less than 100 nm.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that the gate bottom protection region has an upper end portion formed of a curved surface, and the minimum value of the radius of curvature of the upper end portion is greater than the minimum value of the radius of curvature of the second lower end portion.

6. 6. The semiconductor device according to claim 1, further comprising a first conductivity type partial current diffusion layer in contact with the bottom surface of the base bottom buried region and having a higher impurity concentration than the current diffusion layer.

7. 7. The semiconductor device according to claim 1, further comprising a guard ring of a second conductivity type arranged around an active portion in which the insulated gate electrode structure is provided, the guard ring being provided on an upper portion of the drift layer and having a bottom surface at the same level as the bottom surface of the base bottom buried region and having the same impurity concentration as the base bottom buried region.

8. 8. The semiconductor device according to claim 1, wherein the hexagonal semiconductor is silicon carbide.

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