Semiconductor device manufacturing method

Abstract

To suppress the generation of shorts and leakage currents due to the formation of sub-trench shapes on an interlayer dielectric film.SOLUTION: A recess 10c corresponding to a contact part is formed on an interlayer dielectric film 10. A contact hole 10a is formed by dry etching the interlayer dielectric film 10 in a wider range than that.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure. [Background technology]

[0002] When manufacturing a semiconductor device having a semiconductor element with a trench gate structure, as in Patent Document 1, a process is performed in which the trench gate structure is covered with an interlayer insulating film, and then a contact hole is formed in the interlayer insulating film by dry etching. For example, when the semiconductor element is a MOSFET with a trench gate structure, the trench gate structure is covered with an interlayer insulating film, and then a contact hole is formed in the interlayer insulating film to expose a source region, etc. Through this contact hole, electrical connection is made between the source region, etc. and a source electrode formed on the interlayer insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-46908 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a large-area contact hole is formed by etching, the deposition components, i.e., polymers, supplied from the resist serving as an etching mask are relatively small compared to when a small-area opening is formed. This results in an insufficient formation of a protective film made of polymers. Therefore, when ions generated during dry etching are reflected from the sidewalls or bottom of the contact hole, abnormal etching progresses locally at the opening edge of the contact hole, forming a sub-trench shape. This causes a part of the interlayer insulating film to be removed, exposing, for example, the gate electrode located below, or thinning the interlayer insulating film, which may cause a short circuit between the electrode on the interlayer insulating film and the gate electrode, or may cause a leakage current.

[0005] In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the occurrence of short circuits and leak currents caused by the formation of a sub-trench shape in an interlayer insulating film. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention according to claim 1 is a method for manufacturing a semiconductor device having a trench gate structure, comprising the steps of: preparing a substrate (1) made of a semiconductor of a first or second conductivity type; forming a base region (4) of a second conductivity type on the substrate via a drift layer (2, 3) of a first conductivity type, and forming a first conductivity type layer (5) and a contact region (6) of the base region on a surface layer of the base region; forming an element portion of a semiconductor element having a trench gate structure in which a gate electrode (9) is disposed via a gate insulating film (8) in a trench (7) that penetrates the first conductivity type layer and the base region to reach the drift layer; forming an interlayer insulating film (10) on the trench gate structure, the first conductivity type layer, and the contact region; the first mask being removed, and then a second mask (21) being formed with a second opening (21a) having an opening end positioned outside the cell region relative to the opening end of the first opening, at least on both sides of the longitudinal direction of the trench gate structure; forming a contact hole (10a) by dry etching using the second mask, thereby exposing the first conductive type layer and the contact region through the contact hole while leaving the interlayer insulating film in the trench, thereby forming a contact portion; and forming a surface electrode (11) in the contact portion that is in contact with the first conductive type layer and the contact region.

[0007] In this way, a recess corresponding to the contact portion is formed in the interlayer insulating film, and then the interlayer insulating film is dry-etched over a wider area to form a contact hole, thereby exposing the first conductive type layer and the contact region to form the contact portion. This makes it possible to prevent a sub-trench shape from being formed at the opening end of the contact hole, and makes it possible to prevent the occurrence of short circuits and leak currents.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device including a MOSFET manufactured by a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a top view of the semiconductor device shown in FIG. [Figure 3A] 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 during a manufacturing process. [Figure 3B] FIG. 3B is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 3A. [Figure 3C] FIG. 3C is a cross-sectional view of the semiconductor device during the manufacturing process subsequent to FIG. 3B. [Figure 3D] 3D is a cross-sectional view of the semiconductor device during the manufacturing process subsequent to FIG. 3C. [Figure 4] FIG. 1 is a cross-sectional view of a semiconductor device in which a sub-trench shape is formed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0011] (First embodiment) A first embodiment of the present invention will be described. Here, a manufacturing method of a semiconductor device including a MOSFET as a semiconductor element having a trench gate structure will be described, but before that, a schematic configuration of a MOSFET manufactured by the manufacturing method will be described with reference to Fig. 1. Note that Fig. 1 shows a cross section near the outer edge of a cell region in which a MOSFET having a trench gate structure is formed, and the semiconductor device is composed of the cell region shown here and a peripheral breakdown withstand structure (not shown) formed so as to surround the cell region.

[0012] As shown in Fig. 1, the semiconductor device is formed using a substrate 1 made of a semiconductor material such as silicon (Si) or silicon carbide (SiC). The substrate 1 is n-type and is doped with a high concentration of n-type impurities. On the substrate 1, a n-type semiconductor layer with a lower impurity concentration than the substrate 1 is formed. - In addition, the n-type impurity layer 2 is formed. - An n-type current spreading layer 3 is formed on the surface of the n-type impurity layer 2, and a p-type base region 4 is further formed thereon. - The n-type impurity layer 2 and the n-type impurity layer 3 constitute a drift layer. - The p-type base region 4 has a higher concentration than the p-type impurity layer 2 and thus serves to distribute the current in the planar direction of the substrate 1. The p-type base region 4 constitutes a second conductivity type layer that constitutes the channel of the vertical MOSFET, and is formed so as to contact the side surfaces of the trench 7 on both sides of the trench 7 that constitutes a trench gate structure described later.

[0013] The surface layer of the p-type base region 4 on the trench gate structure side is doped with n-type impurities at a high concentration, and the n-type impurity layer corresponds to a first conductive type layer. + The p-type source region 5 is formed in the surface layer of the p-type base region 4. + At the opposite side of the trench gate structure across the source region 5, a p + A mold contact region 6 is formed.

[0014] Furthermore, the p-type base region 4 and the n + The n-type source region 5 is - A trench 7 is formed so as to reach the n-type impurity layer 2. The p-type base region 4 and the n-type impurity layer 2 are formed so as to contact the side surfaces of the trench 7. +A type source region 5 is disposed in the trench 7. The inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and a gate electrode 9 made of doped poly-Si is formed on the surface of the gate insulating film 8. In this manner, the gate insulating film 8 and the gate electrode 9 are disposed in the trench 7, thereby forming a trench gate structure.

[0015] As shown in Fig. 2, the trench gate structure is shaped like a strip with its longitudinal direction extending in the vertical direction of the page, or in the normal direction to the page in Fig. 1. A cell region with multiple cells is formed by arranging multiple trench gate structures in the shape of stripes at equal intervals in the horizontal direction of the page.

[0016] As shown in FIG. 1, the trench gate structure is located at the outer edge of the cell region, that is, between the parts located outside the contact part described later. + No type source region 5 is formed, and the p-type base region 4 is left up to the surface. Therefore, this portion is a region where MOS operation does not occur, even though a trench gate structure is formed. The gate electrode 9 located on the outermost side of the cell region is left on the p-type base region 4 further outside the cell region, forming a gate liner 8a. Although not shown, gate liners 8a are also formed at both ends in the vertical direction of the paper surface of FIG. 2 so as to be perpendicular to each trench gate structure. Each gate electrode 9 is electrically connected via this gate liner 8a, so that the same gate voltage is applied.

[0017] An interlayer insulating film 10 is formed on the p-type base region 4 and the trench gate structure. + Type source region 5 and p + A contact hole 10a is formed so that the contact region 6 can make contact with a source electrode 11, which will be described later. The bottom of the contact hole 10a is + Type source region 5 and p +This becomes a contact portion where contact is made between the type contact region 6 and the source electrode 11, and in the contact portion, the interlayer insulating film 10 remains only in the portion covering the gate electrode 9.

[0018] Specifically, in the contact portion, the interlayer insulating film 10 remains only in the trench 7, and the trench 7 is filled with the trench gate structure and the interlayer insulating film 10. Therefore, in the present embodiment, in the contact portion, the surface of the interlayer insulating film 10 and the n + Type source region 5 and p + The surface of the n-type contact region 6 is flush with the surface of the n-type contact region 6. The interlayer insulating film 10 is removed outside the trench 7. + Type source region 5 and p + The p-type contact region 6 is exposed. The interlayer insulating film 10 is left thin by a predetermined width so as to surround the outer periphery of the contact part (hereinafter, this part is referred to as thin part 10b). Furthermore, the interlayer insulating film 10 is left thick on the p-type base region 4 at a position on the outer periphery side of the thin part 10b, covering the trench gate structure and the like in the part where MOS does not operate.

[0019] In addition, the interlayer insulating film 10 and n + Type source region 5 and p + A source electrode 11 corresponding to a surface electrode is formed on the n-type contact region 6. + Type source region 5 and p + The source electrode 11 and the gate electrode 9 are in ohmic contact with the contact region 6. As described above, the interlayer insulating film 10 is left in the trench 7, so that the source electrode 11 and the gate electrode 9 are insulated from each other.

[0020] Furthermore, a drain electrode 12 corresponding to a back electrode electrically connected to the substrate 1 is formed on the back side of the substrate 1. With this structure, an n-channel type inversion type vertical MOSFET with a trench gate structure is formed. As described above, although not shown, a peripheral breakdown voltage structure, such as a guard ring, is formed on the periphery of the cell region. The cell region and the peripheral breakdown voltage structure form a semiconductor device.

[0021] Next, a method for manufacturing the semiconductor device of this embodiment will be described. However, since the manufacturing process of each part of the element portion constituting the MOSFET in the manufacturing method of the semiconductor device is the same as the conventional method, the manufacturing process after forming the element portion will be mainly described here.

[0022] First, a substrate 1 is prepared, and a n - The n-type impurity layer 2, the n-type current spreading layer 3, and the p-type base region 4 are epitaxially grown in this order. Next, the n-type impurity layer 2, the n-type current spreading layer 3, and the p-type base region 4 are epitaxially grown in this order. + Type source region 5 and p + Then, the n-type contact region 6 is formed. + After forming trenches 7 from the surfaces of the p-type source region 5 and p-type base region 4 through the p-type base region 4 to reach the n-type current spreading layer 3, a gate insulating film 8 is formed by deposition of an oxide film or the like. Furthermore, doped polysilicon is formed on the surface of the gate insulating film 8, and then etched back to leave a gate electrode 9 in the trench 7. This forms a trench gate structure. At this time, the doped polysilicon is partially masked and etched back at the outer edge of the cell region. As a result, a gate liner 8a is left, and the tip of the trench gate structure and the gate electrode 9 located at the outermost part of the cell region are connected to the gate liner 8a.

[0023] Then, as shown in FIG. + Type source region 5 and p +An interlayer insulating film 10 is formed so as to cover the trench gate structure in addition to the contact region 6 and to fill the trench 7. The interlayer insulating film 10 may have a single layer structure made of a single type of insulating film, or a laminated structure made of multiple insulating films. When the interlayer insulating film 10 has a laminated structure made of multiple insulating films, the insulating films may be of multiple types, or the same type of film may be laminated multiple times. Here, a case is shown in which the interlayer insulating film 10 is formed of a laminated structure made of two types of insulating films, a first insulating film 101 and a second insulating film 102.

[0024] Then, a resist 20 is placed as a first mask, and after exposure using a first reticle (not shown), development is performed to pattern the resist 20 to form a first opening 20a in the cell region. At this time, the first reticle used has a size such that the first opening 20a corresponds to the size of the contact portion.

[0025] 3B, the interlayer insulating film 10 is etched partway in the thickness direction using the resist 20 as a mask. For example, the interlayer insulating film 10 is etched to a predetermined thickness, in this case, the second insulating film 102 is removed to form the recess 10c. Either dry etching or wet etching may be used for the etching, but wet etching is preferable because it allows the corners of the recess 10c in the interlayer insulating film 10 to be rounded.

[0026] After that, the resist 20 is removed, and then, as shown in FIG. 3C, a resist 21 is arranged again as a second mask, and after exposure is performed using a second reticle (not shown), development is performed to pattern the resist 21 to form a second opening 21a. At this time, as the second reticle different from the first reticle, one is used in which the second opening 21a is one size larger than the contact portion so that the opening area of ​​the second opening 21a is larger than the opening area of ​​the first opening 20a. In other words, by using the second reticle, the opening end of the second opening 21a is made larger than the first opening 20a formed in the resist 20 in the process of FIG. 3A on both sides in the longitudinal direction of the trench gate structure and on both sides in the perpendicular direction.

[0027] Then, as shown in FIG. 3D, the interlayer insulating film 10 is etched using the resist 21 as a mask to form a contact hole 10a in the contact portion. At this time, a recess 10c having dimensions corresponding to the contact portion is formed by dry etching using the resist 20, and the interlayer insulating film 10 is left thick outside the recess 10c, and then the next etching using the resist 21 is performed. Therefore, etching progresses at the position where the recess 10c is formed, and n + Type source region 5 and p + The n-type contact region 6 is exposed, and a contact portion is formed. + Type source region 5 and p + Since the etching can be completed by exposing the mold contact region 6, a self-aligned contact can be achieved, in which the contact portion is defined in a self-aligned manner and the etching can be completed. Outside the recess 10c, the etching is performed with the interlayer insulating film 10 remaining thick, so that when the contact portion is formed, the interlayer insulating film 10 is not completely removed, and a thin portion 10b remains. In addition, in the portion covered with the resist 21, the interlayer insulating film 10 remains thicker than the thin portion 10b.

[0028] Although the subsequent steps are not shown, after removing the resist 21, a film of electrode material is formed and then patterned to form n+ Type source region 5 and p + A source electrode 11 electrically connected to the contact region 6 is formed. Furthermore, a drain electrode 12 is formed by depositing an electrode material on the back surface of the substrate 1. In this manner, the semiconductor device shown in FIG. 1 is completed.

[0029] As described above, in this embodiment, the recess 10c corresponding to the contact portion is first formed in the interlayer insulating film 10, and then the interlayer insulating film 10 is dry-etched over a wider area to form the contact hole 10a. This prevents a sub-trench shape from being formed at the opening end of the contact hole 10a. The reason why such an effect is obtained will be described below.

[0030] First, in the conventional method, as shown in FIG. 4, a contact hole 10a is formed in an interlayer insulating film 10 by one dry etching process using a resist 30 as a mask. When a large-area contact hole 10a is formed by etching, the deposition component, i.e., polymer, supplied from the resist 30 is relatively small compared to when a small-area contact hole is formed. As a result, a protective film made of polymer is not formed sufficiently. Therefore, abnormal etching progresses locally at the opening end of the contact hole 10a, forming a sub-trench shape. In this way, the removal of a part of the interlayer insulating film 10 causes a short circuit or a leak current between the source electrode 11 and the gate electrode 9 on the interlayer insulating film 10.

[0031] In contrast, in this embodiment, a recess 10c corresponding to the contact portion is formed in the interlayer insulating film 10, and then the interlayer insulating film 10 is dry-etched in a wider range to form the contact hole 10a. In this case, dry etching is performed in a state where the interlayer insulating film 10 remains thicker on the outer periphery side of the contact portion than on the inside. Therefore, even if the deposition component supplied from the resist 21 is reduced due to the large area of ​​the contact hole 10a and abnormal etching progresses locally at the opening end of the contact hole 10a, the part where the interlayer insulating film 10 remains thick is etched. Therefore, the formation of a sub-trench shape at the opening end of the contact hole 10a is suppressed, and the interlayer insulating film 10 can be left at the opening end of the contact hole 10a without being scraped off. This makes it possible to suppress the source electrode 11 and the gate electrode 9 on the interlayer insulating film 10 from shorting out and the occurrence of a leak current.

[0032] In particular, if wet etching is used to form the recess 10c using the resist 20 as the first mask, the corners of the recess 10c will be rounded. Therefore, the rounded remaining portions allow the interlayer insulating film 10 to remain thicker at the corners of the recess 10c, and it becomes possible to further suppress the formation of a sub-trench shape in these portions.

[0033] Furthermore, in the case where the interlayer insulating film 10 is composed of multiple types of insulating films as in this embodiment, when only a portion of them is etched using the first mask, the remaining insulating films can be used as etching stoppers to detect the end point of the etching.

[0034] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0035] For example, in the above embodiment, the interlayer insulating film 10 is configured with a multi-layer structure of the first insulating film 101 and the second insulating film 102, but it may have a single-layer structure. In this case, too, the interlayer insulating film 10 is etched halfway in the thickness direction with a first mask, and then the interlayer insulating film 10 is removed with a second mask having a larger opening area, thereby obtaining the same effect as in the above embodiment.

[0036] In the above embodiment, wet etching is taken as an example of a preferred form for etching the interlayer insulating film 10 using the first mask, but dry etching may also be used.

[0037] In the above embodiment, the opening area of ​​the first opening 20a of the resist 21 serving as the second mask is made larger than the opening area of ​​the first opening 20a of the resist 20 serving as the first mask. For example, the second opening 21a is made one size larger than the contact portion. However, the sub-trench shape is particularly formed at both ends of the longitudinal direction of the trench gate structure as circled in FIG. 2. Therefore, it is sufficient that the opening end of the second opening 21a is located outside the cell region more than the opening end of the first opening 20a at least on both sides of the longitudinal direction of the trench gate structure.

[0038] In addition, in each of the above embodiments, an n-channel type trench gate MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type is given as an example of a semiconductor element. However, this is merely an example, and a semiconductor element of another structure, for example, a p-channel type trench gate MOSFET in which the conductivity type of each component is inverted from that of an n-channel type, may be used. Furthermore, the present invention can be applied to an IGBT having a similar structure in addition to a MOSFET. In the case of an IGBT, it is the same as the vertical MOSFET described in the above embodiment, except that the conductivity type of the substrate 1 is changed from n-type to p-type. [Explanation of symbols]

[0039] 1 Board 2n - type impurity layer 3 n-type current distribution layer 4 p-type base region 5n + Type Source Area 6 p + Mold Contact Area 7. Trench 9 Gate electrode 10 Interlayer insulating film 20, 21 Resist

Claims

1. A method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure, comprising the steps of: Preparing a substrate (1) made of a semiconductor of a first or second conductivity type; forming an element portion of a semiconductor element having a trench gate structure in which a second conductivity type base region (4) is formed on the substrate via a first conductivity type drift layer (2, 3), a first conductivity type layer (5) and a contact region (6) of the base region are formed on a surface layer of the base region, and a gate electrode (9) is disposed via a gate insulating film (8) in a trench (7) that penetrates the first conductivity type layer and the base region to reach the drift layer; forming an interlayer insulating film (10) on the trench gate structure, the first conductive type layer, and the contact region; placing a first mask (20) having a first opening (20a) formed therein on the interlayer insulating film in a cell region in which the semiconductor element is to be formed; performing etching using the first mask to remove the interlayer insulating film to a middle of its thickness direction to form a recess (10c); After removing the first mask, a second mask (21) is disposed on at least both sides of the trench gate structure in a longitudinal direction, the second mask (21) having a second opening (21 a) whose opening end is located outside the cell region relative to the opening end of the first opening; forming a contact hole (10a) by dry etching using the second mask, thereby exposing the first conductive type layer and the contact region through the contact hole while leaving the interlayer insulating film in the trench, thereby forming a contact portion; forming a surface electrode (11) in contact with the first conductive type layer and the contact region in the contact portion; A method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure, comprising:

2. 2. The method for manufacturing a semiconductor device having a trench gate structure semiconductor element as described in claim 1, wherein the second mask is positioned such that an opening end of the second opening is located outside the cell region relative to an opening end of the first opening on both sides in a direction perpendicular to the longitudinal direction.

3. In the step of disposing the first mask, a resist (20) constituting the first mask is disposed, and then exposure using a first reticle is performed and development is performed to form the first opening portion; 3. The method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure according to claim 1, wherein the second mask is formed by disposing a resist (21) constituting the second mask, and then performing exposure and development using a second reticle different from the first reticle to form the second opening.

4. The disposing of the first mask and the disposing of the second mask include:

4. The method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure according to claim 3, wherein the first opening and the second opening are formed across the plurality of trench gate structures arranged in a stripe shape in a direction perpendicular to the longitudinal direction.

5. 5. The method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure according to claim 1, wherein the contact portion is formed so that surfaces of the first conductive type layer and the contact region are flush with a surface of the interlayer insulating film remaining in the trench.

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