Semiconductor device and method for manufacturing the same

Abstract

To prevent a decrease in breakdown voltage performance.SOLUTION: A semiconductor device 1001 comprises a semiconductor substrate 1 of a first conductivity type, a resurf layer 2 of a second conductivity type, an embedded layer 3 of the second conductivity type formed in a bottom of a high-side circuit, and a MOSFET which uses the resurf layer 2 as a drift layer. The MOSFET comprises an N-type semiconductor layer 4 of the second conductivity type functioning as the drain layer, a P-type semiconductor layer 6 of the first conductivity type on the low-side circuit side of the N-type semiconductor layer 4, and an N-type semiconductor layer 7 of the second conductivity type formed on a surface of the P-type semiconductor layer 6 and functioning as the source layer. An end part of the N-type semiconductor layer 4 is located closer to the low-side circuit side than an end part of the embedded layer 3. In a plan view, the end part of the embedded layer 3 includes a curved part 30 and the end part of the N-type semiconductor layer 4 includes a curved part 40. The position of a curvature center O' of the curved part 40 is located closer to the high-side circuit than the curved part 30. A curvature of the curved part 40 is smaller than a curvature of the curved part 30.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device including a metal-oxide-semiconductor field-effect-transistor (MOSFET) and a method for manufacturing the semiconductor device. [Background technology]

[0002] Power control ICs (Integrated Circuits), which are mainly used to drive the gates of power semiconductor devices, output drive signals from their output terminals to turn on and off the gates of power switching elements in response to input signals from their input terminals. Power control ICs generally include a low-side circuit that operates with the ground (GND) potential as its reference potential, a high-side circuit that operates with a potential different from the GND potential as its reference potential, and a level shift circuit that transmits signals between the low-side circuit and the high-side circuit.

[0003] In particular, power control ICs require power supplies to drive both the low-side circuit and the high-side circuit, and a known technology involves providing a bootstrap circuit within the IC to generate power for the high-side circuit, and using a MOSFET formed in the RESURF layer as the high-voltage element in the bootstrap circuit. In a semiconductor device with such a RESURF layer, when a high voltage is applied between the source and drain when the MOSFET is turned off, an electric field is generated, and the high breakdown voltage is maintained during the breakdown voltage maintenance period, which is the period until the avalanche begins. This is because the RESURF layer must be fully depleted to maintain the high breakdown voltage. of On the other hand, limiting the impurity concentration in the RESURF layer ToThis prevents the reduction of the on-resistance of the MOSFET formed on the resurf layer. For example, increasing the length of the resurf layer in the direction along the substrate plane of the MOSFET improves the withstand voltage performance of the MOSFET, but causes the on-resistance of the MOSFET to increase. In other words, in a MOSFET formed on a resurf layer, there is a trade-off between improving the withstand voltage performance and reducing the on-resistance.

[0004] Therefore, technology to improve the trade-off between improved withstand voltage performance and reduced on-resistance has been studied. For example, in Patent Document 1, a structure is provided with an N-type buried diffusion layer and an N-type diffusion layer, and the position of the outer end of the N-type diffusion layer (on the low-side circuit side) is closer to the low-side circuit than the position of the outer end of the N-type buried diffusion layer, thereby improving the trade-off between improved withstand voltage performance and reduced on-resistance of a MOSFET formed in a resurf layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-103731 Summary of the Invention [Problem to be solved by the invention]

[0006] According to the semiconductor device of Patent Document 1, the trade-off between improved breakdown voltage performance and reduced on-resistance is improved by extending the N-type diffusion layer toward the low-side circuit side from the N-type buried diffusion layer. On the other hand, in an N-type diffusion layer having a linear region and a corner region in a plan view, if the extension of the N-type diffusion layer in the linear region is also applied to the corner region, there is a problem that the electric field is concentrated in the corner region, degrading the breakdown voltage performance.

[0007] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device capable of preventing a decrease in voltage resistance performance. [Means for solving the problem]

[0008] The semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type, a resurf layer of a second conductivity type formed in a surface layer portion of the semiconductor substrate and separating a high side circuit and a low side circuit, a buried layer of the second conductivity type formed in a bottom portion of the high side circuit between the semiconductor substrate and the resurf layer and having a higher impurity concentration than the resurf layer, and a MOSFET using the resurf layer as a drift layer, the MOSFET including a first semiconductor layer of the second conductivity type formed in the surface layer portion of the resurf layer and having a higher impurity concentration than the resurf layer, a second semiconductor layer of the first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer, and a buried layer of the second conductivity type formed in the surface layer portion of the second semiconductor layer. and a third semiconductor layer of a second conductivity type functioning as a source layer, wherein an end of the first semiconductor layer is located farther from the high side circuit than an end of the buried layer, the end of the buried layer has, in a planar view, a first straight portion, a second straight portion, and a curved portion whose both ends are connected to the first straight portion and the second straight portion, respectively, and the end of the first semiconductor layer has, in a planar view, a third straight portion, a fourth straight portion, and a curved portion whose both ends are connected to the third straight portion and the fourth straight portion, respectively, the position of the center of curvature of the curved portion of the first semiconductor layer is closer to the high side circuit than the curved portion of the buried layer, and the curvature of the curved portion of the first semiconductor layer is smaller than that of the curved portion of the buried layer.

[0009] A semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type, a resurf layer of a second conductivity type formed in a surface layer portion of the semiconductor substrate and separating a high side circuit and a low side circuit, a buried layer of the second conductivity type formed in a bottom portion of the high side circuit between the semiconductor substrate and the resurf layer and having a higher impurity concentration than the resurf layer, and a MOSFET using the resurf layer as a drift layer, the MOSFET including a first semiconductor layer of the second conductivity type formed in the surface layer portion of the resurf layer and having a higher impurity concentration than the resurf layer, the first semiconductor layer functioning as a drain layer, and a second semiconductor layer of the first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in a surface layer portion of the second semiconductor layer and functioning as a source layer, wherein an end of the first semiconductor layer is located farther from the high side circuit than an end of the buried layer, wherein the end of the first semiconductor layer has, in a planar view, a first straight portion, a second straight portion, and a portion whose both ends are connected to the first straight portion and the second straight portion, respectively, a third straight portion connected to the first straight portion at an obtuse angle, and a fourth straight portion connected to the second straight portion at an obtuse angle, and wherein the end of the buried layer has, in a planar view, a fifth straight portion, a sixth straight portion, and a curved portion whose both ends are connected to the fifth straight portion and the sixth straight portion, respectively.

[0010] The semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type, a resurf layer of a second conductivity type formed in a surface layer portion of the semiconductor substrate and separating a high side circuit and a low side circuit, a buried layer of the second conductivity type formed in a bottom portion of the high side circuit between the semiconductor substrate and the resurf layer and having a higher impurity concentration than the resurf layer, and a MOSFET using the resurf layer as a drift layer, the MOSFET including a first semiconductor layer of the second conductivity type formed in a surface layer portion of the resurf layer and having a higher impurity concentration than the resurf layer, the second semiconductor layer of the first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer, and a buried ... second semiconductor layer. and a third semiconductor layer of a second conductivity type functioning as a source layer formed in a portion of the first semiconductor layer, the end of the first semiconductor layer being located farther from the high side circuit than the end of the buried layer, the end of the buried layer having a first straight portion, a second straight portion, and a first curved portion having both ends connected to the first straight portion and the second straight portion, respectively, in a planar view, the end of the first semiconductor layer having a third straight portion, a fourth straight portion, and a second curved portion having both ends connected to the third straight portion and the fourth straight portion, respectively, in a planar view, and the impurity concentration of a portion of the first semiconductor layer including the second curved portion and located inside the second curved portion is lower than the impurity concentration of the first semiconductor layer other than the portion.

[0011] A method for manufacturing a semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type, a resurf layer of a second conductivity type formed in a surface layer portion of the semiconductor substrate and separating a high side circuit and a low side circuit, a buried layer of the second conductivity type formed in a bottom portion of the high side circuit between the semiconductor substrate and the resurf layer and having a higher impurity concentration than the resurf layer, and a MOSFET having the resurf layer as a drift layer, the MOSFET including: a first semiconductor layer of the second conductivity type formed in the surface layer portion of the resurf layer and functioning as a drain layer having a higher impurity concentration than the resurf layer, a second semiconductor layer of the first conductivity type provided on a side away from the high side circuit than the first semiconductor layer, and a third semiconductor layer of the second conductivity type formed in the surface layer portion of the second semiconductor layer and functioning as a source layer, an end of the first semiconductor layer is located farther from the high side circuit than an end of the buried layer, and the end of the buried layer is arranged to have a first straight portion and a second straight portion in a plan view. a first semiconductor layer having a first straight portion and a second curved portion whose both ends are connected to the first straight portion and the second straight portion, respectively, in a planar view, and an end of the first semiconductor layer having a third straight portion and a fourth straight portion and a second curved portion whose both ends are connected to the third straight portion and the fourth straight portion, respectively, in a planar view, the step of forming the first semiconductor layer includes a step of forming a mask material on a substrate, the mask material having a first impurity injection opening, a plurality of second impurity injection openings, and a blocking portion that defines the first impurity injection opening and the plurality of second impurity injection openings, a step of irradiating the substrate with impurities to introduce the impurities into the substrate from the first impurity injection opening and the plurality of second impurity injection openings, a step of removing the mask material from the substrate, and a step of performing a heat treatment on the substrate into which the impurities have been introduced, Effect of the Invention

[0012] According to the present disclosure, it is possible to prevent a decrease in pressure resistance performance. [Brief description of the drawings]

[0013] [Figure 1]1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 5] 13 is a graph showing the relationship between the change in elongation value S of an N-type semiconductor layer and the source-drain breakdown voltage in a semiconductor device of a comparative example and a semiconductor device according to the first embodiment. [Figure 6] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 7] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 13] 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 14] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 18]FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In Figures 1, 6, 9 and 14, the left side is conveniently called "inside" and the right side is conveniently called "outside." Also, in Figures 3, 4, 7, 8, 10-13, and 15-19, the left and lower directions are called "inside" and the right and upper directions are called "outside." As will be understood from the explanation given later, the inside in each figure corresponds to the side approaching a high-side circuit described below, and the outside corresponds to the side away from the high-side circuit.

[0015] Embodiment 1 A semiconductor device 1001 according to the present embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 1001 in this embodiment, and corresponds to the AA cross section in FIG. 2, which will be described later. The semiconductor device 1001 includes a MOSFET formed in a RESURF layer 2. Hereinafter, the MOSFET refers to a lateral N-channel MOSFET formed in the RESURF layer 2. In the following description, the first conductivity type is P-type and the second conductivity type is N-type, and the semiconductor layer of the first conductivity type is a "P-type semiconductor layer" and the semiconductor layer of the second conductivity type is an "N-type semiconductor layer". However, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0016] The semiconductor device 1001 includes a semiconductor layer 100. The semiconductor layer 100 includes a P-type semiconductor substrate 1, a RESURF layer 2 which is an N-type semiconductor layer formed in a surface layer portion of the semiconductor substrate, and a buried layer 3 which is an N-type semiconductor layer having a higher impurity concentration than the RESURF layer 2 and is formed in a bottom portion of a high side circuit described later between the semiconductor substrate 1 and the RESURF layer 2. The semiconductor layer 100 includes an N-type semiconductor layer 4 which is formed in a surface layer portion of the RESURF layer 2 and has a higher impurity concentration than the RESURF layer 2, and an N-type semiconductor layer 5 which is formed in a surface layer portion of the N-type semiconductor layer 4 and has a higher impurity concentration than the N-type semiconductor layer 4. The semiconductor layer 100 includes a P-type semiconductor layer 6 which is formed outside the N-type semiconductor layer 4, an N-type semiconductor layer 7 which is formed in a surface layer portion of the P-type semiconductor layer 6, and a P-type semiconductor layer 8 which is formed in a surface layer portion of the P-type semiconductor layer 6 and has a higher impurity concentration than the P-type semiconductor layer 6. The semiconductor layer 100 further includes a P-type semiconductor layer 16 formed on the surface layer of the semiconductor substrate 1 outside the RESURF layer 2 and in contact with the RESURF layer 2, and a P-type semiconductor layer 17 formed on the surface layer of the P-type semiconductor layer 16 and having a higher impurity concentration than the P-type semiconductor layer 16. The impurity concentrations of the N-type semiconductor layers increase in the order of RESURF layer 2, N-type semiconductor layer 4, buried layer 3, and N-type semiconductor layer 5. The impurity concentration of N-type semiconductor layer 7 is equal to that of N-type semiconductor layer 5.

[0017] The semiconductor device 1001 includes an insulating film 12 provided on a semiconductor layer 100, and a field oxide film 9 provided on the surface of the semiconductor layer 100 between the N-type semiconductor layer 5 and the N-type semiconductor layer 7, on the inside of the N-type semiconductor layer 5, between the P-type semiconductor layer 8 and the P-type semiconductor layer 17, and on the outside of the P-type semiconductor layer 17, so as to be covered by the insulating film 12. The semiconductor device 1001 includes polysilicon 10 provided to cover an inner end of the field oxide film 9 between the N-type semiconductor layer 5 and the N-type semiconductor layer 7, and polysilicon 11 provided to cover an outer end of the field oxide film 9 between the N-type semiconductor layer 5 and the N-type semiconductor layer 7. The semiconductor device 1001 further includes a drain electrode 13 connected to the N-type semiconductor layer 5, a source electrode 14 connected to the N-type semiconductor layer 7 and the P-type semiconductor layer 8, and a reference potential fixing electrode 15 connected to the P-type semiconductor layer 17, each of which is formed to be embedded in the insulating film 12. The polysilicon 10 is embedded in the insulating film 12 and is used as a mask material 56 during implantation to form the N-type semiconductor layer 5. The polysilicon 11 is embedded in the insulating film 12 and is used as the gate electrode of the MOSFET.

[0018] The semiconductor device 1001 constitutes a high-voltage integrated circuit called an HVIC, and includes a high-side circuit and a low-side circuit. Both the high-side circuit and the low-side circuit are constituted by an N-type semiconductor layer and a P-type semiconductor layer, which are not shown in FIG. 1, in the semiconductor layer 100. The high-side circuit includes a digital circuit and an analog circuit, and generates a signal for driving the power semiconductor element and supplies it to the high-side power semiconductor element. The low-side circuit includes a digital circuit and an analog circuit, and generates a signal for driving the power semiconductor element and supplies it to the low-side power semiconductor element. The power semiconductor element is, for example, a MOSFET or an IGBT (Insulated Gate Bipolar Transistor), and is provided outside the semiconductor device 1001.

[0019] The semiconductor substrate 1 and the semiconductor layer 100 are made of semiconductor materials such as silicon (Si) or silicon carbide (SiC). In particular, the semiconductor device 1001 using silicon carbide or the like, which has a wider band gap than silicon, is superior in operation at high voltages and high temperatures compared to the conventional semiconductor device 1001 using silicon.

[0020] The RESURF layer 2 separates the high-side circuit from the low-side circuit, and also serves as the drift layer of the MOSFET.

[0021] The buried layer 3 has the effect of suppressing vertical parasitic operation of elements in the high side circuit, and the effect of preventing the depletion layer of the RESURF layer 2 from extending into the high side circuit when the withstand voltage is maintained, thereby preventing adverse effects on the operation of the elements in the high side circuit.

[0022] The N-type semiconductor layer 4 has a structure in which the position of the outer end of the N-type semiconductor layer 4 is farther from the high side circuit than the position of the outer end of the buried layer 3, and has the effect of reducing the on-resistance of the MOSFET and the effect of preventing field inversion. In addition, the N-type semiconductor layer 4 and the N-type semiconductor layer 5 play the role of the drain layer of the MOSFET, and the N-type semiconductor layer 5 plays the role of electrically connecting the N-type semiconductor layer 4 and the drain electrode 13. In this embodiment, the buried layer 3 and the N-type semiconductor layer 4 are separated from each other, but they may be in contact with each other.

[0023] The P-type semiconductor layer 6 serves as a backgate layer of the MOSFET, the N-type semiconductor layer 7 serves as a source layer of the MOSFET, and the P-type semiconductor layer 8 serves to electrically connect the P-type semiconductor layer 6 to a source electrode 14 which serves as a backgate electrode.

[0024] The P-type semiconductor layer 16 is an outer end portion of the semiconductor device 1001, and serves to fix the potential of the semiconductor substrate 1 to a reference potential. The P-type semiconductor layer 17 serves to electrically connect the P-type semiconductor layer 16 and the electrode 15 for fixing the reference potential.

[0025] FIG. 2 is a plan view showing a part of the semiconductor device 1001 of the present embodiment. 2, the outermost edge is the outer edge of the semiconductor substrate 1, that is, the outer edge of the semiconductor device 1001. The semiconductor device 1001 includes a level shift circuit 50 that transmits a signal between a high-side circuit and a low-side circuit. 2 is a portion that does not overlap with the buried layer 3 in a planar view, and this non-overlapping portion is formed in an annular shape with the level shift circuit 50 sandwiched therebetween. The RESURF layer 2 shown in Fig. 2 is a portion that does not overlap with the buried layer 3, the N-type semiconductor layer 4, and the N-type semiconductor layer 5 in a planar view, and this non-overlapping portion is also formed in an annular shape with the level shift circuit 50 sandwiched therebetween. The outer edge of each of the RESURF layer 2, the N-type semiconductor layer 4, and the buried layer 3 has an approximately rectangular shape with four corners. Each corner has a curved portion whose both ends are connected to two straight portions. These two straight portions correspond to two adjacent sides of the approximately rectangular shape. In each of the RESURF layer 2, the N-type semiconductor layer 4, and the buried layer 3, the region including the curved portion and inside the curved portion is a corner region, and the region including the straight portions of each side and inside the straight portions is a straight region. In FIG. 2, one of the four corner regions is a corner region 51, and the two straight regions adjacent to the corner region 51 are each a straight region 52.

[0026] The high-side circuit is disposed in the buried layer 3 of Fig. 2. The low-side circuit is disposed next to the high-side circuit with the RESURF layer 2 and the level shift circuit 50 in between, specifically, above the RESURF layer 2 and the level shift circuit 50 (not shown). The MOSFET according to this embodiment, which is provided in the RESURF layer 2 (the shaded area in FIG. 2) surrounding the high-side circuit, is an element that constitutes a bootstrap circuit and is used in place of a bootstrap diode. The bootstrap circuit is a circuit that generates the operating power supply for the high-side circuit, and includes a MOSFET and a capacitor connected to the MOSFET.

[0027] FIG. 3 is a plan view showing a part of the corner region 51 and the straight line region 52 of this embodiment. FIG. 3 is an enlarged view of the buried layer 3 and the N-type semiconductor layer 4 in the corner region 51 shown in FIG. The solid lines represent the contours of the ends of the buried layer 3 and the N-type semiconductor layer 4. The end of the N-type semiconductor layer 4 is defined by a straight line portion 41 included in one straight line region 52, a straight line portion 42 included in the other straight line region 52, and a curved portion 40 of a corner region 51 whose both ends are connected to the straight line portion 41 and the straight line portion 42, respectively. The straight line portion 41 and the straight line portion 42 are in a perpendicular relationship with each other along their extensions. The end of the buried layer 3 is also defined by a straight line portion 31 included in one straight line region 52, a straight line portion 32 included in the other straight line region 52, and a curved portion 30 of a corner region 51 whose both ends are connected to the straight line portion 31 and the straight line portion 32, respectively. The straight line portion 31 and the straight line portion 32 are in a perpendicular relationship with each other along their extensions. Therefore, the straight line portion 41 and the straight line portion 31 are parallel, and the straight line portion 42 and the straight line portion 31 are also parallel. The center of curvature O of the curved portion 30 of the buried layer 3 and the center of curvature O' of the curved portion 40 of the N-type semiconductor layer 4 are at different positions and have different curvatures. The distance between the contour line of the buried layer 3 and the contour line of the N-type semiconductor layer 4 does not have the same value in the corner region 51 and the straight region 52.

[0028] In contrast, the dotted line represents the contour of the outer edge of the N-type semiconductor layer 4A as a comparative example. The end of the N-type semiconductor layer 4A is defined by a straight line portion 41A included in one straight line region 52, a straight line portion 42A included in the other straight line region 52, and a curved portion 40A of a corner region 51 whose both ends are connected to the straight line portion 41A and the straight line portion 42A, respectively. The straight line portion 41A and the straight line portion 42A are in a perpendicular relationship with each other along their extension lines. The center of curvature of the curved portion 40A of the N-type semiconductor layer 4A is at the same position as the center of curvature O of the curved portion 30 of the buried layer 3, and the curvatures of the two are different. The distance between the contour of the buried layer 3 and the contour of the N-type semiconductor layer 4A is the same value in the corner region 51 and the straight line region 52. The distance between a point on the contour of buried layer 3 and the contour of N-type semiconductor layer 4 is expressed as the distance from that point to a point on the contour of N-type semiconductor layer 4 where a line perpendicular to the tangent at that point intersects with that point.

[0029] As shown in Figure 3, the curvature of the curved portion 40 of the N-type semiconductor layer 4 is smaller than the curvature of the curved portion 30 of the buried layer 3, and the center of curvature O' of the curved portion 40 of the N-type semiconductor layer 4 is recessed inward compared to the center of curvature O of the curved portion 30 of the buried layer 3. Furthermore, the distance L' between the intersection N' of the curved portion 40 and the straight portion 42 of the N-type semiconductor layer 4 and the intersection M' of the straight line drawn horizontally from the intersection N' and the contour of the buried layer 3 is made larger by an extension value S shown in FIG. 3 than the distance L between the intersection N of the curved portion 40A and the straight portion 42A of the N-type semiconductor layer 4A and the intersection M of the straight line drawn horizontally from the intersection N and the contour of the buried layer 3. Specifically, as shown in FIG. 4, when the intersection A is the intersection between the center of curvature O and the straight line passing through the center of curvature O' and the curved portion 40A of the N-type semiconductor layer 4A, and the intersection B is the intersection between the center of curvature O and the straight line passing through the center of curvature O' and the curved portion 40B of the N-type semiconductor layer 4B, the line segment AB is extended by the extension value S. Here, the extension value S refers to the horizontal distance between the intersection N and the intersection N' of the corner region 51 and the straight region 52 of the N-type semiconductor layer 4. FIG. 3 particularly illustrates a case where the contour of the N-type semiconductor layer 4 contacts the contour of the N-type semiconductor layer 4A at a point on the contour of the N-type semiconductor layer 4 that is the shortest distance from the center of curvature O in the corner region 51. Although the corner region 51 has been described, the shapes of the other three corner regions can be configured in the same manner as in FIG.

[0030] Fig. 4 is a plan view in which an N-type semiconductor layer 4B is superimposed on Fig. 3 as another comparative example. The N-type semiconductor layer 4B is indicated by a dashed line, and the distance L from the buried layer 3 is extended by an extension value S. However, unlike the N-type semiconductor layer 4A, as shown in Fig. 4, the center of curvature is kept at the same position as the curved portion 40A of the N-type semiconductor layer 4A, and the distance L is extended by the extension value S. Therefore, the corner regions 51 of the N-type semiconductor layer 4B are generally extended by the extension value S in the same manner as the linear regions 52 compared to the N-type semiconductor layer 4A.

[0031] The effects of the semiconductor device 1001 in this embodiment will be described. In the semiconductor device 1001 of this embodiment, when the breakdown voltage is maintained, the resurf layer 2 is fully depleted at least in the portion outside the N-type semiconductor layer 4, thereby realizing a high breakdown voltage of the MOSFET, while the buried layer 3 prevents the depletion layer generated at the PN junction between the semiconductor substrate 1 and the resurf layer 2 from extending into the high side circuit and adversely affecting the operation of the elements in the high side circuit. The buried layer 3 also plays a role in suppressing the operation of the vertical parasitic PNP transistor in the high side circuit. In addition, the N-type semiconductor layer 4, which has a higher impurity concentration than the resurf layer 2 that acts as a drift layer, is provided in the surface layer of the resurf layer 2, thereby improving the surface concentration and reducing the on-resistance of the MOSFET.

[0032] Furthermore, since the buried layer 3 and the N-type semiconductor layer 4 are both formed in the RESURF layer 2, the buried layer 3 is not completely depleted when the withstand voltage is maintained. Therefore, the electric field concentration generated in the buried layer 3 is dispersed by the buried layer 3 and the N-type semiconductor layer 4, thereby improving the withstand voltage performance of the MOSFET.

[0033] These effects are also achieved in a semiconductor device having an N-type semiconductor layer 4A according to a comparative example. Suppose that the N-type semiconductor layer 4A is extended to become an N-type semiconductor layer 4B in order to further reduce the on-resistance of the MOSFET. In this case, the N-type semiconductor layer 4B is extended by an extension value S from the N-type semiconductor layer 4A as a whole not only in the linear region 52 but also in the corner region 51. Therefore, although the on-resistance is reduced compared to the case of the N-type semiconductor layer 4A, an electric field is likely to concentrate in the corner region 51 of the N-type semiconductor layer 4B, and the breakdown voltage performance is deteriorated.

[0034] In contrast, also in the present embodiment, the N-type semiconductor layer 4A is extended to become the N-type semiconductor layer 4, that is, in the linear region 52, the distance L of the N-type semiconductor layer 4A increases by the extension value S, thereby reducing the on-resistance of the MOSFET. However, in this embodiment, when the intersection point Z is the intersection point between a straight line passing through the center of curvature O and the center of curvature O' and the curved portion 40 of the N-type semiconductor layer 4, the line segment AZ is smaller than the line segment AB, so that electric field concentration in the corner region 51 of the N-type semiconductor layer 4 is suppressed compared to the N-type semiconductor layer 4B, and a decrease in the withstand voltage performance is prevented. Also, compared to the N-type semiconductor layer 4A, in the N-type semiconductor layer 4 as in this embodiment, the curvature of the N-type semiconductor layer 4 in the corner region 51 is smaller, so that the on-resistance can be reduced and the electric field concentration of the N-type semiconductor layer 4 in the corner region 51 is also suppressed.

[0035] FIG. 5 is a graph showing the relationship between the change in elongation value S of N-type semiconductor layer 4 and the source-drain breakdown voltage in a MOSFET of a comparative example and a MOSFET of this embodiment. In FIG. 5, the solid line graph shows the change in withstand voltage when the extension value S of the N-type semiconductor layer 4B of the comparative example is changed. The dashed line graph shows the change in withstand voltage when the extension value S is changed in a state where the curvature center O' of the curved portion 40 of the N-type semiconductor layer 4 of the present embodiment is displaced 10 μm to the left and downward in FIG. 4. The dotted line graph shows the change in withstand voltage when the extension value S is changed in a state where the curvature center O' of the curved portion 40 of the N-type semiconductor layer 4 of the present embodiment is displaced 20 μm to the left and downward in FIG. 4. The dashed line graph shows the change in withstand voltage when the extension value S is changed in a state where the curvature center O' of the curved portion 40 of the N-type semiconductor layer 4 of the present embodiment is displaced 30 μm to the left and downward in FIG. The evaluation was performed with the distance L in the reference N-type semiconductor layer 4A being 21 μm.

[0036] As shown in FIG. 5, the peak value of the withstand voltage is higher in the MOSFET of the present embodiment than in the MOSFET of the comparative example, and therefore the withstand voltage performance of the MOSFET of the present embodiment is improved compared to the MOSFET of the comparative example. Furthermore, the extension value S when the withstand voltage reaches its peak value is 19 μm in the MOSFET of the comparative example, whereas it is 23 μm, 24 μm, and 25 μm in the three examples of the MOSFET of this embodiment, respectively. Therefore, since the extension value of the N-type semiconductor layer 4 of the MOSFET of this embodiment can be increased compared to the MOSFET of the comparative example, a reduction in the on-resistance can also be expected. In other words, the MOSFET of this embodiment can improve the trade-off between improved voltage resistance and reduced on-resistance, compared to a conventional MOSFET.

[0037] In the present embodiment, the back gate layer of the MOSFET is formed of the P-type semiconductor layer 6, and the source electrode 14 is substituted for the back gate electrode, but as shown in FIG. 6, the back gate layer may be formed of the P-type semiconductor layer 16, and the reference potential fixing electrode 15 may be substituted for the back gate electrode. In this case, the N-type semiconductor layer 18 is provided on the surface layer of the P-type semiconductor layer 16, and the N-type semiconductor layer 19 connected to the source electrode 14 is provided on the surface layer of the N-type semiconductor layer 18. The N-type semiconductor layer 18 and the N-type semiconductor layer 19 become the source layer of the MOSFET. The impurity concentrations of the N-type semiconductor layer 18 and the N-type semiconductor layer 19 are the same as those of the N-type semiconductor layers 4 and 5, respectively.

[0038] Embodiment 2 FIG. 7 is a plan view showing a part of the corner region 51 and the straight line region 52 of this embodiment. In the first embodiment, the curvature of the curved portion 40 of the N-type semiconductor layer 4 is smaller than the curvature of the curved portion 30 of the buried layer 3, and the center of curvature O' of the curved portion 40 of the N-type semiconductor layer 4 is set back inward compared to the center of curvature O of the curved portion 30 of the buried layer 3. However, in the present embodiment, the shape of the corner region 51 of the N-type semiconductor layer 4C is different from that of the first embodiment in that the curved portion 40B of the N-type semiconductor layer 4B is chamfered. The other configurations are the same as those of the first embodiment, and the same reference numerals are used for the same or corresponding parts as those of the first embodiment.

[0039] FIG. 7 is an enlarged view of buried layer 3 and N-type semiconductor layer 4 in corner region 51 shown in FIG. 2 according to the present embodiment. The N-type semiconductor layer 4C indicated by a solid line represents a contour line of a shape obtained by chamfering the curved portion 40B of the N-type semiconductor layer 4B at the intersection point A. The surface formed by chamfering the curved portion 40B of the N-type semiconductor layer 4B is in contact with the contour line of the curved portion 40A of the N-type semiconductor layer 4A, but may be separated therefrom.

[0040] Fig. 8 is a plan view of another example showing a part of the corner region 51 and the straight region 52 of the present embodiment. As shown in Fig. 8, the N-type semiconductor layer 4D has a shape in which the curved portion 40B of the N-type semiconductor layer 4B is chamfered while leaving a part of the contour of the curved portion 40A of the N-type semiconductor layer 4A so that a surface formed by chamfering the curved portion 40B of the N-type semiconductor layer 4B overlaps with the contour of the curved portion 40A of the N-type semiconductor layer 4A.

[0041] 7 and 8 show a shape where the curved portion 40B of the N-type semiconductor layer 4B is chamfered, the curved portion 40 of the N-type semiconductor layer 4 may be chamfered to form the N-type semiconductor layer 4C.

[0042] According to this embodiment, each end of the N-type semiconductor layer is, in plan view, a straight line portion 41C or 41D, and a straight line portion 42C or 42D and both ends are straight line portions 41C or 41D and straight line portions 42C or 42D The straight line portion 43C or 43D is connected to the straight line portion 41C or 41D at an obtuse angle, and the straight line portion 42C or 42D and a straight portion 44C or 44D which is connected at an obtuse angle.

[0043] 7, straight line portion 43C and straight line portion 44C form a single straight line. Straight line portion 41C and straight line portion 42C are perpendicular to each other on their respective extensions, and straight line portion 43C intersects straight line portion 41C at an angle of 135 degrees, and straight line portion 44C intersects straight line portion 42C at an angle of 135 degrees. 8, this portion further has a curved portion 40D whose ends are connected to straight portion 43D and straight portion 44D. Straight portion 41D and straight portion 42D are perpendicular to each other on their respective extension lines, and straight portion 43D intersects with straight portion 41D at an angle of 135 degrees, and straight portion 44D intersects with straight portion 42D at an angle of 135 degrees.

[0044] In the semiconductor device 1002 of the present embodiment, when the N-type semiconductor layer 4A is extended to become the N-type semiconductor layer 4C, the distance L of the N-type semiconductor layer 4A increases by the extension value S, thereby reducing the on-resistance. Furthermore, when the intersection point C is the intersection point between the straight line passing through the center of curvature O and the center of curvature O' and the contour line of the curved portion 40C of the N-type semiconductor layer 4C, the line segment AC is smaller than the line segment AB. Therefore, electric field concentration in the corner region 51 of the N-type semiconductor layer 4 is suppressed compared to the N-type semiconductor layer 4B, and a decrease in the withstand voltage performance is prevented.

[0045] In the N-type semiconductor layer shown in FIGS. 7 and 8, the corner region 51 has been described, but the shapes of the other three corner regions can be configured similarly to those shown in FIG. Moreover, the back gate layer and the source layer of this embodiment may be configured as the P-type semiconductor layer 16 and the N-type semiconductor layers 18 and 19 in FIG.

[0046] In addition, although the straight line portion 43C is directly connected to the straight line portion 41C in Fig. 7, a curved portion may be inserted between the straight line portion 43C and the straight line portion 41C. Therefore, "a straight line portion is connected to another straight line portion at an obtuse angle" also includes a case where a curved portion is connected between two straight lines whose extension lines intersect at an obtuse angle. For example, the same applies to between the straight line portion 44C and the straight line portion 42C in Fig. 7, between the straight line portion 43D and the straight line portion 41D in Fig. 8, and between the straight line portion 44D and the straight line portion 42D.

[0047] Embodiment 3 Fig. 9 is a cross-sectional view showing the structure of semiconductor device 1003 in this embodiment, and corresponds to the AA cross section in this embodiment of Fig. 2. Figs. 10, 11, and 12 are plan views showing parts of corner region 51 and straight region 52 in this embodiment. In the first embodiment, the curvature of the curved portion 40 of the N-type semiconductor layer 4 is smaller than that of the curved portion 30 of the buried layer 3, and the center of curvature O' of the curved portion 40 of the N-type semiconductor layer 4 is set back inward compared to the center of curvature O of the curved portion 30 of the buried layer 3. However, in the present embodiment, the curvature of the curved portion 40 of the N-type semiconductor layer 4 is smaller than that of the curved portion 30 of the buried layer 3, and the center of curvature O' of the curved portion 40 of the N-type semiconductor layer 4 is at the same position as the center of curvature O of the curved portion 30 of the buried layer 3, which is different from the first embodiment, and the impurity concentration of a part of the region including the curved portion 40 of the N-type semiconductor layer 4 is different from the first embodiment. The other configurations are the same as those in the first embodiment, and the same reference numerals are used for the same or corresponding parts as those in the first embodiment.

[0048] 9, the N-type semiconductor layer 4E is composed of two regions E1 and E2 with different impurity concentrations. Region E1 is located at the end of the N-type semiconductor layer 4E, and region E2 is located inside region E1. The impurity concentration of region E1 is lower than that of region E2.

[0049] 10, 11, and 12 are enlarged views of the buried layer 3 and the N-type semiconductor layer 4E in the corner region 51 shown in FIG. 2 in this embodiment, superimposed with a mask material 56 having a first impurity implantation opening 53, a plurality of second impurity implantation openings 54, and a blocking portion 55, which will be described later. The dashed and dotted lines represent the contours of the end of the N-type semiconductor layer 4E. The end of the N-type semiconductor layer 4E is defined by a straight line portion 41E included in one straight line region 52, a straight line portion 42E included in the other straight line region 52, and a curved portion 40E of a corner region 51 whose both ends are connected to the straight line portion 41E and the straight line portion 42E, respectively. The contour of the N-type semiconductor layer 4E almost coincides with the N-type semiconductor layer 4B. Region E1 corresponds to a region that includes the curved portion 40E and is located inside the curved portion 40E. The solid lines represent the contours of the first impurity implantation opening 53 and the second impurity implantation opening 54. A region obtained by subtracting the first impurity implantation opening 53 and the second impurity implantation opening 54 shown by the solid lines from the N-type semiconductor layer 4E shown by the dashed dotted line becomes a blocking portion 55 of the mask material 56. The first impurity implantation opening 53 indicates an opening pattern of a mask material 56 for forming the region E2 of the N-type semiconductor layer 4E, and the shape of the first impurity implantation opening 53 approximately coincides with the shape of the N-type semiconductor layer 4C. The second impurity implantation opening 54 indicates an opening pattern of the mask material 56 for forming the region E1 of the N-type semiconductor layer 4E. The second impurity implantation opening 54 is disposed in a region having a shape substantially equal to an area obtained by subtracting the N-type semiconductor layer 4C from the N-type semiconductor layer 4E. 10 to 12, the boundary between region E1 and region E2 formed by mask material 56 is defined in plan view by straight line portion 43E connected to straight line portion 41E at an obtuse angle and straight line portion 44E connected to straight line portion 42E at an obtuse angle. Straight line portion 43E and straight line portion 44E form a single straight line.

[0050] In FIG. 10, a plurality of trapezoidal second impurity implantation openings 54 having a pattern width W are arranged in an area E1 along a tangent direction of the intersection point A at equal intervals with a pattern interval I. 11, a plurality of square dot-shaped second impurity implantation openings 54 are arranged in the region E1. Although an example in which the shape of the second impurity implantation openings 54 is a square dot shape is shown, any dot shape may be used, such as a chain dot shape or a round dot shape. In FIG. 12, a plurality of rectangular second impurity implantation openings 54 having a pattern width W are arranged in a region E1 along the horizontal direction at equal intervals with a pattern interval I.

[0051] A method for manufacturing the semiconductor device 1003, particularly a process for forming the N-type semiconductor layer 4E, will be described with reference to FIG. 13. First, a mask material 56 having a first impurity implantation opening 53, a plurality of second impurity implantation openings 54, and a blocking portion 55 defining these openings, as shown in any one of FIG. 10 to FIG. 12, is formed on the substrate 57 in a region E1' in the substrate 57 corresponding to the region E1 in the corner region 51 and a region E2' in the substrate 57 corresponding to the region E2. The first impurity implantation opening 53 and the plurality of second impurity implantation openings 54 open the surface of the substrate 57. Next, the substrate 57 is irradiated with impurities. The impurities are introduced into the substrate 57 through the first impurity implantation opening 53 and the plurality of second impurity implantation openings 54, and the introduction of the impurities is blocked by the blocking portion 55. Thereafter, the substrate 57 into which the impurities have been introduced is subjected to a heat treatment. The impurities are diffused in a direction in which the concentration becomes uniform by this heat treatment, and the N-type semiconductor layer 4E shown in FIG. 9 is formed. In region E1', the impurities are partially blocked by mask material 56 having an opening pattern of second impurity implantation opening 54, so that region E1 having an impurity concentration smaller than that of region E2 is formed as shown in Fig. 9. Note that the mask material 56 is removed after the introduction of the impurities and before the heat treatment, but it may be removed after the heat treatment.

[0052] In the semiconductor device 1003 of the present embodiment, when the N-type semiconductor layer 4A is extended to become the N-type semiconductor layer 4E, the distance L of the N-type semiconductor layer 4A increases by the extension value S, thereby reducing the on-resistance. Furthermore, by arranging the second impurity implantation opening 54 in the region E1 and making the impurity concentration lower than that in the region E2, electric field concentration in the corner region 51 of the N-type semiconductor layer 4E is suppressed compared to the N-type semiconductor layer 4B, and a decrease in the breakdown voltage performance is prevented.

[0053] In the present embodiment, an example in which the second impurity implantation opening 54 is disposed in the region E1 has been described. However, as shown in FIG. 14, in the region E1, strip-shaped second impurity implantation openings 54 having a pattern width W may be disposed at equal intervals with a pattern interval I along the curvature of the curved portion 40A of the N-type semiconductor layer 4A. 。 In the N-type semiconductor layer 4E formed using the mask material 56 in FIG. 14, two regions E1 and E2 having different impurity concentrations are also formed. The difference from the N-type semiconductor layer 4E formed using the mask material 56 in each of FIGS. 10 to 12 is the shape of the region E2. The contour of the N-type semiconductor layer 4E in plan view is almost the same as the contour of the N-type semiconductor layer 4B, and the region E1 corresponds to the region obtained by subtracting the N-type semiconductor layer 4D from the N-type semiconductor layer 4B. The region E2 corresponds to the region obtained by subtracting the region E1 from the N-type semiconductor layer 4E. Thus, the boundary between the region E1 and the region E2 is defined in plan view by the straight line portion 43E connected to the straight line portion 41E at an obtuse angle, the straight line portion 44E connected to the straight line portion 42E at an obtuse angle, and the curved portion 45E whose both ends are connected to the straight line portion 43E and the straight line portion 44E, respectively. The impurity concentration is higher in the region E2 than in the region E1.

[0054] In addition, in this embodiment, examples have been shown in which the shape of the second impurity injection opening 54 is a trapezoid, a dot shape, or a rectangle. However, as long as the impurity concentration is higher in region E2 than in region E1, the shape, dimensions, and spacing of the second impurity injection opening 54 are not limited.

[0055] Also, while corner region 51 is described in Figures 10, 11, 12 and 14, the shapes of the other three corner regions can be configured in the same manner as any of Figures 10, 11, 12 and 14. Moreover, the back gate layer and the source layer of this embodiment may be configured as the P-type semiconductor layer 16 and the N-type semiconductor layers 18 and 19 in FIG.

[0056] Embodiment 4 Fig. 15 is a cross-sectional view showing the structure of semiconductor device 1004 in this embodiment, and corresponds to the AA cross section in this embodiment of Fig. 2. Figs. 16, 17, 18, 19, and 20 are plan views showing parts of corner region 51 and straight region 52 in this embodiment. In the third embodiment, the configuration in which the impurity concentration is higher in region E2 than in region E1 has been described, but in the present embodiment, the impurity concentration is higher in region F2 (to be described later) than in region F1 (to be described later), and the impurity concentration in region F1 has a concentration gradient, which is different from the third embodiment. The rest of the configuration is the same as in the third embodiment, and the same reference numerals are used to designate the same or corresponding parts as in the third embodiment.

[0057] 15, the N-type semiconductor layer 4F is composed of two regions F1 and F2 with different impurity concentrations. Region F1 is located at the end of the N-type semiconductor layer 4F, and region F2 is located inside region F1. The impurity concentration of region F1 is lower than that of region F2.

[0058] FIG. 16 is an enlarged view of the buried layer 3 and the N-type semiconductor layer 4F in the corner region 51 shown in FIG. 2 in this embodiment, superimposed on a mask material 56 having a first impurity implantation opening 53, a plurality of second impurity implantation openings 54, and a blocking portion 55. The dashed and dotted line represents the contour of the N-type semiconductor layer 4F. The end of the N-type semiconductor layer 4F is defined by a straight line portion 41F included in one straight line region 52, a straight line portion 42F included in the other straight line region 52, and a curved portion 40F of a corner region 51 whose both ends are connected to the straight line portion 41F and the straight line portion 42F, respectively. The contour of the N-type semiconductor layer 4F almost coincides with the N-type semiconductor layer 4B. Region F1 corresponds to a region including the curved portion 40F and located inside the curved portion 40F. The solid lines represent the contours of the first impurity implantation opening 53 and the second impurity implantation opening 54. A region obtained by subtracting the first impurity implantation opening 53 and the second impurity implantation opening 54 shown by the solid lines from the N-type semiconductor layer 4F shown by the dashed dotted line becomes a blocking portion 55 of the mask material 56. The first impurity implantation opening 53 indicates an opening pattern of the mask material 56 for forming the region F2 of the N-type semiconductor layer 4F, and the shape of the first impurity implantation opening 53 approximately coincides with the shape of the N-type semiconductor layer 4C. The second impurity injection pitch 54 indicates the opening pattern of the mask material 56 for forming the region F1 of the N-type semiconductor layer 4F. The second impurity injection pitch 54 is arranged in a region having a shape that substantially coincides with the region obtained by subtracting the N-type semiconductor layer 4C from the N-type semiconductor layer 4F. The boundary between the region F1 and the region F2 formed by the mask material 56 in FIG. 16 is defined, in a plan view, by a straight line portion 43F that is obtusely connected to the straight line portion 41F and a straight line portion 44F that is obtusely connected to the straight line portion 42F. The straight line portion 43F and the straight line portion 44F form a single straight line.

[0059] FIG. 16 shows that the second impurity injection pitch 54 is arranged such that as it approaches the portion corresponding to the curved portion 40F, that is, as the second impurity injection pitch 54 is arranged outside the semiconductor device 1004, the pattern width W becomes successively narrower such that W1>W2···>Wn, and the pattern pitch I becomes successively larger such that I1<I2···<In.

[0060] In the semiconductor device 1004 of the present embodiment, when the N-type semiconductor layer 4A is extended to become the N-type semiconductor layer 4F, the distance L of the N-type semiconductor layer 4A increases by the extension value S, thereby reducing the on-resistance. Further, by arranging the second impurity injection pitch 54 in the region F1, making the impurity concentration lower than that in the region F2, and making the impurity concentration in the region F1 lower toward the outside of the semiconductor device 1004, compared with the N-type semiconductor layer 4B, the electric field concentration in the corner region 51 of the N-type semiconductor layer 4F is suppressed, preventing a decrease in breakdown voltage performance.

[0061] Note that although an example has been shown in which as the second impurity injection pitch 54 is arranged outside the semiconductor device 1004 in the present embodiment, the pattern width W becomes successively narrower such that W1>W2···>Wn, and the pattern pitch I becomes successively larger such that I1<I2···<In, it is not necessary to change both the pattern width W and the pattern pitch I as the second impurity injection pitch 54 is arranged outside the semiconductor device 1004, and either the pattern width W or the pattern pitch I may be constant.

[0062] The N-type semiconductor layer 4F shown in each of FIGS. 17 and 18 is composed of two regions F1 and F2 with different impurity concentrations. The contour line of the N-type semiconductor layer 4F in plan view substantially coincides with the contour line of the N-type semiconductor layer 4B, and the region F1 corresponds to the region obtained by subtracting the N-type semiconductor layer 4D from the N-type semiconductor layer 4B. The region F2 corresponds to the region obtained by subtracting the region F1 from the N-type semiconductor layer 4F. Therefore, the boundary between the region F1 and the region F2 is, in plan view, a straight line portion 43F that is obtusely connected to the straight line portion 41F, a straight line portion 44F that is obtusely connected to the straight line portion 42F, and a curved portion 45F whose both ends are connected to the straight line portion 43F and the straight line portion 44F respectively. The impurity concentration is higher in the region F2 than in the region F1, and further, the impurity concentration in the region F1 decreases toward the outside of the semiconductor device 1004. In order to form the N-type semiconductor layer 4F, as shown in FIGS. 17 and 18, as the second impurity injection aperture 54 is arranged outside the semiconductor device 1004 in the region F1 corresponding to the region obtained by subtracting the N-type semiconductor layer 4D from the N-type semiconductor layer 4B, the pattern width W may be arranged to be successively narrower so that W1>W2···>Wn, and the pattern interval I may be arranged to be successively larger so that I1<I2···<In. In FIG. 17, strip-shaped second impurity injection apertures 54 are arranged side by side, and in FIG. 18, dot-shaped second impurity injection apertures 54 are arranged radially.

[0063] Also, in the present embodiment, an example in which the pattern width W and the pattern interval I of the second impurity injection aperture 54 are gradually changed as the second impurity injection aperture 54 is arranged outside the semiconductor device 1004 so that the impurity concentration in the region F1 decreases toward the outside of the semiconductor device 1004 has been shown. However, as shown in FIGS. 19 and 20, it is also possible to simply arrange the second impurity injection apertures 54 radially while keeping the pattern width W constant. FIG. 19 shows a rectangular second impurity injection aperture 54, and FIG. 20 shows a dot-shaped second impurity injection aperture 54. In both FIGS. 19 and 20, the interval between adjacent second impurity injection apertures 54 along the direction of the curved portion becomes larger as the radial direction of the radial shape.

[0064] Although the corner region 51 has been described with reference to FIGS. 16 to 20, the shapes of the other three corner regions can be configured as shown in any one of FIGS. Moreover, the back gate layer and the source layer of this embodiment may be configured as the P-type semiconductor layer 16 and the N-type semiconductor layers 18 and 19 in FIG.

[0065] In addition to the above, the embodiments may be freely combined, any of the components of the embodiments may be modified, or any of the components of the embodiments may be omitted. [Explanation of symbols]

[0066] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 resurf layer, 3 buried layer, 4 N-type semiconductor layer, 5 N-type semiconductor layer, 6 P-type semiconductor layer, 7 N-type semiconductor layer, 8 P-type semiconductor layer, 9 field oxide film, 10 polysilicon, 11 polysilicon, 12 insulating film, 13 drain electrode, 14 source electrode, 15 reference potential fixing electrode, 30, 40 curved portion, 31, 32, 41, 42 straight portion, 50 level shift circuit, 51 corner region, 52 straight region, 53 first impurity implantation opening, 54 second impurity implantation opening, 55 blocking portion, 56 mask material, 100 semiconductor layer, 1001, 1002, 1003, 1004 semiconductor device

Claims

1. a semiconductor substrate of a first conductivity type; a second conductivity type RESURF layer formed on a surface layer of the semiconductor substrate and separating a high side circuit from a low side circuit; a buried layer of a second conductivity type formed at a bottom of the high side circuit between the semiconductor substrate and the RESURF layer and having an impurity concentration higher than that of the RESURF layer; a MOSFET having the RESURF layer as a drift layer; Equipped with The MOSFET is a first semiconductor layer of a second conductivity type that is formed on a surface portion of the RESURF layer, has an impurity concentration higher than that of the RESURF layer, and functions as a drain layer; a second semiconductor layer of a first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer; a third semiconductor layer of a second conductivity type formed on a surface layer portion of the second semiconductor layer and functioning as a source layer; Equipped with an end of the first semiconductor layer is located farther from the high-side circuit than an end of the buried layer; the end of the buried layer has, in a plan view, a first straight portion, a second straight portion, and a curved portion having both ends connected to the first straight portion and the second straight portion, respectively; the end portion of the first semiconductor layer has, in a plan view, a third straight portion, a fourth straight portion, and a curved portion having both ends connected to the third straight portion and the fourth straight portion, respectively; a position of a center of curvature of the curved portion of the first semiconductor layer is closer to the high-side circuit than the curved portion of the buried layer; A semiconductor device, comprising: a first semiconductor layer having a curved portion; a first conductive layer formed on the first semiconductor layer; a second conductive layer formed on the second semiconductor layer;

2. a semiconductor substrate of a first conductivity type; a second conductivity type RESURF layer formed on a surface layer of the semiconductor substrate and separating a high side circuit from a low side circuit; a buried layer of a second conductivity type, the buried layer having a higher impurity concentration than the resurf layer, formed at a bottom of the high side circuit between the semiconductor substrate and the resurf layer, and a MOSFET having the resurf layer as a drift layer; Equipped with The MOSFET is a first semiconductor layer of a second conductivity type that is formed on a surface portion of the RESURF layer, has an impurity concentration higher than that of the RESURF layer, and functions as a drain layer; a second semiconductor layer of a first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer; a third semiconductor layer of a second conductivity type formed on a surface layer portion of the second semiconductor layer and functioning as a source layer; Equipped with an end of the first semiconductor layer is located farther from the high-side circuit than an end of the buried layer; the end portion of the first semiconductor layer has, in a plan view, a first straight line portion, a second straight line portion, and a portion having both ends connected to the first straight line portion and the second straight line portion, the portion having a third straight line portion connected to the first straight line portion at an obtuse angle, and a fourth straight line portion connected to the second straight line portion at an obtuse angle; A semiconductor device characterized in that the end of the buried layer has, when viewed in a planar view, a fifth straight portion, a sixth straight portion, and curved portions whose both ends are connected to the fifth straight portion and the sixth straight portion, respectively.

3. 3. The semiconductor device according to claim 2, wherein the third straight portion and the fourth straight portion form one straight line.

4. 3. The semiconductor device according to claim 2, wherein the portion has curved portions, both ends of which are connected to the third straight portion and the fourth straight portion, respectively.

5. a semiconductor substrate of a first conductivity type; a second conductivity type RESURF layer formed on a surface layer of the semiconductor substrate and separating a high side circuit from a low side circuit; a buried layer of a second conductivity type, the buried layer having a higher impurity concentration than the resurf layer, formed at a bottom of the high side circuit between the semiconductor substrate and the resurf layer, and a MOSFET having the resurf layer as a drift layer; Equipped with The MOSFET is a first semiconductor layer of a second conductivity type that is formed on a surface portion of the RESURF layer, has an impurity concentration higher than that of the RESURF layer, and functions as a drain layer; a second semiconductor layer of a first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer; a third semiconductor layer of a second conductivity type formed on a surface layer portion of the second semiconductor layer and functioning as a source layer; Equipped with an end of the first semiconductor layer is located farther from the high-side circuit than an end of the buried layer; the end of the buried layer has, in a plan view, a first straight portion, a second straight portion, and a first curved portion whose both ends are connected to the first straight portion and the second straight portion, respectively; the end portion of the first semiconductor layer has, in a plan view, a third straight portion, a fourth straight portion, and a second curved portion whose both ends are connected to the third straight portion and the fourth straight portion, respectively; a first semiconductor layer having a first bend portion and a second bend portion, the first semiconductor layer having a first impurity concentration lower than the first impurity concentration of the first semiconductor layer other than the first bend portion;

6. The semiconductor device according to claim 5, characterized in that the part is an area defined by the second curved portion and a portion whose both ends are connected to both ends of the second curved portion, and the part has a fifth straight portion connected to the third straight portion at an obtuse angle, and a sixth straight portion connected to the fourth straight portion at an obtuse angle.

7. 7. The semiconductor device according to claim 6, wherein the impurity concentration of the portion decreases toward the second curved portion.

8. 8. The semiconductor device according to claim 6, wherein the fifth straight portion and the sixth straight portion form one straight line.

9. 8. The semiconductor device according to claim 6, wherein the portion has curved portions, both ends of which are connected to the fifth straight portion and the sixth straight portion, respectively.

10. 10. The semiconductor device according to claim 1, wherein the second semiconductor layer is formed on a surface layer of the RESURF layer.

11. 10. The semiconductor device according to claim 1, wherein the second semiconductor layer is formed in a surface layer portion of the semiconductor substrate so as to be in contact with the RESURF layer.

12. 12. The semiconductor device according to claim 1, further comprising: a fourth semiconductor layer of the second conductivity type that is formed in a surface layer portion of the first semiconductor layer, has an impurity concentration higher than that of the first semiconductor layer, and functions as a drain layer.

13. 13. The semiconductor device according to claim 1, wherein the MOSFET is an element constituting a bootstrap circuit that supplies power to the high-side circuit.

14. a semiconductor substrate of a first conductivity type; a second conductivity type RESURF layer formed on a surface layer of the semiconductor substrate and separating a high side circuit from a low side circuit; a buried layer of a second conductivity type, the buried layer having a higher impurity concentration than the resurf layer, formed at a bottom of the high side circuit between the semiconductor substrate and the resurf layer, and a MOSFET having the resurf layer as a drift layer; Equipped with The MOSFET is a first semiconductor layer of a second conductivity type that is formed on a surface portion of the RESURF layer, has an impurity concentration higher than that of the RESURF layer, and functions as a drain layer; a second semiconductor layer of a first conductivity type provided on a side farther from the high side circuit than the first semiconductor layer; a third semiconductor layer of a second conductivity type formed on a surface layer portion of the second semiconductor layer and functioning as a source layer; Equipped with an end of the first semiconductor layer is located farther from the high-side circuit than an end of the buried layer; the end of the buried layer has, in a plan view, a first straight portion, a second straight portion, and a first curved portion whose both ends are connected to the first straight portion and the second straight portion, respectively; a manufacturing method of a semiconductor device, the end portion of the first semiconductor layer having, in a plan view, a third straight portion, a fourth straight portion, and a second curved portion having both ends connected to the third straight portion and the fourth straight portion, The step of forming the first semiconductor layer includes: forming a mask material on a substrate, the mask material having a first impurity implantation opening, a plurality of second impurity implantation openings, and a blocking portion that defines the first impurity implantation opening and the plurality of second impurity implantation openings; irradiating the substrate with impurities and introducing the impurities into the substrate through the first impurity injection opening and the plurality of second impurity injection openings; removing the mask material from the substrate; A step of subjecting the substrate into which the impurities have been introduced to a heat treatment; Equipped with a second impurity implantation opening is provided in a region of the mask material that corresponds to a portion of the first semiconductor layer that is inside the second curved portion when viewed in a plan view, the second impurity implantation opening being provided in a region of the mask material that includes the second curved portion and corresponds to a portion of the first semiconductor layer that is inside the second curved portion.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the mask material is provided so that the width of each of the plurality of second impurity implantation openings becomes smaller toward a portion corresponding to the second curved portion.

16. A method for manufacturing a semiconductor device as described in claim 14 or claim 15, characterized in that the mask material is provided so that the spacing between adjacent impurity injection openings among the plurality of second impurity injection openings becomes larger toward the portion corresponding to the second curved portion.

Images