Power distributor

Abstract

A power divider (100) comprises a common terminal (T0), a ground terminal (GND), a first terminal (T1), a second terminal (T2), a first circuit (CR1) connected to the common terminal, and a second circuit (CR2). The second circuit branches a signal from the first circuit to the first terminal and to the second terminal. The first circuit includes inductors (L11, L12) connected in parallel between the common terminal and a branch point (BP1), and capacitors (C1, C2) connected between respective ends of the inductor (L11) and the ground terminal. The second circuit includes inductors (L21, L22), capacitors (C21, C22), and a resistance element (R1). The inductor (L21) is connected between the branch point and the first terminal. The inductor (L22) is connected between the branch point and the second terminal. The capacitor (C21) is connected between the first terminal and the ground terminal. The capacitor (C22) is connected between the second terminal and the ground terminal. The resistance element is connected between the first terminal and the second terminal.

Description

[Technical field]

[0001] The present disclosure relates to a power splitter, and more particularly to a technique for improving performance in a power splitter. [Background technology]

[0002] WO 2020 / 045576 (Patent Document 1) discloses a power distribution / coupling component for distributing or coupling high-frequency power. The power distribution / coupling component disclosed in WO 2020 / 045576 (Patent Document 1) describes a configuration that improves isolation characteristics by arranging an inductor connected between a common terminal and a connection point that branches a path to a first terminal and a second terminal, and capacitors connected between the common terminal and the connection point and ground, respectively. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 045576 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned power splitter is used, for example, in mobile terminals such as mobile phones or smartphones, and mobile communication base stations. In recent years, array antennas using multiple radiating elements are sometimes adopted as antennas used in these communication devices. In this case, a power splitter such as the above is required to branch a high-frequency signal into multiple paths and supply it to each radiating element.

[0005] In such a power splitter, it is desired to further widen the bandwidth of the characteristics, and in order to achieve this, it is necessary to suppress the characteristic variations between the signals after branching.

[0006] The present disclosure has been made to solve such problems, and has as its object to suppress characteristic fluctuations of a signal after branching in a power divider, thereby achieving a broadband. [Means for solving the problem]

[0007] The power splitter according to the present disclosure includes a common terminal, a ground terminal, a first terminal, a second terminal, a first circuit, and a second circuit. The first circuit is connected to the common terminal. The second circuit is connected to the first terminal and the second terminal, and transmits a signal that has passed through the first circuit to the first terminal and the second terminal by branching at a branch point. The first circuit includes a first inductor and a second inductor connected in parallel between the common terminal and the branch point, a first capacitor connected between the common terminal and the ground terminal, and a second capacitor connected between the branch point and the ground terminal. The second circuit includes a third inductor and a fourth inductor, a third capacitor and a fourth capacitor, and a resistive element. The third inductor has one end connected to the branch point and is disposed on a path from the branch point to the first terminal. The fourth inductor has one end connected to the branch point and is disposed on a path from the branch point to the second terminal. The third capacitor is connected between the other end of the third inductor and the ground terminal. The fourth capacitor is connected between the other end of the fourth inductor and the ground terminal. The resistive element is connected between the other end of the third inductor and the other end of the fourth inductor. Effect of the Invention

[0008] According to the power splitter of the present disclosure, the inductor disposed between the common terminal and the branch point is composed of two inductors connected in parallel. This allows the path from the common terminal to the first terminal and the path from the common terminal to the second terminal to have a symmetrical structure. This makes it possible to suppress the characteristic fluctuation of the signal after branching and to achieve a wide bandwidth. [Brief description of the drawings]

[0009] [Figure 1] 1 is an equivalent circuit diagram of a power splitter according to a first embodiment. [Diagram 2] 1 is an external perspective view of a power splitter according to a first embodiment. [Diagram 3] FIG. 3 is an exploded perspective view of the power splitter of FIG. 2. [Figure 4] 10A and 10B are diagrams for explaining the arrangement of inductors in a laminate; [Diagram 5] FIG. 11 is an equivalent circuit diagram of a power splitter of a comparative example. [Figure 6] 11A and 11B are diagrams for explaining the arrangement of inductors in a comparative example. [Figure 7] 5 is a diagram showing characteristics of the power splitters according to the first embodiment and the comparative example. FIG. [Figure 8] FIG. 11 is an equivalent circuit diagram of a power splitter according to a second embodiment. [Figure 9] FIG. 11 is an external perspective view of a power splitter according to a second embodiment. [Figure 10] FIG. 10 is an exploded perspective view of the power splitter of FIG. [Figure 11] 10A and 10B are diagrams for explaining the arrangement of inductors in a laminate; [Figure 12] FIG. 11 is a first diagram showing characteristics of a power divider according to the second embodiment. [Figure 13] FIG. 2 is a second diagram showing the characteristics of the power divider according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0011] [Embodiment 1] (Circuit configuration of power distributor) 1 is an equivalent circuit diagram of a power splitter 100 according to embodiment 1. The power splitter 100 is used in cases where a common high-frequency signal is distributed to a plurality of radiating elements, such as an array antenna in which a plurality of radiating elements are arranged.

[0012] 1, the power splitter 100 includes a common terminal T0, a first terminal T1, a second terminal T2, a first circuit CR1, and a second circuit CR2. The first circuit CR1 is connected to the common terminal T0. The second circuit CR2 is connected between the first circuit CR1 and the first and second terminals T1 and T2. The second circuit CR2 branches a signal that is supplied to the common terminal T0 and passes through the first circuit CR1, and transmits the branched signal to the first terminal T1 and the second terminal T2.

[0013] The first circuit CR1 includes inductors L11 and L12 and capacitors C1 and C2. The inductors L11 and L12 are connected in parallel between the common terminal T0 and a branch point BP1 in the second circuit CR2. The capacitor C1 is connected between the common terminal T0 and the ground terminal GND. The capacitor C2 is connected between the branch point BP1 and the ground terminal GND. That is, the first circuit CR1 functions as a π-type low-pass filter.

[0014] The second circuit CR2 includes inductors L21 and L22, capacitors C21 and C22, and a resistor R1. The inductor L21 is connected between a branch point BP1 to which the first circuit CR1 is connected and the first terminal T1. The inductor L22 is connected between the branch point BP1 and the second terminal T2.

[0015] The capacitor C21 is connected between the first terminal T1 and the ground terminal GND. The capacitor C22 is connected between the second terminal T2 and the ground terminal GND. The resistor R1 is connected between the first terminal T1 and the second terminal T2.

[0016] In the second circuit CR2, the inductance value of the inductor L21 is set to the same value as the inductance value of the inductor L22. Also, the capacitance value of the capacitor C21 is set to the same value as the capacitance value of the capacitor C22. That is, the impedance value of the path from the branch point BP1 to the first terminal T1 is the same value as the impedance value of the path from the branch point BP1 to the second terminal T2. As a result, the power supplied to the common terminal T0 is equally divided by the second circuit CR2 and output from the first terminal T1 and the second terminal T2.

[0017] In the above circuit, at least one attenuation pole is formed in the isolation characteristic of the path from the first terminal T1 to the second terminal T2 by the first circuit CR1, and one attenuation pole is formed in the isolation characteristic by the resistive element R1 included in the second circuit CR2.

[0018] (Structure of power distributor) Next, a detailed structure of the power splitter 100 will be described with reference to Figures 2 and 3. Figure 2 is an external perspective view of the power splitter 100, and Figure 3 is an exploded perspective view showing an example of the layered structure of the power splitter 100.

[0019] 2 and 3, the power splitter 100 includes a rectangular or substantially rectangular parallelepiped laminate 110 in which a plurality of dielectric layers LY1 to LY9 are laminated in a lamination direction, and a resistive element R1 provided outside the laminate 110. The dielectric layers LY1 to LY9 are formed of ceramics such as low temperature co-fired ceramics (LTCC) or resin. In the laminate 110, the inductors and capacitors in the first circuit CR1 and the second circuit CR2 in FIG. 1 are configured by a plurality of electrodes provided in each dielectric layer and a plurality of vias provided between the dielectric layers. In this specification, the term "via" refers to a conductor provided in a dielectric layer to connect electrodes provided in different dielectric layers. The vias are formed by, for example, conductive paste, plating, and / or metal pins.

[0020] In the following description, the stacking direction of the dielectric layers LY1 to LY9 in the laminate 110 is referred to as the "Z-axis direction", the direction perpendicular to the Z-axis direction and along the long side of the laminate 110 is referred to as the "X-axis direction", and the direction along the short side of the laminate 110 is referred to as the "Y-axis direction". In the following description, the positive direction of the Z-axis in each drawing may be referred to as the upper side, and the negative direction as the lower side.

[0021] The laminate 110 has an upper surface 111, a lower surface 112, and side surfaces 113 to 116. The upper surface 111 is the surface of the laminate 110 in the positive direction of the Z axis, and the lower surface 112 is the surface of the laminate 110 in the negative direction of the Z axis. The side surface 113 is the surface of the laminate 110 in the positive direction of the X axis, and the side surface 114 is the surface of the laminate 110 in the negative direction of the X axis. The side surface 115 is the surface of the laminate 110 in the positive direction of the Y axis, and the side surface 116 is the surface of the laminate 110 in the negative direction of the Y axis.

[0022] A direction mark DM for identifying the direction of the power splitter 100 is arranged on the upper surface 111 (dielectric layer LY1) of the laminate 110. A plurality of external terminals (a common terminal T0, a first terminal T1, a second terminal T2, and a ground terminal GND) for connecting the laminate 110 to other devices are arranged on the side surfaces 115 and 116 of the laminate 110. Each external terminal has a substantially C-shape and extends from the upper surface 111 through the side surface 115 to the lower surface 112, or from the upper surface 111 through the side surface 116 to the lower surface 112. The first terminal T1, the second terminal T2, and the ground terminal GND are arranged on the side surface 115 side. The common terminal T0 and the ground terminal GND are arranged on the side surface 116 side. The resistor element R1 is connected to the first terminal T1 and the second terminal T2.

[0023] The common terminal T0 is connected to a capacitor electrode PC1 arranged on the dielectric layer LY9 on the lower surface 112 side. When the laminate 110 is viewed in a plan view from the stacking direction (Z-axis direction), the capacitor electrode PC1 at least partially overlaps with a substantially rectangular ground electrode PG1 arranged on the dielectric layer LY8. The ground electrode PG1 is connected to the ground terminal GND. The capacitor electrode PC1 and the ground electrode PG1 form a capacitor C1 in the first circuit CR1 in FIG. 1.

[0024] The common terminal T0 is also connected to a plate electrode P10 disposed on the dielectric layer LY2. The plate electrode P10 is a strip-shaped electrode extending in the X-axis direction, and is connected to the common terminal T0 at its center. A via V11 is connected to one end of the plate electrode P10, and a via V15 is connected to the other end of the plate electrode P10.

[0025] The via V11 is connected to one end of a band-shaped plate electrode PL11 arranged on the dielectric layer LY3. The plate electrode PL11 has a substantially U- or C-shape. The via V12 is connected to the other end of the plate electrode PL11. The via V12 is connected to one end of a band-shaped plate electrode PL12 arranged on the dielectric layer LY4. The plate electrode PL12 has a substantially U- or C-shape. The via V13 is connected to the other end of the plate electrode PL12. The via V13 is connected to one end of a band-shaped plate electrode PL13 arranged on the dielectric layer LY5. The plate electrode PL13 has a substantially U- or C-shape. The via V14 is connected to the other end of the plate electrode PL13.

[0026] The plate electrodes PL11, PL12, and PL13 are arranged such that most of their paths overlap each other when the laminate 110 is viewed from above in the stacking direction. That is, the plate electrodes PL11, PL12, and PL13 and the vias V11, V12, V13, and V14 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L11 in FIG. 1.

[0027] The via V15 is connected to one end of a band-shaped plate electrode PL15 arranged on the dielectric layer LY3. The plate electrode PL15 has a substantially U- or C-shape. The via V16 is connected to the other end of the plate electrode PL15. The via V16 is connected to one end of a band-shaped plate electrode PL16 arranged on the dielectric layer LY4. The plate electrode PL16 has a substantially U- or C-shape. The via V17 is connected to the other end of the plate electrode PL16. The via V17 is connected to one end of a band-shaped plate electrode PL17 arranged on the dielectric layer LY5. The plate electrode PL17 has a substantially U- or C-shape. The via V18 is connected to the other end of the plate electrode PL17.

[0028] The plate electrodes PL15, PL16, and PL17 are arranged such that most of their paths overlap each other when the laminate 110 is viewed from above in the stacking direction. That is, the plate electrodes PL15, PL16, and PL17 and the vias V15, V16, V17, and V18 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L12 in FIG. 1.

[0029] The via V14 constituting the inductor L11 and the via V18 constituting the inductor L12 are connected to a plate electrode P11 arranged on the dielectric layer LY6. The plate electrode P11 is a strip-shaped electrode extending in the X-axis direction, with one end of the plate electrode P11 connected to the via V14 and the other end of the plate electrode P11 connected to the via V18. The plate electrode P11 is connected at its center to a plate electrode P12 extending parallel to the plate electrode P11.

[0030] A via V19 is connected to a connection portion P13 that connects the plate electrodes P11 and P12. The via V19 is connected to a plate electrode PC2 disposed on the dielectric layer LY7. The plate electrode PC2 has a rectangular shape, and at least a portion of the plate electrode PC2 overlaps with the ground electrode PG1 of the dielectric layer LY8 when the laminate 110 is viewed from above in the stacking direction. The plate electrode PC2 and the ground electrode PG1 form a capacitor C2 in the first circuit CR1 in FIG. 1.

[0031] The plate electrode P12 is a band-shaped electrode extending in the X-axis direction, with one end of the plate electrode P12 connected to the plate electrode PL21 and the other end of the plate electrode P12 connected to the plate electrode PL25.

[0032] The plate electrode PL21 is a belt-shaped electrode having a substantially U- or C-shape. A via V21 is connected to an end of the plate electrode PL21 opposite to the end connected to the plate electrode P12. The via V21 is connected to one end of a belt-shaped plate electrode PL22 arranged on the dielectric layer LY5. The plate electrode PL22 has a substantially U- or C-shape. The via V22 is connected to the other end of the plate electrode PL22. The via V22 is connected to one end of a belt-shaped plate electrode PL23 arranged on the dielectric layer LY4. The plate electrode PL23 has a substantially U- or C-shape. The via V23 is connected to the other end of the plate electrode PL23. The via V23 is connected to one end of a belt-shaped plate electrode PL24 arranged on the dielectric layer LY3. The plate electrode PL24 has a substantially U- or C-shape. The other end of the plate electrode PL24 is connected to the first terminal T1 disposed on the side surface 115.

[0033] The plate electrodes PL21, PL22, PL23, and PL24 are arranged such that most of their paths overlap each other when the laminate 110 is viewed in a plan view from the stacking direction. That is, the plate electrodes PL21, PL22, PL23, and PL24 and the vias V21, V22, and V23 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L21 in FIG. 1.

[0034] The first terminal T1 is connected to a flat-plate-shaped capacitor electrode PC3 disposed on the dielectric layer LY9. When the laminate 110 is viewed from above in the lamination direction, the capacitor electrode PC3 at least partially overlaps with the ground electrode PG1 of the dielectric layer LY8. The flat-plate electrode PC3 and the ground electrode PG1 form a capacitor C21 in the second circuit CR2 in FIG.

[0035] The plate electrode PL25 on the dielectric layer LY6 is a band-shaped electrode having a substantially U- or C-shape. A via V25 is connected to an end of the plate electrode PL25 opposite to the end connected to the plate electrode P12. The via V25 is connected to one end of a band-shaped plate electrode PL26 arranged on the dielectric layer LY5. The plate electrode PL26 has a substantially U- or C-shape. The via V26 is connected to the other end of the plate electrode PL26. The via V26 is connected to one end of a band-shaped plate electrode PL27 arranged on the dielectric layer LY4. The plate electrode PL27 has a substantially U- or C-shape. The via V27 is connected to the other end of the plate electrode PL27. The via V27 is connected to one end of a band-shaped plate electrode PL28 arranged on the dielectric layer LY3. The plate electrode PL28 has a substantially U- or C-shape. The other end of the plate electrode PL28 is connected to the second terminal T2 disposed on the side surface 115.

[0036] The plate electrodes PL25, PL26, PL27, and PL28 are arranged such that most of their paths overlap each other when the laminate 110 is viewed in a plan view from the stacking direction. That is, the plate electrodes PL25, PL26, PL27, and PL28 and the vias V25, V26, and V27 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L22 in FIG. 1.

[0037] The second terminal T2 is connected to a flat-plate-shaped capacitor electrode PC4 disposed on the dielectric layer LY9. When the laminate 110 is viewed from above in the lamination direction, the capacitor electrode PC4 at least partially overlaps with the ground electrode PG1 of the dielectric layer LY8. The capacitor electrode PC4 and the ground electrode PG1 form a capacitor C22 in the second circuit CR2 in FIG.

[0038] The first terminal T1 and the second terminal T2 are connected to the resistive element R1 in the second circuit CR2 in FIG. 1. The resistive element R1 is configured as an individual chip resistor arranged outside the laminate 110, as shown in FIG. 2, and the external terminal of the resistive element R1 is connected to the first terminal T1 and the second terminal T2. Alternatively, the resistive element R1 may be configured as a plate electrode PR1 arranged inside the laminate 110 or on the upper surface 111. In the example of FIG. 3, the plate electrode PR1 is, for example, a strip-shaped electrode extending in the X-axis direction arranged on the dielectric layer LY2, and the plate electrode PR1 is connected to the first terminal T1 on the side surface 115, and the other end of the plate electrode PR1 is connected to the second terminal T2 on the side surface 115. The plate electrode PR1 may be configured as a meander-shaped electrode in order to obtain a desired resistance value.

[0039] Fig. 4 is a schematic diagram of the inductors L11, L12, L21, and L22 configured in the dielectric layers LY2 to LY6, viewed from the positive direction of the Z axis. As shown in Fig. 4, the inductors L11 and L12 are arranged in line symmetry with respect to a virtual line CL1 passing through the common terminal T0. The inductors L21 and L22 are also arranged in line symmetry with respect to the virtual line CL1.

[0040] Furthermore, the winding direction of inductor L11 (CW direction: first direction) is opposite to the winding direction of inductor L12 (CCW direction: second direction), and the winding direction of inductor L21 (CW direction) is opposite to the winding direction of inductor L22 (CCW direction). On the other hand, the winding direction of inductor L11 is the same as the winding direction of inductor L21, and the winding direction of inductor L12 is the same as the winding direction of inductor L22.

[0041] In this way, the path from the common terminal T0 to the first terminal T1 and the path from the common terminal T0 to the second terminal T2 can be structurally symmetrical by symmetrically arranging the inductors included in the first circuit CR1 and the second circuit CR2 in the laminate 110. Also, by making the winding directions of the inductors arranged on the same side of the virtual line CL1 the same direction and making the winding directions of the inductors arranged on the opposite side of the virtual line CL1 the opposite directions, the electromagnetic fields generated by the inductors can be made symmetrical.

[0042] Such a configuration can be structurally and electromagnetically symmetrical, thereby suppressing fluctuations in phase difference and amplitude difference in the power splitter 100. Furthermore, by winding the inductors arranged on the same side of the virtual line CL1 in the same direction, it is possible to prevent the electromagnetic fields generated by the inductors L11 and L21 from canceling each other out, and the electromagnetic fields generated by the inductors L12 and L22 from canceling each other out, thereby suppressing deterioration of the electromagnetic characteristics.

[0043] (Characteristics of power divider) The characteristics of the power splitter 100 of the first embodiment will be described together with a comparative example. Fig. 5 is an equivalent circuit diagram of a power splitter 100X in the comparative example. Referring to Fig. 5, the power splitter 100X has a configuration in which the first circuit CR1 in the power splitter 100 of Fig. 1 is replaced with a first circuit CR1X. The second circuit CR2 in the power splitter 100X is the same as that in the power splitter 100. In the first circuit CR1X of the power splitter 100X, the parallel circuit of inductors L11 and L12 in the power splitter 100 is replaced with a single inductor L1.

[0044] FIG. 6 is a diagram for explaining an outline of the arrangement of each inductor in a power splitter 100X of a comparative example, and corresponds to FIG. 4 described above. Referring to FIG. 6, the power splitter 100X can be structurally configured to be substantially line-symmetrical with respect to the virtual line CL2, but since there is only one inductor L1 in the first circuit CR1X, the winding direction of the inductor L1 is opposite to the winding direction of either the inductor L21 or the inductor L22. Therefore, the electromagnetic field generated in the power splitter 100X is not symmetrical, and the electromagnetic fields of the inductors (inductor L1 and inductor L22 in FIG. 6) whose winding directions are opposite to each other cancel each other out. This can cause fluctuations in the phase difference and the amplitude difference in the power splitter 100X.

[0045] 7 is a diagram showing a comparison of phase difference (PD) and amplitude balance (AB) in the power splitter 100 of the first embodiment and the power splitter 100X of the comparative example. The upper part of FIG. 7 shows the characteristics of the power splitter 100X of the comparative example, and the lower part shows the characteristics of the power splitter 100 of the first embodiment.

[0046] 7, in the case of the power splitter 100X of the comparative example, both the phase difference (line LN10) and the amplitude balance (line LN15) fluctuate significantly as the frequency increases. On the other hand, in the case of the power splitter 100 of the first embodiment, both the phase difference (line LN11) and the amplitude balance (line LN16) are almost zero even when the frequency changes, and the phase difference and the amplitude difference are improved compared to the comparative example.

[0047] As described above, as in the power splitter 100 of embodiment 1, the inductor arranged between the common terminal T0 and the branch point BP1 is composed of two inductors connected in parallel, and the inductors are arranged so that the path from the common terminal T0 to the first terminal T1 and the path from the common terminal T0 to the second terminal T2 are linearly symmetrical when the laminate is viewed in a plane, thereby making it possible to improve the phase difference and amplitude difference.

[0048] In the above explanation, an example has been given in which the power splitter 100 outputs a signal input to the common terminal T0 from the first terminal T1 and the second terminal T2. However, it is also possible to cause the power splitter 100 to function as a power combiner that combines signals input to the first terminal T1 and the second terminal T2 and outputs the combined signal from the common terminal T0.

[0049] "Inductor L11," "inductor L12," "inductor L21," and "inductor L22" in the first embodiment correspond to the "first inductor," "second inductor," "third inductor," and "fourth inductor" in this disclosure, respectively. "Capacitor C1," "capacitor C2," "capacitor C21," and "capacitor C22" in the first embodiment correspond to the "first capacitor," "second capacitor," "third capacitor," and "fourth capacitor" in this disclosure, respectively.

[0050] [Embodiment 2] In the second embodiment, a configuration in which an additional circuit is added to the second circuit of the power distributor will be described.

[0051] (Circuit configuration of power distributor) 8 is an equivalent circuit diagram of a power splitter 100A according to the second embodiment. The power splitter 100A has a configuration in which the second circuit CR2 in the power splitter 100 of the first embodiment is replaced with a second circuit CR2A. The second circuit CR2A further includes a third circuit CR3 in addition to the configuration of the second circuit CR2 of the first embodiment. Note that the description of the elements of the power splitter 100A that overlap with those of the power splitter 100 of the first embodiment will not be repeated.

[0052] 8, the third circuit CR3 is arranged between the components of the second circuit CR2 and the first and second terminals T1 and T2. The third circuit CR3 includes inductors L31 and L32 and capacitors C31 and C32.

[0053] The inductor L31 is connected between the inductor L21 and the first terminal T1. In other words, the inductors L21 and L31 are connected in series between the branch point BP1 and the first terminal T1. The inductor L32 is connected between the inductor L22 and the second terminal T2. In other words, the inductors L22 and L32 are connected in series between the branch point BP1 and the second terminal T2.

[0054] The capacitor C31 is connected in parallel to the resistor R1, and the capacitor C32 is connected between the first terminal T1 and the second terminal T2.

[0055] The third circuit CR3 included in the second circuit CR2A forms another attenuation pole in the isolation characteristics of the path from the first terminal T1 to the second terminal T2.

[0056] (Structure of power distributor) Next, a detailed structure of the power splitter 100A will be described with reference to Figures 9 and 10. Figure 9 is an external perspective view of the power splitter 100A, and Figure 10 is an exploded perspective view showing an example of the layered structure of the power splitter 100A.

[0057] 9 and 10, the power splitter 100A includes a rectangular or substantially rectangular parallelepiped laminate 110A in which a plurality of dielectric layers LY11-LY23 are laminated in a lamination direction, and a resistive element R1 provided outside the laminate 110A. The dielectric layers LY11-LY23 are formed of ceramics such as low-temperature co-fired ceramics (LTCC) or resin, as in the first embodiment.

[0058] A directional mark DM for specifying the direction of the power distributor 100A is arranged on the top surface 111 (dielectric layer LY11) of the laminate 110A. In the laminate 110A, external terminals are also arranged on the side surfaces 113 and 114. The external terminal on the side surface 114 is a first terminal T1, and the external terminal on the side surface 113 is a second terminal T2. A common terminal T0 and a ground terminal GND are arranged on the side surface 116, and a ground terminal GND and connection terminals T3 and T4 are arranged on the side surface 115. The resistive element R1 is connected to the connection terminals T3 and T4.

[0059] The common terminal T0 is connected to a capacitor electrode PC11 arranged on the dielectric layer LY23 on the lower surface 112 side. When the laminate 110A is viewed in a plan view from the stacking direction, the capacitor electrode PC11 at least partially overlaps with a substantially rectangular ground electrode PG10 arranged on the dielectric layer LY22. The ground electrode PG10 is connected to the ground terminal GND. The capacitor electrode PC11 and the ground electrode PG10 form a capacitor C1 in the first circuit CR1 in FIG. 8.

[0060] The common terminal T0 is also connected to plate electrodes PL31, PL41 arranged on the dielectric layer LY19. Each of the plate electrodes PL31, PL41 is a band-like electrode having a substantially U- or C-shape, and one end of each is connected to the other. The common terminal T0 is connected to the connection portion between the plate electrodes PL31 and PL41. The other end of the plate electrode PL31 is connected to a via V31, and the other end of the plate electrode PL41 is connected to a via V41.

[0061] The via V31 is connected to one end of a strip-shaped plate electrode PL32 arranged on the dielectric layer LY18. The plate electrode PL32 has a substantially U-shaped or C-shaped configuration. The via V32 is connected to the other end of the plate electrode PL32. The via V32 is connected to one end of a strip-shaped plate electrode PL33 arranged on the dielectric layer LY17. The plate electrode PL33 has a substantially U-shaped or C-shaped configuration. The via V33 is connected to the other end of the plate electrode PL33. The via V33 is connected to one end of a strip-shaped plate electrode PL34 arranged on the dielectric layer LY16. The plate electrode PL34 has a substantially U-shaped or C-shaped configuration. The via V34 is connected to the other end of the plate electrode PL34. The via V34 is connected to one end of a strip-shaped plate electrode PL35 arranged on the dielectric layer LY15. The plate electrode PL35 has a substantially U-shaped or C-shaped configuration.

[0062] The plate electrodes PL31, PL32, PL33, PL34, and PL35 are arranged such that the paths of the plate electrodes PL31, PL32, PL33, PL34, and PL35 overlap each other when the laminate 110A is viewed from above in the stacking direction. That is, the plate electrodes PL31, PL32, PL33, PL34, and PL35 and the vias V31, V32, V33, and V34 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L11 in FIG. 8.

[0063] The via V41 is connected to one end of a strip-shaped plate electrode PL42 arranged on the dielectric layer LY18. The plate electrode PL42 has a substantially U-shaped or C-shaped configuration. The via V42 is connected to the other end of the plate electrode PL42. The via V42 is connected to one end of a strip-shaped plate electrode PL43 arranged on the dielectric layer LY17. The plate electrode PL43 has a substantially U-shaped or C-shaped configuration. The via V43 is connected to the other end of the plate electrode PL43. The via V43 is connected to one end of a strip-shaped plate electrode PL44 arranged on the dielectric layer LY16. The plate electrode PL44 has a substantially U-shaped or C-shaped configuration. The via V44 is connected to the other end of the plate electrode PL44. The via V44 is connected to one end of a strip-shaped plate electrode PL45 arranged on the dielectric layer LY15. The plate electrode PL45 has a substantially U-shaped or C-shaped configuration.

[0064] The plate electrodes PL41, PL42, PL43, PL44, and PL45 are arranged such that the paths of the plate electrodes PL41, PL42, PL43, PL44, and PL45 overlap each other when the laminate 110A is viewed from above in the stacking direction. That is, the plate electrodes PL41, PL42, PL43, PL44, and PL45 and the vias V41, V42, V43, and V44 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L12 in FIG. 8.

[0065] In the dielectric layer LY15, a part of the plate electrode PL35 overlaps a part of the plate electrode PL45, and the other ends of the two electrodes are shared. A via V1 is connected to the shared other ends of the plate electrodes PL35 and PL45.

[0066] The via V1 is connected to a plate electrode P20 arranged on the dielectric layer LY14 and a capacitor electrode PC14 arranged on the dielectric layer LY13. Each of the plate electrode P20 and the capacitor electrode PC14 is a band-shaped electrode extending in the X-axis direction, and is connected to the via V1 at the center portion in the extension direction.

[0067] When the laminate 110A is viewed in a plane from the stacking direction, a portion of the capacitor electrode PC14 overlaps with a ground electrode PG11 arranged on the dielectric layer LY12. The ground electrode PG11 is a strip-shaped electrode extending in the X-axis direction. Both ends of the ground electrode PG11 are connected to a ground terminal GND arranged on the side surface 116. The capacitor electrode PC14 and the ground electrode PG11 form a capacitor C2 in the equivalent circuit of FIG. 8.

[0068] A via V51 is connected to one end of the plate electrode P20 on the dielectric layer LY14, and a via V61 is connected to the other end of the plate electrode P20. The via V51 is connected to one end of a plate electrode PL51 arranged on the dielectric layer LY15. The plate electrode PL51 has a substantially U- or C-shape. A via V52 is connected to the other end of the plate electrode PL51. The via V52 is connected to one end of a strip-shaped plate electrode PL52 arranged on the dielectric layer LY16. The plate electrode PL52 has a substantially U- or C-shape. A via V53 is connected to the other end of the plate electrode PL52. The via V53 is connected to one end of a strip-shaped plate electrode PL53 arranged on the dielectric layer LY17. The plate electrode PL53 has a substantially U- or C-shape. A via V54 is connected to the other end of the plate electrode PL53. The via V54 is connected to one end of a belt-shaped plate electrode PL54 arranged on the dielectric layer LY18. The plate electrode PL53 has a substantially U- or C-shape. The other end of the plate electrode PL53 is connected to a connection terminal T3 arranged on the side surface 115 and is also connected to one end of a belt-shaped plate electrode PL71.

[0069] The plate electrodes PL51, PL52, PL53, and PL54 are arranged such that the paths of the plate electrodes PL51, PL52, PL53, and PL54 overlap each other when the laminate 110A is viewed from above in the stacking direction. That is, the plate electrodes PL51, PL52, PL53, and PL54 and the vias V51, V52, V53, and V54 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L21 in FIG. 8.

[0070] The via V61 is connected to one end of a plate electrode PL61 arranged on the dielectric layer LY15. The plate electrode PL61 has a substantially U- or C-shape. The via V62 is connected to the other end of the plate electrode PL61. The via V62 is connected to one end of a strip-shaped plate electrode PL62 arranged on the dielectric layer LY16. The plate electrode PL62 has a substantially U- or C-shape. The via V63 is connected to the other end of the plate electrode PL62. The via V63 is connected to one end of a strip-shaped plate electrode PL63 arranged on the dielectric layer LY17. The plate electrode PL63 has a substantially U- or C-shape. The via V64 is connected to the other end of the plate electrode PL63. The via V64 is connected to one end of a strip-shaped plate electrode PL64 arranged on the dielectric layer LY18. The plate electrode PL63 has a substantially U- or C-shape. The other end of the plate electrode PL63 is connected to a connection terminal T4 disposed on the side surface 115, and is also connected to one end of a strip-shaped plate electrode PL81.

[0071] The plate electrodes PL61, PL62, PL63, and PL64 are arranged such that the majority of the paths overlap each other when the laminate 110A is viewed from above in the lamination direction. That is, the plate electrodes PL61, PL62, PL63, and PL64 and the vias V61, V62, V63, and V64 form a helical coil with the Z-axis as the winding axis. This helical coil corresponds to the inductor L22 in FIG. 8.

[0072] The other end of the plate electrode PL71 on the dielectric layer LY18 is connected to a via V71. The via V71 is connected to one end of a strip-shaped plate electrode PL72 arranged on the dielectric layer LY17. The plate electrode PL72 has a substantially U-shaped or C-shaped. The other end of the plate electrode PL72 is connected to a via V72. The via V72 is connected to one end of a strip-shaped plate electrode PL73 arranged on the dielectric layer LY16. The plate electrode PL73 has a substantially U-shaped or C-shaped. The other end of the plate electrode PL73 is connected to a via V74. The via V74 is connected to one end of a strip-shaped plate electrode PL74 arranged on the dielectric layer LY15. The plate electrode PL74 has a substantially U-shaped or C-shaped. The other end of the plate electrode PL74 is connected to a first terminal T1 arranged on the side surface 114.

[0073] The plate electrodes PL71, PL72, PL73, and PL74 are arranged such that the paths of the plate electrodes PL71, PL72, PL73, and PL74 overlap each other when the laminate 110A is viewed from above in the stacking direction. That is, the plate electrodes PL71, PL72, PL73, and PL74 and the vias V71, V72, and V73 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L31 in FIG. 8.

[0074] The other end of the plate electrode PL81 on the dielectric layer LY18 is connected to a via V81. The via V81 is connected to one end of a strip-shaped plate electrode PL82 arranged on the dielectric layer LY17. The plate electrode PL82 has a substantially U- or C-shape. The other end of the plate electrode PL82 is connected to a via V82. The via V82 is connected to one end of a strip-shaped plate electrode PL83 arranged on the dielectric layer LY16. The plate electrode PL83 has a substantially U- or C-shape. The other end of the plate electrode PL83 is connected to a via V84. The via V84 is connected to one end of a strip-shaped plate electrode PL84 arranged on the dielectric layer LY15. The plate electrode PL84 has a substantially U- or C-shape. The other end of the plate electrode PL84 is connected to a second terminal T2 arranged on the side surface 113.

[0075] The plate electrodes PL81, PL82, PL83, and PL84 are arranged such that most of their paths overlap each other when the laminate 110A is viewed from above in the lamination direction. That is, the plate electrodes PL81, PL82, PL83, and PL84 and the vias V81, V82, and V83 form a helical coil with the Z-axis as its winding axis. This helical coil corresponds to the inductor L32 in FIG. 8.

[0076] In the dielectric layer LY15, a via V2 is connected to the middle of the plate electrode PL74. The via V2 is connected to a capacitor electrode PC15 arranged on the dielectric layer LY13. The capacitor electrode PC15 is a strip-shaped electrode extending in the X-axis direction. Similarly, in the dielectric layer LY15, a via V3 is connected to the middle of the plate electrode PL84. The via V3 is connected to a capacitor electrode PC16 arranged on the dielectric layer LY13. The capacitor electrode PC16 is a strip-shaped electrode extending in the X-axis direction.

[0077] When the laminate 110A is viewed in a plan view from the lamination direction, a part of the capacitor electrode PC15 and a part of the capacitor electrode PC16 overlap with a capacitor electrode PC17 disposed on the dielectric layer LY12. The capacitor electrode PC17 is a strip-shaped electrode extending in the X-axis direction. The capacitor electrodes PC15, PC16, and PC17 form a capacitor C32 in the equivalent circuit of FIG.

[0078] A connection terminal T3 arranged on a side surface 115 of the laminate 110A is connected to plate electrodes PL54 and PL71 arranged on the dielectric layer LY18, a capacitor electrode PC19 arranged on the dielectric layer LY20, and a capacitor electrode PC12 arranged on the dielectric layer LY23. When the laminate 110A is viewed in a plan view from the stacking direction, a portion of the capacitor electrode PC12 arranged on the dielectric layer LY23 overlaps with a ground electrode PG11 of the dielectric layer LY22. The capacitor electrode PC12 and the ground electrode PG11 form a capacitor C21 in the equivalent circuit of FIG. 8.

[0079] A connection terminal T4 arranged on a side surface 115 of the laminate 110A is connected to plate electrodes PL64 and PL81 arranged on the dielectric layer LY18, a capacitor electrode PC20 arranged on the dielectric layer LY20, and a capacitor electrode PC13 arranged on the dielectric layer LY23. When the laminate 110A is viewed in a plan view from the stacking direction, a portion of the capacitor electrode PC13 arranged on the dielectric layer LY23 overlaps with a ground electrode PG11 of the dielectric layer LY22. The capacitor electrode PC13 and the ground electrode PG11 form a capacitor C22 in the equivalent circuit of FIG. 8.

[0080] A portion of the capacitor electrode PC19 arranged on the dielectric layer LY20 and a portion of the capacitor electrode PC20 overlap with the capacitor electrode PC18 arranged on the dielectric layer LY21 when the laminate 110A is viewed in a plan view from the stacking direction. The capacitor electrodes PC18, PC19, and PC20 configure a capacitor C31 in the equivalent circuit of FIG.

[0081] 10, a resistive element R1 provided outside the laminate 110A is connected to the connection terminals T3 and T4. Note that the resistive element R1 may be disposed inside the laminate 110A.

[0082] Fig. 11 is a schematic diagram of the inductors L11, L12, L21, L22, L31, and L32 configured in the dielectric layers LY15 to LY19, viewed from the positive direction of the Z axis. As shown in Fig. 11, the inductors L11 and L12 are arranged in line symmetry with respect to the imaginary line CL2 passing through the common terminal T0. The inductors L21 and L22, and the inductors L31 and L32 are also arranged in line symmetry with respect to the imaginary line CL2.

[0083] The inductors L11, L21, and L31 are all wound in the same CW direction, while the inductors L12, L22, and L32 are all wound in the same CCW direction.

[0084] In this way, by symmetrically arranging the inductors included in the laminate 110A, the path from the common terminal T0 to the first terminal T1 and the path from the common terminal T0 to the second terminal T2 can be structurally symmetrical. Furthermore, by making the winding directions of the inductors arranged on the same side of the virtual line CL2 the same direction, and making the winding directions of the inductors arranged on the opposite side of the virtual line CL2 the opposite directions, the electromagnetic fields generated by the inductors can be made symmetrical.

[0085] This configuration makes it possible to achieve a structurally and electromagnetically symmetrical configuration, thereby suppressing fluctuations in phase difference and amplitude difference in the power splitter 100A. In addition, by winding the inductors arranged on the same side of the virtual line CL2 in the same direction, it is possible to prevent the electromagnetic fields generated by the inductors L11, L21, and L31 from canceling each other out, and the electromagnetic fields generated by the inductors L12, L22, and L32 from canceling each other out, thereby suppressing deterioration of the electromagnetic characteristics.

[0086] (Isolation characteristics) Fig. 12 is a diagram showing isolation between the first terminal T1 and the second terminal T2 in the power splitter 100A of the second embodiment and the power splitter 100X of the comparative example shown in the first embodiment. In Fig. 12, a solid line LN20 indicates the power splitter 100A of the second embodiment, and a dashed line LN21 indicates the power splitter 100X of the comparative example.

[0087] Referring to FIG. 12, the power splitter 100X of the comparative example has two attenuation poles, near 3.5 GHz and near 4.7 GHz. On the other hand, in the power splitter 100A of the second embodiment, an attenuation pole is added by the third circuit CR3, and three attenuation poles are generated near 2.7 GHz, near 3.9 GHz, and near 5.0 GHz. As a result, the attenuation amount in the power splitter 100A of the second embodiment is larger overall than that in the comparative example. Therefore, when comparing frequency bandwidths in which an isolation of, for example, 20 dB can be achieved, the bandwidth BW1 of the power splitter 100A is wider than the bandwidth BW2 in the comparative example (BW1>BW2). That is, a wider bandwidth of the isolation characteristic is realized.

[0088] 13 is a diagram showing the phase difference (PD) and amplitude balance (AB) between the first terminal T1 and the second terminal T2 of the power splitter 100A of the second embodiment. As for the phase difference (line LN30), a slight phase difference occurs as the frequency increases, but the phase difference is suppressed to less than 1°. As for the amplitude balance (line LN31), zero dB is achieved over the entire frequency range. That is, even in the configuration of the power splitter 100A of the second embodiment, the fluctuations in the phase difference and the amplitude difference are suppressed compared to the comparative example shown in FIG.

[0089] As described above, even in a power splitter where a third circuit is added to the circuit after signal branching, fluctuations in phase difference and amplitude difference can be suppressed by arranging the inductors symmetrically and winding the inductors in symmetrical directions.

[0090] It should be noted that "inductor L31" and "inductor L32" in the second embodiment correspond to the "fifth inductor" and "sixth inductor" in this disclosure, respectively. Embodiment 2 "Capacitor C31" and "capacitor C32" in correspond to the "fifth capacitor" and "sixth capacitor" in this disclosure, respectively.

[0091] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, not by the description of the embodiments described above, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0092] 100, 100A, 100X power distributor, 110, 110A laminate, 111 top surface, 112 bottom surface, 113 to 116 side surface, BP1 branch point, C1, C2, C21, C22, C31, C32 capacitor, CR1, CR1X first circuit, CR2, CR2A second circuit, CR3 third circuit, DM directional mark, GND ground terminal, L1, L11, L12, L21, L22, L31, L32 inductor, LY1 to LY9, LY11 to LY23 Dielectric layer, P10~P12, P20, PC2, PC3, PL11~PL13, PL15~PL17, PL21~PL28, PL31~PL35, PL41~PL45, PL51~PL54, PL61~PL64, PL71~PL74, PL81~PL84, PR1 flat plate electrode, P13 connection part, PC1, PC3, PC4, PC11~PC20 capacitor electrodes, PG1, PG10, PG11 ground electrodes, R1 resistive element, T0 common terminal, T1 first terminal, T2 second terminal, T3, T4 Connection terminals, V1~V3, V11~V19, V21~V23, V25~V27, V31~V34, V41~V44, V51~V54, V61~V64, V71~V74, V81~V84 vias.

Claims

1. A common terminal; A ground terminal; A first terminal and a second terminal; a first circuit connected to the common terminal; a second circuit connected to the first terminal and the second terminal, for branching a signal passing through the first circuit at a branch point and transmitting the signal to the first terminal and the second terminal; a laminate in which a plurality of dielectric layers are laminated, The first circuit is a first inductor and a second inductor connected in parallel between the common terminal and the branch point; a first capacitor connected between the common terminal and the ground terminal; a second capacitor connected between the branch point and the ground terminal; The second circuit is a third inductor having one end connected to the branch point and disposed on a path from the branch point to the first terminal; a fourth inductor having one end connected to the branch point and disposed on a path from the branch point to the second terminal; a third capacitor connected between the other end of the third inductor and the ground terminal; a fourth capacitor connected between the other end of the fourth inductor and the ground terminal; a resistive element connected between the other end of the third inductor and the other end of the fourth inductor, each of the first inductor, the second inductor, the third inductor, and the fourth inductor is a coil that is disposed inside the laminate and has a winding axis in a lamination direction of the laminate, When the laminate is viewed in a plane from the lamination direction, the first inductor and the second inductor are disposed at positions symmetrical with respect to a virtual line passing through the common terminal, A power divider, wherein the third inductor and the fourth inductor are arranged at positions symmetrical with respect to the virtual line.

2. When the laminate is viewed in a plane from the lamination direction, a winding direction of the first inductor and the third inductor is a first direction, The power splitter of claim 1 , wherein the second inductor and the fourth inductor are wound in a second direction opposite to the first direction.

3. The power splitter of claim 1 , wherein the resistive element is disposed external to the stack.

4. The second circuit is a fifth inductor connected between the other end of the third inductor and the first terminal; a sixth inductor connected between the other end of the fourth inductor and the second terminal; a fifth capacitor connected in parallel to the resistive element; The power splitter of claim 1 , further comprising a sixth capacitor connected between the first terminal and the second terminal.

5. Each of the fifth inductor and the sixth inductor is a coil disposed inside the laminate and having a winding axis in the stacking direction of the laminate, When the laminate is viewed in a plane from the lamination direction, The power splitter according to claim 4 , wherein the fifth inductor and the sixth inductor are arranged at positions symmetrical with respect to the imaginary line.

6. When the laminate is viewed in a plane from the lamination direction, a winding direction of the first inductor, the third inductor, and the fifth inductor is a first direction; The power splitter of claim 5 , wherein the second inductor, the fourth inductor, and the sixth inductor are wound in a second direction opposite to the first direction.

7. The power splitter of claim 5 , wherein the resistive element is disposed external to the stack.

8. 8. The power splitter according to claim 1, wherein the first circuit generates at least one attenuation pole in an isolation characteristic of a path from the first terminal to the second terminal.

9. 8. The power splitter according to claim 1, wherein the second circuit generates at least one attenuation pole in an isolation characteristic of a path from the first terminal to the second terminal.

Images