Semiconductor Device

Abstract

To suppress the formation of an inversion region near the bottom of a dummy trench portion. [Solution] A semiconductor device is provided which includes a drift region of a first conductivity type formed in a semiconductor substrate, a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region, an accumulation region of the first conductivity type formed between the drift region and the base region and having a doping concentration higher than that of the drift region, and a dummy trench portion formed from the upper surface of the semiconductor substrate through the base region, and at least one of the accumulation region and the dummy trench portion has an inhibition structure which inhibits the formation of an inversion region of the second conductivity type in a region of the first conductivity type adjacent to the dummy trench portion.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices including an IGBT (insulated gate bipolar transistor) and the like are known (see, for example, Patent Document 1). In some cases, dummy trenches are provided in the semiconductor device. Patent Document 1: International Publication No. 2005 / 109521 Pamphlet Summary of the Invention [Problem to be solved by the invention]

[0003] When the semiconductor device is turned on, a P-type inversion region may be formed in the N-type region near the bottom of the dummy trench, which increases turn-on loss. [Means for solving the problem]

[0004] In a first aspect of the present invention, a semiconductor device is provided that includes a semiconductor substrate. The semiconductor device may include a drift region of a first conductivity type formed in the semiconductor substrate. The semiconductor device may include a base region of a second conductivity type formed in the semiconductor substrate between an upper surface of the semiconductor substrate and the drift region. The semiconductor device may include an accumulation region of the first conductivity type formed in the semiconductor substrate between the drift region and the base region and having a doping concentration higher than that of the drift region. The semiconductor device may include a dummy trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate through the base region. At least one of the accumulation region and the dummy trench portion may have an inhibition structure that inhibits the formation of an inversion region of the second conductivity type in a region of the first conductivity type adjacent to the dummy trench portion.

[0005] The semiconductor device may further include a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region, penetrating the base region and the accumulation region. The gate trench portion may have a gate insulating film formed on an inner wall of the trench. The gate trench portion may have a gate conductive portion covered by the gate insulating film. The dummy trench portion may have a dummy insulating film formed on an inner wall of the trench and thicker than the gate insulating film. The dummy trench portion may have a dummy conductive portion covered by the dummy insulating film.

[0006] The thickness of the dummy insulating film may be at least twice as large as the thickness of the gate insulating film. The dummy insulating film in the dummy trench portion may have a uniform thickness.

[0007] The dummy trench portion may be filled with an insulating material, and a lower end of the dummy trench portion may be located above a lower end of the accumulation region.

[0008] The semiconductor device may include a gate trench portion formed in the semiconductor substrate, penetrating the base region and the accumulation region to a position deeper than the dummy trench portion. The dummy trench portion may have a dummy insulating film formed on an inner wall of the trench. The dummy trench portion may have a dummy conductive portion covered with the dummy insulating film. In the depth direction of the semiconductor substrate, the doping concentration distribution in the accumulation region may have a peak. In the depth direction of the semiconductor substrate, the peak of the doping concentration distribution in the accumulation region may be located between a lower end of the dummy conductive portion and a lower end of the dummy insulating film. In the depth direction of the semiconductor substrate, the lower end of the accumulation region may be located between a lower end of the dummy conductive portion and a lower end of the dummy insulating film.

[0009] The dummy insulating film at the bottom of the dummy trench portion may be thicker than the dummy insulating film at the sidewall of the dummy trench portion. The dummy trench portion may have a dummy insulating film formed on an inner wall of the trench. The dummy trench portion may have a dummy conductive portion covered with the dummy insulating film. The dummy insulating film at the bottom of the dummy trench portion may be thicker than the dummy insulating film at the sidewall of the dummy trench portion. A lower end of the dummy insulating film at the bottom of the dummy trench portion may be located below the accumulation region.

[0010] A lower end of the dummy conductive portion may be disposed lower than an upper end of the accumulation region. In the accumulation region, an integral concentration obtained by integrating a doping concentration in a dummy adjacent region adjacent to the dummy trench portion in a depth direction of the semiconductor substrate may be higher than an integral concentration obtained by integrating a doping concentration in a gate adjacent region adjacent to the gate trench portion in a depth direction of the semiconductor substrate.

[0011] The accumulation region may be formed so that the dummy adjacent region is deeper than the gate adjacent region. The dummy adjacent region of the accumulation region may have a doping concentration distribution in a depth direction of the semiconductor substrate that has a first peak and a second peak that is located deeper than the first peak and has a doping concentration higher than the first peak.

[0012] The accumulation region may have a peak doping concentration in the dummy adjacent region higher than a peak doping concentration in the gate adjacent region. In the accumulation region formed between the two dummy trench portions, a central region at the center of the two dummy trench portions may have a lower integrated concentration than a dummy adjacent region adjacent to the dummy trench portions.

[0013] The semiconductor device may include a transistor section formed in a semiconductor substrate and including one or more dummy trench sections, a diode section formed in the semiconductor substrate and including one or more dummy trench sections, and a boundary section formed between the transistor section and the diode section in the semiconductor substrate and including one or more dummy trench sections. A high concentration region of a second conductivity type having a doping concentration higher than that of the base region may be formed on the upper surface of the semiconductor substrate in the mesa section sandwiched between the dummy trench sections in the boundary section.

[0014] The accumulation region may not be formed in at least a portion of the mesa portion at the boundary, or the accumulation region may be formed in the entire mesa portion at the boundary.

[0015] In the mesa portion at the boundary, an integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction of the semiconductor substrate in a region adjacent to the dummy trench portion closer to the transistor portion may be higher than an integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction in a central region of the mesa portion.

[0016] In the mesa portion at the boundary, an integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction of the semiconductor substrate in a region adjacent to the dummy trench portion closer to the diode portion may be higher than an integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction in a central region of the mesa portion.

[0017] The semiconductor device may include a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region, penetrating the base region and the accumulation region. The semiconductor device may include a mesa portion provided inside the semiconductor substrate and sandwiched between the gate trench portion and the dummy trench portion, and in which the base region is disposed. The base region disposed in at least a part of the mesa portions sandwiched between the gate trench portion and the dummy trench portion may not be connected to the emitter electrode.

[0018] The semiconductor device may include a first gate trench portion and a second gate trench portion formed in a semiconductor substrate from an upper surface of the semiconductor substrate to a drift region, penetrating a base region and an accumulation region. Each of the first gate trench portion, the second gate trench portion, and the dummy trench portion may have two extension portions extending in parallel in a predetermined direction on the upper surface of the semiconductor substrate, and a tip portion connecting the tips of the two extension portions. On the upper surface of the semiconductor substrate, the dummy trench portion may be disposed inside the first gate trench portion. On the upper surface of the semiconductor substrate, the second gate trench portion may be disposed inside the dummy trench portion.

[0019] The semiconductor device may further include a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region, penetrating the base region and the accumulation region, and a mesa portion sandwiched between at least one of the dummy trench portion and the gate trench portion. The accumulation region may have a first accumulation region provided below the base region, and a second accumulation region provided between the first accumulation region and the drift region.

[0020] At least one of the dummy trench portion and the gate trench portion may have, on the inner wall of the trench, a thin-film trench portion having an insulating film of a predetermined thickness and a conductive portion covered by the insulating film, and a thick-film trench portion on the inner wall of the trench having an insulating film that is thicker than the insulating film in the thin-film trench portion.

[0021] The conductive portion is provided in the thin trench portion, but does not necessarily have to be provided in the thick trench portion.

[0022] The conductive portion may be provided in both the thin trench portion and the thick trench portion. The conductive portion in the thin trench portion may have a width in the arrangement direction of the trenches larger than that of the conductive portion in the thick trench portion.

[0023] The conductive portion may have the same width in the arrangement direction of the trenches and may be provided in both the thin trench portion and the thick trench portion. At least one of the dummy trench portion and the gate trench portion may have a width in the arrangement direction in the thin trench portion smaller than a width in the arrangement direction in the thick trench portion.

[0024] The thick trench portion may be provided at a position deeper than the base region.

[0025] The accumulation region may further comprise a third accumulation region disposed between the first accumulation region and the second accumulation region.

[0026] In a second aspect of the present invention, a semiconductor device is provided that includes a semiconductor substrate. The semiconductor device may include a drift region of a first conductivity type formed in the semiconductor substrate. The semiconductor device may include a base region of a second conductivity type formed in the semiconductor substrate between an upper surface of the semiconductor substrate and the drift region. The semiconductor device may include an accumulation region of a first conductivity type formed in the semiconductor substrate between the drift region and the base region and having a higher doping concentration than the drift region. The semiconductor device may include a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region, penetrating the base region and the accumulation region. The semiconductor device may include a dummy trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to penetrating the base region. The semiconductor device may include an emitter electrode provided above the upper surface of the semiconductor substrate. The semiconductor device may include a mesa portion provided inside the semiconductor substrate between the gate trench portion and the dummy trench portion, and in which the base region is disposed. The base region disposed in at least a part of the mesa portions sandwiched between the gate trench portion and the dummy trench portion may not be connected to the emitter electrode.

[0027] In a third aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate. The semiconductor device may include a drift region of a first conductivity type formed in the semiconductor substrate. The semiconductor device may include a base region of a second conductivity type formed in the semiconductor substrate between an upper surface of the semiconductor substrate and the drift region. The semiconductor device may include an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a higher doping concentration than the drift region. The semiconductor device may include a first gate trench portion and a second gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region, penetrating the base region and the accumulation region. The semiconductor device may include a dummy trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to penetrating the base region. In the upper surface of the semiconductor substrate, the dummy trench portion may be disposed inside the first gate trench portion. In the upper surface of the semiconductor substrate, the second gate trench portion may be disposed inside the dummy trench portion.

[0028] The above summary of the invention does not list all the features of the present invention. Subcombinations of these features may also be inventions. [Brief description of the drawings]

[0029] [Figure 1] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of a-a cross section in FIG. [Diagram 3] 2 is an enlarged cross-sectional view of the gate trench portion 40 and the dummy trench portion 30 and their vicinity. [Figure 4] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Diagram 5] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Figure 6] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Figure 7] 7 is a diagram showing an example of a doping concentration distribution in the depth direction of the accumulation region 16 shown in FIG. 6. FIG. [Figure 8] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Figure 9] 9 is an enlarged cross-sectional view of the vicinity of the gate trench portion 40 and the dummy trench portion 30 shown in FIG. 8. [Figure 10] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Figure 11] 11 is a diagram showing an example of a doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74 shown in FIG. [Figure 12] 13 is a diagram showing another example of the doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74. FIG. [Figure 13] 1A to 1C are diagrams illustrating an example of the structure of an accumulation region 16 sandwiched between dummy trench portions 30. [Figure 14] 13 is a diagram partially illustrating another example of the upper surface of the semiconductor device 100. FIG. [Figure 15] 15 is a diagram showing an example of a bb cross section of the semiconductor device 100 shown in FIG. [Figure 16A] 1 is a diagram showing an example of a mesa portion 94 in a boundary portion 90. FIG. [Figure 16B] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 16C] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 16D] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 17] 13 is a diagram showing another example of the bb cross section of the semiconductor device 100. FIG. [Figure 18] 13 is a diagram showing another example of the bb cross section of the semiconductor device 100. FIG. [Figure 19A] 1 is a diagram showing an example of a mesa portion 94 in a boundary portion 90. FIG. [Figure 19B] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 19C] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 19D] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 19E]13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 19F] 13 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. [Figure 20] 13 is a diagram showing another example of the bb cross section of the semiconductor device 100. FIG. [Figure 21A] FIG. 2 is a diagram showing an example of a trench portion. [Figure 21B] FIG. 13 is a diagram showing another example of the trench portion. [Figure 21C] FIG. 13 is a diagram showing another example of the trench portion. [Figure 21D] FIG. 13 is a diagram showing another example of the trench portion. [Figure 22] FIG. 1 is a top view illustrating an example of a semiconductor device 200 according to an embodiment of the present invention. [Figure 23] 2 is a diagram showing an example of a cc cross section of the semiconductor device 200. FIG. [Figure 24] 13 is a diagram showing another example of the cc cross section of the semiconductor device 200. FIG. [Diagram 25] FIG. 1 is a top view illustrating an example of a semiconductor device 300 according to an embodiment of the present invention. [Figure 26] 2 is a diagram showing an example of a dd cross section of the semiconductor device 300. FIG. [Figure 27] 13 is a diagram showing another example of the dd cross section of the semiconductor device 300. FIG. [Figure 28] 2 is a diagram showing an example of an ee cross section of the semiconductor device 300. FIG. [Figure 29] FIG. 1 is a top view showing an example of a semiconductor device 400 according to an embodiment of the present invention. [Diagram 30] 2 is a diagram showing an example of an ff cross section of the semiconductor device 400. FIG. [Diagram 31] 13 is a diagram showing another example of the ff cross section of the semiconductor device 400. FIG. [Diagram 32] 1 is a diagram showing an example of a gg cross section of a semiconductor device 400. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower". Of the two main surfaces of a substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity. In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis and Z-axis. The depth direction of the semiconductor substrate is the Z-axis.

[0032] Although the terms "emitter" and "collector" are used in this specification, the semiconductor device is not limited to an IGBT. The "source" and "drain" of a transistor such as a MOSFET may also be included in the scope of the terms "emitter" and "collector" in this specification.

[0033] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0034] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including transistors such as IGBTs. In FIG. 1, the top surface of the chip around the chip end is shown, and other regions are omitted.

[0035] 1 shows an active region of the semiconductor substrate in the semiconductor device 100, but the semiconductor device 100 may have a breakdown voltage structure surrounding the active region. The active region refers to a region through which current flows when the semiconductor device 100 is controlled to be in an on-state. The breakdown voltage structure relieves electric field concentration on the upper surface side of the semiconductor substrate. The breakdown voltage structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0036] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, an accumulation region 16, and a well region 11 formed inside a semiconductor substrate. The accumulation region 16 is not exposed on the upper surface of the semiconductor substrate. In FIG. 1, the region in which the accumulation region 16 is formed in the XY plane parallel to the upper surface of the semiconductor substrate is indicated by a dashed line. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 46 provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 46 are provided separately from each other.

[0037] An interlayer insulating film is formed between the emitter electrode 52 and the upper surface of the semiconductor substrate and between the gate electrode 46 and the upper surface of the semiconductor substrate, but is omitted in Fig. 1. In the interlayer insulating film of this example, contact holes 54, 55, and 56 are formed so as to penetrate the interlayer insulating film.

[0038] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate through a contact hole 54. In this example, the contact hole 54 is formed between each trench portion. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 57 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 57 is formed on the upper surface of the semiconductor substrate. In this example, the contact hole 56 is disposed at the tip of the dummy trench portion 30 in the X-axis direction. An insulating film is provided between the connection portion 57 and the semiconductor substrate 10.

[0039] The gate electrode 46 contacts the gate wiring 45 through the contact hole 55. The gate wiring 45 is formed of polysilicon doped with impurities or the like. The gate wiring 45 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 45 is not connected to the dummy conductive portion in the dummy trench portion 30. The gate wiring 45 in this example is formed from below the contact hole 55 to the tip portion 43 of the gate trench portion 40. At the tip portion 43 of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and contacts the gate wiring 45. An insulating film is provided between the gate wiring 45 and the semiconductor substrate 10.

[0040] The emitter electrode 52 and the gate electrode 46 are made of a material containing metal. For example, at least a portion of each electrode is made of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or the like, and may have a plug made of tungsten or the like in the contact hole.

[0041] The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction on the upper surface of the semiconductor substrate. The arrangement direction in FIG. 1 is the Y-axis direction.

[0042] The gate trench portion 40 in this example may have two extension portions 41 extending in parallel along an extension direction (the X-axis direction in this example) perpendicular to the arrangement direction, and a tip portion 43 connecting the two extension portions 41 at their tips. It is preferable that at least a part of the tip portion 43 is formed in a curved shape on the upper surface of the semiconductor substrate. By connecting the tips of the two extension portions 41 of the gate trench portion 40, electric field concentration at the end of the extension portion 41 can be alleviated.

[0043] One or more dummy trench portions 30 are provided between the respective extension portions 41 of the gate trench portion 40. The dummy trench portion 30 may have a tip portion connecting the tips of the two extension portions, similar to the gate trench portion 40. In this example, a dummy trench portion 30 having two extension portions and a tip portion is formed between the respective extension portions 41 of the gate trench portion 40. In other examples, the dummy trench portion 30 may have a linear shape without having a tip portion. The dummy trench portion 30 is provided at a position that does not overlap with the gate wiring 45.

[0044] The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is formed in a predetermined range from the end of the active region on the side where the gate electrode 46 is provided. The well region 11 in this example is of P+ type. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 46 side are formed in the well region 11. The bottom of the end of the dummy trench portion 30 in the extension direction may be covered by the well region 11.

[0045] A base region 14 is formed in the mesa portion between the trench portions inside the semiconductor substrate. The base region 14 is of P-type, which has a lower doping concentration than the well region 11.

[0046] A P+ type contact region 15 having a higher doping concentration than the base region 14 is formed on the upper surface of the base region 14 of the mesa portion. In addition, an N+ type emitter region 12 having a higher doping concentration than the semiconductor substrate is selectively formed on the upper surface of the base region 14.

[0047] Each of the contact region 15 and the emitter region 12 is formed from one adjacent trench portion to the other adjacent trench portion. The contact region 15 and the emitter region 12 are formed so as to be exposed alternately on the upper surface of the semiconductor substrate along the extension direction (X-axis direction) of the trench portion.

[0048] In another example of the mesa portion, the contact region 15 and the emitter region 12 may be formed in a stripe shape along the extension direction. For example, the emitter region 12 is formed in a region adjacent to the trench portion, and the contact region 15 is formed in a region sandwiched between the emitter regions 12.

[0049] The contact holes 54 are formed above the contact regions 15 and the emitter regions 12. The contact holes 54 are not formed in the regions corresponding to the base region 14 and the well region 11.

[0050] FIG. 2 is a diagram showing an example of the aa cross section in FIG. 1. The aa cross section in this example is a YZ plane. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 58. The interlayer insulating film 26 is silicate glass doped with impurities such as boron and phosphorus. The interlayer insulating film 26 is selectively formed on the upper surface of the semiconductor substrate 10. The emitter electrode 52 is formed on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 26. The collector electrode 58 is formed on the lower surface of the semiconductor substrate 10.

[0051] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0052] An N-type drift region 18 is formed in the semiconductor substrate 10. The drift region 18 in this example is a remaining region of the semiconductor substrate 10 where the emitter region 12, the base region 14, the accumulation region 16, the buffer region 20, and the collector region 22 are not formed.

[0053] A P-type base region 14 is formed between the upper surface of the semiconductor substrate 10 and the drift region 18. The base region 14 may be formed by implanting P-type impurities such as boron from the upper surface of the semiconductor substrate 10.

[0054] An N+ type emitter region 12 is formed on the upper surface of the base region 14. The emitter region 12 may be formed by injecting N type impurities such as phosphorus from the upper surface of the semiconductor substrate 10.

[0055] An N+ type accumulation region 16 is formed between the drift region 18 and the base region 14. The accumulation region 16 may be formed by implanting N type impurities such as phosphorus or protons from the upper surface of the semiconductor substrate 10.

[0056] In this example, the gate trench portion 40 and the dummy trench portion 30 are formed penetrating the emitter region 12, the base region 14, and the accumulation region 16 from the upper surface of the semiconductor substrate 10. The bottoms of the gate trench portion 40 and the dummy trench portion 30 in this example are disposed in the drift region 18. Note that the trench portion penetrating the impurity region is not limited to being manufactured in the order of forming the impurity region and then the trench portion. The trench portion penetrating the impurity region also includes a trench portion formed in which an impurity region is formed between the trench portions after the trench portions are formed.

[0057] The buffer region 20 is formed on the lower surface side of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22. The P+ type collector region 22 is formed on the lower surface side of the buffer region 20.

[0058] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is covered by the gate insulating film 42 inside the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0059] The gate conductive portion 44 includes at least a region facing the adjacent base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0060] The dummy trench portion 30 of this example has a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench portion 30 and is covered by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in this cross section is covered by the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10.

[0061] By providing the dummy trench portion 30, it is possible to enhance the carrier accumulation effect, promote conductivity modulation, and reduce the on-voltage. In addition, by adjusting the ratio of the dummy trench portion 30 to the gate trench portion 40, it is possible to adjust the switching speed of the semiconductor device 100.

[0062] When a predetermined on-voltage is applied to the gate conductive portion 44 to turn on the semiconductor device 100, a reverse bias is applied between the dummy conductive portion 34 and the drift region 18 at the bottom of the dummy trench portion 30. For example, when the width of the depletion layer in the drift region 18 narrows at the time of turn-on and the lower end of the depletion layer is near the bottom of the dummy trench portion 30, the voltage of the dummy conductive portion 34 is the ground potential and the voltage near the bottom of the dummy trench portion 30 is a predetermined positive voltage.

[0063] When a reverse bias is applied near the bottom of the dummy trench portion 30, holes may gather near the bottom of the dummy trench portion 30, forming a P-type inversion region. When a P-type inversion region is formed, holes injected into the drift region 18 escape to the emitter side through the inversion region and the base region 14, increasing turn-on loss.

[0064] In contrast, in the semiconductor device 100, at least one of the accumulation region 16 and the dummy trench portion 30 has an inhibition structure that inhibits the formation of a P-type inversion region in an N-type region (in this example, the drift region 18 and the accumulation region 16) adjacent to the dummy trench portion 30. In the example shown in FIG. 2, the dummy trench portion 30 has the inhibition structure.

[0065] In the dummy trench portion 30 of this example, the thickness of the dummy insulating film 32 is thicker than the thickness of the gate insulating film 42. The thickness of the dummy insulating film 32 may be the average thickness of the entire dummy insulating film 32. The thickness of the dummy insulating film 32 may be the average thickness of the dummy insulating film 32 formed between the dummy conductive portion 34 and the sidewall of the dummy trench in the Y-axis direction.

[0066] The thickness of the gate insulating film 42 may be the average thickness of the entire gate insulating film 42. The thickness of the gate insulating film 42 may be the average thickness of the gate insulating film 42 formed between the gate conductive portion 44 and the side wall of the gate trench in the Y-axis direction.

[0067] By forming the dummy insulating film 32 thick, the capacitance between the dummy conductive portion 34 and the drift region 18 can be reduced, and the number of holes gathering near the bottom of the dummy trench portion 30 can be reduced. Therefore, the formation of a P-type inversion region near the bottom of the dummy trench portion 30 can be suppressed.

[0068] 3 is an enlarged cross-sectional view of the vicinity of the gate trench portion 40 and the dummy trench portion 30. The thickness T1 of the dummy insulating film 32 may be two or more times the thickness T2 of the gate insulating film 42. The thickness T1 of the dummy insulating film 32 may be three or more times the thickness T2 of the gate insulating film 42, or may be four or more times the thickness T2 of the gate insulating film 42.

[0069] Moreover, it is preferable that the dummy insulating film 32 has a uniform thickness. The uniform thickness means, for example, that the error in the thickness of the dummy insulating film 32 at each position in one dummy trench portion 30 is within a range of ±20%. The error range may be within a range of ±10%. For example, the thickness T1 of the dummy insulating film 32 formed on the side wall of the dummy trench portion 30 and the thickness T2 of the dummy insulating film 32 formed on the bottom portion are uniform. However, since the diameter of the trench is likely to vary near the upper end of the dummy trench portion 30 and the boundary between the interlayer insulating film 26 and the dummy insulating film 32 is also unclear, it is sufficient that the dummy insulating film 32 has the above-mentioned uniform thickness in the region below the lower end of the emitter region 12. The gate insulating film 42 may also have a uniform thickness.

[0070] By making the dummy insulating film 32 have a uniform thickness, it becomes easier to inspect whether the thickness of the dummy insulating film 32 is formed as designed. In other words, when inspecting by applying a predetermined test voltage between the dummy conductive portion 34 and the semiconductor substrate 10, if the thickness of the dummy insulating film 32 is not uniform, the thin region will be broken down first, making it difficult to check whether the thickness of the thick region is the specified value. In contrast, by making the entire dummy insulating film 32 uniformly thick, it becomes easier to inspect the thickness of the dummy insulating film 32, and it can be easily confirmed whether the dummy insulating film 32 is formed to a thickness that can suppress the formation of a P-type inversion region.

[0071] The dummy trench portion 30 may be formed to protrude downward from the lower end 17 of the accumulation region 16. The lower end 35 of the dummy conductive portion 34 may be disposed below the lower end 17 of the accumulation region 16. In another example, the lower end 35 of the dummy conductive portion 34 may be disposed above the lower end of the accumulation region 16.

[0072] Fig. 4 is a diagram showing another example of the aa cross section in Fig. 1. In the semiconductor device 100 in this example, the structure of the dummy trench portion 30 is different from that in the example shown in Fig. 2. The other structures may be the same as those in the example shown in Fig. 2.

[0073] In the present embodiment, the dummy trench portion 30 is filled with an insulating material. The insulating material may be a dummy insulating film 32 formed by oxidizing or nitriding the inner wall of the trench, or may be an insulating film formed by a CVD method or the like, and may include a plurality of types of insulating films. No conductive material is provided inside the trench of the dummy trench portion 30. However, a cavity surrounded by an insulating material may be formed inside the trench of the dummy trench portion 30. By filling the trench of the dummy trench portion 30 with an insulating material, it is possible to suppress holes from gathering near the bottom of the dummy trench portion 30.

[0074] Fig. 5 is a diagram showing another example of the aa cross section in Fig. 1. In the semiconductor device 100 in this example, the length of the dummy trench portion 30 in the depth direction (Z-axis direction) is different from that in the example shown in Fig. 4. The other structures may be the same as those in the example shown in Fig. 4.

[0075] In the dummy trench portion 30 of this example, the inside of the trench is filled with an insulating material, similar to the example shown in Fig. 4. The dummy trench portion 30 shown in Fig. 4 is formed penetrating the accumulation region 16. That is, the lower end of the dummy trench portion 30 shown in Fig. 4 is disposed below the lower end of the accumulation region 16.

[0076] In contrast, the dummy trench portion 30 in this example does not penetrate the accumulation region 16. The lower end of the dummy trench portion 30 is disposed above the lower end of the accumulation region 16. In this example, the lower end of the dummy trench portion 30 is disposed within the accumulation region 16. By disposing the lower end of the dummy trench portion 30 within the high-concentration N+ type accumulation region 16, it is possible to further suppress the formation of a P type inversion region near the lower end of the dummy trench portion 30.

[0077] In yet another example, the dummy trench portion 30 may penetrate the accumulation region 16, but the length of the dummy trench portion 30 in the depth direction may be shorter than that of the gate trench portion 40. In other words, the distance between the lower end of the dummy trench portion 30 and the accumulation region 16 is shorter than the distance between the lower end of the gate trench portion 40 and the accumulation region 16. With such a structure, it is possible to suppress the formation of a P-type inversion region near the lower end of the dummy trench portion 30.

[0078] Fig. 6 is a diagram showing another example of the aa cross section in Fig. 1. In the semiconductor device 100 in this example, the length in the depth direction of the dummy trench portion 30 is different from the examples shown in Figs. 2 to 5. The other structure may be the same as any of the examples shown in Figs. 2 to 5.

[0079] The dummy trench portion 30 of this example is formed to a position shallower than the gate trench portion 40, penetrating the emitter region 12, the base region 14, and the accumulation region 16. The gate trench portion 40 is formed to a position deeper than the dummy trench portion 30, penetrating the emitter region 12, the base region 14, and the accumulation region 16.

[0080] The structure inside the trench of the dummy trench portion 30 may be the same as any of the examples shown in Figures 2 to 5, or may have another structure. The dummy trench portion 30 shown in Figure 6 has a dummy insulating film 32 and a dummy conductive portion 34. The film thickness of the dummy insulating film 32 may be the same as the film thickness of the gate insulating film 42, or may be different as shown in Figure 2.

[0081] By forming the dummy trench portion 30 shallowly, the bottom of the dummy trench portion 30 can be brought closer to the accumulation region 16. This makes it possible to suppress the formation of a P-type inversion region near the bottom of the dummy trench portion 30.

[0082] The distance in the depth direction between the lower end of the base region 14 and the lower end of the dummy trench portion 30 is defined as L1, and the distance in the depth direction between the lower end of the base region 14 and the lower end of the gate trench portion 40 is defined as L2. The distance L1 may be 3 / 4 or less, 2 / 3 or less, half or less, 1 / 3 or less, or 1 / 4 or less of the distance L2.

[0083] The width of the dummy trench portion 30 in the present example in the Y-axis direction may be smaller than that of the gate trench portion 40. This allows the shallow dummy trench portion 30 to be easily formed. The polysilicon of the dummy conductive portion 34 and the polysilicon of the gate conductive portion 44 may be formed in the same process or in different processes. By forming the polysilicon in different processes, the height positions of the polysilicon formed in each trench having a different depth can be easily aligned. The upper end of the dummy conductive portion 34 and the upper end of the gate conductive portion 44 may both be located at the same height position as the upper surface of the semiconductor substrate 10.

[0084] When the dummy conductive portion 34 and the gate conductive portion 44 are formed in separate steps, it is preferable to form one of the conductive portions before forming the trench of the other trench portion. This makes it possible to prevent the resist or the like used when forming one of the conductive portions from remaining in the other trench.

[0085] Fig. 7 is a diagram showing an example of a doping concentration distribution in the depth direction of the accumulation region 16 shown in Fig. 6. In Fig. 7, the positions in the depth direction of the bottom end 35 of the dummy conductive portion 34 and the bottom end 33 of the dummy trench portion 30 are shown together. The horizontal axis of Fig. 7 indicates the position in the depth direction based on the top surface position of the semiconductor substrate 10, and the vertical axis indicates the doping concentration in logarithm.

[0086] The doping concentration distribution in the accumulation region 16 has a peak 19 indicating a maximum value. In this example, in the depth direction of the semiconductor substrate 10, the peak 19 is located between the lower end 33 of the dummy insulating film 32 and the lower end 35 of the dummy conductive portion 34. The peak 19 may be located in the center between the lower end 33 of the dummy insulating film 32 and the lower end 35 of the dummy conductive portion 34, or may be located above the center, or may be located below the center.

[0087] This allows the position where the concentration of the N-type impurity reaches its peak to be located near the bottom of the dummy trench portion 30. This makes it possible to suppress the formation of a P-type inversion region near the bottom of the dummy trench portion 30.

[0088] In addition, in the depth direction of the semiconductor substrate 10, the lower end of the accumulation region 16 (i.e., the boundary with the drift region 18) may be located between the lower end 35 of the dummy conductive portion 34 and the lower end 33 of the dummy insulating film 32. In this case, the dummy trench portion 30 penetrates the accumulation region 16. In addition, when each member in each embodiment has a convex shape on the lower side, the lower end of each member refers to the tip of the convex shape.

[0089] Fig. 8 is a diagram showing another example of the aa cross section in Fig. 1. In the semiconductor device 100 in this example, the film thickness distribution of the dummy insulating film 32 in the dummy trench portion 30 is different from the examples shown in Figs. 2 to 7. The other structures may be the same as any of the examples shown in Figs. 2 to 7. In this example, the dummy insulating film 32 at the bottom of the dummy trench portion 30 is thicker than the dummy insulating film 32 on the sidewall of the dummy trench portion 30.

[0090] 9 is an enlarged cross-sectional view of the gate trench portion 40 and the dummy trench portion 30 shown in FIG. 8 and their vicinity. In this example, the gate insulating film 42 has a uniform thickness T3. In contrast, the dummy insulating film 32 has a thickness T5 at the bottom that is larger than the thickness T4 at the sidewall. The thickness T5 may be two or more times the thickness T4, or may be three or more times the thickness T4. The thickness T4 may be the same as the thickness T3.

[0091] The bottom of the dummy trench portion 30 may have a curved shape that is convex downward. In this case, the thickness T5 of the dummy insulating film 32 at the bottom may be the thickness at the bottom end of the convex shape. Furthermore, the thickness T4 of the dummy insulating film 32 at the sidewall may be the average thickness in the range facing the base region 14.

[0092] In this way, by increasing the film thickness of the dummy insulating film 32 at the bottom of the dummy trench portion 30, it is possible to suppress the collection of holes near the bottom of the dummy trench portion 30. As a result, it is possible to suppress the formation of a P-type inversion region near the bottom of the dummy trench portion 30.

[0093] As described above, the thickness distribution of the dummy insulating film 32 shown in FIG. 9 may be combined with the shallowly formed dummy trench portion 30 shown in FIG. 6. This can further suppress the formation of a P-type inversion region. Also, the doping concentration distribution structure shown in FIG. 7 may be further combined. As shown in FIG. 9, by increasing the thickness of the dummy insulating film 32 at the bottom of the dummy trench portion 30, it becomes easy to position the peak 19 of the doping concentration of the accumulation region 16 between the lower end 35 of the dummy conductive portion 34 and the lower end 33 of the dummy insulating film 32.

[0094] In this example, the lower end of the dummy insulating film 32 at the bottom of the dummy trench portion 30 is disposed below the lower end 17 of the accumulation region 16. Also, the lower end 35 of the dummy conductive portion 34 is disposed below the upper end of the accumulation region 16. The lower end 35 of the dummy conductive portion 34 may be disposed between the upper end and the lower end of the accumulation region 16. In another example, the lower end 35 of the dummy conductive portion 34 may be disposed between the upper end and the lower end of the base region 14, and may be disposed below the lower end 17 of the accumulation region 16.

[0095] Fig. 10 is a diagram showing another example of the aa cross section in Fig. 1. In the semiconductor device 100 in this example, the structure of the accumulation region 16 is different from the examples shown in Fig. 2 to Fig. 9. The other structures may be the same as any of the examples shown in Fig. 2 to Fig. 9.

[0096] In this example, the region of the accumulation region 16 adjacent to the dummy trench portion 30 is referred to as a dummy adjacent region 74, and the region adjacent to the gate trench portion 40 is referred to as a gate adjacent region 72. When the width of the accumulation region 16 in the Y-axis direction is W, the gate adjacent region 72 and the dummy adjacent region 74 may each refer to a region having a width of about W / 4 from the position where they contact the corresponding trench portion.

[0097] In this example, the integral concentration obtained by integrating the doping concentration in the dummy-adjacent region 74 in the depth direction of the semiconductor substrate 10 is higher than the integral concentration obtained by integrating the doping concentration in the depth direction in the gate-adjacent region 72. The integral concentration in the dummy-adjacent region 74 may be 1.5 times or more, or may be two times or more, the integral concentration in the gate-adjacent region 72.

[0098] In the example shown in FIG. 10, the dummy adjacent region 74 is formed to a position deeper than the gate adjacent region 72. That is, the length of the dummy adjacent region 74 in the depth direction is longer than the gate adjacent region 72. The length of the dummy adjacent region 74 in the depth direction may be 1.5 times or more, or may be twice or more, the length of the gate adjacent region 72 in the depth direction. The length of the dummy adjacent region 74 in the depth direction may be the length of the portion in contact with the dummy trench portion 30. The length of the gate adjacent region 72 in the depth direction may be the length of the portion in contact with the gate trench portion 40. This makes it possible to make the integrated concentration of the dummy adjacent region 74 higher than the integrated concentration of the gate adjacent region 72.

[0099] By increasing the integrated concentration in the accumulation region 16 adjacent to the dummy trench portion 30, it is possible to suppress the collection of holes near the bottom of the dummy trench portion 30. This makes it possible to suppress the formation of a P-type inversion region.

[0100] 10, the depth positions of the lower surfaces of the gate-adjacent region 72 and the dummy-adjacent region 74 are shown as being stepped, but the lower surfaces of the gate-adjacent region 72 and the dummy-adjacent region 74 may be curved. Also, the accumulation region 16 sandwiched between the dummy trench portions 30 may be formed entirely at the same depth as the dummy-adjacent region 74.

[0101] Fig. 11 is a diagram showing an example of the doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74 shown in Fig. 10. The horizontal axis of Fig. 11 indicates the position in the depth direction based on the upper surface position of the semiconductor substrate 10, and the vertical axis indicates the doping concentration in logarithm. Note that Fig. 11 shows the doping concentration distribution in the portions adjacent to the trench portions.

[0102] In this example, the dummy adjacent region 74 is formed to a deeper position than the gate adjacent region 72. In this example, the dummy adjacent region 74 has more peaks in the doping concentration distribution than the gate adjacent region 72. In the example of Fig. 11, the gate adjacent region 72 has one peak 76, and the dummy adjacent region 74 has a first peak 77 and a second peak 78 that is located deeper than the first peak 77.

[0103] Each peak can be formed by implanting an impurity such as a proton at a plurality of depth positions with different ranges. The depth position of the peak 76 in the gate adjacent region 72 and the first peak 77 in the dummy adjacent region 74 may be the same. The doping concentration D1 of the peak 76 and the doping concentration D2 of the first peak 77 may also be the same.

[0104] The doping concentration D3 of the second peak 78 may be greater than both the doping concentration D1 of the peak 76 and the doping concentration D2 of the first peak 77. By increasing the doping concentration of the second peak 78 located closer to the bottom of the dummy trench portion 30, it is possible to efficiently suppress the formation of a P-type inversion region near the bottom of the dummy trench portion 30. The doping concentration D3 may be 1.5 times or more, or may be twice or more, the doping concentration D2.

[0105] 12 is a diagram showing another example of the doping concentration distribution in the gate-adjacent region 72 and the dummy-adjacent region 74. In this example, the dummy-adjacent region 74 and the gate-adjacent region 72 have the same length in the depth direction. In this example, the dummy-adjacent region 74 has the same number of peaks in the doping concentration distribution as the gate-adjacent region 72. In the example of FIG. 12, the gate-adjacent region 72 and the dummy-adjacent region 74 each have one peak.

[0106] However, the peak doping concentration in the dummy adjacent region 74 is higher than the peak doping concentration in the gate adjacent region 72. With such a structure, the integral concentration in the dummy adjacent region 74 can be increased, and the formation of a P-type inversion region near the bottom of the dummy trench portion 30 can be suppressed.

[0107] The peak doping concentration in the dummy-adjacent region 74 may be 1.5 times or more, or may be two times or more, the peak doping concentration in the gate-adjacent region 72. The peak in the dummy-adjacent region 74 and the peak in the gate-adjacent region 72 may be located at the same depth position.

[0108] 13 is a diagram showing a structural example of an accumulation region 16 sandwiched between dummy trench portions 30. The accumulation region 16 has two dummy adjacent regions 74 adjacent to each dummy trench portion 30, and a central region 79 sandwiched between the two dummy adjacent regions 74. The central region 79 is disposed in the center between the two dummy trench portions 30 in the Y-axis direction.

[0109] In this example, the integrated concentration obtained by integrating the doping concentration in the depth direction in the central region 79 is lower than the integrated concentration in the dummy adjacent region 74. The integrated concentration in the central region 79 may be the integrated concentration at the center between the two dummy trench portions 30 in the Y-axis direction. The integrated concentration in the dummy adjacent region 74 may be the integrated concentration of the portion in contact with the dummy trench portion 30. With this structure, holes can be extracted to the emitter side via the central region 79 at the time of turn-off, etc.

[0110] The integrated concentration in the central region 79 may be 1.5 times or more, or may be two times or more, of the integrated concentration in the dummy adjacent region 74. In the example of FIG. 13, the length of the central region 79 in the depth direction is shorter than the length of the dummy adjacent region 74 in the depth direction. The length of the central region 79 may be 2 / 3 or less, or may be half or less, of the length of the dummy adjacent region 74. In addition, the peak of the doping concentration in the central region 79 may be lower than the peak of the doping concentration in the dummy adjacent region 74. The central region 79 may have the same doping concentration distribution in the depth direction as the gate adjacent region 72.

[0111] 14 is a diagram partially illustrating another example of the upper surface of the semiconductor device 100. The semiconductor device 100 of this example has a transistor section 70 including a transistor such as an IGBT, and a diode section 80 including a diode such as an FWD (Free Wheel Diode), both provided on a semiconductor substrate 10. A boundary section 90 is provided between the transistor section 70 and the diode section 80 on the upper surface of the semiconductor substrate 10. The structure of the transistor section 70 may be the same as that of any of the semiconductor devices 100 described with reference to FIGS. 1 to 13.

[0112] One or more dummy trench portions 30 are arranged along the Y-axis direction in each of the diode portion 80 and the boundary portion 90. The dummy trench portions 30 in the diode portion 80 and the boundary portion 90 may have the same shape and structure as the dummy trench portions 30 in the transistor portion 70.

[0113] A base region 14 is formed in the mesa portion of the diode portion 80 and the boundary portion 90. A contact region 15 is selectively formed in a portion of the base region 14 in the mesa portion of the boundary portion 90. The contact region 15 in the boundary portion 90 is an example of a high concentration region of the second conductivity type. In the boundary portion 90, the contact region 15 may be formed in a region facing the emitter region 12 and the contact region 15 of the adjacent transistor portion 70 across the dummy trench portion 30. The contact region 15 in the boundary portion 90 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0114] 14, the mesa portion of the diode portion 80 does not have the emitter region 12 and the contact region 15 formed therein, but at least one of the emitter region 12 and the contact region 15 may be formed in the mesa portion. The base region 14 of the diode portion 80 is connected to the emitter electrode 52 via a contact hole 54.

[0115] In the diode portion 80 and the boundary portion 90, the contact holes 54 are formed above the contact region 15 and the base region 14. In this example, the contact holes 54 in the transistor portion 70, the diode portion 80 and the boundary portion 90 have the same length in the longitudinal direction of each trench portion.

[0116] The diode section 80 is a region that overlaps with the cathode region 82 in a direction perpendicular to the bottom surface of the semiconductor substrate 10. The transistor section 70 is a region that overlaps with the collector region 22 in a direction perpendicular to the bottom surface of the semiconductor substrate 10, in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged. The boundary section 90 is a region that overlaps with the collector region 22 in a direction perpendicular to the bottom surface of the semiconductor substrate 10, in which predetermined unit configurations including the emitter region 12 and the contact region 15 are not regularly arranged.

[0117] Fig. 15 is a diagram showing an example of a bb cross section of the semiconductor device 100 shown in Fig. 14. The bb cross section is parallel to the YZ plane and passes through the emitter region 12 of the transistor section 70, the contact region 15 of the boundary section 90, and the base region 14 of the diode section 80. The structure of the transistor section 70 may be the same as any of the semiconductor devices 100 described in Figs. 1 to 13. The transistor section 70 shown in Fig. 15 has the same structure as the semiconductor device 100 shown in Fig. 10.

[0118] A region sandwiched between the trench portions is referred to as a mesa portion 94. In Fig. 15, only the mesa portion 94 in the boundary portion 90 is labeled with a reference symbol, but in the transistor portion 70 and the diode portion 80, the region sandwiched between the trench portions is also referred to as a mesa portion 94.

[0119] In this example, the transistor portion 70 refers to a region in the mesa portion 94 on the upper surface side of the semiconductor substrate 10 where the emitter region 12 is provided and the collector region 22 is provided on the lower surface side of the semiconductor substrate 10. The boundary portion 90 refers to a region in the mesa portion 94 on the upper surface side of the semiconductor substrate 10 where the emitter region 12 is not provided and the collector region 22 is provided on the lower surface side of the semiconductor substrate 10. In the mesa portion 94 of the boundary portion 90 in this example, the contact region 15 and the base region 14 are provided in this order from the upper surface side of the semiconductor substrate 10.

[0120] The diode section 80 refers to a region in which a cathode region 82 of a first conductivity type is provided on the lower surface side of the semiconductor substrate 10. The cathode region 82 in this example is N+ type. In the example shown in FIG. 15, a base region 14 is formed in a mesa portion 94 of the diode section 80, and an emitter region 12 is not formed. The cathode region 82 in the diode section 80 in this example is formed at the same depth position as the collector region 22. A buffer region 20 may be formed above the cathode region 82.

[0121] Since the transistor section 70 and the diode section 80 have different layer structures including pn junctions, the electric field distribution is likely to be unbalanced. Therefore, if carriers are accumulated near the boundary between the transistor section 70 and the diode section 80, the avalanche resistance of the semiconductor device 100 decreases. By providing the boundary section 90 in the semiconductor device 100, carriers (e.g., holes) can be easily extracted to the emitter electrode 52 between the transistor section 70 and the diode section 80. Therefore, the avalanche resistance of the semiconductor device 100 can be improved. In addition, since the distance between the transistor section 70 and the cathode region 82 can be increased, carrier injection from the transistor section 70 to the diode section 80 can be suppressed when the semiconductor device 100 is in the on state or when it is turned off.

[0122] The accumulation region 16 may not be formed in at least a part of the mesa portion 94 of the boundary portion 90. In other words, the accumulation region 16 may be selectively formed below the base region 14 in the mesa portion 94 of the boundary portion 90, or the accumulation region 16 may not be formed at all. When the accumulation region 16 is selectively formed, it is preferable that the accumulation region 16 is formed adjacent to the dummy trench portion 30 closer to the transistor portion 70 among the dummy trench portions 30 sandwiching the mesa portion 94. This makes it possible to suppress the formation of a p-type inversion region at the bottom of the dummy trench portion 30 closer to the transistor portion 70, and to reduce the influence on the operation of the transistor portion 70.

[0123] 16A is a diagram showing an example of a mesa portion 94 of a boundary portion 90. In this example, of the dummy trench portions 30 sandwiching the mesa portion 94, the one closer to the transistor portion 70 is referred to as a dummy trench portion 30-1, and the one closer to the diode portion 80 is referred to as a dummy trench portion 30-2. In the mesa portion 94 of this example, an accumulation region 16 is formed in a region adjacent to the dummy trench portion 30-1, and an accumulation region 16 is not formed in a region adjacent to the dummy trench portion 30-2.

[0124] With this structure, it is possible to easily extract holes through the mesa portion 94 while suppressing the formation of a hole inversion region at the bottom of the dummy trench portion 30-1. Furthermore, since the accumulation region 16 is not provided in the region adjacent to the dummy trench portion 30-2, even if the width of the mesa portion 94 is reduced by miniaturizing the semiconductor device 100, it is possible to easily ensure a region without the accumulation region 16. The width in the Y-axis direction of the accumulation region 16 in the mesa portion 94 of the boundary portion 90 may be half or less, or may be one-third or less, of the width of the mesa portion 94.

[0125] 16B is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The accumulation region 16 in the mesa portion 94 of this example has a shape similar to that of the accumulation region 16 shown in FIG. 13. In the mesa portion 94 of the boundary portion 90 of this example, the accumulation region 16 is formed so as to cover the entire lower surface of the base region 14. However, the accumulation region 16 has a dummy adjacent region 74 for each of the dummy trench portion 30-1 and the dummy trench portion 30-2. Also, the accumulation region 16 has a central region 79 in the central region of the mesa portion 94 in the Y-axis direction.

[0126] The dummy adjacent region 74 and the central region 79 are the same as the dummy adjacent region 74 and the central region 79 shown in FIG. 13. That is, the integrated concentration in the dummy adjacent region 74 is higher than the integrated concentration in the central region 79. The dummy adjacent region 74 in the example of FIG. 16B is formed below the central region 79. The accumulation region 16 may have two dummy adjacent regions 74 and not have the central region 79. In this case, at least one of the base region 14 and the drift region 18 is formed in the region where the central region 79 is provided in FIG. 16B.

[0127] With this structure, it is possible to suppress the formation of an inversion region even in the dummy trench portion 30 at the boundary portion 90. Furthermore, by reducing the integrated concentration of impurities near the center of the mesa portion 94, carrier extraction at the boundary portion 90 becomes easier.

[0128] 16C is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The accumulation region 16 in the mesa portion 94 of this example has a dummy adjacent region 74 adjacent to the dummy trench portion 30-1, and does not have a dummy adjacent region 74 in the region adjacent to the dummy trench portion 30-2. The central region 79 extends to the region adjacent to the dummy trench portion 30-2. With this structure, holes can be easily extracted through the mesa portion 94 while suppressing the formation of an inversion region at the bottom of the dummy trench portion 30-1.

[0129] 16D is a diagram showing another example of the mesa portion 94 at the boundary portion 90. In this example, the accumulation region 16 is not provided in the mesa portion 94 at the boundary portion 90. With this structure, holes can be easily extracted at the boundary portion 90.

[0130] FIG. 17 is a diagram showing another example of the bb cross section of the semiconductor device 100. The boundary portion 90 of this example has a plurality of mesa portions 94. Each of the mesa portions 94 may have any of the structures described in FIG. 16A to FIG. 16D. The width of the accumulation region 16 in the Y-axis direction of any of the mesa portions 94 may be smaller than that of the mesa portion 94 closer to the transistor portion 70. As an example, the width of the accumulation region 16 of the mesa portion 94-3 adjacent to the diode portion 80 (zero in the example of FIG. 17) is smaller than the width of the accumulation region 16 of the mesa portion 94-1 adjacent to the transistor portion 70.

[0131] With this structure, it is possible to suppress the formation of an inversion region at the bottom of the dummy trench portion 30 in the mesa portion 94 near the transistor portion 70. Also, in the mesa portion 94 away from the transistor portion 70, carriers can be efficiently extracted.

[0132] 15 to 17, the doping concentration of the accumulation region 16 at the boundary 90 may be higher than the doping concentration of the accumulation region 16 at the center in the Y-axis direction of the transistor section 70. The doping concentration of the accumulation region 16 may be a peak concentration. This reduces carrier accumulation in a region of the transistor section 70 away from the boundary 90, making it easier to extract carriers via the boundary 90.

[0133] Fig. 18 is a diagram showing another example of the bb cross section of the semiconductor device 100. The transistor section 70 of this example has the same structure as the semiconductor device 100 shown in Fig. 6. That is, the dummy trench portion 30 in the transistor section 70 is formed shallower than the gate trench portion 40.

[0134] In this example, at least a portion of the dummy trench portion 30 in the boundary portion 90 and the diode portion 80 is also formed shallower than the gate trench portion 40. In the example of FIG. 18, all of the dummy trench portions 30 in the boundary portion 90 and the diode portion 80 are formed shallower than the gate trench portion 40. The dummy trench portions 30 in the boundary portion 90 and the diode portion 80 may be formed to the same depth as the dummy trench portions 30 in the transistor portion 70.

[0135] 19A is a diagram showing an example of a mesa portion 94 of the boundary portion 90. The dummy trench portion 30-1 and the dummy trench portion 30-2 of this example are formed shallower than the gate trench portion 40. In the mesa portion 94 of this example, the accumulation region 16 is formed so as to cover the entire lower surface of the base region 14. With this structure, it is possible to suppress the formation of an inversion region at the bottom of the dummy trench portion 30-1 and the dummy trench portion 30-2.

[0136] FIG. 19B is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19A, except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. The dummy trench portion 30-2 may be formed to the same depth as the gate trench portion 40. Note that the deeper each trench portion is formed, the larger the width in the Y-axis direction. This structure can also suppress the formation of inversion regions at the bottoms of the dummy trench portion 30-1 and the dummy trench portion 30-2.

[0137] 19C is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19A except that the accumulation region 16 is selectively formed. The accumulation region 16 of this example is formed in a region adjacent to the dummy trench portion 30-1, and is not formed in a region adjacent to the dummy trench portion 30-2. With this structure, it is possible to suppress the formation of an inversion region at the bottom of the dummy trench portion 30-1, and to easily extract carriers at the boundary portion 90.

[0138] 19D is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19C, except that an accumulation region 16 is also formed in the region adjacent to the dummy trench portion 30-2. The accumulation region 16 is not formed in the region near the center of the mesa portion 94 in the Y-axis direction. With this structure, it is possible to suppress the formation of an inversion region at the bottom of each dummy trench portion 30, and to easily extract carriers at the boundary portion 90.

[0139] 19E is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19C except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. With this structure, it is possible to suppress the formation of an inversion region at the bottom of the dummy trench portion 30-1 and to easily extract carriers at the boundary portion 90.

[0140] FIG. 19F is a diagram showing another example of the mesa portion 94 of the boundary portion 90. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19D, except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. Even with such a structure, it is possible to suppress the formation of an inversion region at the bottom of each dummy trench portion 30, and to easily extract carriers at the boundary portion 90. The mesa portion 94 of the boundary portion 90 may have the same structure as any of the examples shown in FIGS. 16A to 16D. Also, each of the examples shown in FIGS. 19A to 19F may be applied to the semiconductor device 100 shown in FIG. 14.

[0141] Fig. 20 is a diagram showing another example of the bb cross section of the semiconductor device 100. In the semiconductor device 100 of this example, the dummy trench portion 30 provided in the diode portion 80 has a larger width in the Y-axis direction than the dummy trench portion 30 provided in the transistor portion 70. The other structure is the same as any one of the semiconductor devices 100 described in Fig. 14 to Fig. 19F. The pitch at which the trench portions are arranged is uniform.

[0142] With this structure, the width of the mesa portion 94 in the diode portion 80 is reduced. This makes it possible to suppress carrier injection into the mesa portion 94. The dummy trench portion 30 in the diode portion 80 may have the same width as the gate trench portion 40. Even if the dummy trench portion 30 in the diode portion 80 is formed deep and a hole inversion region is easily formed at the bottom, the dummy trench portion 30 is separated from the transistor portion 70, and therefore the effect on the operation of the semiconductor device 100 is small.

[0143] 21A is a diagram showing an example of a trench portion. The dummy trench portion 30 of this example includes a trench thin film portion 37 and a trench thick film portion 38. Two accumulation regions, 16-1 and 16-2, are formed below the base region 14. The accumulation region 16-1 is an example of a first accumulation region provided below the base region 14, and the accumulation region 16-2 is an example of a second accumulation region provided between the accumulation region 16-1 and the drift region 18.

[0144] The trench thin-film portion 37 has a dummy insulating film 32 with a predetermined thickness on the inner wall of the trench portion. The trench thin-film portion 37 also has a dummy conductive portion 34 covered with the dummy insulating film 32 in the dummy trench portion 30. The lower end of the trench thin-film portion 37 is formed deeper than the lower end of the base region 14. In this example, the lower end of the trench thin-film portion 37 is located at the same depth as at least a part of the region in which the accumulation region 16-1 is formed. In the trench thin-film portion 37, the dummy conductive portion 34 has a uniform width in the Y-axis direction. That is, the lower end of the trench thin-film portion 37 corresponds to the lower end of the dummy conductive portion 34.

[0145] The trench thick film portion 38 has a dummy insulating film 32 on the inner wall of the trench portion that is thicker than the trench thin film portion 37. The dummy conductive portion 34 is provided in the trench thin film portion 37, but not in the trench thick film portion 38. The trench thick film portion 38 is formed at a position deeper than the base region 14. By providing the trench thick film portion 38, the capacitance between the dummy conductive portion 34 and the drift region 18 can be reduced, and the number of holes that gather near the bottom of the dummy trench portion 30 can be reduced. This makes it possible to suppress the formation of a P-type inversion region near the bottom of the dummy trench portion 30. Therefore, the turn-on loss is reduced.

[0146] In this example, since a plurality of accumulation regions 16 are formed in the mesa portion 94 between the dummy trench portions 30, it is possible to suppress the extraction of carriers via the P-type inversion region at the bottom of the dummy trench portion 30 at the time of turn-on. In addition, it is possible to reduce an increase in turn-on loss while maintaining the reduction in Von voltage due to miniaturization.

[0147] Fig. 21B is a diagram showing another example of the trench portion, which differs from the case of Fig. 21A in that the dummy conductive portion 34 is provided in both the trench thin portion 37 and the trench thick portion 38.

[0148] The dummy conductive portion 34 has a different width in the Y-axis direction between the trench thin film portion 37 and the trench thick film portion 38. In this example, the dummy conductive portion 34 has a width in the Y-axis direction larger in the trench thin film portion 37 than in the trench thick film portion 38. As a result, the dummy insulating film 32 in the trench thin film portion 37 is thinner than the dummy insulating film 32 in the trench thick film portion 38. The trench thick film portion 38 is formed at a position deeper than the base region 14. In addition, the lower end of the dummy conductive portion 34 is formed deeper than the lower end of the accumulation region 16-2. Therefore, the formation of a P-type inversion region near the bottom of the dummy trench portion 30 is suppressed, and the effect of reducing turn-on loss is high.

[0149] 21C is a diagram showing another example of the trench portion. In the dummy trench portion 30 of this example, the thin trench portion 37 and the thick trench portion 38 have different widths in the Y-axis direction. The dummy conductive portion 34 is provided in both the thin trench portion 37 and the thick trench portion 38.

[0150] The dummy trench portion 30 has a smaller width in the Y-axis direction in the trench thin film portion 37 than the trench thick film portion 38. On the other hand, the dummy conductive portion 34 has a uniform width in the Y-axis direction in the trench thin film portion 37 and the trench thick film portion 38. That is, the dummy insulating film 32 in the trench thick film portion 38 is thicker than the dummy insulating film 32 in the trench thin film portion 37. This suppresses the formation of a P-type inversion region near the bottom of the dummy trench portion 30, thereby reducing turn-on loss. The trench thick film portion 38 is formed at a position deeper than the base region 14.

[0151] Fig. 21D is a diagram showing another example of the trench portion. This example differs from the case of Fig. 21C in that the mesa portion 94 sandwiched between the dummy trench portions 30 has three accumulation regions 16-1, 16-2, and 16-3. The accumulation region 16-3 is an example of a third accumulation region provided between the accumulation region 16-1 and the accumulation region 16-2.

[0152] 21A to 21D have been described with reference to the dummy trench portion 30. However, the gate trench portion 40 may also have the structure of the dummy trench portion 30 disclosed in FIGS. 21A to 21D.

[0153] 21A to 21D have been described with respect to the mesa portion 94 sandwiched between adjacent dummy trench portions 30. However, the mesa portion 94 sandwiched between the dummy trench portion 30 and the gate trench portion 40 may also have the structure of the mesa portion 94 disclosed in FIG. 21A to 21D. The same is true for the mesa portion 94 sandwiched between adjacent gate trench portions 40.

[0154] 22 is a top view showing an example of a semiconductor device 200 according to an embodiment of the present invention. The semiconductor device 200 may include a gate trench portion 40 and a dummy trench portion 30 arranged in the same manner as the semiconductor device 100.

[0155] In the semiconductor device 200, the base region 14 disposed in at least a part of the mesa portions 94 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is not directly connected to the emitter electrode 52. In the example of FIG. 22, the base region 14 in a part of the mesa portions 94 sandwiched between the gate trench portion 40 and the dummy trench portion 30, that is, a mesa portion 94-2, is not connected to the emitter electrode 52 on the upper surface of the semiconductor substrate 10. In this example, in the mesa portion 94-2, a contact hole 54 is not disposed in the interlayer insulating film 26 between the emitter electrode 52 and the base region 14. As an example, the mesa portion 94-2 is a mesa portion 94 disposed on both sides in the Y-axis direction of one of the mesa portions 94-1 sandwiched between the two dummy trench portions 30.

[0156] The mesa portion 94-2 does not necessarily have to have the emitter region 12. In the mesa portion 94-2 of this example, a base region 14 is provided over the entire region inside the well region 11 on the upper surface of the semiconductor substrate 10.

[0157] A contact hole 54 is arranged in the mesa portion 94-1 and the mesa portion 94-3. The structure of the mesa portion 94-1 and the mesa portion 94-3 on the upper surface of the semiconductor substrate 10 may be the same as or different from that of the semiconductor device 100 shown in FIG. 1 to FIG. 21D. In this example, the mesa portion 94-1 and the mesa portion 94-3 are arranged such that the emitter region 12 extends in the X-axis direction between the contact hole 54 and each trench portion on the upper surface of the semiconductor substrate 10. A contact region 15 is arranged below the contact hole 54 and extends in the X-axis direction, but is omitted in FIG. 22.

[0158] Of the mesa portions 94 sandwiched between the gate trench portion 40 and the dummy trench portion 30, the base region 14 disposed in a part of the mesa portion 94-2 is not in direct contact with the emitter electrode 52, thereby suppressing extraction of holes in the mesa portion 94-2 and promoting carrier accumulation. As a result, the on-voltage of the semiconductor device 200 can be reduced.

[0159] Moreover, it is preferable that two or less dummy trench portions 30 are disposed between two gate trench portions 40. Among the trench portions, each extension portion that extends linearly in the X-axis direction on the upper surface of the semiconductor substrate 10 is regarded as one trench portion. In the example of FIG. 22, two dummy trench portions 30 are disposed between the two gate trench portions 40.

[0160] In this example, the gate trench portion 40 is directly connected to the gate electrode 46 via a contact hole 55. Moreover, the dummy trench portion 30 is directly connected to the emitter electrode 52 via a contact hole 56. In other words, the semiconductor device 200 of this example does not include a connection portion 57 and a gate wiring 45. With this structure, steps due to the connection portion 57 and the like are eliminated, and the semiconductor device 200 can be easily miniaturized.

[0161] 23 is a diagram showing an example of a cc cross section of the semiconductor device 200. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in FIG. 2. In another example, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in FIGS. 1 to 21D. In addition, each doping region in the mesa portion 94-1 and the mesa portion 94-3 may have the same structure as each doping region in the mesa portion 94 shown in FIGS. 1 to 20.

[0162] The mesa portion 94-1 and the mesa portion 94-3 of this example have a contact region 15 below the contact hole 54. On both sides of the contact region 15, an emitter region 12 is provided.

[0163] The contact region 15 and the emitter region 12 are electrically connected to the emitter electrode 52. The mesa portion 94-1 and the mesa portion 94-3 in this example have a connection portion 96 provided from the upper surface to the inside of the semiconductor substrate 10. The connection portion 96 is in contact with each of the contact region 15, the emitter region 12, and the emitter electrode 52. The connection portion 96 has a lower electrical resistance than the contact region 15. As an example, the connection portion 96 is formed of a metal such as tungsten. The emitter region 12 contacts the side surface of the connection portion 96, and the contact region 15 contacts the bottom surface. With this structure, even if the semiconductor device 200 is miniaturized, electrical connection between the emitter electrode 52 and the contact region 15 and the emitter region 12 is easy.

[0164] Moreover, a connection portion 96 may also be provided in the dummy conductive portion 34 of the dummy trench portion 30. The connection portion 96 is provided below the contact hole 56. The connection portion 96 is connected to the emitter electrode 52 via the contact hole 56.

[0165] Fig. 24 is a diagram showing another example of a cc cross section of the semiconductor device 200. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in Fig. 2. The other structures are the same as those of the semiconductor device 200 shown in Fig. 23.

[0166] The semiconductor device 200 may have a dummy trench portion 30 as shown in Figures 1 to 21D. In other words, the structure in which the base region 14 is not connected to the emitter electrode 52 in any of the mesa portions 94 shown in Figures 22 to 24 may be applied to each of the semiconductor devices 100 in Figures 1 to 21D.

[0167] Fig. 25 is a top view showing an example of a semiconductor device 300 according to an embodiment of the present invention. The semiconductor device 300 of this example differs from the semiconductor devices shown in Fig. 1 to Fig. 24 in the shape and arrangement of the dummy trench portions 30 on the upper surface of the semiconductor substrate 10. Other structures may be similar to any of the semiconductor devices shown in Fig. 1 to Fig. 24.

[0168] In the semiconductor device 300, one or less dummy trench portions 30 are arranged between each of the gate trench portions 40. The dummy trench portions 30 in this example extend linearly in the X-axis direction on the upper surface of the semiconductor substrate 10. In this example, one linear dummy trench portion 30 is arranged between two extension portions 41 connected at the tip portions 43 in the gate trench portion 40.

[0169] By sandwiching each of the dummy trenches 30 between the gate trenches 40, it is possible to promote the disappearance of the depletion layer near the dummy trenches 30 when the device is turned on. This makes it possible to efficiently modulate the conductivity when the device is turned on, thereby reducing turn-on loss.

[0170] Fig. 26 is a diagram showing an example of a dd cross section of the semiconductor device 300. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in Fig. 2. In another example, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in Figs. 1 to 21D. Furthermore, each doping region in the mesa portion 94 may have the same structure as each doping region in the mesa portion 94 shown in Figs. 1 to 20.

[0171] Fig. 27 is a diagram showing another example of a dd cross section of the semiconductor device 300. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in Fig. 2. The other structures are the same as the semiconductor device 200 shown in Fig. 26. The structures shown in Figs. 25 to 27 in which one or less dummy trench portions 30 are provided between each gate trench portion 40 may be applied to each of the semiconductor devices shown in Figs. 1 to 24.

[0172] 28 is a diagram showing an example of an ee cross section of the semiconductor device 300. The ee cross section is an XZ plane passing near the dummy trench portion 30. In the range in which the contact holes 54 are provided in the X-axis direction, the contact regions 15 and the emitter regions 12 are alternately arranged on the upper surface of the semiconductor substrate 10. In the range in which the contact holes 54 are not provided, the base regions 14 and the well regions 11 are arranged on the upper surface of the semiconductor substrate 10.

[0173] The gate trench portion 40 is disposed so as to be surrounded by the well region 11. The gate trench portion 40 is connected to a gate electrode 46 via a gate wiring 45 disposed above the upper surface of the semiconductor substrate 10. An insulating film is formed between the gate wiring 45 and the upper surface of the semiconductor substrate 10.

[0174] Fig. 29 is a top view showing an example of a semiconductor device 400 according to an embodiment of the present invention. The semiconductor device 400 of this example differs from the semiconductor devices shown in Figs. 1 to 24 in the shape and arrangement of the dummy trench portion 30 and the gate trench portion 40 on the upper surface of the semiconductor substrate 10. Other structures may be similar to those of the semiconductor devices shown in Figs. 1 to 24.

[0175] The semiconductor device 400 includes a first gate trench portion 40-1, a second gate trench portion 40-2, and a dummy trench portion 30. The semiconductor device 400 may include a plurality of trench sets, each including the first gate trench portion 40-1, the second gate trench portion 40-2, and the dummy trench portion 30, arranged along the Y-axis direction on the upper surface of the semiconductor substrate 10.

[0176] Each of the first gate trench portion 40-1 and the second gate trench portion 40-2 has an extension portion 41-1, an extension portion 41-2, and a tip portion 43. The extension portion 41-1 and the extension portion 41-2 are provided to extend parallel to the X-axis direction on the upper surface of the semiconductor substrate 10. The tip portion 43 connects the tips of the two extension portions 41.

[0177] The dummy trench portion 30 has an extension portion 31-1, an extension portion 31-2, and a tip portion 36. The extension portion 31-1 and the extension portion 31-2 are provided to extend parallel to the X-axis direction on the upper surface of the semiconductor substrate 10. The tip portion 36 connects the tips of the two extension portions 31.

[0178] The dummy trench portion 30 is disposed inside the first gate trench portion 40-1 on the upper surface of the semiconductor substrate 10. That is, on the upper surface of the semiconductor substrate 10, the two extension portions 31 of the dummy trench portion 30 are disposed in a region sandwiched between the two extension portions 41 of the first gate trench portion 40-1.

[0179] On the upper surface of the semiconductor substrate 10, the second gate trench portion 40-2 is disposed inside the dummy trench portion 30. That is, on the upper surface of the semiconductor substrate 10, the two extension portions 41 of the second gate trench portion 40-2 are disposed in a region sandwiched between the two extension portions 31 of the dummy trench portion 30. Also, on the upper surface of the semiconductor substrate 10, the tip portion 36 of the dummy trench portion 30 is disposed between the tip portion 43 of the first gate trench portion 40-1 and the tip portion 43 of the second gate trench portion 40-2.

[0180] With this structure, the number of extensions 31 of the dummy trench portion 30 sandwiched between the two extensions 41 of the gate trench portion 40 can be reduced to one, while the tips of the extensions (31, 41) in the X-axis direction can be connected at the tips (36, 43). This makes it possible to promote conductivity modulation while mitigating electric field concentration at the tips of the extensions (31, 41).

[0181] The structure other than the gate trench portion 40 and the dummy trench portion 30 may be similar to that of the semiconductor device according to any one of the aspects shown in Figures 1 to 28. The semiconductor device 400 of this example does not have the connection portion 57 and the gate wiring 45, like the semiconductor device 200 shown in Figure 22.

[0182] Each of the first gate trench portion 40-1, the second gate trench portion 40-2, and the dummy trench portion 30 has a portion that overlaps with the gate electrode 46 on the upper surface of the semiconductor substrate 10. For the first gate trench portion 40-1 and the second gate trench portion 40-2, a contact hole 55 is provided in the portion that overlaps with the gate electrode 46.

[0183] Each of the first gate trench portion 40-1, the second gate trench portion 40-2 and the dummy trench portion 30 has a portion that overlaps with the emitter electrode 52 on the upper surface of the semiconductor substrate 10. For the dummy trench portion 30, a contact hole 56 is provided in the portion that overlaps with the emitter electrode 52.

[0184] 30 is a diagram showing an example of an ff cross section of a semiconductor device 400. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in FIG. 2. In another example, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in FIGS. 1 to 21D. Furthermore, each doping region in the mesa portion 94 may have the same structure as each doping region in the mesa portion 94 shown in FIGS. 1 to 20.

[0185] Fig. 31 is a diagram showing another example of an ff cross section of the semiconductor device 400. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in Fig. 2. The other structures are the same as those of the semiconductor device 400 shown in Fig. 30. The shapes and arrangements of the dummy trench portion 30 and the gate trench portion 40 shown in Fig. 29 may be applied to each of the semiconductor devices of Figs. 1 to 24.

[0186] 32 is a diagram showing an example of a gg cross section of the semiconductor device 400. In the semiconductor device 400, each trench portion is directly connected to each electrode. Therefore, the semiconductor device 400 does not include the connection portion 57 and the gate wiring 45.

[0187] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0188] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 bottom end, 18 drift region, 19 peak, 20 buffer region, 22 collector region, 26 interlayer insulating film, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 bottom end, 34 dummy conductive portion, 35 bottom end, 36 tip portion, 37 thin trench portion, 38 thick trench portion, 40 gate trench portion, 41 extension portion, 42 Gate insulating film, 43...tip portion, 44...gate conductive portion, 45...gate wiring, 46...gate electrode, 52...emitter electrode, 54, 55, 56...contact hole, 57...connection portion, 58...collector electrode, 70...transistor portion, 72...gate adjacent region, 74...dummy adjacent region, 76...peak, 77...first peak, 78...second peak, 79...central region, 80...diode portion, 82...cathode region, 90...boundary portion, 94...mesa portion, 96...connection portion, 100, 200, 300, 400...semiconductor device

Claims

1. a drift region of a first conductivity type; a base region of a second conductivity type formed between an upper surface of the semiconductor substrate and the drift region; a gate trench portion formed from an upper surface of the semiconductor substrate through the base region; a dummy trench portion formed from an upper surface of the semiconductor substrate through the base region; an emitter region of a first conductivity type adjacent to the gate trench portion and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type having a doping concentration higher than that of the base region; an emitter electrode provided above an upper surface of the semiconductor substrate; an interlayer insulating film provided between an upper surface of the semiconductor substrate and the emitter electrode; a first contact hole provided in the interlayer insulating film above a predetermined first mesa portion; a second contact hole provided in the interlayer insulating film above the dummy trench portion; a first connection portion provided in the first mesa portion up to the inside of the semiconductor substrate and in contact with the emitter region, the contact region, and the emitter electrode; Equipped with In a cross section in an arrangement direction of the gate trench portion and the dummy trench portion, The dummy trench portion is a first dummy trench portion connected to the emitter electrode via the second contact hole different from the first contact hole; a second dummy trench portion covered with the interlayer insulating film; A semiconductor device having the above structure.

2. The first mesa portion is a mesa portion sandwiched between the gate trench portion and the dummy trench portion. The semiconductor device according to claim 1 .

3. a second mesa portion adjacent to the first dummy trench portion in the cross section; The first contact hole is not provided above the second mesa portion.

3. The semiconductor device according to claim 1 or 2.

4. The emitter region is provided in the first mesa portion and is not provided in the second mesa portion. The semiconductor device according to claim 3 .

5. The emitter region is disposed so as to extend in a direction along the first contact hole when viewed from above. The semiconductor device according to claim 1 .

6. The contact region is disposed so as to extend in a direction along the first contact hole in a top view. The semiconductor device according to claim 1 .

7. In the arrangement direction, two or less of the dummy trench portions are provided between two of the gate trench portions. The semiconductor device according to claim 1 .

8. The first connection portion is formed of a metal containing tungsten. The semiconductor device according to claim 1 .

9. a second connection portion provided below the second contact hole and extending into the semiconductor substrate; The second connection portion is formed of a metal containing tungsten. The semiconductor device according to claim 1 .

10. a well region of a second conductivity type having a lower end deeper than a lower end of the gate trench portion and a lower end of the dummy trench portion and having a doping concentration higher than that of the base region; The base region, the second contact hole, and the second connection portion are provided inside the well region. The semiconductor device according to claim 9.

11. The cross section is a cross section passing through the emitter region. The semiconductor device according to claim 1 .

12. The first contact hole and the second contact hole are provided along an extension direction of the gate trench portion and the dummy trench portion. The semiconductor device according to claim 1 .

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