Disable memory accessor

Abstract

A data processing apparatus (300) is provided that includes a memory circuit (110), the memory circuit (110) being logically divided into a plurality of memory segments (370a, 370b, 370c, 370d) and providing a physical address space that stores a plurality of accessors with associated validity indicators. Each of the accessors controls access to a region of the physical address space according to at least its associated validity indicator. A tracking circuit (310) tracks which of the memory segments an accessor is included in, and an invalidation circuit (320) responds to a request to invalidate an accessor by referencing the tracking circuit to identify a set of equivalent accessors, and invalidates the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.

Description

[Technical field]

[0001] This invention was made with Government support under Contract No. HR001118C0016 awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.

[0002] The present technology relates to data processing, and more particularly to memory systems.

[0003] In a data processing system, memory accessors may be used to control access to particular regions of memory. Such an accessor may contain both a reference to the memory and an access restriction that allows the memory reference to be used only in a specified manner. When the time comes, the accessor may be invalidated. However, if an accessor is duplicated, it is important that the copies of the accessor are also invalidated. If this is not done, it may be possible for the owners of those copies to continue to access the memory space even if the memory space is reclaimed for another purpose. However, scanning memory to locate duplicate accessors may be very time consuming and / or resource intensive.

[0004] Viewed from a first exemplary configuration, a data processing apparatus is provided that provides a physical address space logically divided into a plurality of memory segments, the data processing apparatus comprising: a memory circuit for storing a plurality of accessors with associated validity indicators, each of the accessors controlling access to a region of the physical address space in accordance with at least its associated validity indicator; a tracking circuit for tracking which of the memory segments the accessor is included in; and an invalidation circuit for responding to a request to invalidate an accessor by referring to the tracking circuit to identify a set of equivalent accessors, and invalidating the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.

[0005] Viewed from a second exemplary configuration, a data processing method is provided that includes logically dividing a physical address space of a memory into a plurality of memory segments; storing a plurality of accessors with associated validity indicators, each of the accessors controlling access to a region of the physical address space in accordance with at least its associated validity indicator; tracking which of the memory segments the accessor is included in; responding to a request to invalidate an accessor by referring to the tracking circuitry to identify a set of equivalent accessors; and invalidating the accessor and the equivalent accessors by setting an associated validity indicator of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.

[0006] Viewed from a third exemplary configuration, a computer program for controlling a host data processing apparatus to provide an instruction execution environment includes: a plurality of data structures for storing a plurality of accessors with associated validity indicators, each of the accessors controlling access to one of the data structures according to at least its associated validity indicator; tracing program logic for tracking which of the data structures the accessor is included in; and invalidation program logic for responding to a request to invalidate an accessor by referring to the tracing program logic to identify a set of equivalent accessors, and invalidating the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid. [Brief description of the drawings]

[0007] The present technology will now be further described, by way of example only, with reference to embodiments thereof illustrated in the accompanying drawings, in which: [Figure 1] FIG. 2 illustrates an example of an accessor according to some embodiments. [Figure 2A] FIG. 13 illustrates the manner in which capability replication can be used to gain access to private information. [Figure 2B] FIG. 13 illustrates the manner in which capability replication can be used to gain access to private information. [Diagram 3] FIG. 1 illustrates a data processing apparatus according to some embodiments. [Figure 4] 10 is a flowchart illustrating a process for disabling equal access in accordance with some embodiments. [Diagram 5] 11 is a flowchart illustrating a process for reconstructing Bloom filter entries in accordance with some embodiments. [Figure 6] 1A-1C illustrate some improvements that can be made to the described techniques, according to some embodiments. [Figure 7] 1 is a flowchart illustrating a data processing process according to some embodiments. [Figure 8] FIG. 1 illustrates a simulator implementation that may be used according to some embodiments.

[0008] Before discussing the embodiments with reference to the accompanying drawings, certain embodiments and associated advantages are described below.

[0009] According to one exemplary configuration, a data processing apparatus is provided that provides a physical address space logically divided into a number of memory segments, the data processing apparatus comprising: a memory circuit for storing a number of accessors with associated validity indicators, each of the accessors controlling access to a region of the physical address space in accordance with at least its associated validity indicator; a tracking circuit for tracking which of the memory segments the accessor is included in; and an invalidation circuit for responding to a request to invalidate an accessor by referring to the tracking circuit to identify a set of equivalent accessors, and invalidating the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.

[0010] The memory provides a physical address space (used to address a particular storage cell of the memory). This address space is divided into several memory segments. Note that the address space need not be divided precisely into memory segments, i.e. there may be regions of the address space that are outside of the memory segments. The memory segments may be of different sizes and may be arbitrarily selected, for example, by software. Accessors are used to access regions of the address space. An accessor may take the form of a data structure that includes, for example, a reference to a location in the address space with one or more restrictions on how that reference may be used, and a validity indicator that indicates that the accessor is valid (e.g., not corrupted). The accessor may be stored in the memory, for example in a memory segment, and the tracking circuitry may identify which segment of the physical memory contains the accessor. As a result, when an invalidation request is received indicating that an accessor (and the memory it references) is no longer in use, the tracking circuitry may be queried to identify whether there is an equivalent accessor in the memory. In this manner, the accessor and the accessors that are considered equivalent are invalidated. This inhibits or prevents copies of an accessor from being kept valid once it has been invalidated. Thus, this prevents malicious or improperly formed sections of code (such as untrusted libraries) from accessing secrets stored in memory that are reused for other purposes after being invalidated. Note that while accessors are said to control access to memory regions, they do not exclusively control access to each memory region. In particular, there may be multiple accessors directed to the same region of memory or overlapping regions of memory. Furthermore, there may be other circuitry or mechanisms in place that override the accesses allowed by the accessors.

[0011] There are many ways to determine whether an accessor is equivalent to an accessor that is being invalidated. However, in some examples, the equivalent accessors include those accessors that control access to that region of address space. In these examples, an accessor is considered equivalent if it controls access to the same region of physical address space that the invalidated accessor controls access to. Thus, it is possible to invalidate accessors that would allow access to the same region of address space that is being invalidated. As a result, if this region of memory is subsequently reused, those accessors cannot be used to access any content stored in that region of address space.

[0012] In some examples, an accessor includes a pointer. A pointer can be thought of as a reference to a location in memory where additional data can be stored. Thus, an accessor can include, for example, a pointer that serves to reference a byte in one of the memory segments.

[0013] In some examples, the accessor includes boundary information that defines an area of ​​the physical address space that can be accessed using the pointer. By providing the boundary information, the pointer can be prevented from being used to access locations that are outside the boundary. For example, if the boundary defines a lower limit address of 1000 and an upper limit address of 2000, and the pointer P points to address 1999, the accessor prevents the pointer from being used to access an address equal to P+5, because the result (2004) would be outside the range of 1000 to 2000. The boundary information can be defined in a number of ways. For example, the boundary information can include a lower limit and an upper limit as described above. In other examples, the boundary information can include a lower limit and an offset, which can be used to determine the upper limit by adding the offset to the lower limit. In other examples, an upper limit can be provided, and an offset can be used to define the lower limit. In other examples, two offsets can be provided to the pointer to describe the lower limit and the upper limit. In still other examples, the boundary information can be used to define locations where access is prohibited, and all other memory locations are defined as accessible via the pointer. Other techniques will be apparent to those skilled in the art from the foregoing description. Note that an accessor is not limited to containing only bounds information. In some examples, an accessor may also contain permission information that controls how a pointer can be used to access an address space. For example, in some examples, an accessor may be used to restrict a pointer to be used for read operations.

[0014] In some examples, equivalent accessors include those accessors whose bounds information matches the bounds information of the accessor. Another way to determine whether an accessor is equivalent to an accessor that is being disabled is by considering the bounds information. For example, if the bounds information matches between two accessors, the accessors may be considered equivalent. Note that such a test may include or exclude a match between permissions. For example, two accessors may also be considered equivalent if the permissions match, or if one set of permissions is a subset of the permissions of the accessor being disabled. In other examples, permissions may not be considered when determining equivalence.

[0015] In some examples, equivalent accessors include those accessors whose boundary information defines a subregion of that region of the physical address space. In these examples, an exact match of the boundary information is not required. Instead, an accessor will be considered equivalent to an invalidated accessor if the region defined by the accessor under consideration is a subregion of the region of the address space of the accessor being invalidated. It should be understood that when a region of an address space is subject to invalidation, accessors that reference that portion of the address space will also be invalidated because the memory referenced by the accessor will be invalidated as a result of the broader invalidation occurring. For example, an accessor that accesses memory locations 2-98 will be considered equivalent to an accessor that defines a region consisting of addresses 0-100.

[0016] There are many ways in which the tracing circuitry can track which memory segments contain the accessors. However, in some examples, the tracing circuitry is adapted to indicate whether each of the memory segments contains one of the accessors. Such a tracing circuitry operates by indicating, for each of the memory segments tracked by the tracing circuitry, whether that memory segment contains the accessors. Such information can be determined at the time the accessors are created or duplicated. If a dedicated instruction is used to effectively create or duplicate the accessors, the instruction can be designed such that invoking the instruction updates the tracing circuitry to indicate the location of the accessors within the memory segment. It should be appreciated that such techniques may result in tradeoffs with respect to the size of each of the memory segments. In particular, if the tracing circuitry provides an indicator of whether each memory segment contains an accessor, then a smaller number of memory segments would require less storage space for the tracing circuitry. However, this provides less useful information since larger memory segments are more likely to contain the accessors. Similarly, this more limited information makes it more difficult to locate the accessors more precisely.

[0017] In some examples, the tracking circuitry includes a bit field that includes multiple bits, the multiple bits being adapted to indicate which of the memory segments includes one of the accessors. In these examples, a bit field is used to provide the multiple bits. A subset of the bits of the bit field (a bit vector) is used to represent a particular memory segment. Thus, by considering each bit vector, it is possible to determine whether a particular memory segment includes an accessor. In a simple example, one bit per memory segment can be provided, which only indicates whether the memory segment includes an accessor, i.e., a "1" in the bit field can be used to indicate that the memory segment includes an accessor, while a "0" can be used to indicate that the memory segment does not include an accessor. The reverse encoding is also possible. By using a bit field to store this information, the contents of each of the memory segments can be represented in a compact form.

[0018] In some examples, the tracking circuitry includes a hash table, which accepts as input a hash of at least a portion of the accessor. The term "hash table" is used herein to refer to a table in which the input and / or contents of the hash table are generated using a hash function. For example, a lookup index for the table can be generated by performing a hash on the input value so that a particular index of the table can be accessed directly rather than manually scanning each entry of the table to find a particular entry. A hash function can be considered as a function that converts an input from a large input domain to an output of a smaller output domain. This process need not be cryptographic (one-way). In these examples, at least a portion of the accessor (e.g., boundary information) is hashed to provide an input to the hash table. By using such a data structure, it is possible to determine not only whether a memory segment contains an accessor, but also whether a given memory segment or which memory segments may contain an accessor with a hashed input (e.g., having the same boundary information). This makes it possible to provide a more intelligent assessment of whether a given memory segment contains an accessor of interest. The input to the hash function can be based on an element of the accessor that is considered to define equality between the two accessors. For example, if the boundary and privilege information of two accessors match, the accessors are considered equivalent and this information can be provided as input to a hash so that the tracking circuitry can help identify memory segments that contain equivalent accessors.

[0019] In some examples, the tracking circuitry includes a Bloom filter. A Bloom filter is a data structure that can be used to identify whether an accessor having a particular quality is in a given memory segment. Bloom filters are subject to false positives. In other words, a Bloom filter may report that a given memory segment contains an equivalent accessor even when one does not exist. However, false negatives do not occur. That is, a Bloom filter will not return an indication that an equivalent accessor does not exist in a memory segment when an equivalent accessor does exist. This is important for invalidation where it is inconvenient to unnecessarily perform further analysis of the memory segment to search for an accessor, but it is unsafe to not invalidate an equivalent accessor because it is not reported to exist. Bloom filters can be implemented using a bit field where some bits correspond to one of the memory segments. The number of bits assigned to each memory segment reduces the possibility of false positives at the expense of increased storage space.

[0020] In some examples, if the tracking circuit indicates that a given memory segment contains one of the accessors, the invalidation circuit performs a sweep of the given memory segment to rebuild the Bloom filter entries corresponding to the given memory segment. The tracking circuit can be used to indicate (with a specific probability) that a particular memory segment contains an equivalent accessor. Although the Bloom filter entries can be updated as a result of new accessors being added or moved to a memory segment, the Bloom filter cannot be updated when these accessors are moved or removed from the memory segment. This is because older versions of the entries (except for the accessors being removed) may not be known or retained. Thus, the entries of a given memory segment will eventually become saturated (e.g., always indicating that the accessor is present) unless the entries are periodically rebuilt.

[0021] In some examples, the invalidation circuitry is adapted to reconstruct the Bloom filter entries corresponding to a given memory segment by taking into account the associated validity indicators of each of the accessors in the given memory segment. In these examples, when a sweep occurs, the validity indicators of each of the accessors are taken into account in reconstructing the Bloom filter entries. In particular, the Bloom filter entries are not updated for accessors that are considered invalid because the accessors cannot be used because they are invalid.

[0022] In some examples, Bloom filter entries corresponding to a given memory segment are reconstructed by performing a rewrite of those of the accessors that are in the given memory segment, and the invalidation circuitry is adapted to operate in a sweep mode of operation in which the rewrite is performed by inhibiting the accessors from being physically written to memory if the associated validity indicator indicates validity. In situations where the instructions for creating or duplicating capabilities also involve updating the associated entries of the tracking circuitry, those same instructions can be used to recreate the Bloom filter entries during the sweep. In these situations, a sweep mode of operation may be provided in which those instructions do not physically write data back to memory. Thus, memory bandwidth is saved since no memory writes are actually performed. Note that even if data is not written back to memory using this technique, the entries that are invalidated still have their (now invalid) validity indicators physically written to memory. Furthermore, the Bloom filter table entries are not updated to incorporate these entries since they are now considered invalid.

[0023] In some examples, if the tracing circuit indicates that a given memory segment includes one of the accessors, the invalidation circuit sweeps the given memory segment to identify an equivalent accessor. Once an evaluation is made that a memory segment may include an equivalent accessor, the memory segment must be scanned to locate the equivalent accessor (if any). In some embodiments, at the same time, the Bloom filter entries corresponding to the memory segment being swept are reconstructed. Specifically, the complete set of accessors located in the given memory segment can be used to recreate the Bloom filter entries provided for the given memory segment. It should be noted that the size of the memory segment affects the time it takes for the scan to occur. As mentioned above, the number of memory segments affects the amount of storage required for the tracing circuit. However, if a smaller number of memory segments are provided (thereby using a smaller tracing circuit), each memory segment is likely to be larger, thereby resulting in a longer sweep time.

[0024] In some examples, the invalidation circuitry is adapted to refrain from sweeping a given memory segment if the tracing circuitry indicates that the given memory segment does not contain each of the accessors. If the tracing circuitry indicates that the given memory segment does not contain an accessor, there is no need to sweep the given memory segment to determine whether there is an equivalent accessor within that memory segment. As a result, the tracing circuitry can be used to reduce the number of memory segments to perform a scan.

[0025] In some examples, the memory circuit is further logically divided to include an active stack region. The tracking circuit includes a bit field for tracking the active stack region, and the tracking circuit includes a hash table or Bloom filter for tracking the memory segment. In such data processing apparatus, the active stack region is used by currently active threads to store temporary data values. Due to the nature of these data values, they may be periodically modified, added, and deleted. Such data values ​​may include accessors. It should therefore be appreciated that for the active stack region, the Bloom filter entries will rapidly saturate, thereby periodically indicating the presence of an equivalent accessor (even when there is no equivalent accessor). As a result, in these embodiments, a simpler bit field is used to indicate whether an accessor is present in the active stack region, while at least some other regions of memory are represented using hash table entries or Bloom filter entries, as those sections of memory are less likely to saturate due to less frequent modifications.

[0026] In some other examples, the memory circuit is further logically partitioned to include an active stack region, and the tracing circuitry is limited to tracing the active stack region. In these examples, the tracing circuitry may simply be limited to tracing the active stack region as a whole. This may be done in recognition of the fact that the tracing circuitry is likely to always report the active stack region as containing an accessor. Thus, the active stack region may always be swept for equivalent accessors with reference to the tracing circuitry.

[0027] In some examples, the tracing circuitry is further adapted to trace those accessors that are stored outside the memory segment. In these examples, simpler tracing can be used for regions of memory outside the memory segment. In particular, a series of bits may be used, each bit corresponding to a different portion of memory that is outside the memory segment, to indicate whether an accessor is located within that region of memory.

[0028] Specific embodiments will now be described with reference to the drawings.

[0029] FIG. 1 illustrates an example of a capability 100 (which is an example of a claimed accessor) according to some embodiments. The capability is used to control access to a location in memory provided via a pointer 130. Specifically, the capability 100 includes metadata 120 that controls the manner in which the pointer 130 may be used to access the memory 110. In this example, the metadata 120 includes a set of permissions 150. The permissions 150 indicate the manner in which the pointer may be used. For example, the permissions 150 may indicate that the pointer 130 may be used for read access to the memory 110. In such a case, an attempt to use the pointer 130 for write access will fail, for example, by raising an exception. The metadata 120 also includes bounds information 160, 170 in the form of a base address 160 and a limit address 170. These addresses collectively define a physical region 180 of the memory 110. The boundary information 160, 170 means that if the pointer 130 is used to access an address outside this region 180, the request will fail, for example by raising an exception. The capability 100 also includes a tag 150. In this example, the tag 140 is not part of the metadata 120. However, in other examples, the tag 140 may form part of the metadata 120. The tag 140 (which is an example of a claimed validity indicator) is used to indicate whether the capability 100 is valid and / or uncorrupted. For example, the tag 140 may be set to "0" to indicate that the capability is invalid / corrupted, while a "1" may indicate that the capability 100 is valid / uncorrupted.

[0030] Note that the bounds information 160, 170 may be represented relative to the pointer, in which case the number of bits used to represent the bounds information may be significantly less than the number of bits used to represent the pointer. In this case, when it comes to updating a pointer, it is first determined whether the updated pointer is within the old bounds (calculated using the pointer and the relative bounds). If not, the capability is invalidated.

[0031] Both pointer 130 and metadata 120 may be accessible by user applications. However, if an attempt is made to directly modify metadata 120, tag 140 indicates that the capability has become invalid / corrupted. Some embodiments may allow an accessor's metadata to be legitimately modified using special instructions (e.g., used to shrink bounds or remove permissions). However, the details of such operations are beyond the scope of this disclosure. Valid capabilities may be generated by special instructions (which may require a privileged mode of operation). Capabilities may thus be used to protect access to memory. For example, when a memory allocation request is processed, a capability may be returned that defines a region of the allocated memory and provides a pointer 130 to access that region of memory. Attempts to use the pointer to access a region outside the region of memory will fail.

[0032] Otherwise, capabilities can be treated as regular data structures in the sense that they can be replicated. For example, capability 100 is shown replicated in several locations 190a, 190b, 190c in memory 110. However, this can cause problems. Specifically, if one of capabilities 190a is revoked, the other replicas 190b, 190c must also be located in order to be revoked. These replicas can be used to access private information as shown with respect to Figures 2A and 2B. One way to locate the replicas is by scanning the entire memory 110. However, this is time consuming and resource intensive. Therefore, the present technique seeks to reduce the resources required to disable replicas that are equivalent to the capability being revoked.

[0033] Figures 2A and 2B show the manner in which a copy of a capability can be used to gain access to private information. In this example, compartment A (the victim) calls compartment B, which may take the form of an untrusted library (the attacker). Compartment A first creates a capability C1 that points to an allocated region of memory (shared0). Compartment A then makes a function call to compartment B, passing capability C1. Within compartment B, capability C1 is stored in the heap. Compartment B then uses capability C1 as expected to perform the requested operation. Compartment B then returns to compartment A. Compartment A then releases the memory shared0 pointed to by capability C1. Because this "release" command only invalidates capability C1, the copy held by compartment B has not been invalidated. Instead, the copy held by compartment B remains a valid capability and can be used to access the memory region defined by shared0 (now freed). Compartment A then creates a second capability C2 that contains the secret data. Due to the way memory allocation works, it is quite likely that this memory allocation will use at least some of the memory previously allocated to shared0. In particular, capability C2 will likely reference a memory region that overlaps with capability C1. Compartment A then creates a further capability C3 that describes the region shared1. Compartment A then makes a second call to compartment B, this time passing capability C3. If compartment B is now using the copy of capability C1 that was stored on the heap, then compartment B is in fact accessing the memory region referenced by capability C2 that contains the secret data.This is because, as shown in FIG. 2B, the region of memory encompassed by capability C1 overlaps with the region of memory used to store secret data via C2. In this particular example, capability C1 extends only to a portion of C2, so compartment B may only be able to access a portion of the secret data. However, the reverse is also true, and there may be situations in which capability C1 covers not only C2 but also C3. Note that throughout this process, the restrictions imposed on the capabilities are not violated. In particular, it is legal to duplicate capabilities under the condition that the metadata is not modified. Furthermore, since the invalidation of capability C1 does not invalidate the copy of the capability, the copy of capability C1 stored in the heap of compartment B is not invalidated and can still be used even if the region of memory referenced by it is actually reused for another purpose. This technology aims to solve this problem.

[0034] FIG. 3 illustrates a data processing apparatus 300 according to some embodiments. The data processing apparatus 300 includes a memory circuit 110 that defines a physical address space. At least a portion of the physical address space is logically divided into a number of segments 370a, 370b, 370c, 370d. In this example, a capability C0 380 is stored in one of the segments 370a. A tracking circuit 310 is provided that tracks whether the capability is stored in each of the segments 370a, 370b, 370c, 370d. In this example, the tracking circuit 310 includes a Bloom filter. The Bloom filter 310 provides a bit field that is composed of a number of bit vectors 330, 340, 350, 360. Each of the bit vectors 330, 340, 350, 360 corresponds to one of the segments 370a, 370b, 370c, 370d. It should be noted that the logical divisions may or may not be of consistent size, and the size of each segment may be arbitrarily selected, for example, at startup or run-time by the software.

[0035] The contents of each of the bit vectors 330, 340, 350, 360 are calculated by hashing the bounds of each capability in the corresponding memory segment. For example, if the only capability in the first segment 370a is assumed to be capability C0 380, then the corresponding bit vector 330 is generated by hashing the bounds of capability C0 380. Each time a capability is added or moved to the first segment 370a, the bounds of that capability are hashed and logically ORed with the existing bit vector 330 corresponding to that segment 370a. Note that in the case of a Bloom filter, there is no change in the bit vectors 330, 340, 350, 360 as a result of the capability 380 being removed from the corresponding memory segment 370a. As a result, over multiple additions (logical ORs), the bit vector 330 corresponding to the memory segment 370a will saturate. In other words, the corresponding bit vector 330 will be all ones. This can be solved by periodically rebuilding the Bloom filter. The contents of the tracing circuitry are privileged and therefore can only be accessed in a defined manner, i.e., by hardware or, in some embodiments, via a privileged mode that can be entered by the operating system.

[0036] When revocation of a capability 380 is performed, the revocation circuit 320 queries the tracking circuit 310 to search for an equivalent capability in the memory 300. Threads that can access the address space currently targeted by the revocation circuit are stopped until the revocation is complete. Also, interrupts associated with software that may access the address space are disabled. Therefore, an equivalent capability cannot be transferred to a part of the memory that has already been considered, which may result in a missing capability. In these examples, a hash of the capability 380 to be revoked is created. The hash is then compared to each of the bit vectors 330, 340, 350, 360, which themselves were generated by performing a logical OR of the hashes of the capabilities stored in the corresponding memory segments. This comparison can be achieved by performing a logical AND operation between the hash of the bounds of the capability 380 to be revoked and the bit vector to be tested. If the result is equal to the hash of the bounds of the capability 380 to be revoked, a hit occurs in that entry of the tracking circuit 310.

[0037] For example, consider the situation where capability C1 is equivalent to capability C0 if the bounds of C1 are within the bounds of C0. This can be achieved by considering the upper and lower bounds of each capability separately. For the bounds, the least significant "1" and all lower bits of each capability's bound are set to "1". For example, if C0's bound is 00001000, this hashes to 00001111, and if C1's bound is 00000100, this hashes to 00000111. A logical AND between these produces 00000111, which is equal to the hashed upper bound of C1. In other words, C1's bound is less than or equal to C0's bound.

[0038] For the lower bound, we can perform the same operation by checking the result of the AND operation on C0 instead of C1, which tells us whether C0 is less than or equal to C1 (which means C1 is greater than or equal to C0).

[0039] Since both conditions are met, the upper and lower bounds of C1 are within the upper and lower bounds of C0, so C1 defines a subregion of C0. If a hash entry for a memory segment contains multiple capabilities, the upper and lower bounds of each capability are combined separately using a logical OR to provide a combined lower bound and a combined upper bound. Other hashing algorithms are known to those skilled in the art.

[0040] It should be noted that due to the nature of Bloom filters, even if a hit occurs, this does not guarantee that an entry exists. Therefore, the corresponding memory segment needs to be searched to determine if an equivalent capability really exists. This can be achieved by sweeping the entire relevant memory segment. For example, if a hit occurs in entry 350 of the tracking circuit 310, a sweep occurs in the corresponding memory segment 370c of the memory circuit 110. Since it is expected that a hit will not necessarily occur in any of the entries 330, 340, 350, 360 of the tracking circuit 310, it can be expected that certain segments 370a, 370b, 370c, 370d of memory do not need to be swept, and therefore there is no need to search the entire memory 110 for the corresponding capability.

[0041] Note that in this example, a Bloom filter is used. However, in other examples, a smaller bit field can be used to indicate whether each memory segment 370a, 370b, 370c, 370d contains an accessor / capability. Specifically, for a particular entry, a "1" can be used to indicate that the corresponding memory segment 370a, 370b, 370c, 370d contains the capability, while a "0" can be used to indicate that the memory segment 370a, 370b, 370c, 370d does not contain the capability. Such a data structure has the advantage of being smaller than a Bloom filter. However, this data structure lacks the ability to distinguish between separate capabilities because no bounds information is taken into account. As a result, such a data structure cannot indicate whether a capability with a particular bound is located in that memory segment, and further analysis of the memory segment is likely required. Another option is to track the bounds of capabilities within each memory segment. For example, some embodiments may track the minimum base address and maximum limit (e.g., top) address of each capability in the memory segment. Space can be saved in the tracking circuitry by discarding bits of these addresses (such as the least significant bits) or by tracking hashes of the maximum and minimum addresses. By tracking this additional information, the memory segment is less likely to be investigated in more detail. A further way to track this information is for the tracking circuitry itself to record the boundary information of each capability in the memory segment, either the exact address, the relevant bits, or a hash. This will reduce the probability of false positives. However, it will take longer to check each entry in the tracking circuitry, and the tracking circuitry will require additional storage space.

[0042] In this example, the tracing circuitry 310 is shown as a separate element, but in other examples, the tracing circuitry may take the form of a set of instructions executing on, for example, a central processing unit (CPU). In these embodiments, operations associated with tracing may be initiated, for example, by an operating system or hypervisor. Regardless of whether the tracing circuitry is a separate unit, data used by the tracing circuitry (trace data) may be stored in a memory hierarchy (e.g., in main memory) or may be stored in dedicated storage circuitry.

[0043] FIG. 4 shows a flow chart 400 illustrating a process for invalidating equal access according to some embodiments. The process begins at step 405, where an invalidation request is received for a particular accessor. At step 410, the boundaries defining the access to be invalidated are hashed. Then, at step 415, it is determined whether there are any more entries in the tracking circuit 310 to be considered. If not, the scan of the tracking circuit 310 is completed and the process resumes by returning to step 405 to wait for the next accessor to be invalidated. If not, at step 420, the next entry in the tracking circuit 310 is considered and at step 425, it is determined whether there is a hit against the hashed boundaries calculated at step 410. If not, the process returns to step 415 to consider whether there are any more entries in the tracking circuit 310. If not, the process proceeds to step 430, where the memory segment corresponding to the hit entry is swept. Specifically, at step 435, it is determined whether there are any more entries in the swept segment to be considered. Such an entry may consist of a single byte, or a block of memory of a size equal to the size of the accessor (e.g., capability). For example, if the capability is 128 bits in length, the entry considered may be a multiple of 128 bits so that capabilities are not spread across multiple entries. If there are no more entries to consider, the process returns to step 415. If not, the process proceeds to step 440, where the next entry for the memory segment is obtained. In step 445, it is considered whether the entry under consideration is an accessor that represents a sub-region of the boundary of the accessor to be invalidated. If not, in this example, the entry under consideration is not an equivalent accessor, and the process returns to step 435. If not, the process proceeds to step 450, where it is determined whether there is equivalence between the permissions of the accessor to be invalidated and the current entry in the memory segment. This may be the case if the permissions match, or if one set of permissions is a subset of the other.If not, then in this example the accessors are not considered equivalent and the process returns to step 435. Otherwise, the accessors are considered equivalent and the accessors in the current entry are invalidated in step 455 before the process returns to step 435.

[0044] By checking permissions, it is possible to revoke write capability to an area that is also covered by (for example) read or execute capabilities that are not being revoked.

[0045] Accordingly, each of the entries in the tracking circuitry is tested for a hit. If a hit occurs, the memory segment corresponding to the hit entry is swept. Each entry in the hit memory segment is tested to determine whether they are equivalent. In this example, accessors are considered equivalent if (a) they reference a subregion of the boundary defined by the accessor being invalidated, and (b) their permissions are identical. In other examples, other tests can be provided to test for equality. For example, the two regions may be required to be identical. In some examples, the permissions need not match, or the permissions of one accessor need only be a subset of the permissions of another accessor. Further tests can be added. Specifically, this example does not explicitly require that the validity tag of the accessor being tested be set. However, there is no need to invalidate an accessor that is already invalid, so that a further test that can be performed is whether a particular entry contains an accessor that is currently valid. If the accessor being tested is not valid, then non-equality is assumed.

[0046] As mentioned above, a Bloom filter can be used to provide a probabilistic determination of whether a particular memory segment contains an accessor that is equivalent to an accessor to be invalidated. Specifically, the Bloom filter is pre-populated with a hash of the accessor parameters that define the equivalent (e.g., bounds and / or permissions). However, because the Bloom filter is pre-populated by performing a logical OR between the hash added to the Bloom filter's entry and the current value of the Bloom filter, it is very difficult to update the Bloom filter's entry to represent a capability that is being removed. Thus, after many additions and removals, a Bloom filter entry may always be hit, even if there is no capability left in the corresponding memory segment. One way this situation can be resolved is to periodically rebuild the memory segment's entries, ignoring invalid entries, taking into account the current valid entries in the corresponding memory segment.

[0047] FIG. 5 illustrates a flow chart 500 showing a process for rebuilding Bloom filter entries for a memory segment when a hit occurs in the corresponding Bloom filter entry. Steps 505-555 can be used as an alternative to steps 430-455 shown in FIG. 4. The process shown with respect to FIG. 5 uses a "sweep mode" operation to perform the rebuilding of Bloom filter table entries, which allows existing write mechanisms to be reused for other purposes. Specifically, the process assumes that when a capability is written to memory, the instruction that performs the write also updates the tracking circuitry.

[0048] The process begins at step 505 when a hit occurs at a particular entry of a Bloom filter. At step 505, the corresponding entry of the Bloom filter where the hit occurred is cleared. At step 510, a sweep of the corresponding memory segment begins. This also begins a "sweep mode" operation for the invalidation circuit. At step 515, it is determined whether there are any more entries for the segment under consideration. If not, the process returns to considering whether other memory segments may be hit. For example, this may return to step 415 shown in FIG. 4. If there are more entries, then at step 520, the next entry in the memory segment is considered. At step 525, it is determined whether the entry in the memory segment is a capability. If not, the process returns to step 515. At step 540, it is determined whether the capability defines a sub-region of the boundary defined by the capability to be invalidated. If not, the process proceeds to step 555, discussed below. If so, in step 545, it is determined whether there is equivalence between the permissions (e.g., a match or a subset in some embodiments), as described above. If there is no equivalence, the process returns to step 555. Otherwise, the process proceeds to step 550, where the capability is disabled since it is considered to be an equivalent capability. The process then proceeds to step 535, where a validity tag is set for the capability to indicate that the capability is disabled. In step 555, a data rewrite is performed. Again, the data rewrite process is accomplished using the existing write mechanism, and this rewrite does not require actually physically rewriting the data to memory since sweep mode is being used. This allows the existing process of the write mechanism for updating Bloom filter table entries to be used. However, in this situation, the data does not need to actually be written to memory since the capability's data is already in memory.Thus, when the write mechanism is invoked, the data is not physically written to memory and the contents of the existing memory location remain the same. This allows the existing mechanism to be reused while reducing the impact on memory bandwidth, since no data needs to be provided for the write process to occur. Once the rewrite has been performed, the process returns to step 515.

[0049] A consequence of the sweep mode is that the amount of data that is physically written is reduced: if an entry is invalidated, then only the tag needs to be written; otherwise, no data is actually written and the write mechanism is simply used to update the filter.

[0050] 6 illustrates some improvements that can be made to the described techniques. In particular, the address space provided by memory 110 can be divided into non-secure memory 605 and secure memory 610. Separate tracking tables (e.g., Bloom filter tables) can be provided for a first section of memory 615a in non-secure memory 605 and a second section of memory 615b in the secure section of memory 610. This can be used to aid in the separation of non-secure memory 605 and secure memory 610.

[0051] It should be understood that the entire memory need not be covered by one table of the tracing circuit 310 as shown in Fig. 6. For example, considering the non-secure memory 605, the portion 615a of the memory is covered by the Bloom filter table, while other sections 625, 630, 635, 640 of the memory only use flags to indicate whether the section of the memory contains an accessor / capability. In contrast to Bloom filters, the use of flags may be appropriate either when the section of memory is highly unlikely to contain a capability (and thus detailed reporting is not required) or when capabilities are added and removed so frequently that saturation of the associated Bloom filter entries may occur. This latter situation may occur especially in the case of application stacks, which are data structures used to temporarily store data values ​​during the operation of certain threats.

[0052] The above description shows how multiple tables can be provided for multiple security domains. However, there are other ways that memory space can be managed to avoid a tracking circuit that tracks the entire address space. In some embodiments, the tracking circuit can provide one table (e.g., Bloom filter table) for each different thread or privilege level. When a thread changes, the table to be searched can be switched. As a result, the amount of memory to be searched can be reduced to only the region of memory associated with the current thread, which allows finer granularity of tracking to occur. If a capability is shared between threads, not only the current Bloom filter table (for the current thread) needs to be checked, but also the tables for threads that can share the capability. In some embodiments, one table can be provided per memory protection unit (MPU).

[0053] The above description assumes that each entry in the tracking circuitry is considered to determine which entries have been "hit". For each "hit", the corresponding memory segment is searched to find the equivalent accessor / capability. In other embodiments, the minimum and maximum addresses of the address space allocated to a thread are tracked for that thread. When an invalidation occurs, only entries corresponding to memory segments that are within the minimum and maximum bounds are considered. In this manner, memory segments for which no allocation has occurred are "skipped". In some embodiments, the memory allocations themselves are tracked. Other embodiments may track the minimum and maximum addresses of capability stores, so that only regions of memory containing capabilities are considered. Still other embodiments may only consider entries within the valid MPU region.

[0054] At runtime, the amount of memory being tracked may change, and this can be compensated for. One way to do this is to use the system of "flags" described above for areas outside the main tracked area of ​​memory. In addition, the table can be expanded to accommodate more entries (if sufficient storage is available). If more storage is not available, it is possible to compensate by increasing the "segment size", e.g., the size of each memory area covered by an entry in the tracking circuit.

[0055] With regard to updating the tracking circuit, a buffer can be provided to store frequently accessed entries in the tracking circuit. This is particularly beneficial when the data structures used by the tracking circuit would otherwise have high latency (e.g., stored in main memory). Additionally, an in-memory update instruction can be included. Such an instruction retrieves a value in memory, performs an operation (such as a logical OR operation between the value in memory and an additional value), and writes the result back to memory. In this way, updates of the data in the tracking circuit can be performed without the need to tediously retrieve, manipulate, and write back data from memory in a series of memory transactions.

[0056] FIG. 7 shows a flow chart 700 illustrating a data processing process according to some embodiments. In step 710, an address space is provided in a memory segment. There is no obligation to divide the address space precisely into memory segments, and there may be sections of the address space that are outside of the memory segments. In step 720, one or more accessors used to access a particular region of the address space are stored. In step 730, tracing is performed on the memory segments to determine whether the particular memory segment contains an accessor. This can be achieved by adding capability tracing to the instructions that perform capability operations. For example, the instructions provided to create or duplicate capabilities can be extended to update the tracing circuitry 310. In step 740, an invalidation request for one of the accessors is received. In step 750, equivalent accessors are identified with reference to the tracing circuitry used to perform tracing in step 730. If equivalent accessors are identified, in step 760, the equivalent accessors are invalidated.

[0057] By using the tracking circuitry in this manner, in many situations it is not necessary to search the entire address space of the memory for equality accessors. Instead, the tracking circuitry can be used to limit the sections of memory that need to be searched, thereby reducing the resource intensity of the process performed to invalidate equality accessors. By invalidating equality accessors in this manner, it is possible to limit unauthorized access to regions of memory in a resource-efficient manner.

[0058] FIG. 8 illustrates a simulator implementation that may be used. While the above embodiments implement the invention in terms of apparatus and methods for operating specific processing hardware supporting the technology, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented using a computer program. Such a computer program is often referred to as a simulator insofar as the computer program provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 830, optionally running a host operating system 820 that supports the simulator program 810. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in some situations, for example, when it is desired to execute code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment that has additional features not supported by the host processor hardware, or that are typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0059] Although embodiments have been described above with reference to particular hardware configurations or functions, equivalent functionality may be provided in the simulated embodiments by appropriate software configurations or functions. For example, particular circuits may be implemented as computer program logic in the simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the simulated embodiments. In configurations where one or more of the hardware elements referenced in the foregoing embodiments reside in host hardware (e.g., host processor 830), some simulated embodiments may use the host hardware where appropriate.

[0060] Simulator program 810 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (an instruction execution environment) to target code 800 (which may include applications, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture being modeled by simulator program 810. Thus, program instructions of target code 800 may be executed from within the instruction execution environment using simulator program 810, such that host computer 830, which does not actually have the hardware features of device 300 described above, can emulate those features.

[0061] In this example, simulator program 810 uses memory data structure 812 to emulate memory that may be accessed by target code 800. Memory data structure 812 includes one or more accessor data structures 814 that may be created and / or used by target code 800 and are used to access memory elements 816 in memory data structure 812. Again, memory elements 816 may be created and / or used by target code 800. Simulator program 810 also includes tracing program logic 818, which emulates the functionality of tracing circuitry 810 discussed in connection with FIG. 3 to trace usage of accessor data structures 814 in memory data structure 812. Additionally, simulation 810 uses invalidation program logic 819 to invalidate equivalent accessor data structures 814 in memory data structure 812.

[0062] In this application, the term "configured to..." is used to mean that elements of an apparatus have a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the apparatus elements need to be modified in any way to provide the defined operation.

[0063] Although exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to those precise embodiments, and that various changes, additions, and modifications may be made by those of ordinary skill in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, various combinations of the features of the independent claims may be made with the features of the dependent claims without departing from the scope of the invention.

Claims

1. 1. A data processing device, comprising: a memory circuit for providing a physical address space logically divided into a plurality of memory segments and for storing a plurality of accessors with associated validity indicators, each of said accessors controlling access to a region of said physical address space in accordance with at least its associated validity indicator; a tracking circuit for tracking which of said memory segments contains said accessor; an invalidation circuit for responding to a request to invalidate an accessor by referencing the tracking circuit to identify a set of equivalent accessors, and invalidating the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid; A data processing device comprising:

2. the equivalent accessor includes an accessor that controls access to the area of ​​the physical address space, 2. A data processing apparatus according to claim 1.

3. the accessor comprises a pointer; 3. A data processing device according to claim 1 or 2.

4. the accessor includes boundary information defining the region of the physical address space that can be accessed using the pointer; 4. A data processing device according to claim 3.

5. the equivalent accessors include an accessor whose boundary information matches the boundary information of the accessor; 5. A data processing apparatus according to claim 4.

6. the equivalent accessors include those accessors whose boundary information defines a subregion of the region of the physical address space; 5. A data processing apparatus according to claim 4.

7. the tracing circuitry is adapted to indicate whether each of the memory segments includes one of the accessors; The data processing device according to any one of claims 1 to 6.

8. the tracking circuit includes a bit field including a plurality of bits; the plurality of bits being adapted to indicate which of the memory segments contains one of the accessors; A data processing device according to any one of claims 1 to 7.

9. the tracking circuit includes a hash table; the hash table accepts as input a hash of at least a portion of the accessors; A data processing device according to any one of claims 1 to 8.

10. the tracking circuitry includes a Bloom filter; A data processing device according to any one of claims 1 to 9.

11. if the tracing circuit indicates that a given memory segment contains one of the accessors, the invalidation circuit performs a sweep of the given memory segment to reconstruct an entry in the Bloom filter corresponding to the given memory segment.

11. A data processing apparatus according to claim 10.

12. the invalidation circuitry is adapted to reconstruct the entry of the Bloom filter corresponding to the given memory segment by considering the associated validity indicator of each of the accessors in the given memory segment. A data processing apparatus according to claim 11.

13. the entry of the Bloom filter corresponding to the given memory segment is reconstructed by performing a rewrite of the accessors that are in the given memory segment; the invalidation circuitry is adapted to operate in a sweep mode of operation in which the rewriting is performed by inhibiting the accessor from physically writing to the memory if the associated validity indicator indicates validity; 13. A data processing device according to claim 11 or 12.

14. if the tracing circuit indicates that a given memory segment contains one of the accessors, the invalidation circuit sweeps the given memory segment to identify the equivalent accessor. A data processing device according to any one of claims 1 to 13.

15. if the tracing circuitry indicates that each of the accessors is absent from a given memory segment, the invalidation circuitry refrains from sweeping the given memory segment to identify the equivalent accessors. A data processing device according to any one of claims 1 to 14.

16. the memory circuit is further logically partitioned to include an active stack region; the tracing circuitry includes a bit field for tracking the active stack region; the tracing circuitry includes a hash table or a Bloom filter for tracing the memory segments; A data processing device according to any one of claims 1 to 15.

17. the memory circuit is further logically partitioned to include an active stack region; the tracking circuitry is restricted from tracking the active stack region; A data processing device according to any one of claims 1 to 15.

18. the tracing circuitry is further adapted to trace those of the accessors that are stored outside the memory segment; A data processing device according to any one of claims 1 to 17.

19. 1. A data processing method comprising the steps of: Logically dividing a physical address space of a memory into a plurality of memory segments; storing a plurality of accessors with associated validity indicators, each of the accessors controlling access to a region of the physical address space at least in accordance with its associated validity indicator; Tracking which of the memory segments contains the accessor; Responding to a request to invalidate an accessor by referencing the tracking circuitry to identify a set of equivalent accessors; invalidating the accessor and the equivalent accessor by setting the associated validity indicator of each of the accessor and the equivalent accessor to indicate that the accessor and the equivalent accessor are invalid; A method comprising:

20. 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising: a plurality of data structures for storing a plurality of accessors with associated validity indicators, each of said accessors controlling access to one of said data structures according to at least its associated validity indicator; tracing program logic for tracking which of said data structures contain said accessor; invalidation program logic for responding to a request to invalidate an accessor by referencing the tracing program logic to identify a set of equivalent accessors, and invalidating the accessor and the equivalent accessors by setting the associated validity indicators of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid; A computer program comprising:

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