Solid-state imaging device and electronic device

Abstract

To provide a solid-state image sensor and an electronic device that are compact and may reduce generation of a strong electric field in the vicinity of a transistor. A solid-state image sensor includes a photoelectric conversion device for photoelectric conversion; an element isolation that penetrates from a first principal surface to a second principal surface of a substrate and is formed between pixels including the photoelectric conversion device; and a conductive part provided in close contact with the first principal surface side of the element isolation.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device and an electronic device. [Background technology]

[0002] In recent years, solid-state imaging devices with front full trench isolation (FFTI) have been used. In solid-state imaging devices with FFTI, pixels are separated by an insulator, and each pixel is electrically separated. For this reason, each separated pixel needs to have a contact electrode for connecting the semiconductor substrate to, for example, a ground potential. In order to reduce the area of ​​the contact electrode in a plan view, a solid-state imaging device has been proposed in which a part of the FFTI is used as an active region and a contact electrode is formed thereon (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-39315 A Summary of the Invention [Problem to be solved by the invention]

[0004] In such a solid-state imaging device, in order to miniaturize the device, the impurity regions, which are regions with a high impurity concentration and serve as the source / drain of the transistor, are in close contact with or adjacent to the contact electrodes, which results in the generation of a strong electric field between the impurity regions and the contact electrodes.

[0005] In view of the above, an object of the present disclosure is to provide a solid-state imaging device and electronic device that are compact yet capable of suppressing the generation of a strong electric field near a transistor. [Means for solving the problem]

[0006] In order to solve the above problems, a solid-state imaging element according to one embodiment of the present disclosure is characterized in that it comprises a photoelectric conversion element that performs photoelectric conversion, a fully penetrating type element isolation that penetrates from a first main surface to a second main surface of a substrate and is formed between pixels that include the photoelectric conversion element, and a conductor portion provided in close contact with the first main surface side of the fully penetrating type element isolation.

[0007] In addition, an electronic device according to another aspect of the present disclosure is characterized in that it comprises a solid-state imaging device including a solid-state imaging element having a photoelectric conversion element that performs photoelectric conversion, a fully-penetrating element isolation that penetrates from a first main surface to a second main surface of a substrate and is formed between pixels including the photoelectric conversion element, and a conductor portion provided in close contact with the first main surface side of the fully-penetrating element isolation, an optical lens that focuses image light from a subject on an imaging surface of the solid-state imaging device, and a signal processing circuit that performs signal processing on a signal output from the solid-state imaging device. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing an overall configuration of a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 2A] 1 is a plan view showing an example of a layout of a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 2B] 1 is a cross-sectional view showing an example of a configuration of a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3A] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3B] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3C] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3D] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3E] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3F]1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 3G] 1A to 1C are cross-sectional process diagrams illustrating a method for manufacturing a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 4] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Diagram 5] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 6A] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 6B] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 7] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 8] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 9] 4 is a cross-sectional view showing another example of the configuration of the solid-state imaging element according to the first embodiment of the present disclosure. FIG. [Figure 10] FIG. 11 is a plan view showing an example of a layout of a solid-state imaging element according to a second embodiment of the present disclosure. [Figure 11] FIG. 11 is a plan view showing an example of a layout of a solid-state imaging element according to a second embodiment of the present disclosure. [Figure 12] FIG. 11 is a plan view showing an example of a layout of a solid-state imaging element according to a second embodiment of the present disclosure. [Figure 13] 11 is a cross-sectional view showing an example of the configuration of a solid-state imaging element according to a third embodiment of the present disclosure. FIG. [Figure 14A] FIG. 11 is a plan view showing an example of a layout of a solid-state imaging element according to a fourth embodiment of the present disclosure. [Figure 14B] 11 is a cross-sectional view showing an example of the configuration of a solid-state imaging element according to a fourth embodiment of the present disclosure. FIG. [Figure 14C] 11 is a cross-sectional view showing an example of the configuration of a solid-state imaging element according to a fourth embodiment of the present disclosure. FIG. [Figure 15A]FIG. 13 is a plan view showing an example of a layout of a solid-state imaging element according to a fifth embodiment of the present disclosure. [Figure 15B] 13 is a cross-sectional view showing an example of the configuration of a solid-state imaging element according to a fifth embodiment of the present disclosure. FIG. [Figure 15C] 13 is a cross-sectional view showing an example of the configuration of a solid-state imaging element according to a fifth embodiment of the present disclosure. FIG. [Figure 16] FIG. 13 is a plan view showing an example of a layout of a solid-state imaging element according to a sixth embodiment of the present disclosure. [Figure 17] FIG. 13 is a plan view showing an example of a layout of a solid-state imaging element according to a sixth embodiment of the present disclosure. [Figure 18] FIG. 13 is a schematic configuration diagram of an electronic device according to a seventh embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an example of an optical element, an optical element array, an electronic device, and a manufacturing method of an optical element according to an embodiment of the present disclosure will be described with reference to Figs. 1 to 18. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. In addition, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0010] 1. First embodiment: solid-state imaging device (1.1) Overall configuration of solid-state imaging device (1.2) Structure of solid-state imaging device (1.3) Manufacturing method of solid-state imaging device (1.4) Variations 2. Second embodiment: solid-state imaging device (2.1) First Example of Solid-State Imaging Device 200 (2.2) Second Example of Solid-State Imaging Device 200 (2.3) Third Example of Solid-State Imaging Device 200 3. Third embodiment: Solid-state imaging device (3.1) Structure of solid-state imaging device 4. Fourth embodiment: solid-state imaging device (4.1) Structure of solid-state imaging device 5. Fifth embodiment: Solid-state imaging device (5.1) Structure of solid-state imaging device 6. Sixth embodiment: Solid-state imaging device (6.1) Structure of solid-state imaging device (6.1.1) First Example of Solid-State Imaging Device 600 (6.1.2) Second Example of Solid-State Imaging Device 600 7. Seventh embodiment: Electronic device

[0011] 1. First embodiment: solid-state imaging device (1.1) Overall configuration of solid-state imaging device A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described below. Fig. 1 is a schematic configuration diagram showing the entire solid-state imaging device 1 according to the first embodiment of the present disclosure.

[0012] The solid-state imaging device 1 shown in Fig. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in Fig. 18, the solid-state imaging device 1 captures image light (incident light 1006) from a subject via an optical lens 1002, converts the amount of incident light 1006 focused on an imaging surface into an electrical signal on a pixel-by-pixel basis in a signal processing circuit 1005, and outputs the electrical signal as a video signal (pixel signal). As shown in FIG. 1, the solid-state imaging device 1 of the first embodiment includes a substrate 2, a pixel region 3, a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

[0013] The pixel region 3 has a plurality of pixels 9 regularly arranged in a two-dimensional array on the substrate 2. Each pixel 9 has a photoelectric conversion unit 23 shown in FIG. 2B and a plurality of pixel transistors (not shown). As the plurality of pixel transistors, for example, four transistors can be used: a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor. Alternatively, for example, three transistors excluding the selection transistor may be used.

[0014] The vertical drive circuit 4 is configured, for example, by a shift register, selects a desired pixel drive line L1, supplies a pulse for driving the pixels 9 to the selected pixel drive line L1, and drives each pixel 9 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 9 in the pixel area 3 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in the photoelectric conversion unit 23 of each pixel 9 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line L2.

[0015] The column signal processing circuit 5 is arranged, for example, for each column of pixels 9, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 9. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion for removing fixed pattern noise specific to each pixel. The horizontal drive circuit 6 is, for example, constituted by a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, selects each of the column signal processing circuits 5 in turn, and causes each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to the horizontal signal line L3.

[0016] The output circuit 7 performs signal processing on the pixel signals sequentially supplied through the horizontal signal line L3 from each of the column signal processing circuits 5, and outputs the processed signals. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, and the like. The control circuit 8 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0017] (1.2) Structure of solid-state imaging device Next, a detailed structure of the solid-state imaging device 1 in Fig. 1 will be described with reference to Fig. 2A and Fig. 2B. Fig. 2A is a plan view showing an example of a layout of a solid-state imaging element 100 in a pixel region 3 of the solid-state imaging device 1. Fig. 2B is a cross-sectional view of a pixel 9 of the solid-state imaging element 100 in the A-A' cross section shown in Fig. 2A. The solid-state imaging device 1 having the solid-state imaging element 100 shown in Figs. 2A and 2B is a back-illuminated CMOS image sensor (CMOS type solid-state imaging device).

[0018] 2A, the solid-state imaging element 100 has a plurality of pixels 9 (9a, 9b, etc.) two-dimensionally arranged on a substrate 2. The solid-state imaging element 100 includes a transfer transistor Ttr, a reset transistor Trs, an amplifying transistor Tam, and a select transistor Tsl. The transfer transistor Ttr is a transistor that reads out charges from the photoelectric conversion element 22 and transfers the charges to the floating diffusion 41. The reset transistor Trs is a transistor that resets the potential of the floating diffusion 41 to a power supply voltage. The amplification transistor Tam is a transistor that receives the potential of the floating diffusion 41 at its gate and outputs it to a vertical signal line (VSL) as a source follower. The select transistor Tsl is a transistor that connects the amplification transistor Tam of a row to be read out to the vertical signal line and disconnects the amplification transistor Tam of a row not to be read out from the vertical signal line.

[0019] 2A and 2B, the solid-state imaging element 100 has a structure in which pixels 9 (9a, 9b, etc.) including photoelectric conversion elements (PD: Photo Diode) 22 that photoelectrically convert incident light are separated by front full trench isolation (FFTI: Front Full Trench Isolation) 11. In the solid-state imaging element 100, light is incident on the photoelectric conversion elements 22 from a second main surface (lower surface in FIG. 2B) opposite to a first main surface (upper surface in FIG. 2B) that is a transistor formation surface of the solid-state imaging element 100. Hereinafter, the first main surface may be referred to as the upper surface, and the second main surface may be referred to as the lower surface.

[0020] As shown in FIG. 2B, the solid-state imaging element 100 includes a substrate 2, an FFTI 11, a buried conductor portion 12, an insulating portion 13, a well layer 21, and a photoelectric conversion element 22. The solid-state imaging element 100 also includes a gate insulating film 31, gate electrodes 32, 33, 34, and 35, a floating diffusion 41, and a high-concentration impurity diffusion layer 42. Note that FIGS. 2A and 2B also show a GND contact 50 electrically connected to the buried conductor portion 12. A light collecting layer is formed on the lower surface side of the substrate 2, in which a color filter layer and a wafer lens (not shown) are laminated in this order. Furthermore, a wiring layer and a logic substrate (not shown) are laminated in this order on the transistor-forming side (upper surface) of the substrate 2.

[0021] (substrate) The substrate 2 is made of, for example, silicon (Si). A pixel region 3 in which a plurality of pixels 9 are arranged is formed on the substrate 2. In the pixel region 3, as shown in FIG. 2B, a plurality of pixels 9 including a photoelectric conversion element 22 are formed on the substrate 2 and arranged in a two-dimensional matrix.

[0022] (Complete through-type element isolation) The full through type isolation (FFTI) 11 is formed so as to penetrate from the transistor forming side (top surface) of the substrate 2 to the bottom surface and completely isolate each pixel 9. The FFTI 11 is provided to surround the pixel 9 in a plan view, and each pixel 9 is electrically isolated from adjacent pixels 9 by the FFTI 11. The FFTI 11 has a structure in which an isolation film such as a silicon oxide film or a silicon nitride film is embedded in a trench formed in the substrate 2. The FFTI 11 may also have a two-layer structure of an isolation film formed so as to cover the inner wall of the trench, and a semiconductor film such as silicon embedded in the trench in which the isolation film is formed.

[0023] (Embedded conductor part) The buried conductor 12 functions as a contact electrode for GND contact with the substrate 2 (high-concentration impurity diffusion layer 42). The buried conductor 12 is embedded in a trench formed in the upper surface of the substrate 2. The buried conductor 12 is formed by filling the entire trench provided in the upper part of the substrate 2 with the FFTI 11 as the bottom surface with a conductive film. As described above, in the solid-state imaging device 100, each pixel 9 is electrically isolated by the FFTI 11. For this reason, in the solid-state imaging device 100, each isolated pixel 9 needs to have a potential (reference potential) contact with the well layer 21. In the solid-state imaging device 100, a part of the transistor formation surface side of the FFTI 11 is used as an active region, as the buried conductor 12, and is made to function as a contact electrode. In this way, by arranging the buried conductor 12 closely above the FFTI 11, it is possible to suppress an increase in the area of ​​the solid-state imaging device 100 in a plan view caused by forming a contact electrode, and it is possible to reduce the area of ​​the solid-state imaging device 100.

[0024] 2A, the embedded conductor portions 12 are provided at all of the boundaries between the pixels 9. The GND contacts 50 are provided so as to connect to parts of the embedded conductor portions 12 provided at the boundaries between the pixels 9. The buried conductor 12 is formed above the FFTI 11 (on the transistor formation surface side) in a cross-sectional view. The buried conductor 12 is formed deeper than the insulating portion 13, and is thereby disposed in close contact with the well layer 21 in a region deeper than the insulating portion 13. As a result, the buried conductor 12 is electrically connected to the well layer 21 through an ohmic junction. As shown in FIGS. 2A and 2B, the buried conductor portion 12 is provided above and in close contact with the FFTI 11 provided between the pixels 9, and is shared between two adjacent pixels 9 as a contact electrode for GND contact.

[0025] The buried conductor 12 is formed by a conductive film. As the conductive film, it is preferable to use silicon or other semiconductor material doped with P-type or N-type impurities, or a metal. As the silicon, for example, polycrystalline silicon, amorphous silicon, epitaxially grown silicon, etc. are preferable.

[0026] (insulation part) The insulating portion 13 is an insulating layer provided between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 on the upper surface (the transistor forming side) of the substrate 2. By providing the insulating portion 13 between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42, the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 are brought into close contact with each other, thereby suppressing the generation of a strong electric field between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42.

[0027] The insulating portion 13 is formed by STI (Shallow Trench Isolation) or an insulating film. Any commonly used material may be used for the STI, for example, silicon oxide. As the insulating film, it is preferable to use an oxide film, and in particular, it is preferable to use a silicon oxide film. The insulating portion 13 is formed by embedding, as an insulating film, for example, an oxide film in a trench formed on the upper surface (the side where the transistor is formed) of the substrate 2.

[0028] By providing such an insulating portion 13, the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 described later are not in close contact with each other, and the distance between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 increases. Therefore, a strong electric field is unlikely to be generated between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42, and the stability of the output of the solid-state imaging element 100 is improved. Moreover, by providing such an insulating portion 13, the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 are spaced apart in the vertical direction (depth direction of the substrate 2). Therefore, it is possible to suppress the generation of a strong electric field between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 without increasing the size of the solid-state imaging element 100 in a plan view, and to simultaneously achieve a reduction in the area of ​​the solid-state imaging element 100 and an improvement in the stability of the output. The deeper the insulating portion 13 and the buried conductor portion 12 are formed, the larger the vertical distance between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 becomes. Therefore, for example, the insulating portion 13 and the buried conductor portion 12 can be formed to a depth according to the magnitude of the current flowing through the solid-state imaging element 100, thereby suppressing the generation of a strong electric field.

[0029] (Well layer) The well layer 21 is a P-type region in which P-type (an example of a first conductivity type) impurities are diffused at a low concentration. The well layer 21 is formed in a region deeper than a high-concentration impurity diffusion layer 42, which will be described later. The well layer 21 is disposed in close contact with the conductor portion 12 in a region deeper than the insulating portion 13. The well layer 21 forms a PN junction with the photoelectric conversion element 22, as will be described later.

[0030] (Photoelectric conversion element) The photoelectric conversion element 22 is a photodiode that converts incident light into an amount of charge according to the amount of received light and accumulates the charge. The photoelectric conversion element 22 receives light that is incident through a lens and a color filter arranged relative to the photoelectric conversion element 22 on the lower surface of the substrate and corresponds to the color of the color filter. The photoelectric conversion elements 22 provided in each pixel 9 are separated by the FFTI 11.

[0031] The photoelectric conversion element 22 is a region formed in a region surrounded by the well layer 21, which is a P-type region, in each pixel 9. The photoelectric conversion element 22 is an N-type region in which N-type (an example of a second conductivity type) impurities different from the impurities diffused in the well layer 21 are diffused at a low concentration. As a result, a PN junction is formed between the photoelectric conversion element 22 and the well layer 21, and the photoelectric conversion element 22 has a photoelectric conversion function. The photoelectric conversion element 22 functions as the source region of the transfer transistor Ttr.

[0032] (Gate insulating film) The gate insulating film 31 is an insulating film formed between the photoelectric conversion element 22 and the floating diffusion 41, and between the floating diffusion 41 and the high-concentration impurity diffusion layer 42. The gate insulating film 31 is, for example, a silicon oxide film.

[0033] (gate electrode) Gate electrodes 32, 33, 34 and 35 are the gate electrodes of the transfer transistor Ttr, the reset transistor Trs, the amplifier transistor Tam and the select transistor Tsl, respectively. 2B, the gate electrodes 32, 33, 34, and 35 are formed of a conductive film such as a polycrystalline silicon film. In particular, the gate electrode 32 is formed in a trench formed in the well layer 21 so as to extend to the vicinity of the photoelectric conversion element 22. The gate electrode 32 is formed by embedding a conductive film in the trench having a gate insulating film 31 provided on its surface.

[0034] (Floating Diffusion) The floating diffusion 41 is a region formed on the surface of the transistor formation side (upper side) of the substrate 2, and temporarily holds the charge read out by the transfer transistor Ttr. The floating diffusion 41 is a region in which, for example, N-type (an example of a second conductivity type) impurities are diffused at a high concentration in the transistor formation region on the upper surface of the substrate 2. The floating diffusion 41 is formed in a region of the well layer 21 that includes the boundary between the channel region of the transfer transistor Ttr and the channel region of the reset transistor Trs. The floating diffusion 41 functions as a drain region when the transfer transistor Ttr is driven, and functions as a source region when the reset transistor Trs is driven.

[0035] (High concentration impurity diffusion layer) The high-concentration impurity diffusion layer 42 is formed on the transistor formation surface (upper surface) side of the substrate 2, and is a region in which, for example, N-type (an example of a second conductivity type) impurities are diffused at a high concentration. The high-concentration impurity diffusion layer 42 is formed shallower than the insulating portion 13. The high-concentration impurity diffusion layer 42 functions as a drain region of the reset transistor Trs.

[0036] In the solid-state imaging element 100 of the first embodiment described above, it is possible to suppress the generation of a strong electric field between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 without increasing the size of the solid-state imaging element 100 in a planar view, thereby achieving both a reduction in the area of ​​the solid-state imaging element 100 and improved output stability.

[0037] (1.3) Manufacturing method of solid-state imaging device A method for manufacturing the solid-state imaging element 100 according to the first embodiment will be described with reference to Fig. 3A to Fig. 3G. Fig. 3A to Fig. 3G are process cross-sectional views showing the method for manufacturing the solid-state imaging element 100. Fig. 3A to Fig. 3G show process cross-sectional views of a pixel 9 (unit pixel).

[0038] As shown in FIG. 3A, a trench is formed in a first main surface of the substrate 2, which is to be a surface on which a transistor is to be formed (the upper surface in FIG. 3A), and an insulating material is filled in to form an STI 13A. 3B, a trench is formed penetrating from the first main surface of the substrate 2 to the second main surface, which is the opposite side (the lower surface in FIG. 3B) of the substrate 2, and then an element isolation film 11' such as a silicon oxide film or a silicon nitride film is embedded in the trench. At this time, the trench is formed so as to penetrate the STI.

[0039] 3C, a part of the first main surface of the element isolation film 11' embedded in the trench is removed to form a trench. As a result, the FFTI 11 is formed by the element isolation film 11'. Note that an etching stopper film may be formed on the first main surface of the substrate 2 before removing the part of the first main surface of the element isolation film 11'. 3D, a semiconductor film 12', such as polysilicon doped with impurities, is formed so as to cover the formed trench and the first main surface of the substrate 2. The semiconductor film 12' is formed by, for example, a chemical vapor deposition (CVD) method.

[0040] 3E, the semiconductor film 12' deposited on the first main surface of the substrate 2 is planarized by chemical mechanical polishing (CMP), thereby forming the buried conductor portion 12. As shown in FIG. 3F, a semiconductor element is formed in the pixel 9 separated by the FFTI 11. First, a well layer 21, which is a P-type region, is formed by ion-implanting P-type impurities into the substrate 2. In addition, a photoelectric conversion element 22, which is an N-type region, is formed by ion-implanting N-type impurities into a region surrounded by the well layer 21. A PN junction is formed between the well layer 21 and the photoelectric conversion element 22. Next, a trench extending from the upper surface of the substrate 2 to the vicinity of the upper surface of the photoelectric conversion element 22 is formed by thermally oxidizing the substrate 2. Thereafter, a gate insulating film 31 is formed to cover the upper surface of the substrate 2 and the surface of the trench. Next, a conductive film is embedded in the trench in which the gate insulating film 31 is provided, and a conductive film is formed on the upper surface of the substrate 2. Then, a part of the conductive film is removed using lithography and etching techniques to form a gate electrode 32 of the transfer transistor Ttr and a gate electrode 33 of the reset transistor Trs. Finally, N-type impurities are ion-implanted into a predetermined region on the upper surface of the substrate 2, and the ion-implanted region is activated by heat treatment. As a result, a floating diffusion 41 and a high-concentration impurity diffusion layer 42 are formed.

[0041] As shown in Fig. 3G, an interlayer insulating film is formed so as to cover the upper surface of the substrate 2 on which the transistors are formed, and then a contact hole is formed through the interlayer insulating film to reach the buried conductor 12. Finally, a conductive material is embedded in the contact hole to form a GND contact 50. In Fig. 3G, the interlayer insulating film is not shown, and only the GND contact 50 is shown.

[0042] (1.4) Variations Hereinafter, seven examples of the solid-state imaging element 100, namely solid-state imaging elements 100A, 100B, 100C, 100D, 100E, 100F and 100G, will be described with reference to Fig. 4 to Fig. 9. The solid-state imaging elements 100A to 100G differ from the solid-state imaging element 100 according to the first embodiment in that the solid-state imaging elements 100A to 100G include embedded conductor portions 12A to 12G, respectively, instead of the embedded conductor portion 12.

[0043] Among the solid-state imaging elements 100A to 100G, detailed description of portions having the same functions as those of the solid-state imaging element 100 according to the first embodiment will be omitted, and illustrations in Fig. 4 to Fig. 9 will be omitted. That is, detailed description of the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34, and 35, as well as the floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixels 9 of the solid-state imaging elements 100A to 100G will be omitted.

[0044] (1.4.1) First modified example Fig. 4 is a cross-sectional view of a pixel 9 of a solid-state imaging element 100A which is an example of a modification of the solid-state imaging element 100. Fig. 4 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. 4, the buried conductor 12A of the solid-state imaging device 100A is a conductive film formed on the surface of a trench provided in the upper part of the substrate 2 having the FFTI 11 as the bottom surface. The buried conductor 12A only needs to have a portion in close contact with the well layer 21. In other words, the buried conductor 12A may have a shape in which a portion of the trench is filled with a conductive material (the trench is not completely filled with the conductive material).

[0045] 9, the buried conductor 12B is a conductive film formed on the surface of a trench formed on the upper surface of the substrate 2, and an air space surrounded by the conductive film on the sides and below exists in the trench. The buried conductor 12B may have a configuration in which pure polysilicon or an oxide film is buried in the trench.

[0046] (1.4.2) Second Modification Fig. 5 is a cross-sectional view of a pixel 9 of a solid-state imaging element 100B which is an example of a modification of the solid-state imaging element 100. Fig. 5 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. 5, the buried conductor 12B of the solid-state imaging device 100B is a conductive film formed on the surface of a trench provided in the upper part of the substrate 2 having the FFTI 11 as the bottom surface. The buried conductor 12B only needs to have a portion in close contact with the well layer 21. That is, the buried conductor 12A may have a shape in which a portion of the trench is filled with a conductive material (the trench is not completely filled with the conductive material). That is, the buried conductors 12A and 12B may have a shape in which the trench is not completely filled with the conductive material.

[0047] 5, the buried conductor 12B is a conductive film formed on the surface of a trench formed on the upper surface of the substrate 2, and within the trench there is an air space surrounded on the sides and below by the conductive film. The buried conductor 12B may be configured such that pure polysilicon or an oxide film is buried in the trench.

[0048] (1.4.3) Third Modification Figures 6A and 6B are cross-sectional views of a pixel 9 of a solid-state imaging element 100C which is an example of a modification of the solid-state imaging element 100. Figures 6A and 6B are cross-sectional views corresponding to Figure 2B in the first embodiment. As shown in Figures 6A and 6B, the buried conductors 12C and 12D of the solid-state imaging device 100C are embedded in a trench formed near the upper surface of the substrate 2, with the FFTI 11 as the bottom surface. The buried conductors 12C and 12D have an inverted taper shape or a taper shape in cross-sectional view. Here, Figure 6A illustrates a configuration in which the buried conductor 12C has a taper shape that narrows from the lower surface to the upper surface of the buried conductor 12C. Figure 6B illustrates a configuration in which the buried conductor 12D has a taper shape that narrows from the upper surface to the lower surface of the buried conductor 12C.

[0049] To form the buried conductors 12C and 12D, first, trenches for forming the FFTI 11 and the buried conductors 12C and 12D are formed so as to penetrate the STI formed on the upper surface of the substrate 2, and an insulating film is embedded in the trench to form the FFTI 11. Next, a conductive film is embedded in the trench above the FFTI 11 to form the buried conductors 12C and 12D. Depending on the process such as etching used to form the buried conductors 12C and 12D, the trench may have a tapered shape, and the cross-sectional shapes of the buried conductors 12C and 12D will also have a tapered shape.

[0050] (1.4.4) Fourth Modification Fig. 7 is a cross-sectional view of a pixel 9 of a solid-state imaging element 100D which is an example of a modification of the solid-state imaging element 100. Fig. 7 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. As shown in FIG. 7, the embedded conductor portion 12E and the insulating portion 13E of the solid-state imaging device 100D each have a tapered shape that narrows from the lower surface to the upper surface in a cross-sectional view.

[0051] To form the buried conductor 12E, first, for example, a trench is formed on the upper surface of the substrate 2 to form an STI that will become the insulating portion 13. Next, a trench for forming the FFTI 11 and the buried conductor 12E is formed so as to penetrate the STI, and an insulating film is embedded in the trench to form the FFTI 11. Finally, a conductive film is embedded in the upper part of the FFTI 11 in the trench to form the buried conductor 12E. Depending on the process such as etching used when forming the buried conductor 12E, both the shape of the trench formed when forming the insulating portion 13 and the shape of the trench formed when forming the buried conductor 12E may be tapered. In such a case, the cross-sectional shapes of the insulating portion 13 and the buried conductor 12E are also similarly tapered.

[0052] (1.4.5) Fifth Modification Fig. 8 is a cross-sectional view of a pixel 9 of a solid-state imaging element 100E which is an example of a modification of the solid-state imaging element 100. Fig. 8 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. 8, the buried conductor 12F of the solid-state imaging device 100E is embedded in a trench formed in the vicinity of the upper surface of the substrate 2 and having the FFTI 11 as its bottom surface. The buried conductor 12F has a shape in which multiple cylinders are stacked in a cross-sectional view, the diameter of which gradually increases toward the upper surface of the substrate 2. To form the buried conductor 12F, first, a trench for forming the FFTI 11 and the buried conductor 12F is formed so as to penetrate the STI formed on the upper surface of the substrate 2, and an insulating film is embedded in the trench to form the FFTI 11. Next, a conductive film is embedded in the trench above the FFTI 11 to form the buried conductor 12F. At this time, by forming the trenches for forming the FFTI 11 and the buried conductor portion 12F by etching multiple times, the shape of the trench may become a shape of multiple stacked cylinders. In this case, the cross-sectional shape of the buried conductor portion 12F also becomes a shape of multiple stacked cylinders.

[0053] (1.4.6) Sixth Modification Fig. 9 is a cross-sectional view of a pixel 9 of a solid-state imaging element 100F which is an example of a modification of the solid-state imaging element 100. Fig. 9 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. 9, the buried conductor 12G of the solid-state imaging device 100F is buried in a trench formed in the vicinity of the upper surface of the substrate 2 and having the FFTI 11 as its bottom surface. The buried conductor 12G has a width wider than the FFTI 11 in a cross-sectional view. Depending on the process such as etching used to form the buried conductor 12G, the width of the trench in the portion where the buried conductor 12G is formed may be wider than the width of the trench in the portion where the FFTI 11 is formed. In such a case, the buried conductor 12G will have a width wider than the FFTI 11 in a cross-sectional view.

[0054] <Advantages of the First Embodiment> The solid-state imaging device 1, the solid-state imaging element 100, and the solid-state imaging elements 100A to 100G according to this embodiment provide the following advantages. (1) In the solid-state imaging element 100, a buried conductor 12 functioning as a contact electrode is provided in close contact with and above a full through type element isolation (FFTI) 11 that separates each pixel 9. This eliminates the need to provide a contact electrode within the pixel 9 of the solid-state imaging element 100, and can suppress an increase in the area of ​​each pixel 9 in a plan view, thereby enabling the area of ​​the solid-state imaging element 100 to be reduced.

[0055] (2) In the solid-state imaging element 100, an insulating portion 13 is provided between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 in a plan view. As a result, in the solid-state imaging element 100, the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 are not in close contact with each other, and the distance between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 is increased. As a result, a strong electric field is unlikely to be generated between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42, and the stability of the output of the solid-state imaging element 100 is improved.

[0056] (3) In the solid-state imaging element 100, the insulating portion 13 is provided between the buried conductor portion 12 formed deeper than the insulating portion 13 in a cross-sectional view and the high-concentration impurity diffusion layer 42 formed shallower than the insulating portion 13 near the surface of the transistor formation surface of the substrate 2. This separates the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 in the vertical direction (depth direction of the substrate 2). This makes it possible to suppress the generation of a strong electric field between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42 without increasing the size of the solid-state imaging element 100 in a plan view, thereby achieving both a smaller area of ​​the solid-state imaging element 100 and improved stability of the output.

[0057] 2. Second embodiment: solid-state imaging device A solid-state imaging element 200 according to a second embodiment of the present disclosure will be described below. The solid-state imaging element 200 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment. In the second embodiment, solid-state imaging elements 200A, 200B, and 200C, which are three examples of the solid-state imaging element 200, will be described with reference to Fig. 10 to Fig. 12. Note that, of the solid-state imaging element 200, detailed description and illustration in Fig. 10 to Fig. 12 of portions having the same functions as the solid-state imaging element 100 according to the first embodiment will be omitted. That is, detailed description of the well layer 21, the photoelectric conversion element 22, the gate insulating film 31, the gate electrodes 32, 33, 34, and 35, the floating diffusion 41, and the high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 200A will be omitted.

[0058] (2.1) First Example of Solid-State Imaging Device 200 FIG. 10 is a plan view showing an example of the layout of a solid-state imaging element 200A which is an example of the solid-state imaging element 200. As shown in FIG. As shown in FIG. 10, the solid-state imaging element 200A differs from the solid-state imaging element 100 according to the first embodiment in that the embedded conductor portion 12 is provided in close contact with a portion of the surface of the FFTI 11 provided at the boundary between the pixels 9. The arrangement of the FFTI 11 and the buried conductor portion 12, and the connection of the GND contact 50 will be described below.

[0059] 10, the FFTI 11 of the solid-state imaging element 200A is provided at all of the boundaries between the pixels 9. The embedded conductor portions 12 of the solid-state imaging element 200A are provided only at some of the boundaries between the pixels 9, particularly at the intersections of the four FFTI 11 separating adjacent pixels 9 among the four pixels 9 arranged in a 2×2 array (the central portions of the four pixels 9). In other words, the embedded conductor portions 12 of the solid-state imaging element 200A are provided at the four corners of one pixel 9.

[0060] At the intersection of the four FFTIs 11, a buried conductor 12 is provided adjacent to and above (on the front side in FIG. 10) the FFTIs 11. The buried conductor 12 is formed deeper than the insulating portion 13, and is thereby disposed in close contact with the well layer 21. On the other hand, in areas other than where the four FFTIs 11 intersect, no buried conductor portion 12 is provided above the FFTIs 11 (the front side in Figure 10), and the FFTIs 11 extend from the transistor-forming side of the substrate 2 (the front side in Figure 10) to the bottom side (the back side in Figure 10).

[0061] When the buried conductor portion 12 is provided above a portion of the FFTI 11 (the four corners of one pixel 9), the buried conductor portion 12 may be sealed by removing the upper part of the buried semiconductor material after the semiconductor material is buried, and covering the upper part with an insulator such as silicon oxide.

[0062] The embedded conductor portion 12 is shared as a contact electrode for GND contact between four adjacent pixels 9. Each pixel 9 has four contact electrodes at its four corners. Therefore, in the solid-state imaging element 200A, even if any of the embedded conductor portions 12 no longer functions as a contact electrode, the other embedded conductor portions 12 function as contact electrodes, improving the quality of the solid-state imaging device 1 including the solid-state imaging element 200A.

[0063] (2.2) Second Example of Solid-State Imaging Device 200 FIG. 11 is a plan view showing an example of the layout of a solid-state imaging element 200B which is an example of the solid-state imaging element 200. As shown in FIG. 11, the solid-state imaging element 200B differs from the solid-state imaging element 100 according to the first embodiment in that the embedded conductor portions 12 are provided in close contact with a part of the surface of the FFTI 11 provided at the boundary between the pixels 9. The solid-state imaging element 200B also differs from the solid-state imaging element 200A in that the GND contacts 50 are connected to a part of the formed embedded conductor portions 12, and only a part of the embedded conductor portions 12 functions as a contact electrode. The arrangement of the FFTI 11 and the buried conductor portion 12, and the connection of the GND contact 50 will be described below.

[0064] 11, the FFTI 11 of the solid-state imaging element 200B is provided at all of the boundaries between the pixels 9. Moreover, the embedded conductor portions 12 of the solid-state imaging element 200B are provided only at some of the boundaries between the pixels 9, particularly at the portions (central portions of the four pixels 9) where the four FFTI 11 separating adjacent pixels 9 of the four pixels 9 arranged in a 2×2 array intersect. In other words, the embedded conductor portions 12 of the solid-state imaging element 200B are provided at the four corners of one pixel 9.

[0065] At the intersection of the four FFTIs 11, buried conductors 12 are provided above the FFTIs 11 (on the front side in FIG. 11) so as to be deeper than the insulating portion 13 and to be in contact with the well layer 21. The GND contact 50 is connected to some of the buried conductors 12 provided at the intersection of the four FFTIs 11. It is sufficient that the GND contact 50 can be electrically connected to an adjacent pixel 9. For this reason, for example, as shown in FIG. 11, in one pixel 9, the GND contact 50 is connected to a pair of buried conductors 12 provided at diagonal positions.

[0066] The embedded conductor portions 12 arranged as described above are shared as contact electrodes for GND contact between four adjacent pixels 9. Each pixel 9 has two contact electrodes at two corners. Therefore, even if one embedded conductor portion 12 in the solid-state imaging element 200B no longer functions as a contact electrode, the other embedded conductor portion 12 functions as a contact electrode, improving the quality of the solid-state imaging device 1 including the solid-state imaging element 200B.

[0067] (2.3) Third Example of Solid-State Imaging Device 200 FIG. 12 is a plan view showing an example of the layout of a solid-state imaging element 200C which is an example of the solid-state imaging element 200. As shown in FIG. 12, the solid-state imaging element 200C differs from the solid-state imaging element 100 according to the first embodiment in that the embedded conductor portions 12 are provided in close contact with a portion of the surface of the FFTI 11 provided at the boundary between the pixels 9. The solid-state imaging element 200C also differs from the solid-state imaging element 200A in that the embedded conductor portions 12 are provided only at diagonal positions (two corners) of one pixel 9. The arrangement of the FFTI 11 and the buried conductor portion 12, and the connection of the GND contact 50 will be described below.

[0068] 12, the FFTI 11 of the solid-state imaging element 200C is provided at all of the boundaries between the pixels 9. Moreover, the embedded conductor portions 12 of the solid-state imaging element 200C are provided at some of the boundaries between the pixels 9. The embedded conductor portions 12 are provided at a pair of diagonal positions of one pixel 9.

[0069] At diagonal positions of one pixel 9, buried conductors 12 are provided above the FFTI 11 (on the front side in FIG. 12) so as to be deeper than the insulating portion 13 and to be in contact with the well layer 21. The GND contacts 50 are connected to the buried conductors 12 provided at the diagonal positions of the pixel 9.

[0070] The buried conductor portions 12 arranged as described above are shared as contact electrodes for GND contact between four adjacent pixels 9. Each pixel 9 has two contact electrodes at two corners. Therefore, even if one buried conductor portion 12 in the solid-state imaging element 200C no longer functions as a contact electrode, the other buried conductor portion 12 functions as a contact electrode, improving the quality of the solid-state imaging device 1 including the solid-state imaging element 200C. Furthermore, by not providing the buried conductor portion 12 in the portion where the GND contact 50 is not arranged, as in the solid-state imaging element 200C, the characteristics of the solid-state imaging element 200C and the yield rate during the manufacture of the solid-state imaging element 200C are improved.

[0071] The solid-state imaging element 200 may have, instead of the embedded conductor portion 12, any of the embedded conductor portions 12A to 12G of the modified examples of the first embodiment.

[0072] <Effects of the second embodiment> The solid-state imaging device 200 according to this embodiment has the following advantages in addition to the advantages described in the first embodiment. (4) In the solid-state imaging element 200, embedded conductor portions 12 functioning as contact electrodes are provided at the corners of each pixel 9. As a result, the embedded conductor portions 12 are shared as contact electrodes for GND contact between four adjacent pixels 9, and even if any embedded conductor portion 12 no longer functions as a contact electrode, the other embedded conductor portions 12 function as contact electrodes. This improves the quality of the solid-state imaging device 1 having the solid-state imaging element 200A.

[0073] (5) In the solid-state imaging element 200, the embedded conductor portion 12 is provided only in the diagonal corners (two corners) of each pixel 9. This improves the characteristics of the solid-state imaging element 200C and the yield rate during manufacture of the solid-state imaging element 200C, as compared to a case in which the embedded conductor portion 12 is provided in the four corners of each pixel 9.

[0074] 3. Third embodiment: Solid-state imaging device A solid-state imaging element 300 according to a third embodiment of the present disclosure will be described below. The solid-state imaging element 300 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment.

[0075] (3.1) Structure of solid-state imaging device In the third embodiment, the solid-state imaging element 300 will be described with reference to Fig. 13. Note that, of the solid-state imaging element 300, detailed description and illustration in Fig. 13 will be omitted for portions having the same functions as those of the solid-state imaging element 100 according to the first embodiment. That is, detailed description and illustration will be omitted for the well layer 21, the photoelectric conversion element 22, the gate insulating film 31, the gate electrodes 32, 33, 34, and 35, the floating diffusion 41, and the high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 300.

[0076] Fig. 13 is a cross-sectional view of a pixel 9 of a solid-state imaging element 300. Fig. 13 is a cross-sectional view corresponding to Fig. 2B in the first embodiment. The solid-state imaging element 300 differs from the solid-state imaging element 100 according to the first embodiment in that the solid-state imaging element 300 includes an insulating portion 313 instead of the insulating portion 13. 13, the insulating portion 313 has a two-layer structure consisting of an insulating film covering the surface of a trench provided between the buried conductor portion 12 and the high-concentration impurity diffusion layer 42, and pure polysilicon or oxide embedded in the trench. The insulating portion 313 may have an air layer (air gap) instead of pure polysilicon or oxide. That is, it is sufficient that at least the surface of the insulating portion 313 is made of an insulating material. By providing such insulating portion 313, the width of insulating portion 313 can be made narrower than that of insulating portion 13, which is effective for miniaturizing pixels.

[0077] The solid-state imaging device 300 may have, instead of the embedded conductor portion 12, any of the embedded conductor portions 12A to 12G of the modified examples of the first embodiment.

[0078] <Effects of the third embodiment> The solid-state imaging device 300 according to this embodiment has the following advantages in addition to the advantages described in the first embodiment. (6) In the solid-state imaging device 300, the insulating section 313 has a two-layer structure consisting of an insulating film formed on the surface of the trench and a pure polysilicon or oxide film, or an air layer, embedded in the trench with the insulating film formed in. This allows the width of the insulating section 313 to be made narrower, which is more effective in reducing the area of ​​the solid-state imaging device 300.

[0079] 4. Fourth embodiment: solid-state imaging device A solid-state imaging element 400 according to a fourth embodiment of the present disclosure will be described below. The solid-state imaging element 400 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment.

[0080] (4.1) Structure of solid-state imaging device In the fourth embodiment, a solid-state imaging element 400 will be described with reference to Fig. 14A to Fig. 14C. The solid-state imaging element 400 differs from the solid-state imaging element 100 according to the first embodiment in that it includes embedded conductors 412 for connecting pixels 9 together instead of the embedded conductors 12. The solid-state imaging element 400 also differs from the solid-state imaging element 100 according to the first embodiment in that it includes an insulating portion 414. Furthermore, the solid-state imaging element 400 differs from the solid-state imaging element 100 according to the first embodiment in that a contact electrode 460 and an embedded conductor 43 are provided.

[0081] 14A to 14C of portions of the solid-state imaging element 400 having the same functions as those of the solid-state imaging element 100 according to the first embodiment. That is, detailed descriptions of the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34, and 35, as well as the floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 400 will be omitted.

[0082] Fig. 14A is a plan view showing an example of the layout of the solid-state imaging element 400. Fig. 14B is a cross-sectional view of a pixel 9 of the solid-state imaging element 400 in the B-B' cross section shown in Fig. 14A. Fig. 14B is a cross-sectional view of a portion including the transfer transistor Ttr and the reset transistor Trs. Fig. 14C is a cross-sectional view of a pixel 9 of the solid-state imaging element 400 in the C-C' cross section shown in Fig. 14A. Fig. 14C is a cross-sectional view of a portion including the amplification transistor Tam and the select transistor Tsl.

[0083] 14A, the solid-state imaging element 400 has a contact electrode 460 in a pixel 9. In addition, as shown in FIGS. 14B and 14C, the solid-state imaging element 400 has a buried conductor portion 412 provided on the upper portion of the FFTI 11 and an insulating portion 414 provided on the upper portion of the buried conductor portion 412.

[0084] The buried conductor 412 is provided between the FFTI 11 and the insulating section 414. The buried conductor 412 is formed to a position deeper than the insulating section 13 of the substrate 2, and is disposed in close contact with the well layers 21 of both adjacent pixels 9. In other words, the buried conductor 412 has a function of electrically connecting the pixels 9. On the other hand, unlike the buried conductor 12 of the first embodiment, the buried conductor 412 of the present embodiment does not have a function as a contact electrode. The buried conductor 412 is made of the same material as the buried conductor 12. The buried conductor 412 is formed by burying a conductive film in the upper part of the FFTI 11 and then removing the upper part of the buried conductor.

[0085] The insulating portion 414 is provided on the buried conductor portion 412 and functions as a cap layer for the insulating portion 414. The insulating portion 414 is formed of, for example, silicon oxide or silicon nitride, or other insulating material. The insulating portion 414 is formed by embedding an insulating portion on the buried conductor portion 412 in the trench.

[0086] As shown in FIG. 14A, the contact electrode 460 is a region for connecting to the GND contact 50 and making contact. As shown in FIG. 14C, the contact electrode 460 is connected to the well layer 21 and fixes the well layer 21 to the potential input from the GND contact 50. The contact electrode 460 is formed in the pixel 9 region. The contact electrode 460 may be disposed not only in the pixel 9 region but also outside the pixel 9 region (outside the pixel region 3 shown in FIG. 1). When the contact electrode 460 is formed in the pixel 9 region, one contact electrode 460 is provided for several pixels 9. In this case, the pixel 9 in which the contact electrode 460 is provided is preferably a pixel 9 provided with a blue (B) color filter. This is because, in the pixel 9 into which blue light having a short wavelength is incident, the influence of the difference in the pattern of the transistor formation surface, which is the opposite side to the light incident surface (the upper surface in FIG. 14B), can be suppressed due to the optical characteristics of blue light. Therefore, when the contact electrode 460 is provided in the pixel 9 provided with a blue (B) color filter, the variation in output between the pixels 9 can be suppressed, and the uniformity of the output from each pixel 9 can be improved.

[0087] The pixels 9 are electrically connected by the buried conductor portion 412. Therefore, one contact electrode 460 functions as a potential (reference potential) contact of the well layer 21 of each separated pixel 9. The contact electrode 460 of the pixel 9 is a region in which impurities are diffused at a high concentration, which is provided to make contact with the GND contact 50. As shown in FIG. 14C, the contact electrode 460 is formed at a depth such that the lower surface is in electrical contact with the well layer 21. The contact electrode 460 is formed by embedding a conductive film in a trench provided in the substrate 2. The conductive film is preferably made of, for example, silicon doped with P-type impurities, other semiconductor material, or metal. As the silicon, for example, polycrystalline silicon, amorphous silicon, epitaxially grown silicon, etc. are preferable.

[0088] <Effects of the Fourth Embodiment> The solid-state imaging device 400 according to this embodiment has the following advantages. (7) In the solid-state imaging element 400, the pixels 9 are electrically connected to each other by the embedded conductors 412, and a contact electrode 460 is provided in one of the several pixels 9. This reduces the number of contact electrodes 460 compared to the case where a contact electrode 460 is provided for each pixel 9, which is effective in reducing the area of ​​the solid-state imaging element 300.

[0089] (8) In the solid-state imaging element 400, a blue (B) color filter may be provided and a contact electrode 460 may be provided in the pixel 9 into which short-wavelength blue light is incident. In this case, it is possible to suppress variations in output between pixels 9 due to the presence or absence of the contact electrode 460, and improve the uniformity of the output from each pixel 9.

[0090] 5. Fifth embodiment: Solid-state imaging device A solid-state imaging element 500 according to a fifth embodiment of the present disclosure will be described below. The solid-state imaging element 500 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment.

[0091] (5.1) Structure of solid-state imaging device In the fifth embodiment, a solid-state imaging element 500 will be described with reference to Figs. 15A to 15C. As shown in Fig. 15A, the solid-state imaging element 500 differs from the solid-state imaging element 100 according to the first embodiment in that the embedded conductors 512 are provided in close contact with a part of the surface of the FFTI 11 provided at the boundary between the pixels 9. The solid-state imaging element 500 includes the embedded conductors 512 in each of the regions including the four corners of one pixel 9 in a plan view. The solid-state imaging element 500 also differs from the solid-state imaging element 100 according to the first embodiment in that the solid-state imaging element 500 includes embedded conductors 515 provided on the boundaries between two pixels 9.

[0092] 15A to 15C of portions of the solid-state imaging element 500 having the same functions as those of the solid-state imaging element 100 according to the first embodiment. That is, detailed descriptions of the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34, and 35, as well as the floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 500 will be omitted.

[0093] Fig. 15A is a plan view showing an example of the layout of the solid-state imaging element 500. Fig. 15B is a cross-sectional view of a pixel 9 of the solid-state imaging element 500 in the D-D' cross section shown in Fig. 2A. Fig. 15B is a cross-sectional view of a region including an embedded conductor 515 having an electron trapping function. Fig. 15C is a cross-sectional view of a pixel 9 of the solid-state imaging element 500 in the E-E' cross section shown in Fig. 2A. Fig. 15C is a cross-sectional view of a region including an embedded conductor 512 functioning as a contact electrode.

[0094] The buried conductors 512 provided at the four corners of the pixel 9 function as contact electrodes for fixing the potential of the well layer 21, similar to the buried conductors 12 in the first embodiment. As shown in FIG. 15A, the FFTIs 11 of the solid-state imaging device 500 are provided at all of the boundaries between the pixels 9. The buried conductors 512 of the solid-state imaging device 500 are provided at a part of the boundaries between the pixels 9, particularly in an area including a part (a central part of the four pixels 9) where the four FFTIs 11 that separate the adjacent pixels 9 of the four pixels 9 arranged in a 2×2 pattern intersect. That is, the buried conductors 512 of the solid-state imaging device 500 are provided at the four corners of one pixel 9. As shown in FIG. 15B, the buried conductors 512 are provided above the FFTIs 11 in the area including the four corners of the pixel 9 (upper side of FIG. 15B), deeper than the insulating part 13, and in contact with the well layer 21. FIG. 15A illustrates, as an example, an embedded conductor 512 that is cross-shaped in a plan view. The embedded conductor portion 512 is formed from the same material and by the same manufacturing method as the embedded conductor portion 12 of the first embodiment.

[0095] The buried conductor 515 provided on the boundary between the pixels 9 has an electron trap function for suppressing the overflow of charges to the adjacent pixel 9 via the buried conductor 512 or 515 when a large amount of light is applied. The buried conductor 515 is provided above a part of the FFTI 11 located on the boundary between the pixels 9 (upper side in FIG. 15B), deeper than the insulating part 13 and in contact with the well layer 21. The buried conductor 515 is preferably made of silicon or other semiconductor material doped with N-type impurities, or a metal. As the silicon, for example, polycrystalline silicon, amorphous silicon, epitaxially grown silicon, etc. are preferable.

[0096] The embedded conductor portion 512 is electrically connected to the GND contact 50. As a result, the embedded conductor portion 512 functions as a contact electrode. The embedded conductor portion 512 is shared between four adjacent pixels 9 as a contact electrode for the GND contact. Each pixel 9 has four contact electrodes at its four corners. Therefore, in the solid-state imaging element 500, even if any of the embedded conductor portions 512 no longer functions as a contact electrode, the other embedded conductor portions 512 function as contact electrodes, improving the quality of the solid-state imaging device 1 having the solid-state imaging element 500.

[0097] On the other hand, the embedded conductor 515 is electrically connected to a VDD contact 570 that applies a positive voltage to the embedded conductor 515. The embedded conductor 515 is formed of, for example, an N-type semiconductor material, and traps electrons accumulated in the photoelectric conversion element 22 when a positive voltage is applied. This makes it possible to prevent electrons from flowing to an adjacent pixel 9 even when electrons accumulated in the photoelectric conversion element 22 are likely to overflow to an adjacent pixel due to a large amount of light. This makes it possible for the solid-state imaging element 500 to suppress color mixing between adjacent pixels 9 in which color filters of different colors are arranged. In addition, in the solid-state imaging device 500, it is preferable to provide a difference in strength between the barrier from the photoelectric conversion element 22 to the buried conductor 515 and the barrier from the photoelectric conversion element 22 to each transistor such as the transfer transistor Ttr. This makes it possible to suppress the influence of electrons overflowing from the photoelectric conversion element 22 on each transistor when a large amount of light is present.

[0098] The solid-state imaging element 500 may have any of the embedded conductors 12A to 12G of the modified example of the first embodiment, instead of the embedded conductor 512. In addition, in the solid-state imaging element 500, the embedded conductor 515 may have a configuration similar to that of the embedded conductors 12A to 12G of the modified example of the first embodiment. Furthermore, the solid-state imaging element 500 may have the insulating portion 313 of the third embodiment, instead of the insulating portion 13.

[0099] <Effects of the Fifth Embodiment> The solid-state imaging device 500 according to this embodiment has the following advantages in addition to the advantages described in the first embodiment. (9) The solid-state imaging element 500 is electrically connected to the VDD contact and includes a buried conductor 515 that traps electrons that overflow from the photoelectric conversion element 22 when a positive voltage is applied from the VDD contact. This makes it possible to prevent electrons that overflow from the photoelectric conversion element 22 from flowing into an adjacent pixel 9 when a large amount of light is present, thereby preventing color mixing with the adjacent pixel 9.

[0100] 6. Sixth embodiment A solid-state imaging element 600 according to a sixth embodiment of the present disclosure will be described below. The solid-state imaging element 600 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment.

[0101] (6.1) Structure of solid-state imaging device In the sixth embodiment, solid-state imaging elements 600A and 600B, which are two examples of the solid-state imaging element 600, will be described with reference to Figs. 16 and 17. Note that, of the solid-state imaging element 600, detailed description and illustration in Figs. 16 and 17 will be omitted for portions having the same functions as the solid-state imaging element 100 according to the first embodiment. That is, detailed description will be omitted for the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixels 9 of the solid-state imaging elements 600A and 600B.

[0102] (6.1.1) First Example of Solid-State Imaging Device 600 FIG. 16 is a plan view showing an example of the layout of a solid-state imaging element 600A which is an example of the solid-state imaging element 600. As shown in FIG. 16, the solid-state imaging element 600A differs from the solid-state imaging element 100 according to the first embodiment in that it has an embedded conductor 612A provided in a part of an area on a boundary between two pixels 9, instead of the embedded conductor 12. The solid-state imaging element 600A also differs from the solid-state imaging element 100 according to the first embodiment in that it has an embedded conductor 615A in an area excluding an area on the FFTI 11 surrounding each pixel where the embedded conductor 612A is formed. The arrangement of the FFTI 11, the buried conductor portion 612A and the buried conductor portion 615A, and the connection of the GND contact 50 will be described below.

[0103] The solid-state imaging element 600A is a solid-state imaging element in which two adjacent pixels 9 form a pixel sharing unit. One embedded conductor 612A is provided for two adjacent pixels 9. The embedded conductor 612A is provided on the upper part (the front side in FIG. 16) of an FFTI 11 (not shown) provided at the boundary between two adjacent pixels 9. The embedded conductor 612A is provided near the center of the FFTI 11 sandwiched between the two pixels 9 in a plan view. The upper surface of the embedded conductor 612A is exposed from an embedded conductor 615A described later, and a GND contact 50 is connected to it. The embedded conductor 612A functions as a contact electrode, similar to the embedded conductor 12 described in the first embodiment. The embedded conductor 612A is formed in the same manner as the embedded conductor 12, except that it is provided in a part of the FFTI 11 provided on the boundary between two adjacent pixels 9.

[0104] The buried conductor portion 615A is provided on the upper portion of the FFTI 11 (not shown) provided on the boundary between the pixels 9. The buried conductor portion 615A is formed in a region on the FFTI 11 excluding the region in which the buried conductor portion 612A is formed. The embedded conductor 615A, like the embedded conductor 515 described in the fifth embodiment, has an electron trap function for suppressing overflow of charges to adjacent pixels 9 via the embedded conductor 612A or 615A when a large amount of light is applied. The embedded conductor 615A is formed in the same manner as the embedded conductor 515, except that it is provided in a region surrounding most of each pixel 9.

[0105] A VDD contact 670 that applies a positive voltage to the buried conductor 615A is connected to the buried conductor 615A. When a positive voltage is applied via the VDD contact 670, the buried conductor 615A traps electrons that overflow from the photoelectric conversion element 22. The VDD contact 670 is formed of the same material and by the same method as the VDD contact 570 of the fifth embodiment.

[0106] In such a solid-state imaging element 600A, the embedded conductor portion 612A serving as a GND connection electrode is shared by each pixel sharing unit composed of two pixels 9. When a high-luminance light source is incident on the solid-state imaging element 600A and electrons overflow from the pixel 9 via the embedded conductor portion 612A, the electrons flow into other pixels 9 in the shared pixel unit via the embedded conductor portion 612A, but the flow of electrons into other pixels 9 outside the shared pixel unit can be suppressed. Therefore, degradation of image quality can be suppressed by processing equivalent to pixel correction due to defects in the shared pixel unit.

[0107] (6.1.2) Second Example of Solid-State Imaging Device 600 FIG. 17 is a plan view showing an example of the layout of a solid-state imaging element 600B which is an example of the solid-state imaging element 600. As shown in FIG. 17, the solid-state imaging element 600B differs from the solid-state imaging element 100 according to the first embodiment in that it has an embedded conductor 612B provided in an area on a boundary surrounded by four pixels 9, instead of the embedded conductor 12. The solid-state imaging element 600A also differs from the solid-state imaging element 100 according to the first embodiment in that it has an embedded conductor 615B in an area excluding the area on the FFTI 11 surrounding each pixel where the embedded conductor 612A is formed. The arrangement of the FFTI 11, the buried conductor portion 612B and the buried conductor portion 615B, and the connection of the GND contact 50 will be described below.

[0108] The solid-state imaging element 600B is a solid-state imaging element in which four pixels 9 arranged in a 2×2 matrix form a pixel sharing unit. One embedded conductor 612B is provided for every four pixels 9 arranged in a matrix. The embedded conductor 612B is provided above (on the front side in FIG. 17) an FFTI 11 (not shown) located at the center of the four pixels 9. The upper surface of the embedded conductor 612B is exposed from an embedded conductor 615B described later, and a GND contact 50 is connected to the upper surface.

[0109] The buried conductor portion 615B is provided on the upper portion of the FFTI 11 (not shown) provided at the boundary between the pixels 9. The buried conductor portion 615B is formed in a region on the FFTI 11 excluding the region where the buried conductor portion 612B is formed. The embedded conductor 615B, like the embedded conductor 615A, has an electron trap function for suppressing the overflow of electrons to the adjacent pixel 9 via the embedded conductor 612B or 615B when a large amount of light is applied. The embedded conductor 615B is formed in the same manner as the embedded conductor 515, except that it is provided in a region surrounding most of each pixel 9.

[0110] In such a solid-state imaging element 600B, the embedded conductor portion 612B serving as a GND connection electrode is shared by each pixel sharing unit composed of two pixels 9. When a high-luminance light source is incident on the solid-state imaging element 600B and electrons overflow from the pixel 9 via the embedded conductor portion 612B, the electrons flow into other pixels 9 in the shared pixel unit via the embedded conductor portion 612B, but the flow of electrons into other pixels 9 outside the shared pixel unit can be suppressed. Therefore, degradation of image quality can be suppressed by processing equivalent to pixel correction due to defects in the shared pixel unit.

[0111] <Effects of the Sixth Embodiment> The solid-state imaging device 600 according to this embodiment has the following advantages in addition to the advantages described in the first embodiment. (10) The solid-state imaging element 600 includes buried conductors 615A, 615B that are electrically connected to the VDD contact and trap electrons that overflow from the photoelectric conversion element 22 when a positive voltage is applied from the VDD contact. Therefore, the solid-state imaging element 600 can prevent electrons that overflow from the photoelectric conversion element 22 from flowing into an adjacent pixel 9 when there is a large amount of light, thereby preventing color mixing with the adjacent pixel 9.

[0112] (11) Even if electrons overflow from a pixel 9, the solid-state imaging element 600 can suppress the inflow of electrons into other pixels 9 outside the sharing pixel unit. Therefore, the solid-state imaging element 600 can suppress degradation of image quality by processing equivalent to pixel correction due to defects in the sharing pixel unit.

[0113] 7. Seventh embodiment Next, an electronic device according to a seventh embodiment of the present disclosure will be described. Fig. 18 is a schematic configuration diagram of an electronic device 1000 according to the seventh embodiment of the present disclosure.

[0114] The electronic device 1000 according to the seventh embodiment includes a solid-state imaging device 1, an optical lens 1002, a shutter device 1003, a drive circuit 1004, and a signal processing circuit 1005. The electronic device 1000 according to the seventh embodiment illustrates an embodiment in which the solid-state imaging device 1 according to the first embodiment of the present disclosure is used in an electronic device (e.g., a camera) as the solid-state imaging device 1.

[0115] The optical lens 1002 focuses image light (incident light 106) from a subject on the imaging surface of the solid-state imaging device 1. This causes signal charges to accumulate in the solid-state imaging device 1 for a certain period of time. The shutter device 1003 controls the light irradiation period and light blocking period of the solid-state imaging device 1. The drive circuit 1004 supplies a drive signal that controls the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 1003. The drive signal (timing signal) supplied from the drive circuit 1004 transfers signals in the solid-state imaging device 1. The signal processing circuit 1005 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 1. The video signal that has undergone signal processing is stored in a storage medium such as a memory, or output to a monitor.

[0116] The electronic device 1000 to which the solid-state imaging device 1 can be applied is not limited to a camera, but may be applied to other electronic devices. For example, the solid-state imaging device 1 may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal. In the seventh embodiment, the solid-state imaging device 1 according to the first embodiment is used in an electronic device, but other configurations may be used. For example, the solid-state imaging device 1 according to the second embodiment or the solid-state imaging device 1 according to a modification may be used in an electronic device.

[0117] The present technology can be configured as follows. (1) A photoelectric conversion element that performs photoelectric conversion; A complete through-type element isolation that penetrates from the first main surface to the second main surface of the substrate and is formed between pixels including the photoelectric conversion elements; A conductor portion provided in close contact with the first main surface side of the complete through-type element isolation; A solid-state imaging element comprising: (2) the conductor portion is embedded in a first trench formed in the first main surface of the substrate, a high-concentration impurity diffusion layer formed on the first main surface of the substrate; an insulating portion provided between the conductor portion and the high-concentration impurity diffusion layer. The solid-state imaging device according to (1) above. (3) The conductor portion is formed deeper than the insulating portion, The high-concentration impurity diffusion layer is formed shallower than the insulating portion. The solid-state imaging device according to (2) above. (4) a well layer formed in a region deeper than the high-concentration impurity diffusion layer, The conductor portion is disposed in close contact with the well layer in a region deeper than the insulating portion. The solid-state imaging device according to (2) or (3) above. (5) a cap layer provided in close contact with the first main surface side of the conductor portion, The conductor portion is disposed in close contact with the well layers of a plurality of adjacent pixels. The solid-state imaging device according to (4) above. (6) the complete through-type element isolation is provided to surround the pixel in a plan view, The conductor portion is disposed in close contact with the entire surface or a part of the surface above the full through-type device isolation. A solid-state imaging device according to any one of (1) to (5) above. (7) The conductor portion is provided above the complete through-type isolation sandwiched between two adjacent pixels and above the complete through-type isolation located at the center of four pixels arranged in a 2×2 matrix. The solid-state imaging device according to (6) above. (8) The conductor portion has a shape in which a part or the whole of a second trench having the complete through-type device isolation as a bottom surface is filled with a conductor material. A solid-state imaging device according to any one of (1) to (6) above. (9) At least the surface of the insulating portion is made of an insulating material. The solid-state imaging device according to (2) or (3) above. (10) The insulating portion has a two-layer structure including an insulating film covering the surface of a third trench provided between the conductor portion and the high-concentration impurity diffusion layer, and pure polysilicon or oxide or an air layer embedded in the trench. The solid-state imaging device according to (9) above. (11) The conductor portion is a contact electrode shared between adjacent pixels. A solid-state imaging device according to any one of (1) to (10) above. (12) a solid-state imaging device including a solid-state imaging element having a photoelectric conversion element that performs photoelectric conversion, a complete through-type element isolation that penetrates from a first main surface to a second main surface of a substrate and is formed between pixels including the photoelectric conversion element, and a conductor portion provided in close contact with the complete through-type element isolation on the first main surface side; an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; a signal processing circuit for processing a signal output from the solid-state imaging device; An electronic device comprising:

[0118] In the solid-state imaging device of the present disclosure, it is sufficient that the FFTI and the highly-concentrated impurity region, the buried conductor, and the insulating portion disposed in the vicinity thereof are configured as described above, and the configuration of the other parts is not important. In other words, the configuration of the semiconductor element in the pixel may be any configuration other than the configuration described above. In addition, the conductivity type of the impurity diffusion region of the solid-state imaging device of the present disclosure is an example, and the P-type region and the N-type region may be formed in the opposite direction.

[0119] The scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to the object of the present invention. Moreover, the scope of the present invention is not limited to the combination of inventive features defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0120] 2. Board 9 pixels 11 Full Through-Tunnel Isolation (FFTI) 12, 12A~12G, 412, 512, 515, 612A, 612B, 615A, 615B Buried conductor 13, 13E, 313, 414 Insulation 21 Well Layer 22 Photoelectric conversion element 23 Photoelectric conversion unit 31 Gate insulating film 32~35 Gate electrode 41 Floating Diffusion 42 High concentration impurity diffusion layer 43 Buried conductor 50 GND Contact 60,460 Contact electrode 100, 100A~100G, 200, 200A~200C, 300, 400, 500, 600, 600A, 600B Solid-state imaging element 570,670 VDD contacts Tam Amplification Transistor Trs Reset transistor Tsl select transistor Ttr Transfer transistor

Claims

1. A photoelectric conversion element that performs photoelectric conversion; A complete through-type element isolation that penetrates from a first main surface to a second main surface of a substrate and is formed between pixels including the photoelectric conversion element; A first conductor portion provided in close contact with the first main surface side of the complete through-type element isolation and embedded in a trench formed in the first main surface of the substrate; a second impurity diffusion layer formed on the first main surface of the substrate; an insulating portion provided between the first conductor portion and the second impurity diffusion layer; a well layer formed in a region deeper from the first main surface of the substrate than the second impurity diffusion layer; Equipped with At least a portion of the first conductor is in contact with the well layer in a region that is deeper in a depth direction from the first main surface of the substrate than the insulating portion. Solid-state imaging element.

2. The first conductor portion is formed deeper than the insulating portion, The second impurity diffusion layer is formed shallower than the insulating portion. The solid-state imaging device according to claim 1 .

3. a cap layer provided in close contact with the first principal surface side of the first conductor portion; The first conductor portion is disposed in close contact with the well layers of a plurality of adjacent pixels. The solid-state imaging device according to claim 1 .

4. a contact electrode formed in the pixel and electrically connected to the well layer; The contact electrode fixes the well layers of the adjacent pixels to an input potential via the first conductor portion. The solid-state imaging device according to claim 3 .

5. the complete through-type element isolation is provided to surround the pixel in a plan view, The first conductor portion is disposed in close contact with the entire surface or a part of the surface above the full through-type device isolation. The solid-state imaging device according to claim 1 .

6. The first conductor portion is provided above the complete through-type isolation sandwiched between two adjacent pixels and above the complete through-type isolation located at the center of four pixels arranged in a 2×2 matrix. The solid-state imaging device according to claim 5 .

7. The first conductor portion has a shape in which a part or the whole of the trench having the complete through-type element isolation as a bottom surface is filled with a conductive material. The solid-state imaging device according to claim 1 .

8. At least the surface of the insulating portion is made of an insulating material. The solid-state imaging device according to claim 1 .

9. The insulating portion has a two-layer structure including an insulating film covering the surface of a trench provided between the first conductor portion and the second impurity diffusion layer, and pure polysilicon or oxide or an air layer embedded in the trench. The solid-state imaging device according to claim 8 .

10. The first conductor portion is a contact electrode shared between adjacent pixels. The solid-state imaging device according to claim 1 .

11. a second conductor portion that is disposed in close contact with the entire surface or a part of the surface above the complete through-type device isolation, is provided deeper than the insulating portion and in contact with the well layer, and attracts and traps electrons accumulated in the photoelectric conversion element when a positive voltage is applied thereto; The solid-state imaging device according to claim 1 .

12. The second impurity diffusion layer is a region in which an N-type impurity is diffused. The solid-state imaging device according to claim 1 .

13. a solid-state imaging device including a solid-state imaging element having a photoelectric conversion element that performs photoelectric conversion, a complete through-type device isolation that penetrates from a first main surface to a second main surface of a substrate and is formed between pixels including the photoelectric conversion element, a first conductor portion embedded in the complete through-type device isolation, a second impurity diffusion layer formed on the first main surface of the substrate, an insulating portion provided between the first conductor portion and the second impurity diffusion layer, and a well layer formed in a region deeper from the first main surface of the substrate than the second impurity diffusion layer; an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; a signal processing circuit for processing a signal output from the solid-state imaging device; Equipped with In the solid-state imaging device, at least a portion of the first conductor portion is in contact with the well layer in a region that is deeper in a depth direction from the first main surface of the substrate than the insulating portion. electronic equipment.

Images