Lateral field effect transistor and method of manufacturing same

Abstract

The present application provides a lateral field effect transistor related to the semiconductor technical field and a manufacturing method thereof, in which a gate electrode weld pad and a source electrode weld pad arranged in a non-source region of the lateral field effect transistor respectively extend from a first surface of a device functional layer to a surface of a substrate, in which the gate electrode weld pad itself is insulated and isolated from the device functional layer and the substrate respectively, and the source electrode weld pad is short-connected to the substrate, so that the gate electrode weld pad forms a capacitor structure with the source electrode weld pad short-connected to the substrate, thereby increasing the gate-source capacitance C of the device formed between the gate electrode weld pad and the source electrode weld pad, and effectively mitigating the generated vibration, reducing the wear of the power device and avoiding the false start-up of the lateral field effect transistor.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This application relates to the field of semiconductor technology, and more particularly to lateral field effect transistors and methods for fabricating the same. [Background technology]

[0002] When lateral field-effect transistors (such as LDMOS / GaN HEMT) are applied to hard switching, the influence of factors such as the parasitic capacitance between the internal gate and source electrodes and the wiring inductance will cause the gate electrode driving signal to generate parasitic oscillations, which will increase the wear of the power device. If the oscillation amplitude is relatively large, it may cause the lateral field-effect transistor to falsely start up.

[0003] Due to material and configuration limitations, current lateral field-effect transistors (such as LDMOS / GaN HEMT) typically have a relatively low threshold voltage, and therefore are more sensitive to gate electrode drive signal oscillations, making the lateral field-effect transistor more susceptible to false activation. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application aims to provide a lateral field effect transistor and a manufacturing method thereof, which can improve the oscillation of a gate electrode driving signal during application of the lateral field effect transistor, in response to the shortcomings of the prior art. [Means for solving the problem]

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] One aspect of an embodiment of the present application provides a lateral field effect transistor, in which a gate electrode weld pad and a source electrode weld pad disposed in a non-source region of the lateral field effect transistor extend from a first surface of a device functional layer to a surface of a substrate, respectively, in which the gate electrode weld pad is insulated from the device functional layer and the substrate, respectively, and the source electrode weld pad is short-connected to the substrate.

[0007] Another aspect of an embodiment of the present application provides a method for manufacturing a lateral field effect transistor, comprising forming a first reservoir and a second reservoir in a non-source region of the lateral field effect transistor, in which a gate electrode weld pad is partially filled in the first reservoir, and the gate electrode weld pad is insulated from a device functional layer and a substrate respectively, a source electrode weld pad is partially filled in the second reservoir, and the source electrode weld pad is short-connected to the substrate.

[0008] Advantageous effects of the present application include improving gate electrode drive signal oscillations during application of lateral field effect transistors. [Brief description of the drawings]

[0009] In order to more clearly describe the technical features of the embodiments of the present application, the following briefly introduces the accompanying drawings that are required to be used in the embodiments. Please note that the following accompanying drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For ordinary technical personnel in this field, other related accompanying drawings can be obtained based on these accompanying drawings without creative labor. [Figure 1] FIG. 2 is a top view of a lateral field effect transistor provided by an embodiment of the present application. [Diagram 2] FIG. 2 is a state diagram of a lateral field effect transistor according to an embodiment of the present application; [Diagram 3] FIG. 2 is a second diagram illustrating the state of a lateral field effect transistor according to an embodiment of the present application. [Figure 4]FIG. 3 is a third diagram illustrating the state of a lateral field effect transistor according to an embodiment of the present application. [Diagram 5] FIG. 4 is a fourth state diagram illustrating a lateral field effect transistor according to an embodiment of the present application. [Figure 6] 2 is a cross-sectional view taken along line AA' in FIG. [Figure 7] FIG. 2 is a cross-sectional view of a source region of a lateral field effect transistor according to an embodiment of the present application. [Figure 8] FIG. 2 is an explanatory diagram of distribution of parasitic parameters of a lateral field effect transistor provided by an embodiment of the present application. [Figure 9] 1 is a flow chart of a method for manufacturing a lateral field effect transistor provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The implementation described in the following text provides the information necessary for a person skilled in the art to practice the implementation, and shows the best mode of practicing the implementation. After reading the following description with reference to the accompanying drawings, a person skilled in the art will understand the concepts of the disclosure and recognize applications of these concepts not specifically presented in the text. It is understood that these concepts and applications fall within the scope of this disclosure and the associated claims.

[0011] Additionally, although terms such as first, second, etc. may be used herein to describe various elements, it should be understood that these terms are not intended to be limiting of these elements. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a first element may be referred to as a second element, without departing from the scope of this disclosure. As used herein, the term "and" includes any and all combinations of one or more of the associated listed items.

[0012] Furthermore, when an element (e.g., a layer, region, or substrate) is referred to as "on another element" or "extending onto another element," it is understood that it extends directly onto or directly onto the other element, or there may be intermediate elements present. In contrast, when an element is referred to as "directly on" or "extending directly onto" another element, there are no intermediate elements present. Similarly, when an element (e.g., a layer, region, or substrate) is referred to as "on another element" or "extending onto" another element, it is understood that it extends directly onto or directly onto the other element, or there may be intermediate elements present. In contrast, when an element is referred to as "directly on" or "extending directly onto" another element, there are no intermediate elements present. Additionally, when an element is referred to as being "connected" or "coupled" to another element, it should be understood that it may be directly connected or coupled to the other element, or there may be intervening elements present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0013] For example, terms such as "below" or "above" or "upper" or "bottom" or "horizontal" or "vertical" may be used in the text to describe the relationship of one element, layer or section to another element, layer or section as shown in the figures. It is understood that these terms, and the intent of those terms discussed above, cover orientations other than those depicted in the figures.

[0014] The terms used herein are intended to describe particular implementations and are not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "said" include the plural, unless the context clearly indicates otherwise. It is further understood that when used herein, the term "comprising" means the presence of stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0015] Unless otherwise defined, the meanings of all terms (including technical and scientific terms) used in the present specification are the same as those understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, it is to be understood that the meanings of the terms used in the present specification should be interpreted in a manner consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless so expressly defined in the present specification.

[0016] One aspect of the embodiment of the present application is to provide a lateral field effect transistor, which, as shown in FIG. 1 and FIG. 6, includes a substrate 108 and a device function layer disposed on the substrate 108 and having a first surface away from the substrate 108. The lateral field effect transistor includes a source region 101 and a non-source region 102, in which the non-source region 102 includes a substrate 108 and a device function layer disposed on the substrate 108 and having a first surface away from the substrate 108. The non-source region 102 includes a gate electrode weld pad 104 extending from the first surface to the surface of the substrate 108, and the gate electrode weld pad 104 is insulated from the substrate 108 and the device function layer. The non-source region 102 includes a source electrode weld pad 106, the gate electrode weld pad 104 extending from the first surface to the surface of the substrate 108, and the source electrode weld pad 106 is short-connected to the substrate 108.

[0017] In the lateral field effect transistor of the present application, the gate electrode weld pad 104 and the source electrode weld pad 106 arranged in the non-source region 102 respectively extend from the first surface of the device functional layer to the surface of the substrate 108, in which the gate electrode weld pad 104 itself is insulated and isolated from the device functional layer and the substrate 108, and the source electrode weld pad 106 is short-connected to the substrate 108, so that the gate electrode weld pad 104 forms a capacitor structure with the source electrode weld pad 106 short-connected to the substrate 108, thereby increasing the gate-source capacitance C of the device formed between the gate electrode weld pad 104 and the source electrode weld pad 106, and further effectively mitigating the generated vibration, reducing the wear of the power device and avoiding the erroneous start-up of the lateral field effect transistor.

[0018] In some embodiments, as shown in FIGS. 4 to 6, a first tank 105 corresponding to the gate electrode weld pad 104 and a second tank 107 corresponding to the source electrode weld pad 106 are disposed in the device functional layer of the non-source region 102, respectively. Specifically, for the first tank 105, as shown in FIG. 4, the first tank 105 extends downward from the first surface of the device functional layer to the surface of the substrate 108; as shown in FIG. 5, the first portion of the dielectric layer 113 covers the peripheral wall and bottom wall of the first tank 105, and the second portion of the dielectric layer 113 is continuous with the first portion of the dielectric layer 113 and covers the first peripheral surface of the first tank 105; as shown in FIG. 6, the second portion of the gate electrode welding pad 104 is filled in the first tank 105 completely covered by the dielectric layer 113, and the first portion of the gate electrode welding pad 104 is located outside the first tank 105, and is continuous with the second portion of the gate electrode welding pad 104 and is located on the second portion of the dielectric layer 113, thereby forming a structure in which the gate electrode welding pad 104 is insulated and isolated from the device functional layer and the substrate 108 by the dielectric layer 113, respectively. As for the second tank 107, as shown in FIG. 4, the second tank 107 also extends downward from the first surface of the device functional layer to the surface of the substrate 108, and as shown in FIG. 6, the second portion of the source electrode welding pad 106 is filled directly into the second tank 107, and the first portion of the source electrode welding pad 106 is located outside the second tank 107 and covers the first surface of the periphery of the upper second tank 107 that is continuous with the second portion of the source electrode welding pad 106, thereby forming a structure in which the source electrode welding pad 106 is short-connected to the device functional layer and the substrate 108, respectively.

[0019] A source region 101 and a non-source region 102 are arranged in the lateral field effect transistor, the non-source region 102 has a first side located on one side of the source region 101, and a first tank 105 and a second tank 107 arranged in a device functional layer of the non-source region 102 are both located on the first side, thereby preventing the first tank 105 and the second tank 107 from being blocked by the source region 101, thereby preventing an increase in the gate-source capacitance C of the device from being restricted. For example, in some embodiments, as shown in FIG. 1 , the non-source region 102 surrounds the outer periphery of the source region 101, a first side of the non-source region 102 is located on one side of the source region 101 (the lower side in FIG. 1 ), and when the first tank 105 and the second tank 107 are formed on the device functional layer within the first side of the non-source region 102, the first tank 105 and the second tank 107 can both be located on the first side of the non-source region 102. This makes it possible to avoid a situation in which the source region 101 blocks the second tank 107 and the first tank 105, thereby limiting the increase in the gate-source capacitance C of the device.

[0020] In some embodiments, the number of the first tanks 105 arranged on the device functional layer can be more than one, and can be reasonably set according to actual needs. For example, as shown in FIG. 1, when the number of the first tanks 105 is two, the two first tanks 105 can be diagonally distributed within the vertical projection area of ​​the gate electrode welding pad 104 on the substrate 108.

[0021] In some embodiments, the number of the second tanks 107 disposed on the device functional layer can also be multiple, and can also be reasonably set based on actual needs. For example, as shown in FIG. 1, when the number of the second tanks 107 is four, the four second tanks 107 can be diagonally distributed within the vertical projection area of ​​the source electrode welding pad 106 on the substrate 108.

[0022] In some embodiments, further referring to FIG. 6 , the gate electrode weld pad 104 and the source electrode weld pad 106 are disposed in the non-source region 102, and as shown in FIG. 7 , the lateral field effect transistor further includes a gate electrode, a source electrode 117, and a drain electrode 118 disposed in the source region 101, the gate electrode weld pad 104 is electrically connected to the gate electrode, the source electrode weld pad 106 is electrically connected to the source electrode 117, and when the lateral field effect transistor is disposed such that the gate electrode weld pad 104 is connected in series to the gate electrode driving circuit, the electrical resistance of the circuit structure formed by connecting the gate electrode, the gate electrode weld pad 104, and the gate electrode driving circuit is R, and the gate electrode, the gate electrode weld pad 104, and the gate electrode driving circuit are connected in series to the gate electrode weld pad 104. The parasitic inductance of the circuit structure formed by connecting the circuit is L, and the lateral field effect transistor has a gate-source capacitance C, and the gate electrode weld pad 104 and the source electrode weld pad 106 disposed in the non-source region 102 extend from the first surface of the device functional layer to the surface of the substrate 108, respectively, whereby the gate electrode weld pad 104 itself is insulated and isolated from the device functional layer and the substrate 108, respectively, and the source electrode weld pad 106 is short-connected to the substrate 108, whereby the source electrode weld pad 106 short-connecting the gate electrode weld pad 104 to the substrate 108 forms a capacitor structure, thereby increasing the gate-source capacitance C of the device formed between the gate electrode weld pad 104 and the source electrode weld pad 106. In some embodiments, as shown in FIG. 8, the parasitic parameter distribution of the lateral field effect transistor is shown,

number

[0023] In some embodiments, as shown in FIG. 1, a drain electrode pad 103 is further disposed on the device functional layer in the non-source region 102, and the drain electrode pad 103 can be connected to the drain electrode 118 of the active device in the source region 101.

[0024] In some embodiments, the source electrode weld pad 106 can be arranged to be grounded and the drain electrode 118 can be arranged to connect to a power source.

[0025] In some embodiments, the dielectric layer 113 is the dielectric of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 shorted to the substrate 108, so that the thickness and material of the dielectric layer 113 can be modified to adjust the magnitude of the device gate-source capacitance C accordingly. For example, when the device gate-source capacitance C needs to be adjusted to a certain value, the thickness and / or material can be modified to set the device gate-source capacitance C to a certain value.

[0026] In some embodiments, the breakdown voltage of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 shorted to the substrate 108 should be higher than the working voltage of the lateral field effect transistor, which can effectively improve the stability of the device.

[0027] In some embodiments, the thickness and material of the dielectric layer 113 should be reasonably selected and arranged in consideration of the requirements of the breakdown voltage of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 and the requirements of the device gate-source capacitance C.

[0028] In some embodiments, the depth of the first tank 105 and / or the second tank 107 is greater than the thickness of the device functional layer, e.g., a typical epitaxial thickness for a 650V GaN HEMT is 5 μm, and the first tank 105 and / or the second tank 107 need to be etched into the surface of the substrate 108 to a depth of greater than 5 μm.

[0029] In some embodiments, the thickness of the dielectric layer 113 can be greater than 5 nm, such as 5 nm, 10 nm, 15 nm, etc., to meet the requirements of the breakdown voltage and the device gate-source capacitance C. For example, if the GaN E-HEMT gate operating voltage is 6 V, the dielectric material is SiO2, and the typical breakdown electric field is 6 MV / cm, the thickness of the dielectric layer 113 needs to be greater than 10 nm.

[0030] In some embodiments, the material of the dielectric layer 113 can be one of SiO2, Si3N4, and Al2O3. In some embodiments, the dielectric layer 113 can be a stack of Si3N4 / Al2O3, and the term "dielectric stack" refers to a stack of Si3N4 layers, and then a layer of Al2O3 is deposited on the Si3N4 layers.

[0031] In some embodiments, the lateral field effect transistor is a HEMT device, and the HEMT device includes a substrate 108 and a device functional layer located on the substrate 108, both of which include portions located on the source regions 101 and portions located on the non-source regions 102.

[0032] In some embodiments, the device functional layer may include a plurality of active semiconductor layers formed on the substrate 108, each of the plurality of active semiconductor layers being located in the source region 101 and the non-source region 102, with a two-dimensional electron gas at a heterogeneous interface formed between at least two active semiconductor layers located in the source region 101, and no two-dimensional electron gas at a heterogeneous interface formed between two active semiconductor layers located in the non-source region 102 (the absence of two-dimensional electron gas can be eliminated by adopting industrial techniques such as ion implantation).

[0033] In some embodiments, when the lateral field effect transistor is a HEMT device, the HEMT device includes a substrate 108 and a device functional layer formed on the substrate 108, in which the device functional layer includes a plurality of active semiconductor layers, as shown in FIG. 7, a core-forming layer (not shown) formed on the substrate 108, a buffer layer 109 and a channel layer 110 sequentially formed on the core-forming layer, a shielding layer 111 formed on the channel layer 110, and a damping layer 116 formed on the shielding layer 111, the core-forming layer can reduce the lattice mismatch between the active semiconductor layer of the next layer of the substrate 108, a two-dimensional electron gas is formed between the channel layer 110 and the shielding layer 111 (the portion located in the non-source region 102 is removed), a source electrode 117 and a drain electrode 118 are formed in the damping layer 116 in contact with the shielding layer 111, and a gate electrode is formed between the source electrode 117 and the drain electrode 118 in contact with the shielding layer 111.

[0034] In some embodiments, the gate electrode may include a P-type doped layer 119 formed on the shielding layer 111 and a gate electrode metal 120 formed on the P-type doped layer 119, as shown in FIG.

[0035] In some embodiments, substrate 108 can be made of silicon carbide, sapphire, spinel, zinc oxide, silicon, gallium nitride, aluminum nitride, or any other material capable of supporting the growth of Group III-nitride materials.

[0036] In some embodiments, the core forming layer may include multiple different materials, for example Al. x Ga 1-x N, where 0≦x≦1. The core-forming layer can be formed on the substrate 108 using known semiconductor growth techniques, such as, for example, metal oxide chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0037] In some embodiments, the buffer layer 109 and the channel layer 110 are made of, for example, Al. x Ga y In (1-x-y) The buffer layer 109 and the channel layer 110 can be fabricated using III-nitride materials such as GaN, 0≦x≦1, 0≦y≦1, x+y≦1. For example, the buffer layer 109 and the channel layer 110 can be GaN layers, and in some other embodiments, the GaN layers can be doped with Fe. The buffer layer 109 and the channel layer 110 can be fabricated using the same methods used to grow the core-forming layer.

[0038] In some embodiments, any of the shielding layer 111 and the channel layer 110 may comprise doped or undoped III-nitride materials. The shielding layer 111 may comprise one or more layers of different materials, such as InGaN, AlGaN, AlN, or combinations thereof. The shielding layer 111 may be fabricated using the same methods used to grow the core-forming layers.

[0039] In some embodiments, the material of the source electrode weld pad 106 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel, and in some embodiments, the material of the gate electrode weld pad 104 is one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or alloys of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide. In some embodiments, the material of the drain electrode pad 103 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel. In some embodiments, the material of the source electrode 117 is one of titanium, aluminum, gold, and nickel, or some alloys of titanium, aluminum, gold, and nickel, and in some embodiments, the material of the gate electrode is one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or some alloys of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide, and in some embodiments, the material of the drain electrode 118 is one of titanium, aluminum, gold, and nickel, or some alloys of titanium, aluminum, gold, and nickel.

[0040] In another aspect of an embodiment of the present application, a method for fabricating a lateral field effect transistor is provided, as shown in FIG. 9, the method includes the following steps:

[0041] S010: Provide a device structure, the device structure having a substrate and a device functional layer disposed on the substrate and having a first surface away from the substrate, the device structure having a first area used for forming a source region and a second area used for forming a non-source region disposed therein.

[0042] S020: A first reservoir and a second reservoir are formed in a second area, the first reservoir and second reservoir extending from the first surface to the substrate.

[0043] S030: Producing a dielectric layer, the dielectric layer being configured to include a first portion and a second portion, the first portion of the dielectric layer being disposed on the peripheral wall and bottom wall of the first vessel, and the second portion of the dielectric layer being disposed on the first surface. S040: Prepare a gate electrode weld pad, the gate electrode weld pad being configured to have a first portion and a second portion, the first portion of the gate electrode weld pad being located on a first portion of a peripheral first surface of a first tank, and the second portion of the gate electrode weld pad being filled in the first tank.

[0044] S050: Prepare a source electrode weld pad, the source electrode weld pad being composed of a first portion and a second portion, the first portion of the source electrode weld pad being located on a first portion of a first surface of a periphery of a second tank, and the second portion of the source electrode weld pad being filled in the second tank.

[0045] The present application does not make any changes to the configuration of the active device in the source region, so the modification width to the original device industry can be reduced and the cost can be reduced. At the same time, the second tank and the first tank of the present application are both in the original source electrode welding pad area and gate electrode welding pad area, so that the device size is relatively large due to the occupancy of extra area.

[0046] 2, in S010, the device structure includes a substrate 108 and a device functional layer, the device functional layer is disposed on the substrate 108 and has a first surface away from the substrate 108. A first area and a second area are disposed in the device structure, the first area can form a source region 101, and the second area can form a non-source region 102. A specific method can be performed by surface etching or ion implantation on the second area, thereby forming the non-source region 102 in the second area, and the first area is the source region 101.

[0047] In some embodiments, in S020, as shown in Fig. 3, a photoresist layer 112 is applied on the first surface of the device functional layer of the non-source region 102, and then windows are opened in the photoresist layer 112 by industrial techniques such as exposure and development to expose the device functional layer, thereby defining the positions of the first tank 105 and the second tank 107. As shown in Fig. 4, the device functional layer is etched from the positions where the windows are opened, thereby forming the first tank 105 and the second tank 107 in the device functional layer, respectively. During the etching, the first tank 105 and the second tank 107 formed should extend from the first surface of the device functional layer to the surface of the substrate 108, and the surface of the substrate 108 should be exposed in the first tank 105 and the second tank 107 to peel off the photoresist layer 112.

[0048] In some embodiments, in S030, as shown in FIG. 5, the entire dielectric layer 113 is deposited on the device functional layer, and a second portion of the first surface of the periphery of the first vessel 105 is etched away, which is continuous with a first portion of the peripheral and bottom walls of the first vessel 105 covered by the dielectric layer 113 and the first portion of the dielectric layer 113.

[0049] In some embodiments, as shown in Fig. 6, in S040, the gate electrode weld pad 104 can be prepared by methods of photolithography, deposition, and metal peeling. Based on the position of the window, fill the second part of the gate electrode weld pad 104 into the first tank 105 completely covered by the dielectric layer 113, the first part of the gate electrode weld pad 104 is located outside the first tank 105, and the second part continuous with the gate electrode weld pad 104 is located in the second part of the dielectric layer 113, thereby forming the gate electrode weld pad 104 and forming a structure insulated and isolated by the dielectric layer 113 between the device functional layer and the substrate 108, respectively.

[0050] In some embodiments, as shown in Fig. 6, in S050, the source electrode welding pad 106 can be prepared by methods of photolithography, deposition, and metal peeling. Based on the position of the window, the second portion of the source electrode welding pad 106 is directly filled into the second tank 107, and the first portion of the source electrode welding pad 106 is located outside the second tank 107, and is continuous with the second portion of the source electrode welding pad 106 and covers the first surface of the periphery of the second tank 107. This forms a structure in which the source electrode welding pads 106 contact the device functional layer respectively and are short-connected to the substrate 108.

[0051] In some embodiments, as shown in Fig. 7, when an active device is fabricated in the device functional layer of the source region 101, the entire dull layer 116 is first formed on the surface of the device functional layer, and then a source electrode 117 window and a drain electrode 118 window are formed in the dull layer 116 by photolithography, and the source electrode 117 and the drain electrode 118 are formed in the source electrode 117 window and the drain electrode 118 window by methods such as photolithography, deposition, metal peeling, etc. In the same sense, referring to the industrial technology of forming the source electrode 117 window and the drain electrode 118 window, the dull layer 116 is etched to form a gate electrode cavity in the dull layer 116, and the gate electrode cavity is located between the source electrode 117 and the drain electrode 118, and then a gate electrode is formed in the gate electrode cavity.

[0052] A source region 101 and a non-source region 102 are arranged in the lateral field effect transistor, the non-source region 102 has a first side located on one side of the source region 101, and a first tank 105 and a second tank 107 arranged in a device functional layer of the non-source region 102 are both located on the first side, thereby preventing the first tank 105 and the second tank 107 from being blocked by the source region 101, thereby preventing an increase in the gate-source capacitance C of the device from being restricted. For example, in some embodiments, as shown in FIG. 1 , the non-source region 102 surrounds the outer periphery of the source region 101, a first side of the non-source region 102 is located on one side of the source region 101 (the lower side in FIG. 1 ), and when the first tank 105 and the second tank 107 are formed on the device functional layer within the first side of the non-source region 102, the first tank 105 and the second tank 107 can both be located on the first side of the non-source region 102. This makes it possible to avoid a situation in which the source region 101 blocks the second tank 107 and the first tank 105, thereby limiting the increase in the gate-source capacitance C of the device.

[0053] In some embodiments, further referring to FIG. 6 , the gate electrode weld pad 104 and the source electrode weld pad 106 are disposed in the non-source region 102, and as shown in FIG. 7 , the lateral field effect transistor further includes a gate electrode, a source electrode 117, and a drain electrode 118 disposed in the source region 101, the gate electrode weld pad 104 is electrically connected to the gate electrode, the source electrode weld pad 106 is electrically connected to the source electrode 117, and when the lateral field effect transistor is disposed such that the gate electrode weld pad 104 is connected in series to the gate electrode driving circuit, the electrical resistance of the circuit structure formed by connecting the gate electrode, the gate electrode weld pad 104, and the gate electrode driving circuit is R, and the gate electrode, the gate electrode weld pad 104, and the gate electrode driving circuit are connected in series to the gate electrode driving circuit. The parasitic inductance of the circuit structure formed by connecting the gate electrode weld pad 104 and the source electrode weld pad 106 is L, and the lateral field effect transistor has a gate-source capacitance C, and the gate electrode weld pad 104 itself is insulated and isolated from the device functional layer and the substrate 108, respectively, by the gate electrode weld pad 104 and the source electrode weld pad 106 disposed in the non-source region 102 extending from the first surface of the device functional layer to the surface of the substrate 108, and the source electrode weld pad 106 is short-connected to the substrate 108, thereby forming a capacitor structure by the source electrode weld pad 106 shorting the gate electrode weld pad 104 to the substrate 108, and increasing the gate-source capacitance C of the device formed between the gate electrode weld pad 104 and the source electrode weld pad 106. In some embodiments, as shown in FIG. 8, the parasitic parameter distribution of the lateral field effect transistor is shown,

number

[0054] In some embodiments, the source electrode weld pad 106 is disposed to ground and the drain electrode 118 is disposed to connect to a power source.

[0055] In some embodiments, the dielectric layer 113 is the dielectric of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 shorted to the substrate 108, so that the thickness and material of the dielectric layer 113 can be modified to adjust the magnitude of the device gate-source capacitance C accordingly. For example, when the device gate-source capacitance C needs to be adjusted to a certain value, the thickness and / or material can be modified to set the device gate-source capacitance C to a certain value.

[0056] In some embodiments, the breakdown voltage of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 shorted to the substrate 108 should be higher than the working voltage of the lateral field effect transistor, which can effectively improve the stability of the device.

[0057] In some embodiments, the thickness and material of the dielectric layer 113 should be reasonably selected and arranged in consideration of the requirements of the breakdown voltage of the capacitor formed by the gate electrode weld pad 104 and the source electrode weld pad 106 and the requirements of the device gate-source capacitance C.

[0058] In some embodiments, the depth of the first tank 105 and / or the second tank 107 is greater than the thickness of the device functional layer, e.g., a typical epitaxial thickness for a 650V GaN HEMT is 5 μm, and the first tank 105 and / or the second tank 107 need to be etched into the surface of the substrate 108 to a depth of greater than 5 μm.

[0059] In some embodiments, the thickness of the dielectric layer 113 can be greater than 5 nm, such as 5 nm, 10 nm, 15 nm, etc., to meet the requirements of the breakdown voltage and the device gate-source capacitance C. For example, if the GaN E-HEMT gate operating voltage is 6 V, the dielectric material is SiO2, and the typical breakdown electric field is 6 MV / cm, the thickness of the dielectric layer 113 needs to be greater than 10 nm.

[0060] In some embodiments, the material of the dielectric layer 113 can be one of SiO2, Si3N4, and Al2O3. In some embodiments, the dielectric layer 113 can be a stack of Si3N4 / Al2O3, and the term "dielectric stack" refers to a stack of Si3N4 layers, and then a layer of Al2O3 is deposited on the Si3N4 layers.

[0061] In some embodiments, the lateral field effect transistor is a HEMT device, and the HEMT device includes a substrate 108 and a device functional layer located on the substrate 108, both of which include portions located on the source regions 101 and portions located on the non-source regions 102.

[0062] In some embodiments, the device functional layer may include a plurality of active semiconductor layers formed on the substrate 108, each of which is located in the source region 101 and the non-source region 102, with a two-dimensional electron gas at a heterogeneous interface formed between the two active semiconductor layers located in the source region 101, and no two-dimensional electron gas at a heterogeneous interface formed between the two active semiconductor layers located in the non-source region 102 (the absence of the two-dimensional electron gas can be eliminated by adopting industrial techniques such as ion implantation).

[0063] In some embodiments, when the lateral field effect transistor is a HEMT device, the HEMT device includes a substrate 108 and a device functional layer formed on the substrate 108, in which the device functional layer includes a plurality of active semiconductor layers, as shown in FIG. 7, a core-forming layer (not shown) formed on the substrate 108, a buffer layer 109 and a channel layer 110 sequentially formed on the core-forming layer, a shielding layer 111 formed on the channel layer 110, and a damping layer 116 formed on the shielding layer 111, the core-forming layer can reduce the lattice mismatch between the active semiconductor layer of the next layer of the substrate 108, a two-dimensional electron gas is formed between the channel layer 110 and the shielding layer 111 (the portion located in the non-source region 102 is removed), a source electrode 117 and a drain electrode 118 are formed in the damping layer 116 in contact with the shielding layer 111, and a gate electrode is formed between the source electrode 117 and the drain electrode 118 in contact with the shielding layer 111.

[0064] In some embodiments, the gate electrode may include a P-type doped layer 119 formed on the shielding layer 111 and a gate electrode metal 120 formed on the P-type doped layer 119, as shown in FIG.

[0065] In some embodiments, substrate 108 can be made of silicon carbide, sapphire, spinel, zinc oxide, silicon, gallium nitride, aluminum nitride, or any other material capable of supporting the growth of Group III-nitride materials.

[0066] In some embodiments, the core forming layer may include multiple different materials, for example Al. x Ga 1-x N, where 0≦x≦1. The core-forming layer can be formed on the substrate 108 using known semiconductor growth techniques, such as, for example, metal oxide chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0067] In some embodiments, the buffer layer 109 and the channel layer 110 are made of, for example, Al. x Ga y In (1-x-y) The buffer layer 109 and the channel layer 110 can be fabricated using III-nitride materials such as GaN, 0≦x≦1, 0≦y≦1, x+y≦1. For example, the buffer layer 109 and the channel layer 110 can be GaN layers, and in some other embodiments, the GaN layers can be doped with Fe. The buffer layer 109 and the channel layer 110 can be fabricated using the same methods used to grow the core-forming layer.

[0068] In some embodiments, either the shielding layer 111 or the channel layer 110 may comprise a doped or undoped III-nitride material. The shielding layer 111 may comprise one or more layers of different materials, such as InGaN, AlGaN, AlN, or combinations thereof. The shielding layer 111 may be fabricated using the same methods used to grow the core-forming layers.

[0069] In some embodiments, the material of the source electrode weld pad 106 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel, and in some embodiments, the material of the gate electrode weld pad 104 is one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or alloys of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide. In some embodiments, the material of the drain electrode pad 103 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel.

[0070] In some embodiments, the material of the source electrode 117 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel, and in some embodiments, the material of the gate electrode is one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or alloys of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide, and in some embodiments, the material of the drain electrode 118 is one of titanium, aluminum, gold, and nickel, or alloys of titanium, aluminum, gold, and nickel.

[0071] The above is only a preferred embodiment of the present application, and the present invention is not limited thereto, and various modifications and variations may be made by the skilled artisans in this field. All modifications and equivalent structures within the spirit and principle of the present application are intended to be included in the scope of the claims of the present application. [Explanation of symbols]

[0072] 101 Source Region 102 Non-source area 103 Drain electrode pad 104 Gate electrode welding pad 105 First Tank 106 Source Electrode Welding Pad 107 Second Tank 108 Substrate 109 Buffer Layer 110 Channel Layer 111 Shielding layer 112 Photoresist layer 113 Dielectric Layer 116 Slowing Layer 117 Source Electrode 118 Drain electrode 119 P-type doped layer 120 Gate electrode metal

Claims

1. A substrate; a device functional layer disposed on the substrate and having a first surface remote from the substrate, the lateral field effect transistor having source and non-source regions disposed therein, a gate electrode weld pad disposed on the non-source region, the gate electrode weld pad extending from the first surface to a surface of the substrate, the gate electrode weld pad being insulated from the substrate and the device functional layer, a source electrode weld pad disposed on the non-source region, the source electrode weld pad extending from the first surface to a surface of the substrate, the lateral field effect transistor comprises a first bath extending from the first surface to a surface of the substrate, a dielectric layer disposed on peripheral and bottom walls of the first bath, and a second bath extending from the first surface to a surface of the substrate, the source electrode weld pad directly filling the second bath, the source electrode weld pad being short-connected to the device functional layer and the substrate, and a capacitor structure being formed by the gate electrode weld pad, the dielectric layer, and the source electrode weld pad short-connected to the device functional layer and the substrate.

2. The gate electrode welding pad is composed of a first portion and a second portion, the first portion of the gate electrode welding pad is located on a first surface of a periphery of the first tank, and the second portion of the gate electrode welding pad is filled in the first tank, the dielectric layer is composed of a first portion and a second portion, the first portion of the dielectric layer being disposed on the peripheral wall and the bottom wall of the first vessel, and the second portion of the dielectric layer being disposed on the first surface; 2. The lateral field effect transistor of claim 1, wherein the source electrode weld pad is comprised of a first portion and a second portion, the first portion of the source electrode weld pad being located on a peripheral first surface of the second reservoir, and the second portion of the source electrode weld pad filling a second portion of the second reservoir.

3. 3. The lateral field effect transistor of claim 2, wherein the non-source region has a first side disposed to one side of the source region, and the first tank and the second tank are both located on the first side.

4. The lateral field effect transistor further has a gate electrode, a source electrode and a drain electrode disposed in the source region, the gate electrode welding pad is connected to the gate electrode, the source electrode welding pad is connected to the source electrode, when the lateral field effect transistor is disposed such that the gate electrode welding pad is connected in series with a gate electrode driving circuit, an electric resistance of a circuit structure formed by connecting the gate electrode and the gate electrode welding pad to the gate electrode driving circuit is R, a parasitic inductance of a circuit structure formed by connecting the gate electrode and the gate electrode welding pad to the gate electrode driving circuit is L, and the lateral field effect transistor has a gate-source electric capacitance C, wherein: [0010] 4. The lateral field effect transistor according to claim 1, wherein

5. 5. The lateral field effect transistor of claim 4, wherein the source electrode weld pad can be arranged to be grounded and the drain electrode can be arranged to be connected to a power supply.

6. 4. The lateral field effect transistor according to claim 1, wherein the lateral field effect transistor is a HEMT device, and the device functional layer has a plurality of active semiconductor layers formed on the substrate, and wherein the device functional layer has a two-dimensional electron gas at a heterogeneous interface between at least two of the plurality of active semiconductor layers.

7. 7. A lateral field effect transistor according to claim 6, wherein the material of said active semiconductor layer is a III-V compound.

8. The thickness of the dielectric layer is greater than 5 nm and / or the dielectric layer is made of SiO ２ , Si ３ N ４ , Al ２ O ３ Alternatively, the dielectric layer is Si ３ N ４ and Al ２ O ３ 3. The lateral field effect transistor according to claim 2, characterized in that it is a stack of:

9. The depth of the first tank is greater than the thickness of the device functional layer, and / or the depth of the second tank is greater than the thickness of the device functional layer.

3. A lateral field effect transistor as claimed in claim 2.

10. 2. The lateral field effect transistor of claim 1, wherein the material of the source electrode weld pad is one of titanium, aluminum, gold, and nickel, or several alloys of titanium, aluminum, gold, and nickel, and / or the material of the gate electrode weld pad is one of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or several alloys of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or platinum silicide.

11. 1. A method for making a lateral field effect transistor, comprising the steps of: providing a device structure having a substrate and a device functional layer disposed on the substrate and having a first surface remote from the substrate; a first area used to create a source region and a second area used to create a non-source region are disposed in the device structure; creating a first reservoir and a second reservoir in the second area, the first reservoir extending from the first surface to the substrate; creating a dielectric layer having a first portion and a second portion, the first portion of the dielectric layer being disposed on the peripheral and bottom walls of the first vessel, and the second portion of the dielectric layer being disposed on the first surface; creating a gate electrode weld pad comprising a first portion and a second portion, the first portion of the gate electrode weld pad being located on a first portion of a first peripheral surface of the first bath, and the second portion of the gate electrode weld pad being filled in the first bath; 1. A method for making a lateral field effect transistor comprising: preparing a source electrode weld pad comprising a first portion and a second portion, the first portion of the source electrode weld pad having a first portion located on a peripheral first surface of the second bath, and the second portion of the source electrode weld pad being filled into the second bath.

12. 12. The method of claim 11, wherein the lateral field effect transistor is a HEMT device, and the device functional layer comprises a plurality of active semiconductor layers formed on the substrate, wherein a two-dimensional electron gas is present at a heterogeneous interface between two of the plurality of active semiconductor layers, and the material of the active semiconductor layers is a III-V compound.

13. The thickness of the dielectric layer is greater than 5 nm and / or the dielectric layer is made of SiO ２ , Si ３ N ４ , Al ２ O ３ Alternatively, the dielectric layer is Si ３ N ４ and Al ２ O ３ 12. The method of claim 11, further comprising laminating a first insulating layer and a second insulating layer.

14. 12. A method for making a lateral field effect transistor according to claim 11, characterized in that the depth of the first bath is greater than the thickness of the device functional layer and / or the depth of the second bath is greater than the thickness of the device functional layer.

Images