Semiconductor Device

Abstract

To suppress breakdown voltage degradation of semiconductor devices.SOLUTION: In a LDMOSFET 100, the "STI structure 11" provided in the drain region including a high concentration drain region 10 and a drift region 12 that encompasses the high concentration drain region 10 has a slit region 11A that extends in the x-direction, and in plan view the "STI structure 11" is interposed between the slit region 11A and the high concentration drain region 10.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a laterally diffused MOSFET (LDMOSFET: Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor). [Background technology]

[0002] Non-Patent Document 1 describes a technique for improving the breakdown voltage of an LDMOSFET by improving the structure of the LDMOSFET to alleviate the electric field in an electric field concentration region. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] J. Jang, K. Cho et al., “Interdigitated LDMOS,” Proceedings of The 25th International Symposium on Power Semiconductor Devices & ICs, pp. 245-248. Summary of the Invention [Problem to be solved by the invention]

[0004] In LDMOSFETs, there is a technology to improve the breakdown voltage by forming an "STI structure" in the drift region. However, while the "STI structure" can improve the breakdown voltage, it also increases the on-resistance. For this reason, a technology to provide a slit region in the "STI structure" in order to reduce the on-resistance is being considered. In this regard, while the on-resistance can be reduced by forming the slit region, an electric field concentration region with a high electric field strength is formed in the drift region exposed from the slit region, and this electric field concentration region causes a decrease in the breakdown voltage of the LDMOSFET to become apparent.

[0005] In this regard, it is believed that if the electric field in the electric field concentration region occurring in the drift region exposed from the slit region can be alleviated, the decrease in the breakdown voltage of the LDMOSFET can be suppressed. Therefore, from the viewpoint of suppressing the decrease in the breakdown voltage, it is desired to devise a way to alleviate the electric field in the electric field concentration region occurring in the drift region exposed from the slit region. [Means for solving the problem]

[0006] In one embodiment of a semiconductor device (LDMOSFET), an insulating region provided in a drain region including a heavily doped drain region and a lightly doped drain region containing the heavily doped drain region has a slit region extending in a first direction, and in a plan view, the insulating region is interposed between the slit region and the heavily doped drain region.

[0007] In one embodiment of a semiconductor device (LDMOSFET), an insulating region provided in a drain region including a heavily doped drain region and a lightly doped drain region containing the heavily doped drain region has a slit region extending in a first direction, and in a plan view, a connection region between an end of the slit diffusion region on the source region side exposed from the slit region and the lightly doped drain region is exposed from the gate electrode. Effect of the Invention

[0008] According to one embodiment, it is possible to suppress a decrease in the breakdown voltage of a semiconductor device. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a planar layout of an LDMOSFET in a first related technique. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 13 is a diagram showing a planar layout of an LDMOSFET in a second related technique. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. [Diagram 5] FIG. 13 is a diagram showing a schematic diagram of an electric field distribution in a slit diffusion region. [Figure 6] FIG. 1 is a diagram explaining the concept of the first basic idea. [Figure 7] FIG. 1 is a diagram explaining the concept of the second basic idea. [Figure 8] FIG. 2 is a diagram showing a planar layout of an LDMOSFET according to an embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line AA in FIG. 8. [Figure 10] FIG. 9 is a cross-sectional view taken along line BB in FIG. 8. [Figure 11] 1 is a graph showing the relationship between the dimension “D” and the breakdown voltage of an LDMOSFET when only the first feature is adopted. [Figure 12] 1 is a graph showing the relationship between the dimension “D” and the on-resistance of an LDMOSFET when only the first feature is adopted. [Figure 13] 11 is a graph showing the relationship between the dimension “D” and the breakdown voltage of an LDMOSFET when both the first feature and the second feature are adopted. [Figure 14] 11 is a graph showing the relationship between the dimension “D” and the on-resistance of an LDMOSFET when both the first feature and the second feature are adopted. [Figure 15] FIG. 13 is a diagram showing a planar layout of an LDMOSFET in a first modified example. [Figure 16] FIG. 11 is a diagram showing a planar layout of an LDMOSFET in a second modification. [Figure 17] FIG. 13 is a diagram showing a planar layout of an LDMOSFET in a third modification example. [Figure 18] FIG. 13 is a diagram showing a simulation result of the occurrence frequency of the impact ionization phenomenon in a slit diffusion region. [Figure 19] FIG. 13 is a diagram showing a planar layout of an LDMOSFET in a fourth modified example. [Figure 20] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device in the embodiment. [Figure 21]21 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 21. [Diagram 23] 23 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 22. [Figure 24] 24 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 23. [Diagram 25] 25 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 24. [Figure 26] 26 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 25. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0011] <Consideration of improvements> First, a related technology that is a premise for conceiving the technical idea of ​​the present embodiment will be described. In this specification, the term "related technology" refers to a technology that is not publicly known, but has a problem that the present inventor has found, and is a technology that is a premise for the present invention.

[0012] Fig. 1 is a diagram showing a planar layout of an LDMOSFET 100A in the first related art. In Fig. 1, the LDMOSFET 100A has a heavily doped drain region 10 extending in the y direction (second direction), and a plurality of plugs PLG1 are connected to this heavily doped drain region 10. The LDMOSFET 100A also has a drift region (lightly doped drain region) 12 formed so as to surround the heavily doped drain region 10. The impurity concentration of the drift region 12 is lower than the impurity concentration of the heavily doped drain region 10.

[0013] Furthermore, the LDMOSFET 100A has an insulating region that is in contact with the heavily doped drain region 10 and the drift region 12 and is formed so as to be sandwiched between the heavily doped drain region 10 and an end region 12A of the drift region 12 in the x direction (first direction) intersecting with the y direction in a plan view. This insulating region is the "STI structure 11."

[0014] 1, the LDMOSFET 100A has a body region 14 disposed away from the drift region 12, and has a source region 15 provided outside the body region 14. In this case, a region located between the drift region 12 and the source region 15 functions as a channel region 13. The LDMOSFET 100A further has a body contact region 16 provided outside the source region 15.

[0015] Here, a plurality of plugs PLG2 are connected to the source region 15, and a plurality of plugs PLG3 are connected to the body contact region 16. As shown in Fig. 1, the LDMOSFET 100A has a gate electrode 20 (hatched region in Fig. 1) formed to overlap in plan with a part of the "STI structure 11", an end region 12A of the drift region 12, and the channel region 13.

[0016] FIG. 2 is a cross-sectional view taken along line AA in FIG.

[0017] 2, a heavily doped drain region 10 is formed in a semiconductor substrate SUB, and a buffer region 10A (moderately doped drain region) is formed so as to enclose this heavily doped drain region 10. Furthermore, a drift region 12 is formed so as to enclose this buffer region 10A. Here, the heavily doped drain region 10, the buffer region 10A, and the drift region 12 constitute a "drain region."

[0018] Then, an "STI structure 11" is formed so as to be sandwiched between the heavily doped drain region 10 and the edge region 12A of the drift region 12. Furthermore, a body region 14 is formed in a region away from the edge region 12A of the drift region 12, and a source region 15 and a body contact region 16 are formed so as to be included in this body region 14. Here, the surface region of the semiconductor substrate SUB sandwiched between the edge region 12A of the drift region 12 and the source region 15 becomes a channel region 13.

[0019] Next, a gate electrode 20 is formed on a part of the "STI structure 11", on the edge region 12A of the drift region 12, and on the channel region 13. In particular, the gate electrode 20 is formed on the edge region 12A of the drift region 12 and on the channel region 13 via a gate insulating film 17. Next, an interlayer insulating layer IL is formed on the semiconductor substrate SUB so as to cover the gate electrode 20, and a plurality of plugs penetrating the interlayer insulating layer IL are formed in the interlayer insulating layer IL. For example, as shown in FIG. 2, the plurality of plugs include a plug PLG1 electrically connected to the high concentration drain region 10, a plug PLG2 electrically connected to the source region 15, and a plug PLG3 electrically connected to the body contact region 16. And, for example, the plug PLG1 is electrically connected to the wiring WL1 formed on the interlayer insulating layer IL. On the other hand, the plug PLG2 and the plug PLG3 are electrically connected to the wiring WL2 formed on the interlayer insulating layer IL.

[0020] In this manner, the LDMOSFET 100A in the first related technique is configured. Here, in the LDMOSFET 100A, as shown in FIG. 2, an "STI structure 11" that configures an insulating region in the drift region 12 is provided. As a result, a current path A from the heavily doped drain region 10 to the source region 15 passes through a path (see the arrow in FIG. 2) that bypasses the "STI structure 11". As a result, according to the LDMOSFET 100A in the first related technique, the current path between the heavily doped drain region 10 and the source region 15 becomes longer, and therefore the withstand voltage between the heavily doped drain region 10 and the source region 15 can be ensured.

[0021] However, the longer current path between the heavily doped drain region 10 and the source region 15 also means an increase in on-resistance. Therefore, while the LDMOSFET 100A in the first related technology can improve the breakdown voltage between the heavily doped drain region 10 and the source region 15, it also has the disadvantage of increasing the on-resistance. In other words, in an LDMOSFET, there is a trade-off between improving the breakdown voltage and reducing the on-resistance, and the LDMOSFET 100A in the first related technology has room for improvement in terms of the demand for further reducing the on-resistance while simultaneously improving the breakdown voltage and reducing the on-resistance.

[0022] Therefore, an LDMOSFET structure that can improve the breakdown voltage while reducing the on-resistance further is being studied.

[0023] 3 is a diagram showing a planar layout of an LDMOSFET 100B in the second related technique. In FIG. 3, in the LDMOSFET 100B in the second related technique, a slit region 11A is formed in the "STI structure 11". This slit region 11A extends in the x direction and is connected to the high-concentration drain region 10 and an end region 12A of the drift region 12. The drain region is exposed from this slit region 11A. In particular, in this specification, the drain region exposed from the slit region 11A is referred to as a slit diffusion region 30 (a dotted region).

[0024] FIG. 4 is a cross-sectional view taken along line AA in FIG.

[0025] As shown in FIG. 4, in the second related technique, a slit diffusion region 30 is formed between the high concentration drain region 10 and the end region 12A of the drift region 12. As a result, in the second related technique, not only the current path A similar to that in the first related technique shown in FIG. 2, but also the current path B passing through the slit diffusion region 30 shown in FIG. 4 exists. As a result, in the second related technique, the breakdown voltage can be improved by the detour path of the current path A, and the auxiliary current path B (shortest path) contributes to the reduction of the on-resistance. That is, according to the second related technique, it is possible to meet the demand for further reducing the on-resistance while simultaneously achieving both the improvement of the breakdown voltage and the reduction of the on-resistance. That is, the second related technique is considered to be useful as a structure that overcomes the room for improvement present in the first related technique.

[0026] <<Discovery by the inventors>> However, as a result of examining the structure of the LDMOSFET 100B in the second related technology, the present inventors have newly discovered that an electric field concentration region with high electric field strength is formed in the slit diffusion region 30 connecting the heavily doped drain region 10 and the end region 12A of the drift region 12, and that this electric field concentration region causes a decrease in the breakdown voltage of the LDMOSFET to become apparent.

[0027] The novel findings of the present inventors will be described below.

[0028] For example, Fig. 5 is a diagram showing a schematic diagram of an electric field distribution in a slit diffusion region by simulation. In Fig. 5, when a high voltage is applied between the high-concentration drain region 10 and the source region (not shown), it can be seen that an electric field concentration region CP1 shown by a "black region" and an electric field concentration region CP2 shown by a "black region" exist in the slit diffusion region 30 connecting the high-concentration drain region 10 and the end region 12A of the drift region 12.

[0029] In the second related technique in which such electric field concentration regions CP1 and electric field concentration regions CP2 exist, the electric field concentration regions CP1 and charge concentration regions CP2 described above become "weak points," resulting in a noticeable decrease in the breakdown voltage of the LDMOSFET 100B. That is, in the second related technique, the slit diffusion regions 30 are provided to reduce the on-resistance of the LDMOSFET 100B, but the inventors' studies have revealed that the formation of electric field concentration regions in the slit diffusion regions 30 leads to a decrease in the breakdown voltage of the LDMOSFET 100B.

[0030] In this regard, it is considered that a decrease in the withstand voltage of the LDMOSFET 100B can be suppressed if the electric field can be relaxed in the electric field concentration regions CP1 and CP2 generated in the slit diffusion region 30. Therefore, from the viewpoint of suppressing a decrease in the withstand voltage of the LDMOSFET 100B, it is desired to devise a way to relax the electric field in the electric field concentration regions CP1 and CP2 generated in the slit diffusion region 30.

[0031] Therefore, in the present embodiment, a device is provided to overcome the room for improvement that exists in the second related art. The technical idea of ​​the present embodiment that provides this device will be described below.

[0032] <Basic Concept of the Embodiment> The basic idea in this embodiment includes a first basic idea and a second basic idea, and therefore, in the following, the first basic idea and the second basic idea will be described separately.

[0033] <<First basic idea>> The first basic idea is to remove the electric field concentration region where the electric field concentration occurs from the slit diffusion region. In other words, the first basic idea is to remove a portion of the slit diffusion region where the electric field concentration occurs. As a result, the electric field concentration region is removed from the slit diffusion region, and the electric field concentration region no longer exists in the slit diffusion region. This means that there is no longer an area in the slit diffusion region that can be a "weak point" that reduces the breakdown voltage, making it possible to suppress the reduction in the breakdown voltage of the LDMOSFET.

[0034] FIG. 6 is a diagram for explaining the concept of the first basic idea.

[0035] First, as shown in Fig. 5, an electric field concentration region CP1 occurs in the slit diffusion region 30. Therefore, in the first basic idea, for example, as shown in Fig. 6, a part of the slit diffusion region 30 including the electric field concentration region CP1 is removed. In other words, the concept of the first basic idea is to suppress a decrease in breakdown voltage caused by the electric field concentration region CP1 by removing a part of the slit diffusion region 30 including the electric field concentration region CP1.

[0036] <<Second Basic Thought>> The second basic idea is to remove a part of the gate electrode that overlaps with the slit diffusion region in a planar manner. In other words, the second basic idea is to provide a notch in the gate electrode that overlaps with the slit diffusion region in a planar manner. This makes it possible to suppress electric field concentration caused by a steep potential gradient based on the potential difference between the slit diffusion region and the gate electrode.

[0037] FIG. 7 is a diagram for explaining the concept of the second basic idea.

[0038] 7, the slit diffusion region 30 is provided so as to connect the high-concentration drain region 10 and the end region 12A of the drift region 12. At this time, the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is covered with the gate electrode 20.

[0039] Here, since a high positive voltage is applied to the heavily doped drain region 10, a positive voltage is also applied to the slit diffusion region 30 connected to the heavily doped drain region 10. On the other hand, for example, when the LDMOSFET is off, 0 V (ground potential) is applied to the gate electrode 20. Therefore, when the LDMOSFET is off, in the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12 shown in the upper diagram of FIG. 7, a high positive voltage is applied to the connection region itself, and 0 V is applied to the gate electrode 20 covering the connection region.

[0040] As a result, in the connection region covered by the gate electrode 20, a large potential difference occurs between the gate electrode 20 covering the connection region. As a result, a steep potential gradient based on the large potential difference described above occurs in the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30. As a result, for example, an electric field concentration region CP2 as shown in FIG. 5 is generated.

[0041] Therefore, in the second basic idea, for example, as shown in the lower diagram of Fig. 7, a part of the gate electrode 20 is removed (a notch is provided) so that the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is not covered by the gate electrode 20. In other words, the concept of the second basic idea is to prevent a large potential difference from occurring between the gate electrode 20 covering the connection region and the connection region by removing a part of the gate electrode 20 that overlaps with the connection region in a plan view. As a result, according to the basic idea, it is possible to prevent the occurrence of an electric field concentration region CP2 caused by a steep potential gradient in the connection region, and thereby to prevent a decrease in breakdown voltage caused by the electric field concentration region CP2.

[0042] Note that in this specification, the case where the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is not covered by the gate electrode 20 may be referred to as "the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is exposed from the gate electrode 20". That is, in this specification, the expressions "the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is not covered by the gate electrode 20" and "the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is exposed from the gate electrode 20" are used with the same intended meaning.

[0043] <Specific Configuration of LDMOSFET> Subsequently, the configuration of the LDMOSFET embodying the above-described first basic idea and second basic idea will be described with reference to the drawings.

[0044] FIG. 8 is a diagram showing the planar layout of the LDMOSFET 100 in the present embodiment. In FIG. 8, the LDMOSFET 100 has a high-concentration drain region 10 extending in the y direction (second direction), and a plurality of plugs PLG1 are connected to the high-concentration drain region 10. The LDMOSFET 100 has a drift region 12 formed so as to surround the high-concentration drain region 10. Further, the LDMOSFET 100 has an insulating region that is in contact with the high-concentration drain region 10 and the drift region 12 and is sandwiched between the end region 12A of the drift region 12 in the x direction (first direction) intersecting the y direction in a plan view and the high-concentration drain region 10. This insulating region is the "STI structure 11".

[0045] Subsequently, as shown in FIG. 8, the LDMOSFET 100 has a body region 14 disposed away from the drift region 12 and a source region 15 provided outside the body region 14. At this time, the region located between the drift region 12 and the source region 15 functions as the channel region 13. The LDMOSFET 100 further has a body contact region 16 provided outside the source region 15.

[0046] Here, a plurality of plugs PLG2 are connected to the source region 15, and a plurality of plugs PLG3 are connected to the body contact region 16. As shown in Fig. 8, the LDMOSFET 100 has a gate electrode 20 (hatched region in Fig. 8) formed to overlap at least a part of the "STI structure 11" and the channel region 13 in a planar manner.

[0047] In this embodiment, as shown in FIG. 8, the "STI structure 11" is provided with a slit region 11A extending in the x direction, and a slit diffusion region 30 extending in the x direction and contacting the end region 12A of the drift region 12 is exposed from the slit region 11A. At this time, in the LDMOSFET 100 in this embodiment, a part of the "STI structure 11" is interposed between the slit region 11A and the high-concentration drain region 10. That is, in this embodiment, the slit diffusion region 30 exposed from the slit region 11A is connected to the end region 12A of the drift region 12, but is not connected to the high-concentration drain region 10, unlike the second related art shown in FIG. 3, for example. In other words, the slit diffusion region 30 is separated from the high-concentration drain region 10 in a plan view.

[0048] 8, at least a connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is exposed from the gate electrode 20 in a plan view. In other words, the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 does not overlap with the gate electrode 20 in a plan view.

[0049] Furthermore, in the LDMOSFET 100 of this embodiment, a plurality of slit regions 11A are formed in the "STI structure 11", and the plurality of slit regions 11A are arranged side by side in the y direction (second direction) in a plan view. Then, a slit diffusion region 30 is exposed from each of the plurality of slit regions 11A in a plan view. At this time, the slit diffusion region 30 exposed from each of the plurality of slit regions 11A is exposed from the gate electrode 20 in a plan view.

[0050] FIG. 9 is a cross-sectional view taken along line AA in FIG.

[0051] 9, a high-concentration drain region 10 is formed in a semiconductor substrate SUB, and a buffer region 10A (moderately doped drain region) is formed so as to enclose this high-concentration drain region 10. Furthermore, a drift region 12 (lightly doped drain region) is formed so as to enclose this buffer region 10A. Here, the high-concentration drain region 10, the buffer region 10A, and the drift region 12 constitute a "drain region."

[0052] An “STI structure 11” is formed so as to contact the high-concentration drain region 10 and the drift region 12, and a slit diffusion region 30 is exposed so as to be sandwiched between this “STI structure 11” and an end region 12A of the drift region 12.

[0053] Furthermore, a body region 14 is formed in a region away from end region 12A of drift region 12, and a source region 15 and a body contact region 16 are formed so as to be contained in this body region 14. Here, a surface region of the semiconductor substrate SUB sandwiched between end region 12A of drift region 12 and source region 15 becomes a channel region 13.

[0054] Next, a gate electrode 20 is formed on a part of the "STI structure 11" and on the channel region 13, and in particular, the gate electrode 20 is formed on the channel region 13 via a gate insulating film 17. On the other hand, in this embodiment, the gate electrode 20 is not formed on the slit diffusion region 30 including the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30. That is, in this embodiment, the slit diffusion region 30 including the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is exposed from the gate electrode 20.

[0055] Next, an interlayer insulating layer IL is formed on the semiconductor substrate SUB so as to cover the gate electrode 20, and a plurality of plugs penetrating the interlayer insulating layer IL are formed in the interlayer insulating layer IL. For example, as shown in FIG. 9, the plurality of plugs include a plug PLG1 electrically connected to the high concentration drain region 10, a plug PLG2 electrically connected to the source region 15, and a plug PLG3 electrically connected to the body contact region 16. For example, the plug PLG1 is electrically connected to a wiring WL1 formed on the interlayer insulating layer IL. On the other hand, the plug PLG2 and the plug PLG3 are electrically connected to a wiring WL2 formed on the interlayer insulating layer IL.

[0056] FIG. 10 is a cross-sectional view taken along line BB in FIG.

[0057] 10, a heavily doped drain region 10 is formed in a semiconductor substrate SUB, and a buffer region 10A (moderately doped drain region) is formed so as to enclose this heavily doped drain region 10. Furthermore, a drift region 12 (lightly doped drain region) is formed so as to enclose this buffer region 10A. An "STI structure 11" is formed so as to contact the heavily doped drain region 10 and an end region 12A of the drift region 12.

[0058] Furthermore, a body region 14 is formed in a region away from end region 12A of drift region 12, and a source region 15 and a body contact region 16 are formed so as to be contained in this body region 14. Here, a surface region of the semiconductor substrate SUB sandwiched between end region 12A of drift region 12 and source region 15 becomes a channel region 13.

[0059] Next, a gate electrode 20 is formed on a part of the "STI structure 11" and on the channel region 13. In particular, the gate electrode 20 is formed on the channel region 13 via a gate insulating film 17. On the other hand, in this embodiment, the gate electrode 20 is not formed on a connection region between the end region 12A of the drift region 12 and the "STI structure 11". That is, in this embodiment, the connection region between the end region 12A of the drift region 12 and the "STI structure 11" is exposed from the gate electrode 20. Note that in FIG. 10 as well, the structure (such as a plug structure) relating to the interlayer insulating layer IL is similar to that in FIG. 9, and therefore description thereof will be omitted.

[0060] In this manner, the LDMOSFET 100 of the present embodiment is configured.

[0061] The semiconductor regions constituting the LDMOSFET 100 are, for example, as follows: (1) Semiconductor substrate SUB→p - Semiconductor Substrate (2) Highly doped drain region 10→n + Semiconductor area (3) Buffer region 10A → n-type semiconductor region (4) Drift region 12→n - Semiconductor area (5) Body region 14 → p-type semiconductor region (6) Source region 15→n + Semiconductor area (7) Body contact region 16→p + Semiconductor area

[0062] <Features of the embodiment> Next, features of this embodiment will be described.

[0063] The first feature of this embodiment is that, as shown in FIG. 9, the slit diffusion region 30 does not extend to connect with the high-concentration drain region 10, but is separated from the high-concentration drain region 10, and a part of the "STI structure 11" is interposed between the high-concentration drain region 10 and the slit diffusion region 30. This embodies the above-mentioned first basic idea, and the part of the slit diffusion region 30 exposed from the slit region where the electric field concentration region is formed is removed and replaced with a part of the "STI structure 11". Therefore, according to the first feature of this embodiment, it is possible to suppress the formation of the electric field concentration region in the slit diffusion region 30 exposed from the slit region. In other words, according to the first feature, the formation of a region that becomes a "weak point" of the breakdown voltage reduction in the slit diffusion region 30 is suppressed, and as a result, the breakdown voltage reduction of the LDMOSFET 100 can be suppressed.

[0064] 8, a portion of the gate electrode 20 is removed so that the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is not covered by the gate electrode 20. In other words, the second feature of the present embodiment is that the connection region between the end region 12A of the drift region 12 and the slit diffusion region 30 is exposed from the gate electrode 20.

[0065] According to the second feature, therefore, it is possible to prevent a large potential difference from occurring between the gate electrode 20 (0V: OFF) covering the connection region and the connection region (positive voltage). As a result, it is possible to prevent the occurrence of an electric field concentration region due to a steep potential gradient in the connection region, and thus it is possible to prevent a decrease in breakdown voltage due to the electric field concentration region.

[0066] <Verification of effectiveness> In the following, a description will be given of the verification results showing that, according to this embodiment, while providing a slit diffusion region for reducing the on-resistance, by adopting the above-mentioned first and second features, the breakdown voltage between the source region and the drain region in the off state can be improved.

[0067] Fig. 11 is a graph showing the relationship between the dimension "D" and the breakdown voltage of the LDMOSFET when only the first feature is adopted, and Fig. 12 is a graph showing the relationship between the dimension "D" and the on-resistance of the LDMOSFET when only the first feature is adopted.

[0068] Here, the dimension "D" refers to "D" in Fig. 6, and represents the length of the portion of the slit diffusion region to be removed. On the other hand, the breakdown voltage of the LDMOSFET refers to the breakdown voltage between the source region and the drain region when it is off, and the on-resistance of the LDMOSFET refers to the resistance of the LDMOSFET when it is on.

[0069] As shown in Figure 11, it can be seen that the larger the dimension "D", the higher the breakdown voltage. In other words, by increasing the portion of the slit diffusion region that is removed, the breakdown voltage can be improved. However, as shown in Figure 12, it can be seen that the on-resistance increases when the dimension "D" is increased. This is thought to be because, when the dimension "D" is increased, the remaining portion of the slit diffusion region that contributes to reducing the on-resistance decreases, causing the on-resistance to rise.

[0070] Next, Fig. 13 is a graph showing the relationship between the dimension "D" and the breakdown voltage of the LDMOSFET when both the first and second features are adopted. Also, Fig. 14 is a graph showing the relationship between the dimension "D" and the on-resistance of the LDMOSFET when both the first and second features are adopted.

[0071] 13, it can be seen that by adopting both the first and second feature points, the withstand voltage can be further improved when the dimension "D" is increased. Therefore, from the viewpoint of improving the withstand voltage, it is desirable to adopt both the first and second feature points.

[0072] However, as shown in FIG. 14, when both the first and second characteristic points are adopted, the on-resistance becomes even higher. The following reason is considered to be the reason. That is, when the second characteristic point is not adopted, for example, as shown in FIG. 4, the gate electrode 20 is present on the end region 12A of the drift region 12. Here, when the LDMOSFET is turned on, a positive voltage is applied to the gate electrode 20. Then, n - In the surface of the end region 12A, which is a type semiconductor region, electrons, which are majority carriers, are attracted to the gate electrode 20 to form an accumulation region. In other words, the current path from the heavily doped drain region 10 to the source region 15 includes an accumulation region with low resistance. As a result, when the second feature is not adopted, the on-resistance is low.

[0073] In contrast, when the second characteristic is adopted, as shown in FIG. 9, the gate electrode 20 does not exist on the end region 12A of the drift region 12. Therefore, even when the LDMOSFET is turned on, - No accumulation region is formed on the surface of the end region 12A, which is a type semiconductor region. As a result, a low-resistance accumulation region is not formed in the current path from the heavily doped drain region 10 to the source region 15, which is considered to result in a high on-resistance.

[0074] From the above, when focusing on improvement of the breakdown voltage regardless of the on-resistance, it can be seen that the breakdown voltage of the LDMOSFET can be improved in either case of adopting only the first feature (see FIG. 11) or adopting both the first feature and the second feature (see FIG. 13).

[0075] <Variation 1> Fig. 15 is a diagram showing a planar layout of the LDMOSFET 200 in the present modified example 1. As shown in Fig. 15, the multiple slit diffusion regions 30 arranged side by side in the y direction may be configured to be integrally exposed from the gate electrode 20. In other words, a portion of the gate electrode 20 does not have to be disposed between the adjacent slit diffusion regions 30.

[0076] <Variation 2> Fig. 16 is a diagram showing a planar layout of the LDMOSFET 300 in the present modified example 2. As shown in Fig. 16, the conductor pattern 40 provided between adjacent slit diffusion regions 30 does not have to be formed integrally with the gate electrode 20. In this case, for example, the conductor pattern 40 and the gate electrode 20 are electrically connected via a plug PLG4. In this case, in a planar view, among the multiple slit diffusion regions 30, the conductor pattern 40 is arranged between the slit diffusion regions 30 adjacent to each other in the y direction, and as a result, the multiple conductor patterns 40 are arranged side by side in the y direction.

[0077] <Variation 3> Fig. 17 is a diagram showing a planar layout of an LDMOSFET 400 in the third modification. Comparing the first and second characteristic points in the embodiment (see Figs. 11 to 14), the first characteristic point is more useful in terms of improving the breakdown voltage than the second characteristic point. On the other hand, the first characteristic point causes a larger increase in on-resistance than the second characteristic point. For this reason, in the case of a device in which the improvement in breakdown voltage achieved by the second characteristic point is sufficient, it is possible to adopt only the second characteristic point, for example, as shown in Fig. 17, in order to reduce the on-resistance.

[0078] Fig. 18 is a diagram showing a simulation result of the occurrence frequency of the impact ionization phenomenon in the slit diffusion region 30. In particular, Fig. 18(a) shows the simulation result in a configuration (corresponding to the second related technology) that does not employ the second feature point, and Fig. 18(b) shows the simulation result in a configuration (corresponding to the present modified example 3) that employs the second feature point.

[0079] 18(a), in the case of the second related technology not adopting the second feature, when attention is focused on the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12, it is found that there is a region where impact ionization occurs frequently in this connection region. Here, a region where impact ionization occurs frequently means an electric field concentration region, and therefore, from the simulation result shown in FIG. 18(a), it is found that in the second related technology not adopting the second feature, the above-mentioned electric field concentration region becomes a "weak point," and there is a high possibility that a decrease in the breakdown voltage of the LDMOSFET will become apparent.

[0080] 18(b), in the case of Modification 3 employing the second feature, when attention is focused on the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12, the frequency of occurrence of impact ionization is dispersed in this connection region, and the region where the frequency of occurrence of impact ionization is high is reduced. Here, a region where the frequency of occurrence of impact ionization is high means an electric field concentration region, and therefore, from the simulation result shown in FIG. 18(b), in Modification 3 employing the second feature, it is found that the occurrence of an electric field concentration region is suppressed, and as a result, a decrease in the breakdown voltage of the LDMOSFET can be suppressed.

[0081] In this way, according to the present modification 3 adopting the second feature, electric field concentration in the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12 can be alleviated, thereby suppressing a decrease in the breakdown voltage of the LDMOSFET.

[0082] <Modification 4> Fig. 19 is a diagram showing a planar layout of an LDMOSFET 500 in this modification 4. Here, for example, in a device in which the improvement in withstand voltage is insufficient with only the second feature point, from the viewpoint of improving the withstand voltage, for example, as shown in Fig. 19, a configuration may be adopted in which only the first feature point is adopted, or of course, a configuration may be adopted in which a combination of the first feature point and the second feature point is adopted, as in the embodiment shown in Fig. 8.

[0083] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device in this embodiment will be described with reference to Figures 20 to 26. Figures 20 to 26 show a cross-sectional view taken along line AA in Figure 8, a cross-sectional view taken along line BB in Figure 8, and a cross-sectional view taken along line CC in Figure 8.

[0084] First, as shown in Figure 20, - After preparing a mold semiconductor substrate SUB, an "STI structure 11" is formed on the semiconductor substrate SUB. The "STI structure 11" can be formed, for example, by forming a groove on the surface of the semiconductor substrate SUB using photolithography and etching techniques, and then filling this groove with an insulating film. At this time, a slit region 11A is formed in the "STI structure 11" by adjusting the patterning when forming the "STI structure 11" (see the AA cross section in FIG. 20). The drift region 12 exposed from this slit region 11A is the slit diffusion region 30.

[0085] Then, for example, by using a photolithography technique and an ion implantation method, an n-type impurity (donor) is introduced into the semiconductor substrate SUB. - A drift region 12 made of a type semiconductor region is formed.

[0086] Next, as shown in FIG. 21, a gate insulating film 17 and a gate electrode 20 are formed on the semiconductor substrate SUB. The gate insulating film 17 is made of a silicon oxide film, and can be formed by, for example, a thermal oxidation method. The gate electrode 20 is made of a polysilicon film, and can be formed by, for example, forming a polysilicon film by a CVD (Chemical Vapor Deposition) method, and then patterning the polysilicon film using a photolithography technique and an etching technique. Here, the polysilicon film is patterned so that the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12 is exposed from the gate electrode 20 (see the AA cross-sectional view in FIG. 21). This realizes the second feature of this embodiment, that the connection region between the slit diffusion region 30 and the end region 12A of the drift region 12 is exposed from the gate electrode 20.

[0087] 22, n-type impurities (donors) are introduced into the semiconductor substrate SUB by using photolithography and ion implantation, thereby forming a buffer region 10A made of an n-type semiconductor region contained in the drift region 12.

[0088] Furthermore, p-type impurities (acceptors) are introduced into the semiconductor substrate SUB by using photolithography and ion implantation, thereby forming a body region 14 made of a p-type semiconductor region separated from the drift region 12.

[0089] 23, sidewalls 50 are formed on the side walls of the gate electrode 20. The sidewalls 50 can be formed, for example, by forming an insulating film made of a silicon oxide film or the like on the semiconductor substrate SUB and then subjecting this insulating film to anisotropic etching.

[0090] 24, n-type impurities (donors) are introduced into the semiconductor substrate SUB by using photolithography and ion implantation. +In the same manner, photolithography and ion implantation are used to introduce n-type impurities (donors) into the semiconductor substrate SUB. As a result, the n-type impurities contained in the body region 14 are + A source region 15 made of a type semiconductor region is formed.

[0091] Here, the slit diffusion region 30 is separated from the heavily doped drain region 10, and the first characteristic feature of this embodiment is realized, that is, a part of the "STI structure 11" is interposed between the heavily doped drain region 10 and the slit diffusion region 30.

[0092] 25, p-type impurities (acceptors) are introduced into the semiconductor substrate SUB by using photolithography and ion implantation. + A body contact region 16 made of a type semiconductor region is formed.

[0093] 26, after forming an insulating film on the semiconductor substrate SUB on which the gate electrode 20 is formed, the insulating film is patterned by using photolithography and etching techniques to form a silicide block film 60. Thereafter, a silicide process is performed on the region not covered with the silicide block film 60.

[0094] Thereafter, although not shown, a wiring process is carried out using normal semiconductor manufacturing techniques.

[0095] In this manner, the semiconductor device according to the present embodiment can be manufactured.

[0096] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0097] For example, in the above embodiment, the example in which the "drain region" is composed of the high-concentration drain region 10, the buffer region 10A (medium-concentration drain region), and the drift region 12 (light-concentration drain region) has been described, but the buffer region 10A may be omitted. In other words, the "drain region" may be composed of the high-concentration drain region 10 and the drift region 12.

[0098] Furthermore, for example, as shown in FIG. 8, the embodiment shows an example in which a source region 15 extending in the y direction and a body contact region 16 extending in the y direction are arranged side by side in the x direction (channel direction). However, the basic idea of ​​the embodiment is not limited to this configuration and can be applied to, for example, a configuration in which a plurality of source regions 15 extending in the x direction and a plurality of body contact regions 16 extending in the x direction are arranged alternately in the y direction.

[0099] Furthermore, in the above embodiment, the "STI structure 11" is used as an example of an insulating region, but the basic idea of ​​the above embodiment is not limited to this configuration and can be applied, for example, to a case where a "LOCOS structure" is adopted as an insulating region.

[0100] For example, FIG. 8 shows an example in which the gate electrode 20 has a "gate ring structure" surrounding the heavily doped drain region 10 in a planar view. However, the basic idea of ​​the above embodiment is not limited to this configuration, and can also be applied to a "gate non-ring structure" in which the gate electrode 20 does not surround the entire heavily doped drain region 10 in a planar view. [Explanation of symbols]

[0101] 10 Highly doped drain region 11 “STI structure” 11A Slit area 12 Drift Region 12A end area 13 Channel Area 14 Body Region 15 Source Region 16 Body Contact Area 17 Gate insulating film 20 Gate electrode 30 Slit diffusion area 40 Conductor Pattern 50 Sidewall 60 Silicide Block Film 100LDMOSFET 100A LDMOSFET 100B LDMOSFET 200LDMOSFET 300LDMOSFET 400LDMOSFET 500LDMOSFET CP1 Electric field concentration area CP2 Electric field concentration area IL Interlayer insulation layer PLG1 Plug PLG2 plug PLG3 Plug SUB Semiconductor Substrate WL1 Wiring WL2 Wiring

Claims

1. A drain region; a source region spaced apart from the drain region; a channel region located between the drain region and the source region; a gate insulating film provided on the channel region; a gate electrode provided on the gate insulating film; an insulating region disposed within the drain region; A semiconductor device comprising: The drain region is A heavily doped drain region; a lightly doped drain region including the heavily doped drain region; Including, In a plan view, the insulating region has a slit region extending in a first direction, In a plan view, the insulating region is interposed between the slit region and the high concentration drain region, The insulating region has a plurality of the slit regions, The plurality of slit regions are arranged side by side in a second direction intersecting the first direction, In a planar view, a conductor pattern is arranged between adjacent slit regions in the second direction among the plurality of slit regions, so that the plurality of conductor patterns are arranged side by side in the second direction.

2. 2. The semiconductor device according to claim 1, The slit region is spaced apart from the high concentration drain region.

3. 2. The semiconductor device according to claim 1, The slit region is exposed from the gate electrode.

4. 2. The semiconductor device according to claim 1, a connection region between the lightly doped drain region and an end of the slit diffusion region on the source region side exposed from the slit region, the connection region being exposed from a gate electrode in a plan view.

5. 2. The semiconductor device according to claim 1, In a plan view, the plurality of slit regions are integrally exposed from the gate electrode.

6. 2. The semiconductor device according to claim 1, each of the plurality of conductor patterns is electrically connected to the gate electrode via a plug.

7. A drain region; a source region spaced apart from the drain region; a channel region located between the drain region and the source region; a gate insulating film provided on the channel region; a gate electrode provided on the gate insulating film; an insulating region disposed within the drain region; A semiconductor device comprising: The drain region is A heavily doped drain region; a lightly doped drain region including the heavily doped drain region; Including, In a plan view, the insulating region has a slit region extending in a first direction, In a plan view, a connection region between an end portion of the slit diffusion region on the source region side exposed from the slit region and the low concentration drain region is exposed from a gate electrode; The insulating region has a plurality of the slit regions, The plurality of slit regions are arranged side by side in a second direction intersecting the first direction, In a planar view, a conductor pattern is arranged between adjacent slit regions in the second direction among the plurality of slit regions, so that the plurality of conductor patterns are arranged side by side in the second direction.

8. 8. The semiconductor device according to claim 7, In a plan view, the insulating region is interposed between the slit region and the high-concentration drain region.

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