Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device comprising: an element region (31) having an n-type layer (12), a first p-type layer (13) on the n-type layer, and a second p-type layer (14) which is on the first p-type layer and which has a higher acceptor concentration than the first p-type layer; and an electric field relaxation region (32) surrounding the element region. The electric field relaxation region includes, in the first p-type layer and the second p-type layer, a region containing an impurity element for inactivating a portion of the acceptors in the first p-type layer and the second p-type layer.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a nitride semiconductor device and a manufacturing method thereof. This application claims priority based on Japanese Patent Application No. 2021-072595, filed on April 22, 2021, the contents of which are incorporated herein by reference. [Background technology]

[0002] A technology has been proposed for improving the breakdown voltage of a nitride semiconductor device by forming a termination structure having a p-type guard ring portion around the active portion and an i-type or n-type ion implantation region around that (see, for example, Patent Document 1).

[0003] A technology has been proposed in which a recess groove is formed around the element region to provide an electric field relaxation region by thinning the p-layer, making the electric field relaxation region more susceptible to depletion when a voltage is applied, thereby relaxing the electric field at the edge of the element region and increasing the voltage resistance of the entire element (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-186429 (A) [Patent Document 2] Japanese Patent Application Publication No. 2017-183428 (A) Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, a depletion layer spreads between the p-type guard ring portion and the adjacent i-type or n-type ion implantation region along the surface of the nitride semiconductor layer of the termination structure, and an electric field is applied. Such a guard ring structure has a problem that local electric field concentration is likely to occur. In Patent Document 2, although electric field concentration can be avoided because the electric field relaxation region is a p-layer, there is a problem that electric field concentration is likely to occur at the inner and outer ends of the electric field relaxation region. Furthermore, there is a problem that it is not easy to precisely control the thickness in order to make the p-layer thin, making it difficult to apply to a production process.

[0006] An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage by suppressing electric field concentration in a termination region surrounding an element region, and a method for manufacturing the same. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, there is provided a semiconductor device comprising: an element region having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer and having a higher acceptor concentration than the first p-type layer; and an electric field relaxation region surrounding the element region, wherein the first p-type layer and the second p-type layer have regions containing an impurity element that inactivates a portion of the acceptors in the first p-type layer and the second p-type layer.

[0008] According to the above aspect, in the electric field relaxation region surrounding the element region, a region containing an impurity element that inactivates a part of the acceptor is formed in the first p-type layer and the second p-type layer. Since the region containing the impurity element has a high resistance due to the inactivation of a part of the acceptor, it is possible to suppress the formation of an electric field concentration point where the electric field is locally concentrated, thereby improving the breakdown voltage of the semiconductor device.

[0009] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, including the steps of epitaxially growing an n-type layer on a semiconductor substrate, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer, the second p-type layer having a higher acceptor concentration than the first p-type layer; activating acceptors in the first and second p-type layers; implanting impurity element ions into the first and second p-type layers in an electric field relaxation region surrounding an element region by a multistage ion implantation method to inactivate a portion of the acceptors in the first p-type layer and the second p-type layer; and forming an electrode on a surface of the second p-type layer in the element region.

[0010] According to the above other aspect, it is possible to set an optimum acceptor concentration for the element performance for the first p-type layer and the second p-type layer epitaxially grown in the element region, and in the electric field relaxation region surrounding the element region, impurity element ions that inactivate a portion of the acceptors are implanted into the first p-type layer and the second p-type layer to form a high-resistance region, thereby suppressing the formation of electric field concentration points where the electric field is locally concentrated, and improving the breakdown voltage of the semiconductor device. Effect of the Invention

[0011] According to the present invention, the breakdown voltage of a semiconductor device can be improved. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment. [Figure 2A] 1 is a part of a process diagram (part 1) for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2B] 1 is a part of a process diagram (part 1) for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2C] 1 is a part of a process diagram (part 1) for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 3A] 1 is a part of a process diagram (part 2) for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3B]1 is a part of a process diagram (part 2) for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3C] 1 is a part of a process diagram (part 2) for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram showing conditions for multi-stage ion implantation in a semiconductor device according to an embodiment; [Diagram 5] FIG. 1 is a diagram showing the relationship between the breakdown voltage of a semiconductor device according to an embodiment and the total dose of implanted boron. [Figure 6] 1 is a diagram showing a breakdown voltage of a semiconductor device according to an embodiment obtained by simulation. [Figure 7A] FIG. 13 is a distribution diagram of equipotential surfaces at the time of avalanche occurrence in a semiconductor device having an acceptor surface density of 1.0×10 13 cm −2 . [Figure 7B] FIG. 13 is a distribution diagram of equipotential surfaces at the time of avalanche occurrence in a semiconductor device in which boron ions are not implanted into the electric field relaxation region (no ion implantation). [Figure 8A] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 8B] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 9] FIG. 4 is a diagram showing conditions for multi-stage ion implantation in the semiconductor device of Example 1. [Figure 10] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 11 is a diagram showing the breakdown voltage of the semiconductor device of Example 3 obtained by simulation. [Figure 13] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that elements common to multiple drawings are given the same reference numerals, and detailed descriptions of those elements will be omitted.

[0014] Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment. In this embodiment, a gallium nitride vertical diode having a pn diode formed in an element region is taken as an example of a nitride semiconductor device. For convenience of illustration, Fig. 1 shows the element region to the isolation region at the edge of the element region. The element region, the electric field relaxation region, and the isolation region are regions divided in the in-plane direction of the semiconductor, and are bounded by a plane (a line in the cross-sectional view shown in FIG. 1) perpendicular to the stacking direction. For example, when a semiconductor is viewed in a plan view, an element region is located in the center, an electric field relaxation region surrounding the element region is located around the element region, and an isolation region surrounding the electric field relaxation region is located around the electric field relaxation region.

[0015] Referring to FIG. 1, in the semiconductor device 10, an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are formed in this order on a semiconductor substrate 11. The n-type layer 12, the first p-type layer 13, and the second p-type layer 14 of the element region 31 extend in the horizontal direction at least to an electric field relaxation region 32. In the element region 31 and the electric field relaxation region 32 surrounding the periphery thereof, a protective film 15 is formed on the second p-type layer 14. The protective film 15 is also formed outside the electric field relaxation region 32, and is formed on the n-type layer 12 in an isolation region 33 surrounding the periphery of the electric field relaxation region 32. In the element region 31, an anode electrode 16 is formed on the second p-type layer 14 in an opening of the protective film 15. A cathode electrode 18 is formed on the back side of the gallium nitride semiconductor substrate 11.

[0016] The semiconductor substrate 11 has an impurity element concentration of, for example, 1×10 18 cm -3 The semiconductor substrate 11 is an n+ type semiconductor, and can be made of gallium nitride. The semiconductor substrate 11 made of gallium nitride has a wurtzite (hexagonal) crystal structure, and the main surface is a (0001) plane. The impurity element is, for example, silicon (Si).

[0017] The n-type layer 12 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the semiconductor substrate 11 by metalorganic chemical vapor deposition (MOCVD), and has a thickness of, for example, 10 μm. The n-type layer 12 contains an n-type impurity element, for example, silicon (Si), and the concentration of the impurity element is, for example, 1.3×10 16 cm -3 It is.

[0018] The first p-type layer 13 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the n-type layer 12 by MOCVD, and has a thickness of, for example, 1.0 μm. The first p-type layer 13 contains a p-type impurity element, for example, magnesium (Mg), and has a concentration of, for example, 2×10 18 cm -3 Or less.

[0019] The second p-type layer 14 is a semiconductor crystal layer (gallium nitride) epitaxially grown by MOCVD on the first p-type layer 13, and has a thickness of, for example, 50 nm. The second p-type layer 14 contains a p-type impurity element, for example, magnesium (Mg), and has a concentration of, for example, 1×10 20 cm -3 Or more.

[0020] The element region 31 is located at the center of the pn diode, and is a region through which an on-current flows. In the element region 31, the anode electrode 16 is in ohmic contact with the second p-type layer 14. The anode electrode 16 may be a single metal film having a large work function, such as gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), etc., or an alloy film of these metals, and is preferably a laminate film of a gold (Au) film formed by sputtering on a nickel (Ni) film.

[0021] In the electric field relaxation region 32, an impurity element implanted region 20 is formed in the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14. The impurity element implanted region 20 contains an impurity element that inactivates the acceptors in the first p-type layer 13 and the second p-type layer 14. The impurity element preferably contains at least one element of boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe). This reduces the active acceptor concentration in the first p-type layer 13 and the second p-type layer 14. In terms of electrical and thermal stability of the withstand voltage characteristics, it is particularly preferable for the impurity element to contain boron (B). In the vicinity of the boundary between the first p-type layer 13 and the n-type layer 12, it is preferable to implant the impurity element so that the acceptor surface density of the first p-type layer 13 and the donor surface density of the n-type layer 12 directly below are balanced. This makes it easier to deplete the electric field relaxation region 32 when a reverse bias is applied to the pn diode, and suppresses electric field concentration at the mesa edge 21 at the boundary between the isolation region 33 and the electric field relaxation region 32. As a result, the breakdown voltage of the entire pn diode can be significantly improved.

[0022] The impurity element is implanted by an ion implantation method, and is preferably implanted by a multi-stage implantation method in that it is possible to form a uniform impurity element concentration in the impurity element implanted region 20. The impurity element implanted region 20 may be formed to reach the n-type layer 12 below the first p-type layer 13.

[0023] The impurity element implantation region 20 may be formed in the electric field buffer region 32 such that a plurality of partial regions having different impurity element concentrations are continuously formed from the side closer to the element region 31 to the side farther from the element region 31 (for example, up to the mesa edge 21), or the impurity element concentration may be set higher in the partial region farther from the element region 31 than in the partial region closer to the element region 31. This makes it possible to make the acceptor concentration on the outer periphery side of the electric field buffer region 32 lower than that on the inner periphery side, thereby suppressing electric field concentration and further increasing the breakdown voltage. The number of partial regions may be two, three or more.

[0024] Furthermore, the impurity element implanted region 20 may be formed as a plurality of partial regions in the electric field relaxation region 32 so as to surround the periphery of the element region 31 from the side closer to the element region 31 to the side farther from the element region 31. By providing the impurity element implanted region in the electric field relaxation region 32 so as to surround the element region 31 in multiple parts, it is possible to reduce or avoid the risk of localized electric field concentration due to shape abnormalities of the semiconductor device caused by the manufacturing process.

[0025] In the isolation region 33, a mesa groove 22 is formed, and an n-type layer 12 is formed from which the first p-type layer 13 and the second p-type layer 14 have been removed. This electrically isolates the first p-type layer 13 and the second p-type layer 14 of the semiconductor device 10 from the surroundings. At the mesa edge 21 at the boundary between the isolation region 33 and the electric field reduction region 32, the angle between the surface 14a and the side of the second p-type layer 14 is shown as a right angle (90 degrees) in FIG. 1. This angle may be greater than 90 degrees (i.e., an obtuse angle), and the cross-sectional shape of the mesa structure may be trapezoidal.

[0026] The semiconductor layer at the surface of the mesa groove 22 is an n-type layer 12. An impurity element implanted region 23 may be formed from the surface of the n-type layer 12 to a predetermined depth by implanting an impurity element so as to balance the surface density of the n-type impurity element near the surface of the n-type layer 12. This reduces the active donor concentration of the n-type layer 12. The implanted impurity element may be the same as the impurity element of the impurity element implanted region 20 in the electric field relaxation region 32.

[0027] As a modified example, an insulating region may be formed in the isolation region by inactivating the acceptors in the first p-type layer 13 and the second p-type layer 14, without forming the mesa groove 22. This makes it unnecessary to perform a dry etching process when forming the mesa groove 22, and makes it possible to avoid damage to the crystal layers (the first p-type layer 13 and the second p-type layer 14) that is likely to occur around the mesa edge 21, and suppresses electric field concentration caused by such a manufacturing process.

[0028] The protective film 15 is formed from the outer periphery of the anode electrode 16 in the element region 31 to the surface of the second p-type layer 14 or the n-type layer 12 in the electric field relaxation region 32 and the isolation region 33. The protective film 15 is made of an insulating material and has a thickness of, for example, 1.0 μm. The protective film 15 may be a SiO2 film, a SiN film, or an Al2O3 film. It is preferable to form the SiO2 film by CVD, the SiN film by plasma CVD, and the Al2O3 film by atomic layer deposition (ALD).

[0029] The cathode electrode 18 is formed on the back surface of the semiconductor substrate 11. The cathode electrode 18 is preferably a laminated film of an aluminum (Al) film with a titanium (Ti) film as an undercoat, since this can form an ohmic contact with the semiconductor substrate 11. The cathode electrode 18 may also be a laminated film of three or more layers further laminated with other metals.

[0030] According to this embodiment, in the electric field relaxation region 32 surrounding the element region 31, the impurity element implantation region 20 containing an impurity element that inactivates the acceptor is formed in the first p-type layer 13 and the second p-type layer 14. Since the impurity element implantation region 20 has a high resistance due to inactivation of a part of the acceptor, it is possible to suppress the formation of an electric field concentration point where the electric field is locally concentrated, and to improve the breakdown voltage of the semiconductor device 10. Furthermore, in the isolation region 33 surrounding the electric field relaxation region 32, the first p-type layer 13 and the second p-type layer 14 are removed to form a mesa groove 22 exposing the n-type layer 12, thereby further suppressing the electric field concentration and further improving the breakdown voltage of the semiconductor device 10.

[0031] In this embodiment, the p-type layer has a two-layer structure of the first p-type layer 13 and the second p-type layer 14, but may have a single-layer structure with the same acceptor concentration as the second p-type layer 14.

[0032] 2A to C and 3A to C are process diagrams (part 1 and part 2) of a semiconductor device according to one embodiment. A method for manufacturing a semiconductor device will be described with reference to FIGS. 2A to C and 3A to C.

[0033] 2A, an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are formed in this order on a semiconductor substrate 11. 18 cm -3 An n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are epitaxially grown in this order on an n+-type gallium nitride semiconductor substrate 11 by MOCVD. A semiconductor substrate thus laminated may also be used. Next, a heat treatment is performed in a nitrogen gas atmosphere to activate the acceptor impurity elements in the first p-type layer 13 and the second p-type layer 14. The heat treatment is performed, for example, at 800° C. for 30 minutes, but may be performed under different conditions.

[0034] Next, in the step of FIG. 2B, the first p-type layer 13 and the second p-type layer 14 in the isolation region 33 are removed to expose the n-type layer 12, forming the mesa groove 22. Specifically, a SiO2 film having a thickness of 1.0 μm is formed on the entire surface of the second p-type layer 14 by a CVD method. Next, a resist mask is formed on the SiO2 film by a photolithography method, the SiO2 film in the isolation region 33 is removed by wet etching to expose the second p-type layer 14, and the second p-type layer 14, the first p-type layer 13, and the n-type layer 12 are removed by dry etching, for example, a reactive ion etching method (RIE method), to expose the n-type layer 12. The mesa groove 22 is formed, for example, to a depth of 2.5 μm from the surface of the second p-type layer 14. Next, the SiO2 film on the surface of the second p-type layer 14 is removed.

[0035] Next, in the step of FIG. 2C, impurity element ions that inactivate a part of the acceptor are implanted into the second p-type layer 14, the first p-type layer 13, and the n-type layer 12 of the electric field relaxation region 32 and the n-type layer 12 of the isolation region 33 to form the impurity element implanted region 20 and the impurity element implanted region 23. Specifically, a SiO2 film 24 is formed by a CVD method on the surface of the second p-type layer 14 of the element region 31 and the electric field relaxation region 32 and on the surface of the n-type layer 12 of the isolation region 33 as a through film for the ion implantation method. The SiO2 film 24 has a thickness of, for example, 50 nm. A photoresist film 25 is formed on the SiO2 film 24 of the element region 31 as a mask. Next, impurity element ions are implanted from an impurity element ion source into the electric field relaxation region 32 and the isolation region 33 by a multi-stage ion implantation method. The impurity element ions preferably contain ions of at least one element selected from boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe), and in particular, boron (B) is preferably contained in terms of electrical and thermal stability of the breakdown voltage characteristics. The ion implantation angle is preferably inclined with respect to the c-axis of the crystal axis of the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 (i.e., the c-axis of the crystal axis of the semiconductor substrate 11), and is preferably in the range of 4° to 7°. This makes it possible to suppress ion channeling along the above-mentioned crystal axis.

[0036] In the ion implantation of this embodiment, a multi-stage implantation method is used in which the implantation energy and dose are changed for each implantation. In order to control the depth distribution of the impurity element concentration, it is preferable to perform the implantation in three or more separate steps. In addition, it is preferable to perform the implantation using the highest implantation energy first and gradually reduce the implantation energy for each implantation in order to improve the controllability of the depth distribution. The maximum implantation energy is preferably set so that the implanted impurity element reaches the entire p-type layer, and is set to 400 keV in this embodiment in which the p-type layer thickness is 1 μm. The total dose of the multi-stage ion implantation is set to 1×10 when the acceptor surface density of the first p-type layer 13 is 1×10 13 cm -2In order to suppress electric field concentration in the electric field relaxation region 32, it is preferable to set the value to be in the vicinity of 1×10 13 cm -2 Set to.

[0037] 2C, as shown in FIG. 3A, in the electric field relaxation region 32, the impurity element implantation region 20 is formed from the surface of the second p-type layer 14 to a predetermined depth from the surface (interface with the first p-type layer 13) of the second p-type layer 14, the first p-type layer 13, and the n-type layer 12 in the depth direction from the surface of the second p-type layer 14. In the isolation region 33, the impurity element implantation region 23 is formed from the surface of the n-type layer 12 to a predetermined depth. In the step of FIG. 3A, the photoresist film 25 is removed, and a heat treatment is performed in a nitrogen gas atmosphere to stabilize the characteristics of the impurity element implantation regions 20, 23. The heat treatment is performed, for example, at 800° C. for 30 minutes, but may be performed under different conditions. Furthermore, the SiO2 film 24 is removed by wet etching.

[0038] 2C, multiple ion implantation may be performed by forming a photoresist film 25 on the surface of the second p-type layer 14 in the electric field relaxation region 32, in a ring shape in a plan view, so as to surround the periphery of the element region 31, and forming a plurality of photoresist films spaced apart from each other. As a result, partial regions in which a plurality of impurity elements are implanted from the surface (interface with the first p-type layer 13) of the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 to a predetermined depth in the depth direction from the surface of the second p-type layer 14, so that the impurity element implanted region surrounds the periphery of the element region 31 from the side closer to the element region 31 to the side farther from the element region 31 in the electric field relaxation region 32 (see Example 1 and FIG. 8 described later).

[0039] Furthermore, after the step of FIG. 2C, impurity element ions may be further implanted into the impurity element implantation region 20 of the electric field relaxation region 32, in a portion far from the element region 31, by a multi-stage ion implantation method, to form a partial region having a higher areal density of the impurity element than the impurity element implantation region 20 closer to the element region 31 (see Example 2 and FIG. 10 described later).

[0040] Next, in the step of FIG. 3B, a protective film 15 is formed to cover the surfaces of the second p-type layer 14 in the element region 31 and the electric field relaxation region 32, and the surface of the n-type layer 12 in the isolation region 33, and then an opening is formed in the protective film 15 in the element region 31 to form an anode electrode 16. Specifically, the protective film 15, for example, a SiO2 film (thickness 1 μm) is formed by CVD on the entire surface shown in FIG. 3A. Next, a resist mask is formed on the protective film 15 by photolithography, and the protective film 15 in the portion where the anode electrode 16 is to be formed is removed by wet etching to form an opening having a diameter of, for example, 200 μm to expose the second p-type layer 14. Next, a metal layer, for example, a nickel (Ni) film, is formed by vapor deposition to a thickness of 100 nm to cover the exposed second p-type layer 14 and the protective film 15. Next, a resist mask is formed by photolithography to remove unnecessary metal layers on the protective film 15 by wet etching to form the anode electrode 16.

[0041] Next, in the step of FIG. 3C, a cathode electrode 18 is formed on the rear surface 11a of the semiconductor substrate 11. Specifically, the oxide film on the rear surface 11a of the semiconductor substrate 11 is removed and cleaned, and a metal laminate film, for example, a titanium (Ti) film, an aluminum (Al) film, and a titanium nitride (TiN) film are sequentially deposited on the entire rear surface 11a by a sputtering method or a vapor deposition method to form the cathode electrode 18. Next, a heat treatment is performed in a nitrogen gas atmosphere to reduce the contact resistance of the anode electrode 16 and the cathode electrode 18. The heat treatment is performed, for example, at 550° C. for 10 minutes. In this manner, the semiconductor device 10 is formed.

[0042] According to the manufacturing method of the semiconductor device of the present embodiment, it is possible to set an optimum acceptor concentration for the device performance in the epitaxially grown first p-type layer 13 and second p-type layer 14 in the device region 31, and to form a highly resistive impurity element implanted region 20 by implanting impurity element ions that inactivate a part of the acceptors in the first p-type layer 13 and the second p-type layer 14 in the electric field relaxation region 32 surrounding the device region 31, thereby suppressing the formation of an electric field concentration point where the electric field locally concentrates, and thus improving the breakdown voltage of the semiconductor device 10. Furthermore, in the isolation region 33 surrounding the electric field relaxation region 32, the first p-type layer 13 and the second p-type layer 14 are removed to form a mesa groove 22 exposing the n-type layer 12, thereby further suppressing the electric field concentration, thereby further improving the breakdown voltage of the semiconductor device 10.

[0043] Fig. 4 is a diagram showing conditions for multi-stage ion implantation in a semiconductor device according to an embodiment, and shows an example of the conditions for multi-stage ion implantation in the process of Fig. 2C. Taking boron ions as an example, by implanting boron ions in multiple stages with different implantation energies and doses, conditions were found under which the surface density of the impurity element in the depth direction of the gallium nitride semiconductor substrate becomes approximately uniform. Specifically, as shown in Fig. 2C, a protective SiO2 film (50 nm thick) was formed on the surface of the gallium nitride semiconductor substrate, and a resist mask with a thickness of 3 μm was formed on top of the SiO2 film. As shown in Fig. 4, ion implantation was performed in seven stages. First, 3.2 × 10 12 cm -2 The implantation energy is then gradually decreased until the total dose reaches 1.0×10 13 cm -2After the ion implantation, the SiO2 film was left deposited and then heat-treated in a nitrogen gas atmosphere at 800°C for 30 minutes. A boron profile in the depth direction was obtained by secondary ion mass spectrometry (SIMS analysis), and it was found that boron was distributed at a uniform concentration up to a depth of 0.7 μm, and that the concentration gradually decreased with depth beyond that, and was distributed to a depth of at least 1.5 μm. As a result, it was confirmed that boron was distributed throughout the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14, and reached the n-type layer 12.

[0044] FIG. 5 is a diagram showing the relationship between the breakdown voltage of the semiconductor device according to the embodiment and the total dose of implanted boron, in which the breakdown voltage of the pn diode of the semiconductor device 10 according to the present embodiment was measured against the total dose.

[0045] Referring to FIG. 5, the total dose of boron ions was 3×10 12 cm -2 ~3×10 13 cm -2 It was found that the pn diode with this structure had a maximum breakdown voltage of 1300 V, which was 100 V to 600 V higher than the comparative example in which boron ions were not implanted. This confirmed the effect of improving the breakdown voltage by implanting impurity element ions into the semiconductor device 10 to form the impurity element implanted region 20.

[0046] 6 is a diagram showing a breakdown voltage of a semiconductor device according to an embodiment of the present invention, which is obtained by simulation. The layer structure of the semiconductor device 10 having the mesa structure shown in FIG. 1 is simplified, and the n-type layer has a thickness of 10 μm and a donor concentration of 0.8×10 16 cm -3 The first p-type layer 13 and the second p-type layer 14 are formed to a thickness of 1 μm and an acceptor concentration of 2×10 18 cm -3 In the impurity element implantation region 20 of the electric field relaxation region 32, the acceptor surface density is increased to N A cm -2 So, it is 0.5 × 10 13 cm -2~5×10 13 cm -2 In the simulation, the Poisson equation was numerically solved for a two-dimensional model structure corresponding to the above structure, and the impact ionization coefficient from the literature (IEDM, T. Maeda et.al, Tech. Dig. 2019, pp. 4.2.1 to 4.2.4) was applied to calculate the breakdown voltage.

[0047] Referring to Figure 6, when the acceptor surface density is 0.5 × 10 13 cm -2 As the temperature increases, the breakdown voltage increases from 900V to 1.0×10 13 cm -2 The breakdown voltage reached a maximum value of 1320 V at the acceptor areal density (1.0×10 13 cm -2 ) is the donor areal density of the n-type layer, 0.8×10 13 cm -2 It was found that this is the condition where the acceptor areal density in the impurity element implanted region is nearly equal to the donor areal density in the n-type layer.

[0048] 7A and 7B are distribution diagrams of equipotential surfaces when an avalanche occurs in a semiconductor device. FIG. 7A shows the distribution diagram of equipotential surfaces when the acceptor surface density shown in FIG. 13 cm -27A and 7B are distribution diagrams of equipotential surfaces when the semiconductor device of FIG. 7A shows a breakdown voltage of 1320V, and FIG. 7B is a distribution diagram of equipotential surfaces when the semiconductor device of FIG. 7A shows a breakdown voltage of 750V in an example where boron ions are not implanted, that is, boron is not implanted in the electric field relaxation region 32. FIGS. 7A and 7B are obtained by simulation. The potential distribution at the moment when the voltage applied between the cathode electrode 18 and the anode electrode 16 reaches the breakdown voltage and the avalanche current starts to flow. The horizontal axis is the distance X (μm) from the center of the pn diode, and the vertical axis is the depth from the surface of the second p-type layer 14. For convenience of illustration, the first p-type layer 13 and the second p-type layer 14 are shown as one layer, and the semiconductor substrate 11 and the n-type layer 12 are shown as one layer. The equipotential surfaces in FIGS. 7A and 7B are shown every 70V.

[0049] Referring to FIG. 7A, when the acceptor surface density is 1.0×10 13 cm -2 It can be seen that in this semiconductor device, equipotential surfaces spread at equal intervals in the direction of isolation region 33 on the surface of the p-type layer in electric field relaxation region 32, suppressing electric field concentration. The distribution of these equipotential surfaces is considered to be close to the distribution when the total dose is optimized in electric field relaxation region 32 and the breakdown voltage is maximized.

[0050] 7B, in the example in which boron ions are not implanted into the electric field relaxation region 32, no equipotential surface appears on the surface of the p-type layer of the electric field relaxation region 32, and the equipotential surface narrows near the mesa edge, causing electric field concentration. This is thought to be the reason why the breakdown voltage is reduced to 750V.

[0051] According to the simulation results of Figures 6 and 7A-B above, a mechanism was confirmed in which boron implantation into the p-type layer of the electric field relaxation region 32 reduces the acceptor concentration (and acceptor surface density) of the p-type layer, thereby improving the breakdown voltage of the pn termination structure. EXAMPLES

[0052] The semiconductor device of Example 1 is a vertical pn diode element, and specifically, differs from the semiconductor device according to the embodiment shown in FIG. 1 in the structure of the impurity element implanted region in the electric field relaxation region.

[0053] 8A-B are diagrams showing the configuration of the semiconductor device of Example 1, where FIG. 8A is a cross-sectional view and FIG. 8B is a plan view. In FIG. 8B, the range of the impurity element implantation region of the gallium nitride semiconductor layer below the protective film is indicated by a broken line. With reference to FIGS. 8A and 8B, in the semiconductor device of Example 1, a pn diode is formed in the element region 31, and an anode electrode 16 having a diameter of 200 μm that makes ohmic contact with the second p-type layer 14 is formed in the center of the element region 31 when viewed from above. A cathode electrode 18 is formed on the back surface of the semiconductor substrate 11. The semiconductor substrate 11 is a gallium nitride substrate, and the front surface side is a Ga(0001) plane, a thickness of 350 μm, and an n+ crystal doped with Si. The Si concentration is 1×10 18 cm -3 but may be higher.

[0054] An n-type layer 12 made of gallium nitride formed by epitaxial growth using the MOCVD method, a first p-type layer 13, and a second p-type layer 14 are formed in this order on a semiconductor substrate 11. The n-type layer 12 has a thickness of 10 μm and is doped with Si. The Si concentration is 1.2×10 16 cm -3 At this Si concentration, a breakdown voltage exceeding 1300 V can be obtained. 16 cm -3 By setting it lower than this, a higher breakdown voltage can be obtained.

[0055] The first p-type layer 13 has a thickness of 1 μm and is doped with Mg. The Mg concentration is 1.5×10 18 cm -3 Although this thickness and Mg concentration are functionally effective, if the Mg concentration can be sufficiently controlled to allow the first p-type layer 13 to be epitaxially grown, the Mg concentration should be lower, specifically, 1×10 18 cm -3Setting the value as below is preferable in that the electric field relaxation in the electric field relaxation region 32 becomes significant.

[0056] The second p-type layer 14 has a thickness of 50 nm and is doped with Mg. The Mg concentration is 1×10 20 cm -3 It should be noted that thickness and Mg concentration other than those described above are also applicable as long as the conditions result in low ohmic resistance with the anode electrode 16.

[0057] The anode electrode 16 is a laminated film in which a Ni film and an Au film are laminated by a sputtering method on the second p-type layer 14. This allows the anode electrode 16 to make ohmic contact with the second p-type layer 14. The cathode electrode 18 is a laminated film in which a Ti film and an Al film are laminated on the back surface of the gallium nitride semiconductor substrate 11.

[0058] In the electric field relaxation region 32 surrounding the element region 31 in the first embodiment, boron ions are implanted into at least the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14, forming an inner implantation region 41 close to the element region 31 and an outer implantation region 42 far from the element region, which have different boron concentrations. The total dose of boron in the outer implantation region 42 is greater than that in the inner implantation region 41, and is 3×10 12 cm -2 , 1×10 13 cm -2 The distribution of the boron concentration in the depth direction of the inner implantation region 41 and the outer implantation region 42 is, in detail, approximately uniform from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (the interface between the first p-type layer 13 and the n-type layer 12), and then rapidly decreases from the interface into the n-type layer 12.

[0059] Fig. 9 is a diagram showing the conditions of multistage ion implantation of the semiconductor device of Example 1. Referring to Fig. 9 together with Fig. 8, the multistage implantation of boron ions is performed by the method and under the conditions described in Fig. 2C, but the first multistage ion implantation results in a total dose of 3 × 10 in the inner implantation region 41, the outer implantation region 42, and the impurity element implantation region 43 of the isolation region 33. 12 cm -2Then, the surfaces of the element region 31 and the inner implantation region 41 are covered with a resist film having a thickness of 3 μm, and a second multi-stage ion implantation is performed to implant the outer implantation region 42 and the impurity element implantation region 43 of the isolation region 33 with a total dose of 7×10 12 cm -2 The total dose of boron ions in the first and second implants in the same region is 1×10 13 cm -2 become.

[0060] The width of the inner injection region 41 and the outer injection region 42 in the in-plane direction of the main surface is 10 μm. The width of the inner injection region 41 and the outer injection region 42 is preferably longer, and is preferably 10 μm or more and 50 μm or less in terms of more reliably performing electric field relaxation.

[0061] In the isolation region 33, a mesa groove 22 is formed by removing the entire first p-type layer 13 and the second p-type layer 14, and the n-type layer 12 is exposed on the surface of the mesa groove 22. Boron ions are implanted into the n-type layer 12 to form an impurity element implanted region 43. The boron concentration in the impurity element implanted region 43 is 7×10 12 cm -2 The mesa groove 22 has a depth of 2.5 μm. The depth of the mesa groove 22 may be any depth that completely removes the first p-type layer 13 and the second p-type layer 14, and a deeper depth is preferable in terms of electric field relaxation. The width of the mesa groove 22 is 20 μm, but a width of 50 μm or more is preferable in terms of electric field relaxation.

[0062] The protective film 15 covers the surface of the gallium nitride crystal layer. Specifically, the protective film 15 covers the surface of the second p-type layer 14 and the surface of the n-type layer 12 except for the anode electrode 16. The protective film 15 is a SiO2 film having a thickness of 1 μm formed by a CVD method.

[0063] In FIG. 8, the shape of the mesa structure in plan view is circular, but it may be oval, hexagonal, or any other desired shape. EXAMPLES

[0064] The semiconductor device of Example 2 is a vertical pn diode element, and has a different termination structure from the vertical pn diode element of Example 1. Specifically, the structure of the impurity element implanted region in the electric field relaxation region is different, but otherwise it is similar to Example 1.

[0065] 10 is a cross-sectional view showing the configuration of a semiconductor device of Example 2. Referring to FIG. 10, in a semiconductor device 50 of Example 2, impurity element implanted regions 51 to 53 implanted with boron are formed in an electric field relaxation region 32 so as to surround an element region 31. The semiconductor device 50 has The impurity element implanted regions 51 to 53 are formed in an annular shape in plan view.

[0066] The impurity element implanted regions 51 to 53 are formed by implanting boron ions into the second p-type layer 14 and the first p-type layer 13 by multi-stage ion implantation at least from the surface of the second p-type layer 14 in the depth direction. The impurity element implanted regions 51 to 53 each have a total dose of 1×10 13 cm -2 The distribution of the boron concentration in the impurity element implanted regions 51 to 53 in the depth direction is, in detail, approximately uniform from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (the interface between the first p-type layer 13 and the n-type layer 12), and then rapidly decreases from the interface into the n-type layer 12.

[0067] The width of each of the impurity element implanted regions 51 to 53 in the in-plane direction of the main surface is 10 μm. The width of the impurity element implanted regions 51 to 53 is preferably 5 μm or more and 50 μm or less in terms of more reliable electric field relaxation. The widths of the impurity element implanted regions 51 to 53 may be different from each other. By providing the impurity element implanted regions 51 to 53 in the electric field relaxation region 32 so as to surround the element region 31 in multiple layers, it is possible to reduce or avoid the risk of local electric field concentration due to shape abnormalities of the semiconductor device 50 caused by the manufacturing process. In the second embodiment, three impurity element implanted regions 51 to 53 are provided, but two or four or more may be provided. EXAMPLES

[0068] The semiconductor device of Example 3 is a vertical pn diode element, and is similar to the embodiments except that the termination structure is different from that of the vertical pn diode elements of Examples 1 and 2, specifically, the structure of the impurity element implantation region in the electric field relaxation region is different. Fig. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 3. Referring to Fig. 11, in a semiconductor device 80 of Example 3, impurity element implanted regions 81-85 implanted with boron are formed in an electric field relaxation region 32 so as to surround an element region 31 in an annular shape. The impurity element implantation regions 81-85 are formed by implanting boron ions in multiple stages at least from the surface of the second p-type layer 14 in the depth direction into the second p-type layer 14 and the first p-type layer 13 under the same conditions as in the embodiment. The resist mask used in this ion implantation has four parallel rows of mask regions patterned in an annular shape in the region corresponding to the electric field relaxation region 32, and the impurity element implantation regions 81-85 are formed spaced apart from each other. In the example of FIG. 11, the mask regions with a width of 2 μm are arranged at positions 6 μm, 5 μm, 4 μm, and 3 μm from the mesa edge 21, and the widths of the impurity element implantation regions are designed to decrease in order from the outside to the inside. The dose of boron ions in the impurity element implantation regions 81-85 is 1×10 as in the embodiment. 13 cm -2 and the dose of boron ions in the mask regions sandwiched between the implantation regions is smaller than this. Therefore, the mask regions are more sparsely arranged toward the outside of the electric field relaxation region 32, so the effective boron concentration is high, and the mask regions are more densely arranged toward the inside of the electric field relaxation region 32, so the effective boron concentration is low. The relationship of the boron concentration depending on the position in the electric field relaxation region is similar to that in the first embodiment, but the difference in this embodiment is that the boron concentration changes gradually. Therefore, when a reverse bias is applied, the depletion layer spreads more in the electric field relaxation region 32, making the electric field relaxation more effective. That is, in the semiconductor device of this embodiment, the widths of the partial regions become wider from the side closer to the element region to the side farther from the element region. Of the impurity implanted regions 81 to 85 (plurality of partial regions), the impurity implanted region 85 (partial region) located farthest from the element region may have a width of 1.5 μm to 8 μm, preferably 1.5 μm to 5 μm, and more preferably 1.5 μm to 3 μm. The width of the impurity implanted region 85 farthest from the element region may be 1.5 to 4 times, preferably 1.5 to 3 times, and more preferably 1.5 to 2 times that of the impurity implanted region 81 closest to the element region. The intervals between the impurity implanted regions 81 to 85 may be the same or different. Some of the intervals may be the same and other intervals may be different. Next, the configuration of the semiconductor device X having the mesa structure shown in FIG. 11 was simplified, and the breakdown voltage was obtained by simulation in the same manner as in the embodiment. As in the embodiment, the n-type layer was made to have a thickness of 10 μm and a donor concentration of 0.8×10 16 cm -3 The first p-type layer 13 and the second p-type layer 14 are formed to a thickness of 1 μm and an acceptor concentration of 2×10 18 cm -3 By multi-stage ion implantation of boron ions, the acceptor surface density of the impurity element implanted region was increased to 0.3 × 10 13 cm -2 ~1.5×10 13 cm -2 The mask regions between the impurity element implantation regions have an acceptor surface density N A =2.5×10 13 cm -2 12 shows the breakdown voltage calculated for the above two-dimensional model structure as a function of the average acceptor surface density N A In contrast to the dotted line showing the results of the embodiment, the solid line showing the present embodiment shows that the maximum value of the withstand voltage increases to 1360 V and the N A This means that the breakdown voltage is less likely to change even if the acceptor concentration or thickness of the first p-type layer 13 or the dose of boron ion implantation varies, and if this technique is applied to manufacturing, it is possible to expand the process margin. This embodiment has a great practical merit because it can be realized by simply changing the mask layout without changing the process described in the embodiment. In this embodiment, five impurity element implantation regions are provided, and examples of width and interval are shown, but the number of impurity element implantation regions may be four or less, six or more, and more preferably ten or more. The width and interval are not limited to the example in FIG. EXAMPLES

[0069] The semiconductor device of Example 4 is a vertical pn diode element, and is a modified example of the semiconductor device 10 according to the embodiment shown in Fig. 1. In the semiconductor device 10, a mesa groove 22 is formed by removing the first p-type layer 13 and the second p-type layer 14 in the isolation region 33. In the semiconductor device of Example 4, a mesa groove is not formed, and the first p-type layer 13 and the second p-type layer 14 are insulated.

[0070] 13 is a cross-sectional view showing the configuration of a semiconductor device of Example 4. Referring to FIG. 13, in a semiconductor device 60 of Example 4, an impurity element implantation region 61 is formed in the isolation region 33 from the surface of the second p-type layer 14 of gallium nitride to the depth of the bottom of the second p-type layer 14 and the first p-type layer 13. In the impurity element implantation region 61, boron ions are implanted by multi-stage ion implantation with a maximum implantation energy set to 400 keV so that boron is distributed from the surface of the second p-type layer 14 to the bottom of the first p-type layer 13. This allows the second p-type layer 14 and the first p-type layer 13 to have sufficient insulation, and allows the impurity element implantation region 61 of the i-type layer to be formed.

[0071] The impurity element implantation region 20 of the electric field relaxation region 32 has a total dose of 1×10 13 cm -2 On the other hand, the impurity element implantation region 61 of the isolation region 33 has a total dose of 5×10 14 cm -2 It is set to 3×10 14 cm -2 ~3×10 15 cm -2It is preferable to set the value at 0.1 to 1 in order to suppress electric field concentration.

[0072] According to Example 4, the dry etching process for forming the mesa groove 22 of the semiconductor device according to the embodiment shown in FIG. 2B is not required. This makes it possible to avoid damage to the surface portion of the gallium nitride crystal layer that is likely to occur around the mesa edge 21, and suppresses electric field concentration caused by such a manufacturing process. As a result, the semiconductor device 60 according to Example 4 can more effectively improve the breakdown voltage in addition to the effect of improving the breakdown voltage of the impurity element implanted region 20 of the electric field relaxation region 32 of the semiconductor device 10 according to the embodiment shown in FIG. 1. EXAMPLES

[0073] The semiconductor device of the fifth embodiment is a semiconductor device in which a trench MOS transistor is formed in an element region, and an electric field relaxation region and an isolation region are formed in the same manner as in the fourth embodiment shown in FIG.

[0074] Fig. 14 is a cross-sectional view showing the configuration of a semiconductor device of Example 5. Referring to Fig. 14, in a semiconductor device 70, similar to the semiconductor device 10 according to the embodiment shown in Fig. 1 and Examples 1 to 3, an n-type layer 12 made of gallium nitride formed by epitaxial growth using an MOCVD method, a first p-type layer 13, and a second p-type layer 14 are formed in this order on a semiconductor substrate 11.

[0075] In the element region 31, an n-channel MOS transistor is formed, in which a drift region is formed in the n-type layer 12 and a body region is formed in the second p-type layer 14. In order for the n-channel MOS transistor to perform a normally-off operation with a threshold value of +3 V or more, the impurity concentration of the first p-type layer 13 is designed according to the type and thickness of the gate insulating film and the crystal plane of the gallium nitride. 17 cm -3 5×10 or more 18 cm -3 It is preferable to set it to .

[0076] In the element region 31, a plurality of stripe-shaped trenches 71 are formed, which are arranged parallel to each other and reach from the surface of the second p-type layer 14 to the n-type layer 12. The width of each trench 71 is 2 μm. A gate insulating film 72 made of a SiO2 film is formed on the sidewall and bottom surface of the trench 71, and a gate electrode 73 is formed inside the gate insulating film 72. The gate electrode 73 may be made of, for example, a TiN material. The ends of the gate electrodes 73 in the longitudinal direction (the direction perpendicular to the paper surface in FIG. 14) are connected to each other so that the gate electrodes of the entire element are at the same potential.

[0077] An n+ gallium nitride region 74 is formed in the second p-type layer 14 and the first p-type layer 13 on the surface of the gallium nitride layer on both sides of each trench 71. The n+ gallium nitride region 74 is formed by implanting Si ions and performing activation heat treatment. A source electrode 75 is in ohmic contact with the surface of the n+ gallium nitride region 74. The source electrode 75 is a film formed by laminating a Ti film and an Al film in this order.

[0078] The anode electrode 76 is in ohmic contact with the surface of the second p-type layer 14 between the trenches 71. The anode electrode 76 is in contact with the source electrode 75 so as to have the same potential as the source electrode 75. A Ni film is used for the anode electrode 76. The cathode electrode 18 formed on the back surface of the semiconductor substrate 11 also serves as the drain electrode.

[0079] In the semiconductor device 70 of the fifth embodiment, the isolation region 33 and the electric field relaxation region 32 are configured in the same manner as in the fourth embodiment. In the isolation region 33, in the impurity element implanted region 61, boron is distributed from the surface of the second p-type layer 14 to the bottom of the first p-type layer 13, and boron ions are implanted by multi-stage ion implantation with a maximum implantation energy set to 400 keV so that the layer becomes sufficiently i-type. The impurity element implanted region 20 of the electric field relaxation region 32 is formed to the same depth as in the fourth embodiment. The total dose of the impurity element implanted region 20 is 1×10 13 cm -2 The impurity element implantation region 61 of the isolation region 33 has a total dose of 5×10 14 cm -2However, as in Example 4, it is set to 3 × 10 14 cm -2 ~3×10 15 cm -2 It is preferable to set the value at 0.1 to 1 in order to suppress electric field concentration.

[0080] In the semiconductor device 70, when a positive bias is applied to the gate electrode 73, the trench MOS transistor is turned on and an on-current flows between the drain electrode (cathode electrode 18) and the source electrode 75. When 0 (zero) V or a negative bias is applied to the gate electrode 73, the trench MOS transistor is turned off, and when a reverse bias is applied between the drain electrode (cathode electrode 18) and the source electrode 75, a depletion layer spreads in the n-type layer 12 and the device exhibits voltage resistance characteristics.

[0081] In a trench MOS transistor formed in an epitaxial crystal layer of gallium nitride in the element region 31, the impurity concentration of the p-type layer required for a normally-off design is usually about 1×10 18 cm -3 On the other hand, in the electric field relaxation region 32, in the optimal design, the impurity concentration of the p-type layer is approximately 1×10 17 cm -3 The impurity concentration in the first p-type layer 13 of the electric field relaxation region 32 is 1 / 10 of that in the element region. Therefore, it is difficult to achieve both impurity concentrations in both regions by epitaxial growth of the p-type layer once. In the fifth embodiment, boron is implanted into the first p-type layer 13 of the electric field relaxation region 32 to form an impurity element implanted region 20 having a lower impurity concentration than that of the first p-type layer 13 of the element region, thereby suppressing or avoiding electric field concentration and optimizing the electric field design.

[0082] In the fifth embodiment, a trench MOS transistor is formed in the element region 31, but the present invention is not limited to this. For example, a planar MOS transistor or a high electron mobility transistor (HEMT) may be formed.

[0083] Although the preferred embodiment of the present invention has been described above in detail, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the present invention described in the claims. In Examples 1 to 4, a gallium nitride crystal layer epitaxially grown on a gallium nitride substrate is used as the semiconductor epitaxial layer, but a group III nitride semiconductor epitaxial layer in which a part of gallium is replaced with aluminum (Al) or indium (In) may be used. Also, instead of a gallium nitride substrate, a group III nitride semiconductor crystal layer epitaxially grown on a substrate such as a silicon carbide (SiC) substrate or a sapphire substrate may be applied. As described above, in the present disclosure, it is particularly preferable to use a group III nitride semiconductor, but other wide band gap semiconductors such as SiC and Ga2O3 may also be applied. Also, the embodiment and Examples 1 to 4 may be combined with each other, and for example, the configurations of the impurity element implanted regions in the electric field relaxation regions of Examples 1 and 2 may be applied to the impurity element implanted regions in the electric field relaxation regions of Examples 4 and 4, respectively. [Industrial Applicability]

[0084] The breakdown voltage of the semiconductor device can be improved. [Explanation of symbols]

[0085] 10, 40, 50, 60, 70 Semiconductor device 11 Semiconductor substrate 12 n-type layer 13 1st p-type layer 14 2nd p-type layer 16 Anode electrode 18 Cathode Electrode 20, 51~53, 61 Impurity element implantation region 22 Mesa Groove 31 Element Area 32 Electric field relaxation region 33 Isolation Area 41 Inner injection area 42 Outer injection area

Claims

1. an element region having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer and having a higher acceptor concentration than the first p-type layer, and an electric field relaxation region surrounding the periphery of the element region; the electric field relaxation region has a region in the first p-type layer and the second p-type layer, the region containing an impurity element that inactivates a part of the acceptors in the first p-type layer and the second p-type layer; The impurity element is boron (B).

2. 2. The semiconductor device according to claim 1, wherein in the electric field relaxation region, a plurality of partial regions having different impurity element concentrations are continuously formed from a side closer to the element region to a side farther from the element region, and the impurity element concentration is higher in the partial region farther from the element region than in the partial region closer to the element region.

3. 2. The semiconductor device according to claim 1, wherein said region containing said impurity element in said electric field relaxation region is formed as a plurality of partial regions spaced apart from one another so as to surround said element region from a side closer to said element region to a side farther from said element region.

4. 4. The semiconductor device according to claim 3, wherein the widths of said plurality of partial regions become wider from the side closer to said element region to the side farther from said element region.

5. Further comprising an isolation region surrounding the electric field relaxation region, 5. The semiconductor device according to claim 1, wherein said isolation region has a mesa structure reaching said n-type layer, and has a region containing said impurity element from the surface of said n-type layer to the inside.

6. Further comprising an isolation region surrounding the electric field relaxation region, 5. The semiconductor device according to claim 1, wherein the first and second p-type layers extend in the isolation region, and the first and second p-type layers have their acceptors inactivated by the impurity element to form an insulating region.

7. the semiconductor device constitutes a vertical diode, 5. The semiconductor device according to claim 1, wherein in said element region, an anode electrode is formed on said second p-type layer, and a cathode electrode is formed on a back surface side of said n-type layer.

8. the semiconductor device constitutes a vertical MOS power transistor, 5. The semiconductor device according to claim 1, further comprising a source electrode and a gate electrode in said element region, a drift region in said n-type layer, and a body region in said first p-type layer.

9. forming an n-type layer on a semiconductor substrate by epitaxial growth, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer and having a higher acceptor concentration than the first p-type layer; activating acceptors in the first and second p-type layers; an implantation step of implanting impurity element ions into the first and second p-type layers in an electric field relaxation region surrounding an element region by a multistage ion implantation method, the impurity ions inactivating a part of the acceptors in the first and second p-type layers; forming an electrode on a surface of the second p-type layer in the element region, The method for manufacturing a semiconductor device, wherein the impurity element ions are boron (B) ions.

10. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising, after the implantation step, another implantation step of implanting impurity element ions into the first and second p-type layers by a multistage ion implantation method in a second partial region that is farther away than a first partial region close to the element region in the electric field relaxation region.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in said implanting step, said impurity element ions are implanted so as to form a plurality of partial regions surrounding said element region from a side closer to said element region to a side farther from said element region.

12. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, further comprising the step of etching the first and second p-type layers in the region surrounding the electric field relaxation region to expose the n-type layer and form an isolation region after the implantation step.

13. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, further comprising, after the implantation step, another implantation step of inactivating an acceptor by implanting the impurity element ions into the first and second p-type layers by a multistage ion implantation method in an isolation region surrounding the electric field relaxation region.

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