Field effect transistor and its manufacturing method

Abstract

To mitigate current concentration in a field effect transistor that has trench type gate electrodes in high density.SOLUTION: A field effect transistor has a semiconductor substrate having a plurality of trenches provided on an upper surface. The plurality of trenches extend long in a first direction on the upper surface, and are arranged by leaving intervals in a direction orthogonal to the first direction. A plurality of connection regions are arranged under each body region, extend long in a second direction intersecting with the first direction and are arranged by leaving intervals in a direction orthogonal to the second direction when the semiconductor substrate is seen from an upper side. A plurality of electric field relaxation regions are arranged under each of the connection regions and each of the trenches, extend long in a third direction intersecting with the first direction and the second direction and are arranged by leaving intervals in a direction orthogonal to the third direction when the semiconductor substrate is seen from an upper side.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a field effect transistor and a method for manufacturing the same.

[0002] The field effect transistor disclosed in Patent Document 1 has a trench-type gate electrode. The field effect transistor in Patent Document 1 has a plurality of body regions, a plurality of connection regions, and a plurality of electric field relaxation regions. Each body region is a p-type region and is arranged in an inter-trench semiconductor region located between a plurality of trenches. Each body region is in contact with a gate insulating film on the side of the trench. An n-type drift region is in contact with each body region from below. When the field effect transistor is turned on, a channel is formed in a range adjacent to the gate insulating film of each body region, and the channel is connected to the drift region. Each connection region is a p-type region protruding downward from the corresponding body region. Each connection region extends along the trench. Each connection region is arranged at a position away from each trench. Each electric field relaxation region is a p-type region arranged below each connection region. Each electric field relaxation region is arranged below the gate electrode and extends linearly in a direction intersecting the gate electrode. Each electric field relaxation region is connected to the body region via the connection region. This stabilizes the potential of each electric field relaxation region.

[0003] When the field effect transistor is turned off, a depletion layer spreads from each electric field relaxation region to its surroundings. The depletion layer spreading from each electric field relaxation region relaxes the electric field applied to the gate insulating film near the bottom end of each trench. Therefore, this field effect transistor has a high breakdown voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-046908 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, trench-type gate electrodes are formed at a higher density in order to improve channel density. That is, the interval between trench-type gate electrodes is narrowed. When the interval between trench-type gate electrodes is narrowed to the limit of processing accuracy, each connection region 136 contacts the trench (i.e., the gate insulating film) as shown in Figs. 15 and 16. In Figs. 15 and 16, reference numeral 134 denotes a body region, reference numeral 138 denotes an electric field relaxation region, and reference numeral 140 denotes a drift region. In the configuration of Figs. 15 and 16, in the inter-trench semiconductor region in which the connection region is provided, the channel formed in the body region is not connected to the drift region. That is, no current flows in the range in which the inter-trench semiconductor region is provided. In Figs. 15 and 16, the connection region is provided only in a part of the inter-trench semiconductor region in order to secure the range in which the current flows. In the field effect transistor of Figs. 15 and 16, in the on state, no current flows in the entire inter-trench semiconductor region in which the connection region is provided. For this reason, the current is concentrated in the inter-trench semiconductor region adjacent to the inter-trench semiconductor region in which the connection region is provided. 15 and 16 have a low allowable current capacity. This specification proposes a technique for alleviating current concentration in a field effect transistor having trench-type gate electrodes at high density. [Means for solving the problem]

[0006] The field effect transistor disclosed in this specification includes a semiconductor substrate having a plurality of trenches on its upper surface, a gate insulating film and a gate electrode disposed in each of the trenches, and a source electrode covering the upper surface of the semiconductor substrate. The plurality of trenches extend long in a first direction on the upper surface and are disposed at intervals in a direction perpendicular to the first direction. The semiconductor substrate includes a plurality of inter-trench semiconductor regions located between the plurality of trenches. Each of the inter-trench semiconductor regions includes a source region, a contact region, and a body region. The source region is an n-type region in contact with the source electrode and in contact with the gate insulating film. The contact region is a p-type region in contact with the source electrode. The body region is a p-type region in contact with the contact region and the source region from below, in contact with the gate insulating film below the source region, and having a p-type impurity concentration lower than that of the contact region. The semiconductor substrate includes a plurality of p-type connection regions, a plurality of p-type electric field relaxation regions, and an n-type drift region. The plurality of connection regions are disposed below the body regions, extend long in a second direction intersecting the first direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the second direction. The connection regions are connected to the body regions at their intersections with the body regions. The plurality of electric field relief regions are disposed below the connection regions and the trenches, extend long in a third direction intersecting the first direction and the second direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the third direction. The electric field relief regions are connected to the connection regions at their intersections with the connection regions. The drift region is distributed across the gaps between the connection regions, the gaps between the electric field relief regions, and the lower parts of the electric field relief regions, contacts the body regions from below, and contacts the gate insulating film below the body regions.

[0007] Each electric field relief region may partially overlap with each connection region and each trench in the depth direction. In other words, the above phrase "the electric field relief regions are disposed below each connection region and each trench" means that at least a portion of the electric field relief regions is disposed below each connection region, and at least a portion of the electric field relief regions is disposed below each trench.

[0008] In this field effect transistor, each connection region extends along a second direction intersecting both the first direction in which each trench extends and the third direction in which each electric field relaxation region extends. Also, each connection region is connected to each electric field relaxation region at an intersection with each electric field relaxation region. Also, each connection region is connected to each body region at an intersection with each body region. Therefore, each electric field relaxation region is connected to each body region via each connection region. This stabilizes the potential of each electric field relaxation region. Also, when the field effect transistor is turned on, at the intersection between each connection region and each trench, the channel is not connected to the drift region and no current flows. Since each electric field relaxation region extends along a direction intersecting the trench, the intersection between each electric field relaxation region and the trench (i.e., the portion where no current flows) is distributed and arranged in a plurality of trenches. Therefore, it is possible to suppress the current from concentrating in a specific inter-trench semiconductor region. In this way, this field effect transistor can suppress the current concentration.

[0009] This specification also proposes a method for manufacturing the above-mentioned field effect transistor, which includes a step of implanting a p-type impurity into the contact region and the connection region through a common mask.

[0010] According to this manufacturing method, the field effect transistor can be manufactured efficiently. [Brief description of the drawings]

[0011] [Figure 1]1A to 1C are cross-sectional perspective views of a MOSFET according to an embodiment (a view showing an upper surface of a semiconductor substrate, a cross section along an xz plane, and a cross section along a yz plane). [Diagram 2] 2 is a plan view showing the upper surface of a semiconductor substrate of the MOSFET according to the embodiment; [Diagram 3] 3 is a cross-sectional view taken along the xz plane of the MOSFET according to the embodiment (a cross-sectional view taken along line III-III in FIG. 2). [Figure 4] 4 is a cross-sectional view taken along the xz plane of the MOSFET according to the embodiment (a cross-sectional view taken along line IV-IV in FIG. 2). [Diagram 5] 3 is a cross-sectional view taken along the yz plane of the MOSFET according to the embodiment (a cross-sectional view taken along the line VV in FIG. 2). [Figure 6] 6 is a cross-sectional view of the MOSFET according to the embodiment taken along the yz plane (a cross-sectional view taken along line VI-VI in FIG. 2). [Figure 7] 3A and 3B are cross-sectional perspective views of a MOSFET according to an embodiment (a view showing a cross section along an xy plane, a cross section along an xz plane, and a cross section along a yz plane in a range including a connection region 36). [Figure 8] 3 is a plan view showing the arrangement of trenches 14, connection regions 36, and electric field reduction regions 38 when the semiconductor substrate is viewed from above. FIG. [Figure 9] FIG. 4 is a diagram showing channels and current paths in the cross section of FIG. 3. [Figure 10] FIG. 3 is a plan view of a MOSFET of a comparative example, which corresponds to FIG. 2 . [Figure 11] 3A to 3C are explanatory views of a method for manufacturing a MOSFET according to an embodiment. [Figure 12] FIG. 9 is a plan view of a MOSFET according to a first modification, corresponding to FIG. 8; [Figure 13] 9 is a plan view of a MOSFET according to a second modification, corresponding to FIG. 8; FIG. [Figure 14] 10 is a cross-sectional view of a MOSFET according to a third modification, corresponding to FIG. 3; [Figure 15] FIG. 4 is a cross-sectional view of a MOSFET according to a comparative example. [Figure 16] FIG. 2 is a plan view of a MOSFET according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In one example field effect transistor disclosed in this specification, each of the contact regions may extend along the second direction while overlapping with a corresponding one of the connection regions when viewed from above the semiconductor substrate.

[0013] When the field effect transistor is turned on, the channel is not connected to the source electrode at the intersections of each contact region and each trench, and no current flows. Since each contact region overlaps with the corresponding connection region, the areas where no current flows (i.e., the intersections of each connection region and trench, and the intersections of each contact region and trench) overlap, and the area of ​​the areas where no current flows can be reduced. Therefore, the on-resistance of the field effect transistor can be reduced.

[0014] In the field effect transistor according to an example disclosed herein, the second direction may obliquely intersect with the first direction.

[0015] According to this configuration, the intersections between the connection regions and the trenches (i.e., the portions through which no current flows) are distributed along the longitudinal direction (i.e., the first direction) of the trenches, thereby making it possible to more effectively reduce current concentration.

[0016] In the example field effect transistor disclosed in this specification, a side surface of each of the connection regions may extend linearly along the second direction.

[0017] This configuration stabilizes the characteristics of the field effect transistor.

[0018] The MOSFET 10 (metal-oxide-semiconductor field effect transistor) of the embodiment shown in FIG. 1 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (one direction perpendicular to the z direction) is referred to as the x direction, and the direction perpendicular to the x direction and the z direction is referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may be made of other semiconductor materials such as silicon and gallium nitride. In FIG. 1, the source electrode 22 provided on the upper surface 12a of the semiconductor substrate 12 is not shown.

[0019] 1 and 2, a plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. The plurality of trenches 14 extend elongately in the y direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x direction.

[0020] As shown in Figures 1 to 5, the inner surface (i.e., the side surface and bottom surface) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in Figures 3 to 5, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.

[0021] As shown in FIGS. 3 to 6, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 contacts the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 contacts the entire lower surface 12b of the semiconductor substrate 12.

[0022] 1, 3, and 4, the semiconductor substrate 12 has inter-trench semiconductor regions 26 sandwiched between the trenches 14. Each inter-trench semiconductor region 26 extends longitudinally in the y direction along the trenches 14. In each inter-trench semiconductor region 26, a source region 30, a contact region 32, and a body region 34 are provided.

[0023] As shown in FIGS. 1 to 4, a plurality of source regions 30 and a plurality of contact regions 32 are provided in a range including the upper surface 12a of the semiconductor substrate 12. Each source region 30 is an n-type region and has a high n-type impurity concentration. Each contact region 32 is a p-type region and has a high p-type impurity concentration. As shown in FIGS. 3 and 4, each source region 30 and each contact region 32 are in ohmic contact with the source electrode 22. As shown in FIGS. 1 and 2, each source region 30 and each contact region 32 has a shape elongated in a direction 100 that obliquely intersects with the longitudinal direction of each trench 14 (i.e., the y direction). The plurality of source regions 30 and the plurality of contact regions 32 are alternately arranged along a direction perpendicular to the direction 100. That is, the plurality of contact regions 32 extend elongatedly in a direction 100 that intersects with the y direction when the semiconductor substrate 12 is viewed from above as shown in FIG. 2, and are arranged at intervals in a direction perpendicular to the direction 100. 2, the multiple source regions 30 extend long in a direction 100 intersecting the y direction and are arranged at intervals in a direction perpendicular to the direction 100. The source regions 30 are arranged between the multiple contact regions 32, and the contact regions 32 are arranged between the multiple source regions 30. As shown in FIGS. 1 and 3, each source region 30 contacts the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each contact region 32 contacts the gate insulating film 16 at the uppermost part of the side surface of the trench 14.

[0024] Each body region 34 is a p-type region and has a lower p-type impurity concentration than the contact region 32. As shown in FIGS. 1, 3, 4, and 6, each body region 34 is disposed below the source regions 30 and the contact regions 32. In each inter-trench semiconductor region 26, each body region 34 is distributed over the entire area in the x and y directions. Each body region 34 contacts the source regions 30 and the contact regions 32 from below. Each body region 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source regions 30 and the contact regions 32.

[0025] As shown in FIGS. 3 to 6, the semiconductor substrate 12 has a plurality of connection regions 36, a plurality of electric field reduction regions 38, a drift region 40, a buffer region 42, and a drain region 44.

[0026] The multiple connection regions 36 are p-type regions and have a higher p-type impurity concentration than the body region 34. As shown in FIGS. 1, 3 to 6, each connection region 36 is disposed below each body region 34. As shown in FIG. 7, the multiple connection regions 36 extend long in a direction 100 that crosses the y direction obliquely when the semiconductor substrate 12 is viewed from above. The multiple connection regions 36 are disposed at intervals in a direction perpendicular to the direction 100 when the semiconductor substrate 12 is viewed from above. As shown in FIGS. 1 and 3, each connection region 36 is disposed directly below the corresponding contact region 32. Therefore, each contact region 32 extends long in the direction 100 while overlapping with the corresponding connection region 36 when the semiconductor substrate 12 is viewed from above. As shown in FIGS. 3, 4, and 6, each connection region 36 is connected to each body region 34 at an intersection 35 where the connection region 36 crosses each body region 34. Each connection region 36 extends from the lower surface of each body region 34 to a position lower than the lower end of each trench 14. Each connection region 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below each body region 34 .

[0027] The electric field relaxation regions 38 are p-type regions. Each electric field relaxation region 38 has a p-type impurity concentration higher than that of each body region 34 and lower than that of each connection region 36. As shown in FIGS. 1, 3, 5 to 6, each electric field relaxation region 38 is disposed below each connection region 36. As shown in FIGS. 1 and 8, each electric field relaxation region 38 has a shape elongated in the x direction. That is, when the semiconductor substrate 12 is viewed from above, each electric field relaxation region 38 extends elongatedly in the x direction intersecting with the y direction (i.e., the longitudinal direction of the trench 14) and the direction 100 (i.e., the longitudinal direction of the connection region 36). The electric field relaxation regions 38 are disposed at intervals in the y direction perpendicular to the x direction. As shown in FIGS. 3, 5 and 6, the upper end of each electric field relaxation region 38 is disposed within a depth range overlapping with the lower end of each connection region 36. Therefore, each electric field relaxation region 38 is connected to each connection region 36 at an intersection 37 with each connection region 36. Each of the electric field relief regions 38 is connected to the source electrode 22 via each of the connection regions 36 , each of the body regions 34 , and each of the contact regions 32 .

[0028] The drift region 40 is an n-type region. As shown in FIGS. 1 and 3 to 6, the drift region 40 is distributed from a position contacting the lower surface of each body region 34 to a position below each electric field relaxation region 38. That is, the drift region 40 is distributed across the gaps 36x between each connection region 36, the gaps 38x between each electric field relaxation region 38, and the region below each electric field relaxation region 38. The drift region 40 is in contact with the lower surface of the body region 34 in the gaps 36x between each connection region 36. The drift region 40 in the gaps 36x is in contact with the gate insulating film 16 on the side surface of the trench 14 located below each body region 34 and on the bottom surface of the trench 14. The drift region 40 has a high concentration region 40a and a low concentration region 40b. The n-type impurity concentration of the high concentration region 40a is higher than the n-type impurity concentration of the low concentration region 40b. The high concentration region 40a is distributed across the gaps 36x between the connection regions 36, the gaps 38x between the electric field relaxation regions 38, and the region below the electric field relaxation regions 38. The low concentration region 40b is disposed below the high concentration region 40a. The low concentration region 40b contacts the high concentration region 40a from below.

[0029] The buffer region 42 is an n-type region and has a higher n-type impurity concentration than the low-concentration region 40b of the drift region 40. The buffer region 42 contacts the low-concentration region 40b from below.

[0030] The drain region 44 is an n-type region and has a higher n-type impurity concentration than the buffer region 42. The drain region 44 contacts the buffer region 42 from below. The drain region 44 is disposed in a range including the lower surface 12b of the semiconductor substrate 12. The drain region 44 is in ohmic contact with the drain electrode 24 at the lower surface 12b.

[0031] The MOSFET 10 is used in a state where a potential higher than that of the source electrode 22 is applied to the drain electrode 24. When a potential equal to or higher than the gate threshold is applied to each gate electrode 18, a channel 50 is formed in the body region 34 near the gate insulating film 16 as shown in FIG. 9. The source region 30 and the drift region 40 are connected by the channel 50. Therefore, as shown by an arrow 102 in FIG. 9, electrons flow from the source region 30 to the drift region 40 through the channel 50. Therefore, electrons flow from the source electrode 22 to the drain electrode 24 through the source region 30, the channel 50, the drift region 40, the buffer region 42, and the drain region 44.

[0032] When the potential of each gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel 50 disappears and the flow of electrons stops. That is, the MOSFET 10 turns off. When the channel 50 disappears, the potential of the drift region 40 rises. On the other hand, since each body region 34 is connected to the source electrode 22 via each contact region 32, the potential of each body region 34 is maintained at approximately the same potential as the source electrode 22 (i.e., a low potential). Therefore, when the channel 50 disappears, a reverse voltage is applied to the pn junction at the interface between each body region 34 and the drift region 40. Therefore, a depletion layer spreads from each body region 34 to the drift region 40. In addition, each electric field relaxation region 38 is connected to the source electrode 22 via each connection region 36, each body region 34, and each contact region 32. Therefore, the potential of each connection region 36 is also maintained at approximately the same potential as the source electrode 22 (i.e., a low potential). Therefore, when the channel 50 disappears, a reverse voltage is applied to the pn junction at the interface between each electric field relaxation region 38 and the drift region 40, and a depletion layer spreads from each electric field relaxation region 38 to the drift region 40. The depletion layer spreading from each electric field relaxation region 38 quickly depletes the drift region 40 around the bottom end of the trench 14. This suppresses electric field concentration near the bottom end of the trench 14.

[0033] 8, in the MOSFET 10 of this embodiment, the connection regions 36 extend in a direction intersecting the electric field relaxation regions 38, so that the electric field relaxation regions 38 can be reliably connected to the body regions 34 via the connection regions 36. Therefore, a depletion layer easily spreads from each electric field relaxation region 38 to the drift region 40, and electric field concentration at the bottom end of each trench 14 can be effectively suppressed.

[0034] In the MOSFET 10 of this embodiment, each connection region 36 extends in a direction intersecting with each trench 14 as shown in FIG. 8, so that electric field concentration can be suppressed when the MOSFET 10 is in an on-state. The suppression of electric field concentration will be described in detail below. As shown in FIG. 9, in the overlapping portion between the connection region 36 and the trench 14, the connection region 36 exists below the body region 34, so that the channel 50 formed in the body region 34 is not connected to the drift region 40. Therefore, in the overlapping portion between the connection region 36 and the trench 14, no current flows through the channel 50. In this embodiment, each connection region 36 extends in a direction intersecting with each trench 14 as shown in FIG. 8, so that the overlapping portions (i.e., intersections) between the connection region 36 and the trench 14 are distributed and disposed in each trench 14. That is, the entire side surface of a specific trench does not overlap with the connection region 136 as shown in FIGS. 15 and 16. If the entire side surface of a specific trench overlaps with the connection region 136 as shown in FIGS. 15 and 16, current concentrates in the channel next to the overlapping portion. In contrast, in the MOSFET 10 of this embodiment, as shown in FIG. 8, the overlapping portions (i.e., intersections) between the connection regions 36 and the trenches 14 are distributed among the trenches 14, so that the regions through which no current flows are distributed and current concentration is unlikely to occur. In particular, in this embodiment, the connection regions 36 diagonally intersect with the trenches 14, so that the overlapping portions (i.e., intersections) are distributed among the trenches 14 in the longitudinal direction. This further suppresses current concentration in the MOSFET 10 of this embodiment. As a result, the MOSFET 10 of this embodiment has a high allowable current flow.

[0035] In the MOSFET 10 of this embodiment, each contact region 32 is disposed at a position overlapping the corresponding connection region 36 when the semiconductor substrate 12 is viewed from above. This reduces the on-resistance of the MOSFET 10. The reduction in on-resistance will be described in detail below. As shown in FIG. 9, in the overlapping portion between the contact region 32 and the trench 14, the contact region 32 exists above the body region 34, so that the channel 50 formed in the body region 34 is not connected to the source region 30. Therefore, no current flows through the channel 50 in the overlapping portion between the contact region 32 and the trench 14. If the connection region 36 and the contact region 32 extend in different directions as in the MOSFET of the comparative example shown in FIG. 10, the intersection of the contact region 32 and the trench 14 (i.e., the portion where no current flows through the channel) is formed at a position different from the intersection of the connection region 36 and the trench 14 (i.e., the portion where no current flows through the channel). Therefore, the region through which the current can flow is narrow. In contrast, in the MOSFET 10 of this embodiment, the contact region 32 and the connection region 36 extend along the direction 100 while overlapping each other. Therefore, when the semiconductor substrate 12 is viewed from above, the position of the intersection between the contact region 32 and the trench 14 substantially coincides with the position of the intersection between the connection region 36 and the trench 14. This makes it possible to ensure a wide region through which a current can flow. Therefore, the MOSFET 10 of this embodiment has a low on-resistance.

[0036] In the MOSFET 10 of this embodiment, each connection region 36 crosses the trench 14 obliquely. Therefore, as shown in FIG. 8, the interval W1 between the connection regions 36 is narrower than the interval W2 between the connection regions 36 in the direction along the trench 14. When a high voltage is applied to the MOSFET 10 in the off state, a depletion layer spreads from each connection region 36 to the drift region 40 around it, and the voltage is held by the depletion layer. Since the interval W1 is narrow, the drift region 40 within the range of the interval W1 is easily depleted by the depletion layer spreading from each connection region 36. Therefore, this configuration can further improve the breakdown voltage of the MOSFET 10. Furthermore, since the interval W2 in the direction along the trench 14 is wide, a region in which a current can flow through the channel (i.e., a region of the trench 14 that does not overlap with the connection region 36) can be widely secured. Therefore, this configuration can reduce the on-resistance of the MOSFET 10. In this manner, this configuration can achieve a high breakdown voltage and a low on-resistance.

[0037] Next, a method for manufacturing the MOSFET 10 of this embodiment will be described. Note that this manufacturing method is characterized by the steps of forming the contact region 32 and the connection region 36, so only the steps of forming the contact region 32 and the connection region 36 will be described.

[0038] In the step of forming the contact region 32 and the connection region 36, as shown in FIG. 11, a mask 90 is formed on the upper surface 12a of the semiconductor substrate 12. Here, the mask 90 is formed so that an opening 92 is located above the ranges corresponding to the contact region 32 and the connection region 36. Next, p-type impurities are ion-implanted into the semiconductor substrate 12 through the mask 90. ​​Here, the ion-implantation energy is changed to implant the p-type impurities into the depth range of the connection region 36 and the depth range of the contact region 32. Then, activation annealing of the impurities is performed to form the connection region 36 and the contact region 32. In this manner, in this manufacturing method, the connection region 36 and the contact region 32 can be formed by an ion-implantation step using the common mask 90. ​​Therefore, the MOSFET 10 can be manufactured efficiently.

[0039] In the MOSFET 10 according to the embodiment described above, the side surface of each connection region 36 extends linearly along the direction 100 as shown in FIG. 8. However, for example, as shown in FIG. 12, the side surface of each connection region 36 may extend while curving along the direction 100. However, in a region close to the limit of semiconductor processing accuracy (particularly, pattern exposure accuracy), when attempting to form a connection region 36 with a curved side surface as shown in FIG. 12, the shape of each connection region 36 will vary greatly. In contrast, if the side surface of each connection region 36 extends linearly along the direction 100 as shown in FIG. 8, each connection region 36 can be formed with high accuracy, and variation in the characteristics of the MOSFET 10 can be suppressed.

[0040] In the above embodiment, the electric field relief region 38 extends along a direction perpendicular to the trench 14 when the semiconductor substrate 12 is viewed from above, as shown in Fig. 8. However, the electric field relief region 38 may extend along a direction obliquely intersecting the trench 14, as shown in Fig. 13.

[0041] In the above embodiment, as shown in Fig. 3, a gap is provided between the electric field relaxation region 38 and the lower end of the trench 14. However, as shown in Fig. 14, the electric field relaxation region 38 may contact the lower end of the trench 14.

[0042] The y direction in the embodiment is an example of a first direction, the direction 100 in the embodiment is an example of a second direction, and the x direction in the embodiment is an example of a third direction.

[0043] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0044] 12: semiconductor substrate, 14: trench, 16: gate insulating film, 18: gate electrode, 26: inter-trench semiconductor region, 30: source region, 32: contact region, 34: body region, 36: connection region, 38: electric field relaxation region, 40: drift region

Claims

1. A field effect transistor (10), comprising: A semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface thereof; a gate insulating film (16) and a gate electrode (18) disposed in each of the trenches; a source electrode (22) overlying the top surface of the semiconductor substrate; having The trenches extend elongately in a first direction on the top surface and are spaced apart in a direction perpendicular to the first direction; the semiconductor substrate having a plurality of inter-trench semiconductor regions (26) located between the plurality of trenches; Each of the inter-trench semiconductor regions is an n-type source region (30) in contact with the source electrode and in contact with the gate insulating film; A p-type contact region (32) in contact with the source electrode; a p-type body region (34) that is in contact with the contact region and the source region from below, is in contact with the gate insulating film below the source region, and has a p-type impurity concentration lower than that of the contact region; having The semiconductor substrate has a plurality of p-type connection regions (36), a plurality of p-type field relief regions (38), and an n-type drift region (40); a plurality of the connection regions are disposed below each of the body regions, extend longitudinally in a second direction intersecting the first direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the second direction; each connection region is connected to each body region at an intersection with each body region; a plurality of the electric field relaxation regions are disposed below each of the connection regions and each of the trenches, extend longitudinally in a third direction intersecting the first direction and the second direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the third direction; Each of the electric field relief regions is connected to each of the connection regions at an intersection with each of the connection regions, the drift region is distributed across gaps (36x) between the plurality of connection regions, gaps (38x) between the plurality of electric field relaxation regions, and lower portions of the plurality of electric field relaxation regions, and is in contact with each of the body regions from below, and is in contact with the gate insulating film at the lower side of each of the body regions; Each of the contact regions extends along the second direction while overlapping with the corresponding connection region when the semiconductor substrate is viewed from above. Field effect transistor.

2. The field effect transistor according to claim 1 , wherein the second direction intersects the first direction at an angle.

3. The field effect transistor according to claim 1 , wherein a side surface of each of the connection regions extends linearly along the second direction.

4. 1. A method for manufacturing a field effect transistor, comprising the steps of: The field effect transistor is A semiconductor substrate having a plurality of trenches formed on an upper surface thereof; a gate insulating film and a gate electrode disposed in each of the trenches; a source electrode overlying the top surface of the semiconductor substrate; having The trenches extend elongately in a first direction on the top surface and are spaced apart in a direction perpendicular to the first direction; the semiconductor substrate has a plurality of inter-trench semiconductor regions located between the plurality of trenches; Each of the inter-trench semiconductor regions is an n-type source region in contact with the source electrode and in contact with the gate insulating film; a p-type contact region in contact with the source electrode; a p-type body region in contact with the contact region and the source region from below, in contact with the gate insulating film below the source region, and having a p-type impurity concentration lower than that of the contact region; having the semiconductor substrate has a plurality of p-type connection regions, a plurality of p-type electric field relaxation regions, and an n-type drift region; a plurality of the connection regions are disposed below each of the body regions, extend longitudinally in a second direction intersecting the first direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the second direction; each connection region is connected to each body region at an intersection with each body region; a plurality of the electric field relaxation regions are disposed below each of the connection regions and each of the trenches, extend longitudinally in a third direction intersecting the first direction and the second direction when the semiconductor substrate is viewed from above, and are disposed at intervals in a direction perpendicular to the third direction; Each of the electric field relief regions is connected to each of the connection regions at an intersection with each of the connection regions, the drift region is distributed across gaps between the connection regions, gaps between the electric field relaxation regions, and lower portions of the electric field relaxation regions, is in contact with each of the body regions from below, and is in contact with the gate insulating film at the lower side of each of the body regions; each of the contact regions extends along the second direction while overlapping with a corresponding one of the connection regions when the semiconductor substrate is viewed from above; The manufacturing method includes a step of implanting p-type impurities into the contact region and the connection region through a common mask (90).

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